From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1585) id D0BD33836663; Wed, 1 Jun 2022 10:24:53 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D0BD33836663 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Luis Machado To: gdb-cvs@sourceware.org Subject: [binutils-gdb] [arm] Cleanup: use hex for offsets X-Act-Checkin: binutils-gdb X-Git-Author: Yvan Roux X-Git-Refname: refs/heads/master X-Git-Oldrev: 68538bbeaa9f6c5ebe68ce31465e44c46393e170 X-Git-Newrev: 1d2eeb660f0885807320792ee18c033b34522225 Message-Id: <20220601102453.D0BD33836663@sourceware.org> Date: Wed, 1 Jun 2022 10:24:53 +0000 (GMT) X-BeenThere: gdb-cvs@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 01 Jun 2022 10:24:53 -0000 https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D1d2eeb660f08= 85807320792ee18c033b34522225 commit 1d2eeb660f0885807320792ee18c033b34522225 Author: Yvan Roux Date: Wed Jun 1 11:08:00 2022 +0000 [arm] Cleanup: use hex for offsets =20 Changed offset from decimal to hex to match architecture reference manual terminology and keep coherency with the rest of the code. =20 Signed-off-by: Torbj=C3=B6rn SVENSSON Signed-off-by: Yvan Roux Diff: --- gdb/arm-tdep.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 49664093f00..5ea66898747 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -3438,13 +3438,13 @@ arm_m_exception_cache (struct frame_info *this_fram= e) "B1.5.6 Exception entry behavior" in "ARMv7-M Architecture Reference Manual". */ cache->saved_regs[0].set_addr (unwound_sp + sp_r0_offset); - cache->saved_regs[1].set_addr (unwound_sp + sp_r0_offset + 4); - cache->saved_regs[2].set_addr (unwound_sp + sp_r0_offset + 8); - cache->saved_regs[3].set_addr (unwound_sp + sp_r0_offset + 12); - cache->saved_regs[ARM_IP_REGNUM].set_addr (unwound_sp + sp_r0_offset + 1= 6); - cache->saved_regs[ARM_LR_REGNUM].set_addr (unwound_sp + sp_r0_offset + 2= 0); - cache->saved_regs[ARM_PC_REGNUM].set_addr (unwound_sp + sp_r0_offset + 2= 4); - cache->saved_regs[ARM_PS_REGNUM].set_addr (unwound_sp + sp_r0_offset + 2= 8); + cache->saved_regs[1].set_addr (unwound_sp + sp_r0_offset + 0x04); + cache->saved_regs[2].set_addr (unwound_sp + sp_r0_offset + 0x08); + cache->saved_regs[3].set_addr (unwound_sp + sp_r0_offset + 0x0C); + cache->saved_regs[ARM_IP_REGNUM].set_addr (unwound_sp + sp_r0_offset + 0= x10); + cache->saved_regs[ARM_LR_REGNUM].set_addr (unwound_sp + sp_r0_offset + 0= x14); + cache->saved_regs[ARM_PC_REGNUM].set_addr (unwound_sp + sp_r0_offset + 0= x18); + cache->saved_regs[ARM_PS_REGNUM].set_addr (unwound_sp + sp_r0_offset + 0= x1C); =20 /* Check EXC_RETURN bit FTYPE if extended stack frame (FPU regs stored) type used. */ @@ -3499,7 +3499,8 @@ arm_m_exception_cache (struct frame_info *this_frame) /* If bit 9 of the saved xPSR is set, then there is a four-byte aligner between the top of the 32-byte stack frame and the previous context's stack pointer. */ - if (safe_read_memory_integer (unwound_sp + sp_r0_offset + 28, 4, byte_or= der, &xpsr) + if (safe_read_memory_integer (unwound_sp + sp_r0_offset + 0x1C, 4, + byte_order, &xpsr) && (xpsr & (1 << 9)) !=3D 0) arm_cache_set_active_sp_value (cache, tdep, arm_cache_get_prev_sp_value (cache, tdep) + 4);