From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2126) id 505DE3857BAD; Thu, 2 Jun 2022 15:29:49 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 505DE3857BAD Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Tom Tromey To: gdb-cvs@sourceware.org Subject: [binutils-gdb] ODR warnings for "struct insn_decode_record_t" X-Act-Checkin: binutils-gdb X-Git-Author: Tom Tromey X-Git-Refname: refs/heads/master X-Git-Oldrev: 131430937d0eac8a7143306b8d1afa1bc5762877 X-Git-Newrev: 4748a9be449fddcd69e865bdc484519c30701e55 Message-Id: <20220602152949.505DE3857BAD@sourceware.org> Date: Thu, 2 Jun 2022 15:29:49 +0000 (GMT) X-BeenThere: gdb-cvs@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 02 Jun 2022 15:29:49 -0000 https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D4748a9be449f= ddcd69e865bdc484519c30701e55 commit 4748a9be449fddcd69e865bdc484519c30701e55 Author: Tom Tromey Date: Wed May 18 10:10:57 2022 -0600 ODR warnings for "struct insn_decode_record_t" =20 "struct insn_decode_record_t" is defined in multiple .c files, causing ODR warnings. This patch renames the types, and removes the use of "typedef" here -- this is a C-ism that's no longer needed. =20 Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=3D22395 Diff: --- gdb/aarch64-tdep.c | 28 ++++++++-------- gdb/arm-tdep.c | 95 +++++++++++++++++++++++++++-----------------------= ---- 2 files changed, 62 insertions(+), 61 deletions(-) diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c index 67a3f96e1a7..15b577c8a00 100644 --- a/gdb/aarch64-tdep.c +++ b/gdb/aarch64-tdep.c @@ -3775,7 +3775,7 @@ enum aarch64_record_result AARCH64_RECORD_UNKNOWN }; =20 -typedef struct insn_decode_record_t +struct aarch64_insn_decode_record { struct gdbarch *gdbarch; struct regcache *regcache; @@ -3785,12 +3785,12 @@ typedef struct insn_decode_record_t uint32_t reg_rec_count; /* Count of register records. */ uint32_t *aarch64_regs; /* Registers to be recorded. */ struct aarch64_mem_r *aarch64_mems; /* Memory locations to be recorded.= */ -} insn_decode_record; +}; =20 /* Record handler for data processing - register instructions. */ =20 static unsigned int -aarch64_record_data_proc_reg (insn_decode_record *aarch64_insn_r) +aarch64_record_data_proc_reg (aarch64_insn_decode_record *aarch64_insn_r) { uint8_t reg_rd, insn_bits24_27, insn_bits21_23; uint32_t record_buf[4]; @@ -3866,7 +3866,7 @@ aarch64_record_data_proc_reg (insn_decode_record *aar= ch64_insn_r) /* Record handler for data processing - immediate instructions. */ =20 static unsigned int -aarch64_record_data_proc_imm (insn_decode_record *aarch64_insn_r) +aarch64_record_data_proc_imm (aarch64_insn_decode_record *aarch64_insn_r) { uint8_t reg_rd, insn_bit23, insn_bits24_27, setflags; uint32_t record_buf[4]; @@ -3911,7 +3911,7 @@ aarch64_record_data_proc_imm (insn_decode_record *aar= ch64_insn_r) /* Record handler for branch, exception generation and system instructions= . */ =20 static unsigned int -aarch64_record_branch_except_sys (insn_decode_record *aarch64_insn_r) +aarch64_record_branch_except_sys (aarch64_insn_decode_record *aarch64_insn= _r) { =20 aarch64_gdbarch_tdep *tdep @@ -3993,7 +3993,7 @@ aarch64_record_branch_except_sys (insn_decode_record = *aarch64_insn_r) /* Record handler for advanced SIMD load and store instructions. */ =20 static unsigned int -aarch64_record_asimd_load_store (insn_decode_record *aarch64_insn_r) +aarch64_record_asimd_load_store (aarch64_insn_decode_record *aarch64_insn_= r) { CORE_ADDR address; uint64_t addr_offset =3D 0; @@ -4159,7 +4159,7 @@ aarch64_record_asimd_load_store (insn_decode_record *= aarch64_insn_r) /* Record handler for load and store instructions. */ =20 static unsigned int -aarch64_record_load_store (insn_decode_record *aarch64_insn_r) +aarch64_record_load_store (aarch64_insn_decode_record *aarch64_insn_r) { uint8_t insn_bits24_27, insn_bits28_29, insn_bits10_11; uint8_t insn_bit23, insn_bit21; @@ -4447,7 +4447,7 @@ aarch64_record_load_store (insn_decode_record *aarch6= 4_insn_r) /* Record handler for data processing SIMD and floating point instructions= . */ =20 static unsigned int -aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r) +aarch64_record_data_proc_simd_fp (aarch64_insn_decode_record *aarch64_insn= _r) { uint8_t insn_bit21, opcode, rmode, reg_rd; uint8_t insn_bits24_27, insn_bits28_31, insn_bits10_11, insn_bits12_15; @@ -4600,7 +4600,7 @@ aarch64_record_data_proc_simd_fp (insn_decode_record = *aarch64_insn_r) /* Decodes insns type and invokes its record handler. */ =20 static unsigned int -aarch64_record_decode_insn_handler (insn_decode_record *aarch64_insn_r) +aarch64_record_decode_insn_handler (aarch64_insn_decode_record *aarch64_in= sn_r) { uint32_t ins_bit25, ins_bit26, ins_bit27, ins_bit28; =20 @@ -4635,7 +4635,7 @@ aarch64_record_decode_insn_handler (insn_decode_recor= d *aarch64_insn_r) /* Cleans up local record registers and memory allocations. */ =20 static void -deallocate_reg_mem (insn_decode_record *record) +deallocate_reg_mem (aarch64_insn_decode_record *record) { xfree (record->aarch64_regs); xfree (record->aarch64_mems); @@ -4655,9 +4655,9 @@ aarch64_process_record_test (void) struct gdbarch *gdbarch =3D gdbarch_find_by_info (info); SELF_CHECK (gdbarch !=3D NULL); =20 - insn_decode_record aarch64_record; + aarch64_insn_decode_record aarch64_record; =20 - memset (&aarch64_record, 0, sizeof (insn_decode_record)); + memset (&aarch64_record, 0, sizeof (aarch64_insn_decode_record)); aarch64_record.regcache =3D NULL; aarch64_record.this_addr =3D 0; aarch64_record.gdbarch =3D gdbarch; @@ -4687,10 +4687,10 @@ aarch64_process_record (struct gdbarch *gdbarch, st= ruct regcache *regcache, uint8_t insn_size =3D 4; uint32_t ret =3D 0; gdb_byte buf[insn_size]; - insn_decode_record aarch64_record; + aarch64_insn_decode_record aarch64_record; =20 memset (&buf[0], 0, insn_size); - memset (&aarch64_record, 0, sizeof (insn_decode_record)); + memset (&aarch64_record, 0, sizeof (aarch64_insn_decode_record)); target_read_memory (insn_addr, &buf[0], insn_size); aarch64_record.aarch64_insn =3D (uint32_t) extract_unsigned_integer (&buf[0], diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 35b3d9baa5e..591a2da99f2 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -10663,7 +10663,7 @@ struct arm_mem_r contains list of to-be-modified registers and memory blocks (on return from decode_insn()). */ =20 -typedef struct insn_decode_record_t +struct arm_insn_decode_record { struct gdbarch *gdbarch; struct regcache *regcache; @@ -10676,7 +10676,7 @@ typedef struct insn_decode_record_t uint32_t reg_rec_count; /* No of reg records. */ uint32_t *arm_regs; /* Registers to be saved for this record. = */ struct arm_mem_r *arm_mems; /* Memory to be saved for this record. */ -} insn_decode_record; +}; =20 =20 /* Checks ARM SBZ and SBO mandatory fields. */ @@ -10724,7 +10724,7 @@ enum record_type_t =20 =20 static int -arm_record_strx (insn_decode_record *arm_insn_r, uint32_t *record_buf,=20 +arm_record_strx (arm_insn_decode_record *arm_insn_r, uint32_t *record_buf,= =20 uint32_t *record_buf_mem, arm_record_strx_t str_type) { =20 @@ -10892,7 +10892,7 @@ arm_record_strx (insn_decode_record *arm_insn_r, ui= nt32_t *record_buf, /* Handling ARM extension space insns. */ =20 static int -arm_record_extension_space (insn_decode_record *arm_insn_r) +arm_record_extension_space (arm_insn_decode_record *arm_insn_r) { int ret =3D 0; /* Return value: -1:record failure ; 0:success */ uint32_t opcode1 =3D 0, opcode2 =3D 0, insn_op1 =3D 0; @@ -11155,7 +11155,7 @@ arm_record_extension_space (insn_decode_record *arm= _insn_r) /* Handling opcode 000 insns. */ =20 static int -arm_record_data_proc_misc_ld_str (insn_decode_record *arm_insn_r) +arm_record_data_proc_misc_ld_str (arm_insn_decode_record *arm_insn_r) { struct regcache *reg_cache =3D arm_insn_r->regcache; uint32_t record_buf[8], record_buf_mem[8]; @@ -11448,7 +11448,7 @@ arm_record_data_proc_misc_ld_str (insn_decode_recor= d *arm_insn_r) /* Handling opcode 001 insns. */ =20 static int -arm_record_data_proc_imm (insn_decode_record *arm_insn_r) +arm_record_data_proc_imm (arm_insn_decode_record *arm_insn_r) { uint32_t record_buf[8], record_buf_mem[8]; =20 @@ -11492,7 +11492,7 @@ arm_record_data_proc_imm (insn_decode_record *arm_i= nsn_r) } =20 static int -arm_record_media (insn_decode_record *arm_insn_r) +arm_record_media (arm_insn_decode_record *arm_insn_r) { uint32_t record_buf[8]; =20 @@ -11576,7 +11576,7 @@ arm_record_media (insn_decode_record *arm_insn_r) /* Handle ARM mode instructions with opcode 010. */ =20 static int -arm_record_ld_st_imm_offset (insn_decode_record *arm_insn_r) +arm_record_ld_st_imm_offset (arm_insn_decode_record *arm_insn_r) { struct regcache *reg_cache =3D arm_insn_r->regcache; =20 @@ -11667,7 +11667,7 @@ arm_record_ld_st_imm_offset (insn_decode_record *ar= m_insn_r) /* Handling opcode 011 insns. */ =20 static int -arm_record_ld_st_reg_offset (insn_decode_record *arm_insn_r) +arm_record_ld_st_reg_offset (arm_insn_decode_record *arm_insn_r) { struct regcache *reg_cache =3D arm_insn_r->regcache; =20 @@ -11933,7 +11933,7 @@ arm_record_ld_st_reg_offset (insn_decode_record *ar= m_insn_r) /* Handle ARM mode instructions with opcode 100. */ =20 static int -arm_record_ld_st_multiple (insn_decode_record *arm_insn_r) +arm_record_ld_st_multiple (arm_insn_decode_record *arm_insn_r) { struct regcache *reg_cache =3D arm_insn_r->regcache; uint32_t register_count =3D 0, register_bits; @@ -12033,7 +12033,7 @@ arm_record_ld_st_multiple (insn_decode_record *arm_= insn_r) /* Handling opcode 101 insns. */ =20 static int -arm_record_b_bl (insn_decode_record *arm_insn_r) +arm_record_b_bl (arm_insn_decode_record *arm_insn_r) { uint32_t record_buf[8]; =20 @@ -12053,7 +12053,7 @@ arm_record_b_bl (insn_decode_record *arm_insn_r) } =20 static int -arm_record_unsupported_insn (insn_decode_record *arm_insn_r) +arm_record_unsupported_insn (arm_insn_decode_record *arm_insn_r) { gdb_printf (gdb_stderr, _("Process record does not support instruction " @@ -12066,7 +12066,7 @@ arm_record_unsupported_insn (insn_decode_record *ar= m_insn_r) /* Record handler for vector data transfer instructions. */ =20 static int -arm_record_vdata_transfer_insn (insn_decode_record *arm_insn_r) +arm_record_vdata_transfer_insn (arm_insn_decode_record *arm_insn_r) { uint32_t bits_a, bit_c, bit_l, reg_t, reg_v; uint32_t record_buf[4]; @@ -12152,7 +12152,7 @@ arm_record_vdata_transfer_insn (insn_decode_record = *arm_insn_r) /* Record handler for extension register load/store instructions. */ =20 static int -arm_record_exreg_ld_st_insn (insn_decode_record *arm_insn_r) +arm_record_exreg_ld_st_insn (arm_insn_decode_record *arm_insn_r) { uint32_t opcode, single_reg; uint8_t op_vldm_vstm; @@ -12347,7 +12347,7 @@ arm_record_exreg_ld_st_insn (insn_decode_record *ar= m_insn_r) /* Record handler for arm/thumb mode VFP data processing instructions. */ =20 static int -arm_record_vfp_data_proc_insn (insn_decode_record *arm_insn_r) +arm_record_vfp_data_proc_insn (arm_insn_decode_record *arm_insn_r) { uint32_t opc1, opc2, opc3, dp_op_sz, bit_d, reg_vd; uint32_t record_buf[4]; @@ -12559,7 +12559,7 @@ arm_record_vfp_data_proc_insn (insn_decode_record *= arm_insn_r) /* Handling opcode 110 insns. */ =20 static int -arm_record_asimd_vfp_coproc (insn_decode_record *arm_insn_r) +arm_record_asimd_vfp_coproc (arm_insn_decode_record *arm_insn_r) { uint32_t op1, op1_ebit, coproc; =20 @@ -12613,7 +12613,7 @@ arm_record_asimd_vfp_coproc (insn_decode_record *ar= m_insn_r) /* Handling opcode 111 insns. */ =20 static int -arm_record_coproc_data_proc (insn_decode_record *arm_insn_r) +arm_record_coproc_data_proc (arm_insn_decode_record *arm_insn_r) { uint32_t op, op1_ebit, coproc, bits_24_25; arm_gdbarch_tdep *tdep @@ -12744,7 +12744,7 @@ arm_record_coproc_data_proc (insn_decode_record *ar= m_insn_r) /* Handling opcode 000 insns. */ =20 static int -thumb_record_shift_add_sub (insn_decode_record *thumb_insn_r) +thumb_record_shift_add_sub (arm_insn_decode_record *thumb_insn_r) { uint32_t record_buf[8]; uint32_t reg_src1 =3D 0; @@ -12764,7 +12764,7 @@ thumb_record_shift_add_sub (insn_decode_record *thu= mb_insn_r) /* Handling opcode 001 insns. */ =20 static int -thumb_record_add_sub_cmp_mov (insn_decode_record *thumb_insn_r) +thumb_record_add_sub_cmp_mov (arm_insn_decode_record *thumb_insn_r) { uint32_t record_buf[8]; uint32_t reg_src1 =3D 0; @@ -12783,7 +12783,7 @@ thumb_record_add_sub_cmp_mov (insn_decode_record *t= humb_insn_r) /* Handling opcode 010 insns. */ =20 static int -thumb_record_ld_st_reg_offset (insn_decode_record *thumb_insn_r) +thumb_record_ld_st_reg_offset (arm_insn_decode_record *thumb_insn_r) { struct regcache *reg_cache =3D thumb_insn_r->regcache; uint32_t record_buf[8], record_buf_mem[8]; @@ -12875,7 +12875,7 @@ thumb_record_ld_st_reg_offset (insn_decode_record *= thumb_insn_r) /* Handling opcode 001 insns. */ =20 static int -thumb_record_ld_st_imm_offset (insn_decode_record *thumb_insn_r) +thumb_record_ld_st_imm_offset (arm_insn_decode_record *thumb_insn_r) { struct regcache *reg_cache =3D thumb_insn_r->regcache; uint32_t record_buf[8], record_buf_mem[8]; @@ -12915,7 +12915,7 @@ thumb_record_ld_st_imm_offset (insn_decode_record *= thumb_insn_r) /* Handling opcode 100 insns. */ =20 static int -thumb_record_ld_st_stack (insn_decode_record *thumb_insn_r) +thumb_record_ld_st_stack (arm_insn_decode_record *thumb_insn_r) { struct regcache *reg_cache =3D thumb_insn_r->regcache; uint32_t record_buf[8], record_buf_mem[8]; @@ -12971,7 +12971,7 @@ thumb_record_ld_st_stack (insn_decode_record *thumb= _insn_r) /* Handling opcode 101 insns. */ =20 static int -thumb_record_misc (insn_decode_record *thumb_insn_r) +thumb_record_misc (arm_insn_decode_record *thumb_insn_r) { struct regcache *reg_cache =3D thumb_insn_r->regcache; =20 @@ -13102,7 +13102,7 @@ thumb_record_misc (insn_decode_record *thumb_insn_r) /* Handling opcode 110 insns. */ =20 static int -thumb_record_ldm_stm_swi (insn_decode_record *thumb_insn_r) +thumb_record_ldm_stm_swi (arm_insn_decode_record *thumb_insn_r) { arm_gdbarch_tdep *tdep =3D (arm_gdbarch_tdep *) gdbarch_tdep (thumb_insn_r->gdbarch); @@ -13187,7 +13187,7 @@ thumb_record_ldm_stm_swi (insn_decode_record *thumb= _insn_r) /* Handling opcode 111 insns. */ =20 static int -thumb_record_branch (insn_decode_record *thumb_insn_r) +thumb_record_branch (arm_insn_decode_record *thumb_insn_r) { uint32_t record_buf[8]; uint32_t bits_h =3D 0; @@ -13219,7 +13219,7 @@ thumb_record_branch (insn_decode_record *thumb_insn= _r) /* Handler for thumb2 load/store multiple instructions. */ =20 static int -thumb2_record_ld_st_multiple (insn_decode_record *thumb2_insn_r) +thumb2_record_ld_st_multiple (arm_insn_decode_record *thumb2_insn_r) { struct regcache *reg_cache =3D thumb2_insn_r->regcache; =20 @@ -13314,7 +13314,7 @@ thumb2_record_ld_st_multiple (insn_decode_record *t= humb2_insn_r) instructions. */ =20 static int -thumb2_record_ld_st_dual_ex_tbb (insn_decode_record *thumb2_insn_r) +thumb2_record_ld_st_dual_ex_tbb (arm_insn_decode_record *thumb2_insn_r) { struct regcache *reg_cache =3D thumb2_insn_r->regcache; =20 @@ -13431,7 +13431,7 @@ thumb2_record_ld_st_dual_ex_tbb (insn_decode_record= *thumb2_insn_r) instructions. */ =20 static int -thumb2_record_data_proc_sreg_mimm (insn_decode_record *thumb2_insn_r) +thumb2_record_data_proc_sreg_mimm (arm_insn_decode_record *thumb2_insn_r) { uint32_t reg_rd, op; uint32_t record_buf[8]; @@ -13460,7 +13460,7 @@ thumb2_record_data_proc_sreg_mimm (insn_decode_reco= rd *thumb2_insn_r) registers. */ =20 static int -thumb2_record_ps_dest_generic (insn_decode_record *thumb2_insn_r) +thumb2_record_ps_dest_generic (arm_insn_decode_record *thumb2_insn_r) { uint32_t reg_rd; uint32_t record_buf[8]; @@ -13479,7 +13479,7 @@ thumb2_record_ps_dest_generic (insn_decode_record *= thumb2_insn_r) /* Handler for thumb2 branch and miscellaneous control instructions. */ =20 static int -thumb2_record_branch_misc_cntrl (insn_decode_record *thumb2_insn_r) +thumb2_record_branch_misc_cntrl (arm_insn_decode_record *thumb2_insn_r) { uint32_t op, op1, op2; uint32_t record_buf[8]; @@ -13519,7 +13519,7 @@ thumb2_record_branch_misc_cntrl (insn_decode_record= *thumb2_insn_r) /* Handler for thumb2 store single data item instructions. */ =20 static int -thumb2_record_str_single_data (insn_decode_record *thumb2_insn_r) +thumb2_record_str_single_data (arm_insn_decode_record *thumb2_insn_r) { struct regcache *reg_cache =3D thumb2_insn_r->regcache; =20 @@ -13609,7 +13609,7 @@ thumb2_record_str_single_data (insn_decode_record *= thumb2_insn_r) /* Handler for thumb2 load memory hints instructions. */ =20 static int -thumb2_record_ld_mem_hints (insn_decode_record *thumb2_insn_r) +thumb2_record_ld_mem_hints (arm_insn_decode_record *thumb2_insn_r) { uint32_t record_buf[8]; uint32_t reg_rt, reg_rn; @@ -13635,7 +13635,7 @@ thumb2_record_ld_mem_hints (insn_decode_record *thu= mb2_insn_r) /* Handler for thumb2 load word instructions. */ =20 static int -thumb2_record_ld_word (insn_decode_record *thumb2_insn_r) +thumb2_record_ld_word (arm_insn_decode_record *thumb2_insn_r) { uint32_t record_buf[8]; =20 @@ -13652,7 +13652,7 @@ thumb2_record_ld_word (insn_decode_record *thumb2_i= nsn_r) divide instructions. */ =20 static int -thumb2_record_lmul_lmla_div (insn_decode_record *thumb2_insn_r) +thumb2_record_lmul_lmla_div (arm_insn_decode_record *thumb2_insn_r) { uint32_t opcode1 =3D 0, opcode2 =3D 0; uint32_t record_buf[8]; @@ -13688,7 +13688,7 @@ thumb2_record_lmul_lmla_div (insn_decode_record *th= umb2_insn_r) /* Record handler for thumb32 coprocessor instructions. */ =20 static int -thumb2_record_coproc_insn (insn_decode_record *thumb2_insn_r) +thumb2_record_coproc_insn (arm_insn_decode_record *thumb2_insn_r) { if (bit (thumb2_insn_r->arm_insn, 25)) return arm_record_coproc_data_proc (thumb2_insn_r); @@ -13699,7 +13699,7 @@ thumb2_record_coproc_insn (insn_decode_record *thum= b2_insn_r) /* Record handler for advance SIMD structure load/store instructions. */ =20 static int -thumb2_record_asimd_struct_ld_st (insn_decode_record *thumb2_insn_r) +thumb2_record_asimd_struct_ld_st (arm_insn_decode_record *thumb2_insn_r) { struct regcache *reg_cache =3D thumb2_insn_r->regcache; uint32_t l_bit, a_bit, b_bits; @@ -13887,7 +13887,7 @@ thumb2_record_asimd_struct_ld_st (insn_decode_recor= d *thumb2_insn_r) /* Decodes thumb2 instruction type and invokes its record handler. */ =20 static unsigned int -thumb2_record_decode_insn_handler (insn_decode_record *thumb2_insn_r) +thumb2_record_decode_insn_handler (arm_insn_decode_record *thumb2_insn_r) { uint32_t op, op1, op2; =20 @@ -14021,7 +14021,7 @@ and positive val on failure. */ =20 static int extract_arm_insn (abstract_memory_reader& reader, - insn_decode_record *insn_record, uint32_t insn_size) + arm_insn_decode_record *insn_record, uint32_t insn_size) { gdb_byte buf[insn_size]; =20 @@ -14035,13 +14035,14 @@ extract_arm_insn (abstract_memory_reader& reader, return 0; } =20 -typedef int (*sti_arm_hdl_fp_t) (insn_decode_record*); +typedef int (*sti_arm_hdl_fp_t) (arm_insn_decode_record*); =20 /* Decode arm/thumb insn depending on condition cods and opcodes; and dispatch it. */ =20 static int -decode_insn (abstract_memory_reader &reader, insn_decode_record *arm_recor= d, +decode_insn (abstract_memory_reader &reader, + arm_insn_decode_record *arm_record, record_type_t record_type, uint32_t insn_size) { =20 @@ -14192,9 +14193,9 @@ arm_record_test (void) =20 /* 16-bit Thumb instructions. */ { - insn_decode_record arm_record; + arm_insn_decode_record arm_record; =20 - memset (&arm_record, 0, sizeof (insn_decode_record)); + memset (&arm_record, 0, sizeof (arm_insn_decode_record)); arm_record.gdbarch =3D gdbarch; =20 static const uint16_t insns[] =3D { @@ -14226,9 +14227,9 @@ arm_record_test (void) =20 /* 32-bit Thumb-2 instructions. */ { - insn_decode_record arm_record; + arm_insn_decode_record arm_record; =20 - memset (&arm_record, 0, sizeof (insn_decode_record)); + memset (&arm_record, 0, sizeof (arm_insn_decode_record)); arm_record.gdbarch =3D gdbarch; =20 static const uint16_t insns[] =3D { @@ -14307,7 +14308,7 @@ arm_analyze_prologue_test () /* Cleans up local record registers and memory allocations. */ =20 static void=20 -deallocate_reg_mem (insn_decode_record *record) +deallocate_reg_mem (arm_insn_decode_record *record) { xfree (record->arm_regs); xfree (record->arm_mems); =20 @@ -14329,9 +14330,9 @@ arm_process_record (struct gdbarch *gdbarch, struct= regcache *regcache, =20 ULONGEST u_regval =3D 0; =20 - insn_decode_record arm_record; + arm_insn_decode_record arm_record; =20 - memset (&arm_record, 0, sizeof (insn_decode_record)); + memset (&arm_record, 0, sizeof (arm_insn_decode_record)); arm_record.regcache =3D regcache; arm_record.this_addr =3D insn_addr; arm_record.gdbarch =3D gdbarch;