From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1844) id 0BCDF385AE68; Thu, 9 Jun 2022 14:47:58 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 0BCDF385AE68 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Yvan Roux To: gdb-cvs@sourceware.org Subject: [binutils-gdb] gdb/arm: Document and fix exception stack offsets X-Act-Checkin: binutils-gdb X-Git-Author: Yvan Roux X-Git-Refname: refs/heads/master X-Git-Oldrev: 1ef3351b7b11e3d3bcdccdbc1bf2690ce35a70ba X-Git-Newrev: 2d9cf99d9a6c701de912d3e95ea3ffa134af4c62 Message-Id: <20220609144758.0BCDF385AE68@sourceware.org> Date: Thu, 9 Jun 2022 14:47:58 +0000 (GMT) X-BeenThere: gdb-cvs@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 09 Jun 2022 14:47:58 -0000 https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D2d9cf99d9a6c= 701de912d3e95ea3ffa134af4c62 commit 2d9cf99d9a6c701de912d3e95ea3ffa134af4c62 Author: Yvan Roux Date: Thu Jun 9 16:44:50 2022 +0200 gdb/arm: Document and fix exception stack offsets =20 Add a description of exception entry context stacking and fix next frame offset (at 0xA8 relative to R0 location) as well as FPU registers ones (starting at 0x68 relative to R0). =20 Signed-off-by: Torbj=C3=B6rn SVENSSON Signed-off-by: Yvan Roux Diff: --- gdb/arm-tdep.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++++++= ---- 1 file changed, 61 insertions(+), 4 deletions(-) diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 23f3d5f02f2..456649afdaa 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -3429,6 +3429,60 @@ arm_m_exception_cache (struct frame_info *this_frame) /* Fetch the SP to use for this frame. */ unwound_sp =3D arm_cache_get_prev_sp_value (cache, tdep); =20 + /* Exception entry context stacking are described in ARMv8-M (section B3= .19) + and ARMv7-M (sections B1.5.6 and B1.5.7) Architecture Reference Manua= ls. + + The following figure shows the structure of the stack frame when Secu= rity + and Floating-point extensions are present. + + SP Offsets + Without With + Callee Regs Callee Regs + (Secure -> Non-Secure) + +-------------------+ + 0xA8 | | 0xD0 + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D+ --+ <-- Original SP + 0xA4 | S31 | 0xCC | + +-------------------+ | + ... | Additional FP conte= xt + +-------------------+ | + 0x68 | S16 | 0x90 | + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D+ --+ + 0x64 | Reserved | 0x8C | + +-------------------+ | + 0x60 | FPSCR | 0x88 | + +-------------------+ | + 0x5C | S15 | 0x84 | FP context + +-------------------+ | + ... | + +-------------------+ | + 0x20 | S0 | 0x48 | + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D+ --+ + 0x1C | xPSR | 0x44 | + +-------------------+ | + 0x18 | Return address | 0x40 | + +-------------------+ | + 0x14 | LR(R14) | 0x3C | + +-------------------+ | + 0x10 | R12 | 0x38 | State context + +-------------------+ | + 0x0C | R3 | 0x34 | + +-------------------+ | + ... | + +-------------------+ | + 0x00 | R0 | 0x28 | + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D+ --+ + | R11 | 0x24 | + +-------------------+ | + ... | + +-------------------+ | Additional state co= ntext + | R4 | 0x08 | when transitioning = from + +-------------------+ | Secure to Non-Secure + | Reserved | 0x04 | + +-------------------+ | + | Magic signature | 0x00 | + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D+ --+ <-- New SP */ + /* With the Security extension, the hardware saves R4..R11 too. */ if (exc_return && tdep->have_sec_ext && secure_stack_used && (!default_callee_register_stacking || exception_domain_is_secure)) @@ -3487,25 +3541,28 @@ arm_m_exception_cache (struct frame_info *this_fram= e) if (tdep->have_sec_ext && !default_callee_register_stacking) { /* Handle floating-point callee saved registers. */ - fpu_regs_stack_offset =3D 0x90; + fpu_regs_stack_offset =3D unwound_sp + sp_r0_offset + 0x68; for (i =3D 8; i < 16; i++) { cache->saved_regs[ARM_D0_REGNUM + i].set_addr (fpu_regs_stack_offse= t); fpu_regs_stack_offset +=3D 8; } =20 - arm_cache_set_active_sp_value (cache, tdep, unwound_sp + sp_r0_offset += 0xD0); + arm_cache_set_active_sp_value (cache, tdep, + unwound_sp + sp_r0_offset + 0xA8); } else { /* Offset 0x64 is reserved. */ - arm_cache_set_active_sp_value (cache, tdep, unwound_sp + sp_r0_offset += 0x68); + arm_cache_set_active_sp_value (cache, tdep, + unwound_sp + sp_r0_offset + 0x68); } } else { /* Standard stack frame type used. */ - arm_cache_set_active_sp_value (cache, tdep, unwound_sp + sp_r0_offse= t + 0x20); + arm_cache_set_active_sp_value (cache, tdep, + unwound_sp + sp_r0_offset + 0x20); } =20 /* If bit 9 of the saved xPSR is set, then there is a four-byte