[binutils-gdb] Fix bugs in aarch64-ravenscar-thread.c

[Tom Tromey <tromey@sourceware.org>]

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=2808125fbb5f9c55f52e863283b7f1c5f0ef1a65

commit 2808125fbb5f9c55f52e863283b7f1c5f0ef1a65
Author: Tom Tromey <tromey@adacore.com>
Date:   Tue May 3 11:23:47 2022 -0600

    Fix bugs in aarch64-ravenscar-thread.c
    
    We found a few bugs in aarch64-ravenscar-thread.c.
    
    First, some of the register offsets were incorrect.  The "bb-runtimes"
    file for this runtime had the wrong offsets in comments, which GDB
    took to be correct.  However, those comments didn't account for
    alignment.  This patch adjusts the offsets.
    
    Next, the "FPU Saved field" is not a register -- it is an
    implementation detail of the runtime.  This is removed.
    
    Finally, I think the FP registers are actually named V0-V31, and the
    "Q" names are pseudo-registers.  This patch fixes the comment.

Diff:
---
 gdb/aarch64-ravenscar-thread.c | 23 ++++++++++-------------
 1 file changed, 10 insertions(+), 13 deletions(-)

diff --git a/gdb/aarch64-ravenscar-thread.c b/gdb/aarch64-ravenscar-thread.c
index a60471d7275..dc35537e3d5 100644
--- a/gdb/aarch64-ravenscar-thread.c
+++ b/gdb/aarch64-ravenscar-thread.c
@@ -47,21 +47,18 @@ static const int aarch64_context_offsets[] =
   80,        88,        96,        88,
   NO_OFFSET,
 
-  /* Q0 - Q31 */
-  112,       128,       144,       160,
-  176,       192,       208,       224,
-  240,       256,       272,       288,
-  304,       320,       336,       352,
-  368,       384,       400,       416,
-  432,       448,       464,       480,
-  496,       512,       528,       544,
-  560,       576,       592,       608,
+  /* V0 - V31 */
+  128,       144,       160,       176,
+  192,       208,       224,       240,
+  256,       272,       288,       304,
+  320,       336,       352,       368,
+  384,       400,       416,       432,
+  448,       464,       480,       496,
+  512,       528,       544,       560,
+  576,       592,       608,       624,
 
   /* FPSR, FPCR */
-  104,       108,
-
-  /* FPU Saved field */
-  624
+  112,       116,
 };
 
 /* The register layout info.  */