From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2126) id EAB503852751; Tue, 14 Jun 2022 15:13:11 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org EAB503852751 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Tom Tromey To: gdb-cvs@sourceware.org Subject: [binutils-gdb] Fix bugs in aarch64-ravenscar-thread.c X-Act-Checkin: binutils-gdb X-Git-Author: Tom Tromey X-Git-Refname: refs/heads/master X-Git-Oldrev: edb6b77c755545afb969fcebfa900b07a4b93c94 X-Git-Newrev: 2808125fbb5f9c55f52e863283b7f1c5f0ef1a65 Message-Id: <20220614151311.EAB503852751@sourceware.org> Date: Tue, 14 Jun 2022 15:13:11 +0000 (GMT) X-BeenThere: gdb-cvs@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 14 Jun 2022 15:13:12 -0000 https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D2808125fbb5f= 9c55f52e863283b7f1c5f0ef1a65 commit 2808125fbb5f9c55f52e863283b7f1c5f0ef1a65 Author: Tom Tromey Date: Tue May 3 11:23:47 2022 -0600 Fix bugs in aarch64-ravenscar-thread.c =20 We found a few bugs in aarch64-ravenscar-thread.c. =20 First, some of the register offsets were incorrect. The "bb-runtimes" file for this runtime had the wrong offsets in comments, which GDB took to be correct. However, those comments didn't account for alignment. This patch adjusts the offsets. =20 Next, the "FPU Saved field" is not a register -- it is an implementation detail of the runtime. This is removed. =20 Finally, I think the FP registers are actually named V0-V31, and the "Q" names are pseudo-registers. This patch fixes the comment. Diff: --- gdb/aarch64-ravenscar-thread.c | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/gdb/aarch64-ravenscar-thread.c b/gdb/aarch64-ravenscar-thread.c index a60471d7275..dc35537e3d5 100644 --- a/gdb/aarch64-ravenscar-thread.c +++ b/gdb/aarch64-ravenscar-thread.c @@ -47,21 +47,18 @@ static const int aarch64_context_offsets[] =3D 80, 88, 96, 88, NO_OFFSET, =20 - /* Q0 - Q31 */ - 112, 128, 144, 160, - 176, 192, 208, 224, - 240, 256, 272, 288, - 304, 320, 336, 352, - 368, 384, 400, 416, - 432, 448, 464, 480, - 496, 512, 528, 544, - 560, 576, 592, 608, + /* V0 - V31 */ + 128, 144, 160, 176, + 192, 208, 224, 240, + 256, 272, 288, 304, + 320, 336, 352, 368, + 384, 400, 416, 432, + 448, 464, 480, 496, + 512, 528, 544, 560, + 576, 592, 608, 624, =20 /* FPSR, FPCR */ - 104, 108, - - /* FPU Saved field */ - 624 + 112, 116, }; =20 /* The register layout info. */