From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1844) id 90CA0386F0D6; Mon, 27 Jun 2022 11:28:28 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 90CA0386F0D6 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Yvan Roux To: gdb-cvs@sourceware.org Subject: [binutils-gdb] gdb/arm: Unwind Non-Secure callbacks from Secure X-Act-Checkin: binutils-gdb X-Git-Author: Yvan Roux X-Git-Refname: refs/heads/master X-Git-Oldrev: a3f1431a5087445ec3987d38b5ee37bcb802214c X-Git-Newrev: 8c9ae6df3c244a7a738085ab461cb098df1d46f6 Message-Id: <20220627112828.90CA0386F0D6@sourceware.org> Date: Mon, 27 Jun 2022 11:28:28 +0000 (GMT) X-BeenThere: gdb-cvs@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 27 Jun 2022 11:28:28 -0000 https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D8c9ae6df3c24= 4a7a738085ab461cb098df1d46f6 commit 8c9ae6df3c244a7a738085ab461cb098df1d46f6 Author: Yvan Roux Date: Mon Jun 27 13:26:36 2022 +0200 gdb/arm: Unwind Non-Secure callbacks from Secure =20 Without this changeset, the unwinding doesn't take into account Non-Secure to Secure stack unwinding enablement status and doesn't choose the proper SP to do the unwinding. =20 This patch only unwinds the stack when Non-Secure to Secure unwinding is enabled, previous SP is set w/r to the current mode (Handler -> msp_s, Thread -> psp_s) and then the Secure stack is unwound. Ensure thumb bit is set in PSR when needed. Also, drop thumb bit from PC if set. =20 Signed-off-by: Torbj=C3=B6rn SVENSSON Signed-off-by: Yvan ROUX Diff: --- gdb/arm-tdep.c | 114 ++++++++++++++++++++++++++++++++++++++++++-----------= ---- 1 file changed, 84 insertions(+), 30 deletions(-) diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 96d70d40b28..e36bde9b3da 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -309,6 +309,21 @@ struct arm_prologue_cache arm_prologue_cache() =3D default; }; =20 + +/* Reconstruct T bit in program status register from LR value. */ + +static inline ULONGEST +reconstruct_t_bit(struct gdbarch *gdbarch, CORE_ADDR lr, ULONGEST psr) +{ + ULONGEST t_bit =3D arm_psr_thumb_bit (gdbarch); + if (IS_THUMB_ADDR (lr)) + psr |=3D t_bit; + else + psr &=3D ~t_bit; + + return psr; +} + /* Initialize stack pointers, and flag the active one. */ =20 static inline void @@ -2348,15 +2363,10 @@ arm_prologue_prev_register (struct frame_info *this= _frame, but the processor status is likely valid. */ if (prev_regnum =3D=3D ARM_PS_REGNUM) { - CORE_ADDR lr, cpsr; - ULONGEST t_bit =3D arm_psr_thumb_bit (gdbarch); + ULONGEST cpsr =3D get_frame_register_unsigned (this_frame, prev_regn= um); + CORE_ADDR lr =3D frame_unwind_register_unsigned (this_frame, ARM_LR_= REGNUM); =20 - cpsr =3D get_frame_register_unsigned (this_frame, prev_regnum); - lr =3D frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); - if (IS_THUMB_ADDR (lr)) - cpsr |=3D t_bit; - else - cpsr &=3D ~t_bit; + cpsr =3D reconstruct_t_bit (gdbarch, lr, cpsr); return frame_unwind_got_constant (this_frame, prev_regnum, cpsr); } =20 @@ -3369,24 +3379,46 @@ arm_m_exception_cache (struct frame_info *this_fram= e) return cache; } =20 - fnc_return =3D ((lr & 0xfffffffe) =3D=3D 0xfefffffe); + fnc_return =3D (((lr >> 24) & 0xff) =3D=3D 0xfe); if (tdep->have_sec_ext && fnc_return) { - int actual_sp; + if (!arm_unwind_secure_frames) + { + warning (_("Non-secure to secure stack unwinding disabled.")); =20 - arm_cache_switch_prev_sp (cache, tdep, tdep->m_profile_msp_ns_regnum= ); - arm_cache_set_active_sp_value (cache, tdep, sp); - if (lr & 1) - actual_sp =3D tdep->m_profile_msp_s_regnum; + /* Terminate any further stack unwinding by referring to self. */ + arm_cache_set_active_sp_value (cache, tdep, sp); + return cache; + } + + xpsr =3D get_frame_register_unsigned (this_frame, ARM_PS_REGNUM); + if ((xpsr & 0xff) !=3D 0) + /* Handler mode: This is the mode that exceptions are handled in. */ + arm_cache_switch_prev_sp (cache, tdep, tdep->m_profile_msp_s_regnum); else - actual_sp =3D tdep->m_profile_msp_ns_regnum; + /* Thread mode: This is the normal mode that programs run in. */ + arm_cache_switch_prev_sp (cache, tdep, tdep->m_profile_psp_s_regnum); =20 - arm_cache_switch_prev_sp (cache, tdep, actual_sp); - sp =3D get_frame_register_unsigned (this_frame, actual_sp); + unwound_sp =3D arm_cache_get_prev_sp_value (cache, tdep); =20 - cache->saved_regs[ARM_LR_REGNUM].set_addr (sp); + /* Stack layout for a function call from Secure to Non-Secure state + (ARMv8-M section B3.16): =20 - arm_cache_set_active_sp_value (cache, tdep, sp + 8); + SP Offset + + +-------------------+ + 0x08 | | + +-------------------+ <-- Original SP + 0x04 | Partial xPSR | + +-------------------+ + 0x00 | Return Address | + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+ <-- Ne= w SP */ + + cache->saved_regs[ARM_PC_REGNUM].set_addr (unwound_sp + 0x00); + cache->saved_regs[ARM_LR_REGNUM].set_addr (unwound_sp + 0x00); + cache->saved_regs[ARM_PS_REGNUM].set_addr (unwound_sp + 0x04); + + arm_cache_set_active_sp_value (cache, tdep, unwound_sp + 0x08); =20 return cache; } @@ -3447,11 +3479,6 @@ arm_m_exception_cache (struct frame_info *this_frame) arm_cache_switch_prev_sp (cache, tdep, tdep->m_profile_msp_regnum); } } - else - { - /* Main stack used, use MSP as SP. */ - arm_cache_switch_prev_sp (cache, tdep, tdep->m_profile_msp_regnum); - } =20 /* Fetch the SP to use for this frame. */ unwound_sp =3D arm_cache_get_prev_sp_value (cache, tdep); @@ -3647,6 +3674,17 @@ arm_m_exception_prev_register (struct frame_info *th= is_frame, return frame_unwind_got_constant (this_frame, prev_regnum, arm_cache_get_prev_sp_value (cache, tdep)); =20 + /* If we are asked to unwind the PC, strip the saved T bit. */ + if (prev_regnum =3D=3D ARM_PC_REGNUM) + { + struct value *value =3D trad_frame_get_prev_register (this_frame, + cache->saved_regs, + prev_regnum); + CORE_ADDR pc =3D value_as_address (value); + return frame_unwind_got_constant (this_frame, prev_regnum, + UNMAKE_THUMB_ADDR (pc)); + } + /* The value might be one of the alternative SP, if so, use the value already constructed. */ if (arm_cache_is_sp_register (cache, tdep, prev_regnum)) @@ -3655,6 +3693,25 @@ arm_m_exception_prev_register (struct frame_info *th= is_frame, return frame_unwind_got_constant (this_frame, prev_regnum, sp_value); } =20 + /* If we are asked to unwind the xPSR, set T bit if PC is in thumb mode. + LR register is unreliable as it contains FNC_RETURN or EXC_RETURN + pattern. */ + if (prev_regnum =3D=3D ARM_PS_REGNUM) + { + struct gdbarch *gdbarch =3D get_frame_arch (this_frame); + struct value *value =3D trad_frame_get_prev_register (this_frame, + cache->saved_regs, + ARM_PC_REGNUM); + CORE_ADDR pc =3D value_as_address (value); + value =3D trad_frame_get_prev_register (this_frame, cache->saved_reg= s, + ARM_PS_REGNUM); + ULONGEST xpsr =3D value_as_long (value); + + /* Reconstruct the T bit; see arm_prologue_prev_register for details= . */ + xpsr =3D reconstruct_t_bit (gdbarch, pc, xpsr); + return frame_unwind_got_constant (this_frame, ARM_PS_REGNUM, xpsr); + } + return trad_frame_get_prev_register (this_frame, cache->saved_regs, prev_regnum); } @@ -3717,8 +3774,8 @@ arm_dwarf2_prev_register (struct frame_info *this_fra= me, void **this_cache, { struct gdbarch * gdbarch =3D get_frame_arch (this_frame); arm_gdbarch_tdep *tdep =3D (arm_gdbarch_tdep *) gdbarch_tdep (gdbarch); - CORE_ADDR lr, cpsr; - ULONGEST t_bit =3D arm_psr_thumb_bit (gdbarch); + CORE_ADDR lr; + ULONGEST cpsr; =20 switch (regnum) { @@ -3747,10 +3804,7 @@ arm_dwarf2_prev_register (struct frame_info *this_fr= ame, void **this_cache, /* Reconstruct the T bit; see arm_prologue_prev_register for details= . */ cpsr =3D get_frame_register_unsigned (this_frame, regnum); lr =3D frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); - if (IS_THUMB_ADDR (lr)) - cpsr |=3D t_bit; - else - cpsr &=3D ~t_bit; + cpsr =3D reconstruct_t_bit (gdbarch, lr, cpsr); return frame_unwind_got_constant (this_frame, regnum, cpsr); =20 default: