From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1844) id BB3C6385AE6D; Wed, 29 Jun 2022 12:03:36 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org BB3C6385AE6D Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Yvan Roux To: gdb-cvs@sourceware.org Subject: [binutils-gdb] gdb/arm: Only stack S16..S31 when FPU registers are secure X-Act-Checkin: binutils-gdb X-Git-Author: Yvan Roux X-Git-Refname: refs/heads/master X-Git-Oldrev: 6837a663c55602490ed095e5891e0c4deff4b9db X-Git-Newrev: 69b46464badb01340a88d0ee57cdef0b7fdf545e Message-Id: <20220629120336.BB3C6385AE6D@sourceware.org> Date: Wed, 29 Jun 2022 12:03:36 +0000 (GMT) X-BeenThere: gdb-cvs@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 29 Jun 2022 12:03:36 -0000 https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D69b46464badb= 01340a88d0ee57cdef0b7fdf545e commit 69b46464badb01340a88d0ee57cdef0b7fdf545e Author: Yvan Roux Date: Wed Jun 29 14:01:45 2022 +0200 gdb/arm: Only stack S16..S31 when FPU registers are secure =20 The FPCCR.TS bit is used to identify if FPU registers are considered non-secure or secure. If they are secure, then callee saved registers (S16 to S31) are stacked on exception entry or otherwise skipped. =20 Signed-off-by: Torbj=C3=B6rn SVENSSON Signed-off-by: Yvan Roux Diff: --- gdb/arch/arm.h | 9 +++++++++ gdb/arm-tdep.c | 9 ++++++++- 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/gdb/arch/arm.h b/gdb/arch/arm.h index 4ad329f6f1f..36757493406 100644 --- a/gdb/arch/arm.h +++ b/gdb/arch/arm.h @@ -109,6 +109,15 @@ enum arm_m_profile_type { ARM_M_TYPE_INVALID }; =20 +/* System control registers accessible through an addresses. */ +enum system_register_address : CORE_ADDR +{ + /* M-profile Floating-Point Context Control Register address, defined in + ARMv7-M (Section B3.2.2) and ARMv8-M (Section D1.2.99) reference + manuals. */ + FPCCR =3D 0xe000ef34 +}; + /* Instruction condition field values. */ #define INST_EQ 0x0 #define INST_NE 0x1 diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index e36bde9b3da..3a1b52c2380 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -3573,6 +3573,13 @@ arm_m_exception_cache (struct frame_info *this_frame) { int i; int fpu_regs_stack_offset; + ULONGEST fpccr; + + /* Read FPCCR register. */ + gdb_assert (safe_read_memory_unsigned_integer (FPCCR, + ARM_INT_REGISTER_SIZE, + byte_order, &fpccr)); + bool fpccr_ts =3D bit (fpccr,26); =20 /* This code does not take into account the lazy stacking, see "Lazy context save of FP state", in B1.5.7, also ARM AN298, supported @@ -3592,7 +3599,7 @@ arm_m_exception_cache (struct frame_info *this_frame) cache->saved_regs[ARM_FPSCR_REGNUM].set_addr (unwound_sp + sp_r0_off= set + 0x60); fpu_regs_stack_offset +=3D 4; =20 - if (tdep->have_sec_ext && !default_callee_register_stacking) + if (tdep->have_sec_ext && !default_callee_register_stacking && fpccr= _ts) { /* Handle floating-point callee saved registers. */ fpu_regs_stack_offset =3D unwound_sp + sp_r0_offset + 0x68;