From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1844) id B3B9C3875A34; Mon, 25 Jul 2022 13:31:30 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B3B9C3875A34 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Yvan Roux To: gdb-cvs@sourceware.org Subject: [binutils-gdb] gdb/arm: Sync sp with other *sp registers X-Act-Checkin: binutils-gdb X-Git-Author: Yvan Roux X-Git-Refname: refs/heads/master X-Git-Oldrev: 42e11f363c5e2c5e750e9b9b67fbae511d83974d X-Git-Newrev: a6e4a48c02acf29d6bec2ff63fc909b57cf4bc78 Message-Id: <20220725133130.B3B9C3875A34@sourceware.org> Date: Mon, 25 Jul 2022 13:31:30 +0000 (GMT) X-BeenThere: gdb-cvs@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 25 Jul 2022 13:31:30 -0000 https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3Da6e4a48c02ac= f29d6bec2ff63fc909b57cf4bc78 commit a6e4a48c02acf29d6bec2ff63fc909b57cf4bc78 Author: Yvan Roux Date: Mon Jul 25 15:26:24 2022 +0200 gdb/arm: Sync sp with other *sp registers =20 For Arm Cortex-M33 with security extensions, there are 4 different stack pointers (msp_s, msp_ns, psp_s, psp_ns), without security extensions and for other Cortex-M targets, there are 2 different stack pointers (msp and psp). =20 With this patch, sp will always be in sync with one of the real stack pointers on Arm targets that contain more than one stack pointer. =20 Signed-off-by: Torbj=C3=B6rn SVENSSON Signed-off-by: Yvan Roux Diff: --- gdb/arm-tdep.c | 80 ++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 80 insertions(+) diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 7d0944f9e3f..7d8d040f8f1 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -3815,6 +3815,78 @@ arm_dwarf2_prev_register (struct frame_info *this_fr= ame, void **this_cache, cpsr =3D reconstruct_t_bit (gdbarch, lr, cpsr); return frame_unwind_got_constant (this_frame, regnum, cpsr); } + else if (arm_is_alternative_sp_register (tdep, regnum)) + { + /* Handle the alternative SP registers on Cortex-M. */ + bool override_with_sp_value =3D false; + CORE_ADDR val; + + if (tdep->have_sec_ext) + { + CORE_ADDR sp + =3D get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); + CORE_ADDR msp_s + =3D get_frame_register_unsigned (this_frame, + tdep->m_profile_msp_s_regnum); + CORE_ADDR msp_ns + =3D get_frame_register_unsigned (this_frame, + tdep->m_profile_msp_ns_regnum); + CORE_ADDR psp_s + =3D get_frame_register_unsigned (this_frame, + tdep->m_profile_psp_s_regnum); + CORE_ADDR psp_ns + =3D get_frame_register_unsigned (this_frame, + tdep->m_profile_psp_ns_regnum); + + bool is_msp =3D (regnum =3D=3D tdep->m_profile_msp_regnum) + && (msp_s =3D=3D sp || msp_ns =3D=3D sp); + bool is_msp_s =3D (regnum =3D=3D tdep->m_profile_msp_s_regnum) + && (msp_s =3D=3D sp); + bool is_msp_ns =3D (regnum =3D=3D tdep->m_profile_msp_ns_regnum) + && (msp_ns =3D=3D sp); + bool is_psp =3D (regnum =3D=3D tdep->m_profile_psp_regnum) + && (psp_s =3D=3D sp || psp_ns =3D=3D sp); + bool is_psp_s =3D (regnum =3D=3D tdep->m_profile_psp_s_regnum) + && (psp_s =3D=3D sp); + bool is_psp_ns =3D (regnum =3D=3D tdep->m_profile_psp_ns_regnum) + && (psp_ns =3D=3D sp); + + override_with_sp_value =3D is_msp || is_msp_s || is_msp_ns + || is_psp || is_psp_s || is_psp_ns; + + } + else if (tdep->is_m) + { + CORE_ADDR sp + =3D get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); + CORE_ADDR msp + =3D get_frame_register_unsigned (this_frame, + tdep->m_profile_msp_regnum); + CORE_ADDR psp + =3D get_frame_register_unsigned (this_frame, + tdep->m_profile_psp_regnum); + + bool is_msp =3D (regnum =3D=3D tdep->m_profile_msp_regnum) && (sp =3D= =3D msp); + bool is_psp =3D (regnum =3D=3D tdep->m_profile_psp_regnum) && (sp =3D= =3D psp); + + override_with_sp_value =3D is_msp || is_psp; + } + + if (override_with_sp_value) + { + /* Use value of SP from previous frame. */ + struct frame_info *prev_frame =3D get_prev_frame (this_frame); + if (prev_frame) + val =3D get_frame_register_unsigned (prev_frame, ARM_SP_REGNUM); + else + val =3D get_frame_base (this_frame); + } + else + /* Use value for the register from previous frame. */ + val =3D get_frame_register_unsigned (this_frame, regnum); + + return frame_unwind_got_constant (this_frame, regnum, val); + } =20 internal_error (__FILE__, __LINE__, _("Unexpected register %d"), regnum); @@ -4934,6 +5006,8 @@ arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, i= nt regnum, struct dwarf2_frame_state_reg *reg, struct frame_info *this_frame) { + arm_gdbarch_tdep *tdep =3D gdbarch_tdep (gdbarch); + if (is_pacbti_pseudo (gdbarch, regnum)) { /* Initialize RA_AUTH_CODE to zero. */ @@ -4950,6 +5024,12 @@ arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, = int regnum, } else if (regnum =3D=3D ARM_SP_REGNUM) reg->how =3D DWARF2_FRAME_REG_CFA; + else if (arm_is_alternative_sp_register (tdep, regnum)) + { + /* Handle the alternative SP registers on Cortex-M. */ + reg->how =3D DWARF2_FRAME_REG_FN; + reg->loc.fn =3D arm_dwarf2_prev_register; + } } =20 /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand