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From: Andrew Burgess <aburgess@sourceware.org>
To: gdb-cvs@sourceware.org
Subject: [binutils-gdb] gdb/riscv: implement cannot_store_register gdbarch method
Date: Wed, 10 Aug 2022 15:14:02 +0000 (GMT)	[thread overview]
Message-ID: <20220810151402.881133858D1E@sourceware.org> (raw)

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=f8053219836de69ceb8ff0e3e311b0585b1187b3

commit f8053219836de69ceb8ff0e3e311b0585b1187b3
Author: mga-sc <mark.goncharov@syntacore.com>
Date:   Mon Aug 8 16:01:47 2022 +0300

    gdb/riscv: implement cannot_store_register gdbarch method
    
    The x0 (zero) register is read-only on RISC-V.  Implement the
    cannot_store_register gdbarch method to tell GDB this.
    
    Without this method GDB will try to write to x0, and relies on the
    target to ignore such writes.  If you are using a target that
    complains (or throws an error) when writing to x0, this change will
    prevent this from happening.
    
    The gdb.arch/riscv-reg-aliases.exp test exercises writing to x0, and
    will show the errors when using a suitable target.

Diff:
---
 gdb/riscv-tdep.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index 2d41be96b20..b9a51f7ae6a 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -933,6 +933,15 @@ riscv_register_name (struct gdbarch *gdbarch, int regnum)
   return name;
 }
 
+/* Implement the cannot_store_register gdbarch method.  The zero register
+   (x0) is read-only on RISC-V.  */
+
+static int
+riscv_cannot_store_register (struct gdbarch *gdbarch, int regnum)
+{
+  return regnum == RISCV_ZERO_REGNUM;
+}
+
 /* Construct a type for 64-bit FP registers.  */
 
 static struct type *
@@ -3822,6 +3831,9 @@ riscv_gdbarch_init (struct gdbarch_info info,
      registers, no matter what the target description called them.  */
   set_gdbarch_register_name (gdbarch, riscv_register_name);
 
+  /* Tell GDB which RISC-V registers are read-only. */
+  set_gdbarch_cannot_store_register (gdbarch, riscv_cannot_store_register);
+
   /* Override the register group callback setup by the target description
      mechanism.  This allows us to force registers into the groups we
      want, ignoring what the target tells us.  */


                 reply	other threads:[~2022-08-10 15:14 UTC|newest]

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