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From: Andrew Burgess <aburgess@sourceware.org> To: gdb-cvs@sourceware.org Subject: [binutils-gdb] sim/riscv: Complete tidying up with SBREAK Date: Mon, 5 Sep 2022 08:42:43 +0000 (GMT) [thread overview] Message-ID: <20220905084243.93FFD3858D32@sourceware.org> (raw) https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=b9593cb70533f28d276ab8d582dfe622aa4591d5 commit b9593cb70533f28d276ab8d582dfe622aa4591d5 Author: Tsukasa OI <research_trasio@irq.a4lg.com> Date: Sun Sep 4 07:45:06 2022 +0000 sim/riscv: Complete tidying up with SBREAK This commit removes SBREAK-related references on the simulator as it's renamed to EBREAK in 2016 (the RISC-V ISA, version 2.1). sim/ChangeLog: * riscv/sim-main.c (execute_i): Use "ebreak" instead of "sbreak". Diff: --- sim/riscv/sim-main.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c index 62f475671c9..30d2f1e1c9a 100644 --- a/sim/riscv/sim-main.c +++ b/sim/riscv/sim-main.c @@ -583,9 +583,9 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op) case MATCH_FENCE_I: TRACE_INSN (cpu, "fence.i;"); break; - case MATCH_SBREAK: - TRACE_INSN (cpu, "sbreak;"); - /* GDB expects us to step over SBREAK. */ + case MATCH_EBREAK: + TRACE_INSN (cpu, "ebreak;"); + /* GDB expects us to step over EBREAK. */ sim_engine_halt (sd, cpu, NULL, cpu->pc + 4, sim_stopped, SIM_SIGTRAP); break; case MATCH_ECALL:
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