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From: Jiangshuai Li <jiangshuaili@sourceware.org>
To: gdb-cvs@sourceware.org
Subject: [binutils-gdb] gdb/csky add cskyv2-linux.xml for cskyv2-linux.c
X-Act-Checkin: binutils-gdb
X-Git-Author: Jiangshuai Li <jiangshuai_li@linux.alibaba.com>
X-Git-Refname: refs/heads/master
X-Git-Oldrev: 22997c77b024c3ee4e6618b44c44dc0f0179add8
X-Git-Newrev: 8e037eae6823caf5b9cb5b4feb3de838abb25956
Message-Id: <20220923025157.13FEE3858422@sourceware.org>
Date: Fri, 23 Sep 2022 02:51:57 +0000 (GMT)
List-Id: <gdb-cvs.sourceware.org>

https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D8e037eae6823=
caf5b9cb5b4feb3de838abb25956

commit 8e037eae6823caf5b9cb5b4feb3de838abb25956
Author: Jiangshuai Li <jiangshuai_li@linux.alibaba.com>
Date:   Fri Sep 23 10:46:44 2022 +0800

    gdb/csky add cskyv2-linux.xml for cskyv2-linux.c
   =20
    Add cskyv2-linux.xml for re-generating cskyv2-linux.c if needed.
    Also update cskyv2-linux.c.

Diff:
---
 gdb/arch/csky.c               |   2 +-
 gdb/features/Makefile         |   1 +
 gdb/features/cskyv2-linux.c   | 162 +++++++++++++++++++++-----------------=
----
 gdb/features/cskyv2-linux.xml | 102 ++++++++++++++++++++++++++
 4 files changed, 185 insertions(+), 82 deletions(-)

diff --git a/gdb/arch/csky.c b/gdb/arch/csky.c
index 887796753c6..3a97cff4919 100644
--- a/gdb/arch/csky.c
+++ b/gdb/arch/csky.c
@@ -32,7 +32,7 @@ csky_create_target_description (void)
   set_tdesc_architecture (tdesc.get (), arch_name.c_str ());
 #endif
=20
-  create_feature_cskyv2_linux (tdesc.get ());
+  create_feature_cskyv2_linux (tdesc.get (), 0);
=20
   return tdesc;
 }
diff --git a/gdb/features/Makefile b/gdb/features/Makefile
index 061cb2ed032..4bc85962dfe 100644
--- a/gdb/features/Makefile
+++ b/gdb/features/Makefile
@@ -213,6 +213,7 @@ FEATURE_XMLFILES =3D aarch64-core.xml \
 	arm/arm-vfpv2.xml \
 	arm/arm-vfpv3.xml \
 	arm/xscale-iwmmxt.xml \
+	cskyv2-linux.xml \
 	i386/32bit-core.xml \
 	i386/32bit-sse.xml \
 	i386/32bit-linux.xml \
diff --git a/gdb/features/cskyv2-linux.c b/gdb/features/cskyv2-linux.c
index e49b68c4b8d..dbf3d058bd2 100644
--- a/gdb/features/cskyv2-linux.c
+++ b/gdb/features/cskyv2-linux.c
@@ -1,67 +1,14 @@
 /* THIS FILE IS GENERATED.  -*- buffer-read-only: t -*- vi:set ro:
-   Original: cskyv2-linux.xml */
+  Original: cskyv2-linux.xml */
=20
 #include "gdbsupport/tdesc.h"
=20
-static void
-create_feature_cskyv2_linux (struct target_desc *result)
+static int
+create_feature_cskyv2_linux (struct target_desc *result, long regnum)
 {
   struct tdesc_feature *feature;
=20
   feature =3D tdesc_create_feature (result, "org.gnu.gdb.csky.abiv2");
-  tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r5", 5, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r6", 6, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r7", 7, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r8", 8, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r9", 9, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r10", 10, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r11", 11, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r12", 12, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r13", 13, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r14", 14, 1, NULL, 32, "data_ptr");
-  tdesc_create_reg (feature, "r15", 15, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r16", 16, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r17", 17, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r18", 18, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r19", 19, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r20", 20, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r21", 21, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r22", 22, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r23", 23, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r24", 24, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r25", 25, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r26", 26, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r27", 27, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r28", 28, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "int");
-
-  tdesc_create_reg (feature, "lo", 36, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "hi", 37, 1, NULL, 32, "int");
-
-  tdesc_create_reg (feature, "fr0", 40, 1, NULL, 64, "ieee_double");
-  tdesc_create_reg (feature, "fr1", 41, 1, NULL, 64, "ieee_double");
-  tdesc_create_reg (feature, "fr2", 42, 1, NULL, 64, "ieee_double");
-  tdesc_create_reg (feature, "fr3", 43, 1, NULL, 64, "ieee_double");
-  tdesc_create_reg (feature, "fr4", 44, 1, NULL, 64, "ieee_double");
-  tdesc_create_reg (feature, "fr5", 45, 1, NULL, 64, "ieee_double");
-  tdesc_create_reg (feature, "fr6", 46, 1, NULL, 64, "ieee_double");
-  tdesc_create_reg (feature, "fr7", 47, 1, NULL, 64, "ieee_double");
-  tdesc_create_reg (feature, "fr8", 48, 1, NULL, 64, "ieee_double");
-  tdesc_create_reg (feature, "fr9", 49, 1, NULL, 64, "ieee_double");
-  tdesc_create_reg (feature, "fr10", 50, 1, NULL, 64, "ieee_double");
-  tdesc_create_reg (feature, "fr11", 51, 1, NULL, 64, "ieee_double");
-  tdesc_create_reg (feature, "fr12", 52, 1, NULL, 64, "ieee_double");
-  tdesc_create_reg (feature, "fr13", 53, 1, NULL, 64, "ieee_double");
-  tdesc_create_reg (feature, "fr14", 54, 1, NULL, 64, "ieee_double");
-  tdesc_create_reg (feature, "fr15", 55, 1, NULL, 64, "ieee_double");
-
   tdesc_type *element_type;
   element_type =3D tdesc_named_type (feature, "ieee_single");
   tdesc_create_vector (feature, "v4f", element_type, 4);
@@ -99,29 +46,82 @@ create_feature_cskyv2_linux (struct target_desc *result)
   field_type =3D tdesc_named_type (feature, "uint128");
   tdesc_add_field (type_with_fields, "uint128", field_type);
=20
-
-  tdesc_create_reg (feature, "vr0", 56, 1, NULL, 128, "vec128");
-  tdesc_create_reg (feature, "vr1", 57, 1, NULL, 128, "vec128");
-  tdesc_create_reg (feature, "vr2", 58, 1, NULL, 128, "vec128");
-  tdesc_create_reg (feature, "vr3", 59, 1, NULL, 128, "vec128");
-  tdesc_create_reg (feature, "vr4", 60, 1, NULL, 128, "vec128");
-  tdesc_create_reg (feature, "vr5", 61, 1, NULL, 128, "vec128");
-  tdesc_create_reg (feature, "vr6", 62, 1, NULL, 128, "vec128");
-  tdesc_create_reg (feature, "vr7", 63, 1, NULL, 128, "vec128");
-  tdesc_create_reg (feature, "vr8", 64, 1, NULL, 128, "vec128");
-  tdesc_create_reg (feature, "vr9", 65, 1, NULL, 128, "vec128");
-  tdesc_create_reg (feature, "vr10", 66, 1, NULL, 128, "vec128");
-  tdesc_create_reg (feature, "vr11", 67, 1, NULL, 128, "vec128");
-  tdesc_create_reg (feature, "vr12", 68, 1, NULL, 128, "vec128");
-  tdesc_create_reg (feature, "vr13", 69, 1, NULL, 128, "vec128");
-  tdesc_create_reg (feature, "vr14", 70, 1, NULL, 128, "vec128");
-  tdesc_create_reg (feature, "vr15", 71, 1, NULL, 128, "vec128");
-
-  tdesc_create_reg (feature, "pc", 72, 1, NULL, 32, "code_ptr");
-  tdesc_create_reg (feature, "psr", 89, 1, NULL, 32, "int");
-
-  tdesc_create_reg (feature, "fid", 121, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "fcr", 122, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "fesr", 123, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "usp", 127, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r0", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r1", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r2", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r3", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r4", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r5", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r6", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r7", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r8", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r9", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r10", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r11", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r12", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r13", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r14", regnum++, 1, NULL, 32, "data_ptr");
+  tdesc_create_reg (feature, "r15", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r16", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r17", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r18", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r19", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r20", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r21", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r22", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r23", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r24", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r25", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r26", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r27", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r28", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r29", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r30", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r31", regnum++, 1, NULL, 32, "int");
+  regnum =3D 36;
+  tdesc_create_reg (feature, "hi", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "lo", regnum++, 1, NULL, 32, "int");
+  regnum =3D 40;
+  tdesc_create_reg (feature, "fr0", regnum++, 1, NULL, 64, "ieee_double");
+  tdesc_create_reg (feature, "fr1", regnum++, 1, NULL, 64, "ieee_double");
+  tdesc_create_reg (feature, "fr2", regnum++, 1, NULL, 64, "ieee_double");
+  tdesc_create_reg (feature, "fr3", regnum++, 1, NULL, 64, "ieee_double");
+  tdesc_create_reg (feature, "fr4", regnum++, 1, NULL, 64, "ieee_double");
+  tdesc_create_reg (feature, "fr5", regnum++, 1, NULL, 64, "ieee_double");
+  tdesc_create_reg (feature, "fr6", regnum++, 1, NULL, 64, "ieee_double");
+  tdesc_create_reg (feature, "fr7", regnum++, 1, NULL, 64, "ieee_double");
+  tdesc_create_reg (feature, "fr8", regnum++, 1, NULL, 64, "ieee_double");
+  tdesc_create_reg (feature, "fr9", regnum++, 1, NULL, 64, "ieee_double");
+  tdesc_create_reg (feature, "fr10", regnum++, 1, NULL, 64, "ieee_double");
+  tdesc_create_reg (feature, "fr11", regnum++, 1, NULL, 64, "ieee_double");
+  tdesc_create_reg (feature, "fr12", regnum++, 1, NULL, 64, "ieee_double");
+  tdesc_create_reg (feature, "fr13", regnum++, 1, NULL, 64, "ieee_double");
+  tdesc_create_reg (feature, "fr14", regnum++, 1, NULL, 64, "ieee_double");
+  tdesc_create_reg (feature, "fr15", regnum++, 1, NULL, 64, "ieee_double");
+  tdesc_create_reg (feature, "vr0", regnum++, 1, NULL, 128, "vec128");
+  tdesc_create_reg (feature, "vr1", regnum++, 1, NULL, 128, "vec128");
+  tdesc_create_reg (feature, "vr2", regnum++, 1, NULL, 128, "vec128");
+  tdesc_create_reg (feature, "vr3", regnum++, 1, NULL, 128, "vec128");
+  tdesc_create_reg (feature, "vr4", regnum++, 1, NULL, 128, "vec128");
+  tdesc_create_reg (feature, "vr5", regnum++, 1, NULL, 128, "vec128");
+  tdesc_create_reg (feature, "vr6", regnum++, 1, NULL, 128, "vec128");
+  tdesc_create_reg (feature, "vr7", regnum++, 1, NULL, 128, "vec128");
+  tdesc_create_reg (feature, "vr8", regnum++, 1, NULL, 128, "vec128");
+  tdesc_create_reg (feature, "vr9", regnum++, 1, NULL, 128, "vec128");
+  tdesc_create_reg (feature, "vr10", regnum++, 1, NULL, 128, "vec128");
+  tdesc_create_reg (feature, "vr11", regnum++, 1, NULL, 128, "vec128");
+  tdesc_create_reg (feature, "vr12", regnum++, 1, NULL, 128, "vec128");
+  tdesc_create_reg (feature, "vr13", regnum++, 1, NULL, 128, "vec128");
+  tdesc_create_reg (feature, "vr14", regnum++, 1, NULL, 128, "vec128");
+  tdesc_create_reg (feature, "vr15", regnum++, 1, NULL, 128, "vec128");
+  tdesc_create_reg (feature, "pc", regnum++, 1, NULL, 32, "code_ptr");
+  regnum =3D 89;
+  tdesc_create_reg (feature, "psr", regnum++, 1, NULL, 32, "int");
+  regnum =3D 121;
+  tdesc_create_reg (feature, "fid", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "fcr", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "fesr", regnum++, 1, NULL, 32, "int");
+  regnum =3D 127;
+  tdesc_create_reg (feature, "usp", regnum++, 1, NULL, 32, "int");
+  return regnum;
 }
diff --git a/gdb/features/cskyv2-linux.xml b/gdb/features/cskyv2-linux.xml
new file mode 100644
index 00000000000..d4d45c36fad
--- /dev/null
+++ b/gdb/features/cskyv2-linux.xml
@@ -0,0 +1,102 @@
+<?xml version=3D"1.0"?>
+<!-- Copyright (C) 2022 Free Software Foundation, Inc.
+
+     Copying and distribution of this file, with or without modification,
+     are permitted in any medium without royalty provided the copyright
+     notice and this notice are preserved.  -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name=3D"org.gnu.gdb.csky.abiv2">
+  <reg name=3D"r0"  bitsize=3D"32" regnum=3D"0"/>
+  <reg name=3D"r1"  bitsize=3D"32"/>
+  <reg name=3D"r2"  bitsize=3D"32"/>
+  <reg name=3D"r3"  bitsize=3D"32"/>
+  <reg name=3D"r4"  bitsize=3D"32"/>
+  <reg name=3D"r5"  bitsize=3D"32"/>
+  <reg name=3D"r6"  bitsize=3D"32"/>
+  <reg name=3D"r7"  bitsize=3D"32"/>
+  <reg name=3D"r8"  bitsize=3D"32"/>
+  <reg name=3D"r9"  bitsize=3D"32"/>
+  <reg name=3D"r10" bitsize=3D"32"/>
+  <reg name=3D"r11" bitsize=3D"32"/>
+  <reg name=3D"r12" bitsize=3D"32"/>
+  <reg name=3D"r13" bitsize=3D"32"/>
+  <reg name=3D"r14" bitsize=3D"32" type=3D"data_ptr"/>
+  <reg name=3D"r15" bitsize=3D"32"/>
+  <reg name=3D"r16" bitsize=3D"32"/>
+  <reg name=3D"r17" bitsize=3D"32"/>
+  <reg name=3D"r18" bitsize=3D"32"/>
+  <reg name=3D"r19" bitsize=3D"32"/>
+  <reg name=3D"r20" bitsize=3D"32"/>
+  <reg name=3D"r21" bitsize=3D"32"/>
+  <reg name=3D"r22" bitsize=3D"32"/>
+  <reg name=3D"r23" bitsize=3D"32"/>
+  <reg name=3D"r24" bitsize=3D"32"/>
+  <reg name=3D"r25" bitsize=3D"32"/>
+  <reg name=3D"r26" bitsize=3D"32"/>
+  <reg name=3D"r27" bitsize=3D"32"/>
+  <reg name=3D"r28" bitsize=3D"32"/>
+  <reg name=3D"r29" bitsize=3D"32"/>
+  <reg name=3D"r30" bitsize=3D"32"/>
+  <reg name=3D"r31" bitsize=3D"32"/>
+
+  <reg name=3D"hi" bitsize=3D"32" regnum=3D"36"/>
+  <reg name=3D"lo" bitsize=3D"32"/>
+
+  <reg name=3D"fr0"  bitsize=3D"64" type=3D"ieee_double" regnum=3D"40"/>
+  <reg name=3D"fr1"  bitsize=3D"64" type=3D"ieee_double"/>
+  <reg name=3D"fr2"  bitsize=3D"64" type=3D"ieee_double"/>
+  <reg name=3D"fr3"  bitsize=3D"64" type=3D"ieee_double"/>
+  <reg name=3D"fr4"  bitsize=3D"64" type=3D"ieee_double"/>
+  <reg name=3D"fr5"  bitsize=3D"64" type=3D"ieee_double"/>
+  <reg name=3D"fr6"  bitsize=3D"64" type=3D"ieee_double"/>
+  <reg name=3D"fr7"  bitsize=3D"64" type=3D"ieee_double"/>
+  <reg name=3D"fr8"  bitsize=3D"64" type=3D"ieee_double"/>
+  <reg name=3D"fr9"  bitsize=3D"64" type=3D"ieee_double"/>
+  <reg name=3D"fr10" bitsize=3D"64" type=3D"ieee_double"/>
+  <reg name=3D"fr11" bitsize=3D"64" type=3D"ieee_double"/>
+  <reg name=3D"fr12" bitsize=3D"64" type=3D"ieee_double"/>
+  <reg name=3D"fr13" bitsize=3D"64" type=3D"ieee_double"/>
+  <reg name=3D"fr14" bitsize=3D"64" type=3D"ieee_double"/>
+  <reg name=3D"fr15" bitsize=3D"64" type=3D"ieee_double"/>
+
+  <vector id=3D"v4f"   type=3D"ieee_single" count=3D"4"/>
+  <vector id=3D"v2d"   type=3D"ieee_double" count=3D"2"/>
+  <vector id=3D"v16i8" type=3D"int8" count=3D"16"/>
+  <vector id=3D"v8i16" type=3D"int16" count=3D"8"/>
+  <vector id=3D"v4i32" type=3D"int32" count=3D"4"/>
+  <vector id=3D"v2i64" type=3D"int64" count=3D"2"/>
+  <union id=3D"vec128">
+    <field name=3D"v4_float"  type=3D"v4f"/>
+    <field name=3D"v2_double" type=3D"v2d"/>
+    <field name=3D"v16_int8"  type=3D"v16i8"/>
+    <field name=3D"v8_int16"  type=3D"v8i16"/>
+    <field name=3D"v4_int32"  type=3D"v4i32"/>
+    <field name=3D"v2_int64"  type=3D"v2i64"/>
+    <field name=3D"uint128"   type=3D"uint128"/>
+  </union>
+  <reg name=3D"vr0"  bitsize=3D"128" type=3D"vec128" regnum=3D"56"/>
+  <reg name=3D"vr1"  bitsize=3D"128" type=3D"vec128"/>
+  <reg name=3D"vr2"  bitsize=3D"128" type=3D"vec128"/>
+  <reg name=3D"vr3"  bitsize=3D"128" type=3D"vec128"/>
+  <reg name=3D"vr4"  bitsize=3D"128" type=3D"vec128"/>
+  <reg name=3D"vr5"  bitsize=3D"128" type=3D"vec128"/>
+  <reg name=3D"vr6"  bitsize=3D"128" type=3D"vec128"/>
+  <reg name=3D"vr7"  bitsize=3D"128" type=3D"vec128"/>
+  <reg name=3D"vr8"  bitsize=3D"128" type=3D"vec128"/>
+  <reg name=3D"vr9"  bitsize=3D"128" type=3D"vec128"/>
+  <reg name=3D"vr10" bitsize=3D"128" type=3D"vec128"/>
+  <reg name=3D"vr11" bitsize=3D"128" type=3D"vec128"/>
+  <reg name=3D"vr12" bitsize=3D"128" type=3D"vec128"/>
+  <reg name=3D"vr13" bitsize=3D"128" type=3D"vec128"/>
+  <reg name=3D"vr14" bitsize=3D"128" type=3D"vec128"/>
+  <reg name=3D"vr15" bitsize=3D"128" type=3D"vec128"/>
+
+  <reg name=3D"pc"   bitsize=3D"32" type=3D"code_ptr" regnum=3D"72"/>
+  <reg name=3D"psr"  bitsize=3D"32" regnum=3D"89"/>
+
+  <reg name=3D"fid"  bitsize=3D"32" regnum=3D"121"/>
+  <reg name=3D"fcr"  bitsize=3D"32"/>
+  <reg name=3D"fesr" bitsize=3D"32"/>
+  <reg name=3D"usp"  bitsize=3D"32" regnum=3D"127"/>
+</feature>