From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1585) id AB5F8385380D; Tue, 4 Oct 2022 08:15:09 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org AB5F8385380D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1664871309; bh=aJFomnn5thNmzLQCl4IrONQT1BX5zxdGol+g8TioHbQ=; h=From:To:Subject:Date:From; b=dm32D9ypOlPMZDSASRsOnWSRkyfE8d7ZwRADGKzDGre7Fz+r1NH7TMG5jeGndQvY0 G7TNn38W+416RTHvDf0h8TUalMecEtZKRr5wrj8jJ2wWm23pj4W0UfINYI6f8VRCNk tL/Vq3chac5TmagIObvqCYIIKoy3+Ed1V5idRdJE= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Luis Machado To: gdb-cvs@sourceware.org Subject: [binutils-gdb] [AArch64] Update FPSR/FPCR fields for FPU and SVE X-Act-Checkin: binutils-gdb X-Git-Author: Luis Machado X-Git-Refname: refs/heads/master X-Git-Oldrev: 758dd750bc6d752b290aefdd62048ca2ea5899d4 X-Git-Newrev: f4b581f2d1ac69c27a06a328e11763b44544aadb Message-Id: <20221004081509.AB5F8385380D@sourceware.org> Date: Tue, 4 Oct 2022 08:15:09 +0000 (GMT) List-Id: https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3Df4b581f2d1ac= 69c27a06a328e11763b44544aadb commit f4b581f2d1ac69c27a06a328e11763b44544aadb Author: Luis Machado Date: Thu Sep 22 12:53:33 2022 +0100 [AArch64] Update FPSR/FPCR fields for FPU and SVE =20 I noticed some missing flags/fields from FPSR and FPCR registers in both the FPU and SVE target descriptions. =20 This patch adds those and makes the SVE versions of FPSR and FPCR use the proper flags/bitfields types. Diff: --- gdb/features/aarch64-fpu.c | 3 +++ gdb/features/aarch64-fpu.xml | 14 ++++++++++++++ gdb/features/aarch64-sve.c | 38 ++++++++++++++++++++++++++++++++++++-- 3 files changed, 53 insertions(+), 2 deletions(-) diff --git a/gdb/features/aarch64-fpu.c b/gdb/features/aarch64-fpu.c index a80b7d4c1b8..27e75524cfe 100644 --- a/gdb/features/aarch64-fpu.c +++ b/gdb/features/aarch64-fpu.c @@ -126,8 +126,11 @@ create_feature_aarch64_fpu (struct target_desc *result= , long regnum) tdesc_add_flag (type_with_fields, 10, "OFE"); tdesc_add_flag (type_with_fields, 11, "UFE"); tdesc_add_flag (type_with_fields, 12, "IXE"); + tdesc_add_flag (type_with_fields, 13, "EBF"); tdesc_add_flag (type_with_fields, 15, "IDE"); + tdesc_add_bitfield (type_with_fields, "Len", 16, 18); tdesc_add_flag (type_with_fields, 19, "FZ16"); + tdesc_add_bitfield (type_with_fields, "Stride", 20, 21); tdesc_add_bitfield (type_with_fields, "RMode", 22, 23); tdesc_add_flag (type_with_fields, 24, "FZ"); tdesc_add_flag (type_with_fields, 25, "DN"); diff --git a/gdb/features/aarch64-fpu.xml b/gdb/features/aarch64-fpu.xml index 4db5c50f250..89bbcc0a855 100644 --- a/gdb/features/aarch64-fpu.xml +++ b/gdb/features/aarch64-fpu.xml @@ -142,11 +142,25 @@ + + + + + + diff --git a/gdb/features/aarch64-sve.c b/gdb/features/aarch64-sve.c index 54182e85090..fe25f812afc 100644 --- a/gdb/features/aarch64-sve.c +++ b/gdb/features/aarch64-sve.c @@ -121,6 +121,40 @@ create_feature_aarch64_sve (struct target_desc *result= , long regnum, field_type =3D tdesc_named_type (feature, "uint8"); tdesc_create_vector (feature, "svep", field_type, 2 * scale); =20 + /* FPSR register type */ + type_with_fields =3D tdesc_create_flags (feature, "fpsr_flags", 4); + tdesc_add_flag (type_with_fields, 0, "IOC"); + tdesc_add_flag (type_with_fields, 1, "DZC"); + tdesc_add_flag (type_with_fields, 2, "OFC"); + tdesc_add_flag (type_with_fields, 3, "UFC"); + tdesc_add_flag (type_with_fields, 4, "IXC"); + tdesc_add_flag (type_with_fields, 7, "IDC"); + tdesc_add_flag (type_with_fields, 27, "QC"); + tdesc_add_flag (type_with_fields, 28, "V"); + tdesc_add_flag (type_with_fields, 29, "C"); + tdesc_add_flag (type_with_fields, 30, "Z"); + tdesc_add_flag (type_with_fields, 31, "N"); + + /* FPCR register type */ + type_with_fields =3D tdesc_create_flags (feature, "fpcr_flags", 4); + tdesc_add_flag (type_with_fields, 0, "FIZ"); + tdesc_add_flag (type_with_fields, 1, "AH"); + tdesc_add_flag (type_with_fields, 2, "NEP"); + tdesc_add_flag (type_with_fields, 8, "IOE"); + tdesc_add_flag (type_with_fields, 9, "DZE"); + tdesc_add_flag (type_with_fields, 10, "OFE"); + tdesc_add_flag (type_with_fields, 11, "UFE"); + tdesc_add_flag (type_with_fields, 12, "IXE"); + tdesc_add_flag (type_with_fields, 13, "EBF"); + tdesc_add_flag (type_with_fields, 15, "IDE"); + tdesc_add_bitfield (type_with_fields, "Len", 16, 18); + tdesc_add_flag (type_with_fields, 19, "FZ16"); + tdesc_add_bitfield (type_with_fields, "Stride", 20, 21); + tdesc_add_bitfield (type_with_fields, "RMode", 22, 23); + tdesc_add_flag (type_with_fields, 24, "FZ"); + tdesc_add_flag (type_with_fields, 25, "DN"); + tdesc_add_flag (type_with_fields, 26, "AHP"); + tdesc_create_reg (feature, "z0", regnum++, 1, NULL, 128 * scale, "svev"); tdesc_create_reg (feature, "z1", regnum++, 1, NULL, 128 * scale, "svev"); tdesc_create_reg (feature, "z2", regnum++, 1, NULL, 128 * scale, "svev"); @@ -153,8 +187,8 @@ create_feature_aarch64_sve (struct target_desc *result,= long regnum, tdesc_create_reg (feature, "z29", regnum++, 1, NULL, 128 * scale, "svev"= ); tdesc_create_reg (feature, "z30", regnum++, 1, NULL, 128 * scale, "svev"= ); tdesc_create_reg (feature, "z31", regnum++, 1, NULL, 128 * scale, "svev"= ); - tdesc_create_reg (feature, "fpsr", regnum++, 1, NULL, 32, "int"); - tdesc_create_reg (feature, "fpcr", regnum++, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "fpsr", regnum++, 1, NULL, 32, "fpsr_flags"); + tdesc_create_reg (feature, "fpcr", regnum++, 1, NULL, 32, "fpcr_flags"); tdesc_create_reg (feature, "p0", regnum++, 1, NULL, 16 * scale, "svep"); tdesc_create_reg (feature, "p1", regnum++, 1, NULL, 16 * scale, "svep"); tdesc_create_reg (feature, "p2", regnum++, 1, NULL, 16 * scale, "svep");