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* [binutils-gdb] gdb/riscv: Partial support for instructions up to 176-bit
@ 2022-10-04 13:23 Tsukasa OI
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From: Tsukasa OI @ 2022-10-04 13:23 UTC (permalink / raw)
To: gdb-cvs
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=436a7b5ef27e6d866a631d6020e904321cbee7e8
commit 436a7b5ef27e6d866a631d6020e904321cbee7e8
Author: Tsukasa OI <research_trasio@irq.a4lg.com>
Date: Tue Oct 4 08:42:35 2022 +0000
gdb/riscv: Partial support for instructions up to 176-bit
Because riscv_insn_length started to support instructions up to 176-bit,
we need to increase buf size to 176-bit in size.
Also, that would break an assumption in riscv_insn::decode so this commit
fixes it, noting that instructions longer than 64-bit are not fully
supported yet.
Diff:
---
gdb/riscv-tdep.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index 47d8f9e601b..63ebed4ff19 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -1770,7 +1770,7 @@ riscv_insn::fetch_instruction (struct gdbarch *gdbarch,
CORE_ADDR addr, int *len)
{
enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch);
- gdb_byte buf[8];
+ gdb_byte buf[RISCV_MAX_INSN_LEN];
int instlen, status;
/* All insns are at least 16 bits. */
@@ -1933,9 +1933,10 @@ riscv_insn::decode (struct gdbarch *gdbarch, CORE_ADDR pc)
}
else
{
- /* This must be a 6 or 8 byte instruction, we don't currently decode
- any of these, so just ignore it. */
- gdb_assert (m_length == 6 || m_length == 8);
+ /* 6 bytes or more. If the instruction is longer than 8 bytes, we don't
+ have full instruction bits in ival. At least, such long instructions
+ are not defined yet, so just ignore it. */
+ gdb_assert (m_length > 0 && m_length % 2 == 0);
m_opcode = OTHER;
}
}
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