From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7896) id 70AFF3858D3C; Tue, 4 Oct 2022 13:23:33 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 70AFF3858D3C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1664889813; bh=2xlr4ytLkBK2uj5Omd+FkBLRlwZ8yTdFipOSeYzlcF0=; h=From:To:Subject:Date:From; b=jxEyS15cFgPLtQotQZyjJ/ckvZ02w/Y8LGWQs9/Htm/pdn7Mn1HIh17prP5OV3vlA y+6RfPYh9m+82IBu/Fur33lhRs/njgW+4V8knep7lcyOysQE42mj019a5IFJfVSDIZ mKArl66Uqf6ZmkvpfQboXevnkYk9TtPwKRjdStwM= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Tsukasa OI To: gdb-cvs@sourceware.org Subject: [binutils-gdb] gdb/riscv: Partial support for instructions up to 176-bit X-Act-Checkin: binutils-gdb X-Git-Author: Tsukasa OI X-Git-Refname: refs/heads/master X-Git-Oldrev: 73e30e726cd778d055a81c1f4c2ccff1c1acdaa9 X-Git-Newrev: 436a7b5ef27e6d866a631d6020e904321cbee7e8 Message-Id: <20221004132333.70AFF3858D3C@sourceware.org> Date: Tue, 4 Oct 2022 13:23:33 +0000 (GMT) List-Id: https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D436a7b5ef27e= 6d866a631d6020e904321cbee7e8 commit 436a7b5ef27e6d866a631d6020e904321cbee7e8 Author: Tsukasa OI Date: Tue Oct 4 08:42:35 2022 +0000 gdb/riscv: Partial support for instructions up to 176-bit =20 Because riscv_insn_length started to support instructions up to 176-bit, we need to increase buf size to 176-bit in size. =20 Also, that would break an assumption in riscv_insn::decode so this comm= it fixes it, noting that instructions longer than 64-bit are not fully supported yet. Diff: --- gdb/riscv-tdep.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c index 47d8f9e601b..63ebed4ff19 100644 --- a/gdb/riscv-tdep.c +++ b/gdb/riscv-tdep.c @@ -1770,7 +1770,7 @@ riscv_insn::fetch_instruction (struct gdbarch *gdbarc= h, CORE_ADDR addr, int *len) { enum bfd_endian byte_order =3D gdbarch_byte_order_for_code (gdbarch); - gdb_byte buf[8]; + gdb_byte buf[RISCV_MAX_INSN_LEN]; int instlen, status; =20 /* All insns are at least 16 bits. */ @@ -1933,9 +1933,10 @@ riscv_insn::decode (struct gdbarch *gdbarch, CORE_AD= DR pc) } else { - /* This must be a 6 or 8 byte instruction, we don't currently decode - any of these, so just ignore it. */ - gdb_assert (m_length =3D=3D 6 || m_length =3D=3D 8); + /* 6 bytes or more. If the instruction is longer than 8 bytes, we d= on't + have full instruction bits in ival. At least, such long instructions + are not defined yet, so just ignore it. */ + gdb_assert (m_length > 0 && m_length % 2 =3D=3D 0); m_opcode =3D OTHER; } }