From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1726) id 66A163858C20; Tue, 11 Oct 2022 11:38:44 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 66A163858C20 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1665488324; bh=K3mQWlfDzS7i56p0Mo6PRi6r7EAj1usmXY/7FFISKR4=; h=From:To:Subject:Date:From; b=BoGk7YP/iEJCy6ZBJSKa4y7kz+9esQXmE0k7RXEBxP/g+gsUdbxLziF7OQ8xBA41c BWzqQL/aOzkI8VX1YbVPZSNN4IUh/O+mGu9GiC1TkqEVATQ3m3nPOVAq3rXW9r28hW lJpMJ6E0hNaLrz/Dxfw4uluqg/T5s3ysCaK3WoX8= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Andrew Burgess To: gdb-cvs@sourceware.org Subject: [binutils-gdb] sim/riscv: fix multiply instructions on simulator X-Act-Checkin: binutils-gdb X-Git-Author: Tsukasa OI X-Git-Refname: refs/heads/master X-Git-Oldrev: 029b1ee8d8805ba8cbc4481c107c8e5f32b48eab X-Git-Newrev: c6422d7be70f14bf7140085f2fc7a592737f5df5 Message-Id: <20221011113844.66A163858C20@sourceware.org> Date: Tue, 11 Oct 2022 11:38:44 +0000 (GMT) List-Id: https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3Dc6422d7be70f= 14bf7140085f2fc7a592737f5df5 commit c6422d7be70f14bf7140085f2fc7a592737f5df5 Author: Tsukasa OI Date: Wed Aug 31 01:46:08 2022 +0000 sim/riscv: fix multiply instructions on simulator =20 After this commit: =20 commit 0938b032daa52129b4215d8e0eedb6c9804f5280 Date: Wed Feb 2 10:06:15 2022 +0900 =20 RISC-V: Add 'Zmmul' extension in assembler. =20 some instructions in the RISC-V simulator stopped working as a new instruction class 'INSN_CLASS_ZMMUL' was added, and some existing instructions were moved into this class. =20 The simulator doesn't currently handle this instruction class, and so the instructions will now cause an illegal instruction trap. =20 This commit adds support for INSN_CLASS_ZMMUL, and adds a test that ensures the affected instructions can be executed by the simulator. =20 Reviewed-by: Palmer Dabbelt Reviewed-by: Andrew Burgess Diff: --- sim/riscv/sim-main.c | 1 + sim/testsuite/riscv/m-ext.s | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+) diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c index 30d2f1e1c9a..0156f791d4b 100644 --- a/sim/riscv/sim-main.c +++ b/sim/riscv/sim-main.c @@ -936,6 +936,7 @@ execute_one (SIM_CPU *cpu, unsigned_word iw, const stru= ct riscv_opcode *op) case INSN_CLASS_I: return execute_i (cpu, iw, op); case INSN_CLASS_M: + case INSN_CLASS_ZMMUL: return execute_m (cpu, iw, op); default: TRACE_INSN (cpu, "UNHANDLED EXTENSION: %d", op->insn_class); diff --git a/sim/testsuite/riscv/m-ext.s b/sim/testsuite/riscv/m-ext.s new file mode 100644 index 00000000000..b80bd140e76 --- /dev/null +++ b/sim/testsuite/riscv/m-ext.s @@ -0,0 +1,18 @@ +# Check that the RV32M instructions run without any faults. +# mach: riscv + +.include "testutils.inc" + + start + + .option arch, +m + mul x0, x1, x2 + mulh x0, x1, x2 + mulhu x0, x1, x2 + mulhsu x0, x1, x2 + div x0, x1, x2 + divu x0, x1, x2 + rem x0, x1, x2 + remu x0, x1, x2 + + pass