From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1726) id 945703857C5B; Mon, 24 Oct 2022 16:23:54 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 945703857C5B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1666628634; bh=YJz34C6KoRWTqHinNvTQtn/g+aSLFIQu8ztOrbUfxzk=; h=From:To:Subject:Date:From; b=fjDUabzn3IUqXjmIj1iOyAuUajuvD1Qym3K948vZzfaxubMqvDp6Cj2BFVjjmE3De 5q8T4CHzpxu3QNLJ3BFpV+jZluRkYzbZWNRo7TZLknU7bObImNG4fUQTiBn4UQ138r sOQFKnMHbvogL1DmHdrtxlNCmqNLL7uI43vKDpQ8= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Andrew Burgess To: gdb-cvs@sourceware.org Subject: [binutils-gdb] sim/h8300: avoid self assignment X-Act-Checkin: binutils-gdb X-Git-Author: Andrew Burgess X-Git-Refname: refs/heads/master X-Git-Oldrev: 36edbb454fc9e720e723923d549b9f5356657a73 X-Git-Newrev: da8b81754bcd9eb2e45cec4997770a591cc61a8f Message-Id: <20221024162354.945703857C5B@sourceware.org> Date: Mon, 24 Oct 2022 16:23:54 +0000 (GMT) List-Id: https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3Dda8b81754bcd= 9eb2e45cec4997770a591cc61a8f commit da8b81754bcd9eb2e45cec4997770a591cc61a8f Author: Andrew Burgess Date: Wed Oct 19 15:19:18 2022 +0100 sim/h8300: avoid self assignment =20 There are two places in the h8300 simulator where we assign a variable to itself. Clang gives a warning for this, which is converted into an error by -Werror. =20 Silence the warning by removing the self assignments. As these assignments were in a complex if/then/else tree, rather than try to adjust all the conditions, I've just replaced the self assignments with a comment and an empty statement. Diff: --- sim/h8300/compile.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sim/h8300/compile.c b/sim/h8300/compile.c index 9be7dd565a9..5f64b4752f0 100644 --- a/sim/h8300/compile.c +++ b/sim/h8300/compile.c @@ -4141,7 +4141,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu) res =3D GET_B_REG (code->src.reg); /* FIXME fetch? */ if (!c && (0 <=3D (res >> 4) && (res >> 4) <=3D 9) &&=20 !h && (0 <=3D (res & 0xf) && (res & 0xf) <=3D 9)) - res =3D res; /* Value added =3D=3D 0. */ + /* Nothing. */; /* Value added =3D=3D 0. */ else if (!c && (0 <=3D (res >> 4) && (res >> 4) <=3D 8) &&=20 !h && (10 <=3D (res & 0xf) && (res & 0xf) <=3D 15)) res =3D res + 0x6; /* Value added =3D=3D 6. */ @@ -4174,7 +4174,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu) res =3D GET_B_REG (code->src.reg); /* FIXME fetch, fetch2... */ if (!c && (0 <=3D (res >> 4) && (res >> 4) <=3D 9) &&=20 !h && (0 <=3D (res & 0xf) && (res & 0xf) <=3D 9)) - res =3D res; /* Value added =3D=3D 0. */ + /* Nothing. */; /* Value added =3D=3D 0. */ else if (!c && (0 <=3D (res >> 4) && (res >> 4) <=3D 8) &&=20 h && (6 <=3D (res & 0xf) && (res & 0xf) <=3D 15)) res =3D res + 0xfa; /* Value added =3D=3D 0xfa. */