From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1585) id 385B3385AC09; Wed, 26 Oct 2022 12:03:52 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 385B3385AC09 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1666785832; bh=6ml6zqgFBCB33LBcek/sf3RqZSrffv2QMqgJ9qGYF8Y=; h=From:To:Subject:Date:From; b=QXcKsMhCcFXK4L4bpnYyUlUJYcg6aibXofho6rCO9ikvW48oFghA0vRNZs88JmiTh D488zicUFOryPVilH0Waj8OFhQw8/lsUz6XeQLRXSsYABmDb1wfImF+8d4u3CH0MKL C50Ox6/hv66+FA9qA50nQNrDg5AS+lNF95So3fl0= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Luis Machado To: gdb-cvs@sourceware.org Subject: [binutils-gdb] gdb/arm: fix IPSR field test in arm_m_exception_cache () X-Act-Checkin: binutils-gdb X-Git-Author: Luis Machado X-Git-Refname: refs/heads/master X-Git-Oldrev: 8b73ee207c9c4b2d692a82a29d1cee2dcfa07394 X-Git-Newrev: b2e9e754e122d97511bbd6b990e38a23dafb6176 Message-Id: <20221026120352.385B3385AC09@sourceware.org> Date: Wed, 26 Oct 2022 12:03:52 +0000 (GMT) List-Id: https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3Db2e9e754e122= d97511bbd6b990e38a23dafb6176 commit b2e9e754e122d97511bbd6b990e38a23dafb6176 Author: Luis Machado Date: Wed Oct 26 13:00:17 2022 +0100 gdb/arm: fix IPSR field test in arm_m_exception_cache () =20 Arm v8-M Architecture Reference Manual, D1.2.141 IPSR, Interrupt Program Status Register reads "Exception, bits [8:0]" =20 9 bits, not 8! It is uncommon but true! =20 Signed-off-by: Tomas Vanek Diff: --- gdb/arm-tdep.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index ae0882f9c4a..247e5522b8e 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -3441,7 +3441,7 @@ arm_m_exception_cache (frame_info_ptr this_frame) } =20 ULONGEST xpsr =3D get_frame_register_unsigned (this_frame, ARM_PS_RE= GNUM); - if ((xpsr & 0xff) !=3D 0) + if ((xpsr & 0x1ff) !=3D 0) /* Handler mode: This is the mode that exceptions are handled in. */ arm_cache_switch_prev_sp (cache, tdep, tdep->m_profile_msp_s_regnum); else