From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <vapier@sourceware.org>
Received: by sourceware.org (Postfix, from userid 1521)
	id C7369385D0E3; Mon, 31 Oct 2022 16:54:53 +0000 (GMT)
DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C7369385D0E3
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org;
	s=default; t=1667235293;
	bh=G/nK97J+vjci0ieoeND5Utl1V9YZW9DPfaSxNq2B4OY=;
	h=From:To:Subject:Date:From;
	b=qbGMGibjbLLntvfH+4WY0FW2XrelPmxG0iaRHM5b0w9Qmuv/DeyjYMZ0uijSikwSv
	 B+wkFrCe/WqRJpW1svbNmH8VD8jDYDkdrws18JaKaRSeAvskXRAhmQY34vsDGsRI1j
	 wLh6+u6Sql1IPBxACNS6AKrBGWgt3o4g3Wytx93s=
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: quoted-printable
From: Michael Frysinger <vapier@sourceware.org>
To: bfd-cvs@sourceware.org, gdb-cvs@sourceware.org
Subject: [binutils-gdb] sim: reg: constify store helper
X-Act-Checkin: binutils-gdb
X-Git-Author: Mike Frysinger <vapier@gentoo.org>
X-Git-Refname: refs/heads/master
X-Git-Oldrev: ed60d3edd51f6c33fb0f3f09400094a1b1c2ceb2
X-Git-Newrev: 5bab16fdf1775c8abd16376458c5843fbe1d4314
Message-Id: <20221031165453.C7369385D0E3@sourceware.org>
Date: Mon, 31 Oct 2022 16:54:53 +0000 (GMT)
List-Id: <gdb-cvs.sourceware.org>

https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D5bab16fdf177=
5c8abd16376458c5843fbe1d4314

commit 5bab16fdf1775c8abd16376458c5843fbe1d4314
Author: Mike Frysinger <vapier@gentoo.org>
Date:   Wed Oct 26 23:01:21 2022 +0545

    sim: reg: constify store helper
   =20
    These functions only read from memory, so mark the pointer as const.

Diff:
---
 include/sim/sim.h       | 3 ++-
 sim/aarch64/interp.c    | 2 +-
 sim/arm/wrapper.c       | 2 +-
 sim/avr/interp.c        | 2 +-
 sim/bfin/machs.c        | 2 +-
 sim/bpf/bpf.c           | 2 +-
 sim/common/sim-cpu.h    | 2 +-
 sim/common/sim-reg.c    | 2 +-
 sim/cr16/interp.c       | 4 ++--
 sim/cris/cris-tmpl.c    | 2 +-
 sim/cris/sim-if.c       | 2 +-
 sim/d10v/interp.c       | 4 ++--
 sim/erc32/interf.c      | 2 +-
 sim/frv/frv.c           | 2 +-
 sim/ft32/interp.c       | 2 +-
 sim/h8300/compile.c     | 2 +-
 sim/iq2000/iq2000.c     | 2 +-
 sim/lm32/lm32.c         | 2 +-
 sim/m32c/gdb-if.c       | 2 +-
 sim/m32r/m32r.c         | 2 +-
 sim/m32r/m32r2.c        | 2 +-
 sim/m32r/m32rx.c        | 2 +-
 sim/m68hc11/interp.c    | 4 ++--
 sim/mcore/interp.c      | 2 +-
 sim/microblaze/interp.c | 2 +-
 sim/mips/interp.c       | 4 ++--
 sim/mn10300/interp.c    | 6 +++---
 sim/moxie/interp.c      | 2 +-
 sim/msp430/msp430-sim.c | 2 +-
 sim/or1k/or1k-sim.h     | 4 ++--
 sim/or1k/or1k.c         | 2 +-
 sim/ppc/gdb-sim.c       | 3 ++-
 sim/pru/interp.c        | 2 +-
 sim/riscv/sim-main.c    | 2 +-
 sim/rl78/gdb-if.c       | 2 +-
 sim/rx/gdb-if.c         | 2 +-
 sim/sh/interp.c         | 2 +-
 sim/v850/interp.c       | 4 ++--
 38 files changed, 48 insertions(+), 46 deletions(-)

diff --git a/include/sim/sim.h b/include/sim/sim.h
index ae8f19499ee..4afdf01d1ba 100644
--- a/include/sim/sim.h
+++ b/include/sim/sim.h
@@ -203,7 +203,8 @@ int sim_fetch_register (SIM_DESC sd, int regno, unsigne=
d char *buf, int length);
    Return a LENGTH of 0 to indicate the register was not updated
    but no error has occurred. */
=20
-int sim_store_register (SIM_DESC sd, int regno, unsigned char *buf, int le=
ngth);
+int sim_store_register (SIM_DESC sd, int regno, const unsigned char *buf,
+			int length);
=20
=20
 /* Print whatever statistics the simulator has collected.
diff --git a/sim/aarch64/interp.c b/sim/aarch64/interp.c
index ac95c7dfaac..34a4c72d6d7 100644
--- a/sim/aarch64/interp.c
+++ b/sim/aarch64/interp.c
@@ -257,7 +257,7 @@ aarch64_reg_get (SIM_CPU *cpu, int regno, unsigned char=
 *buf, int length)
 }
=20
 static int
-aarch64_reg_set (SIM_CPU *cpu, int regno, unsigned char *buf, int length)
+aarch64_reg_set (SIM_CPU *cpu, int regno, const unsigned char *buf, int le=
ngth)
 {
   size_t size;
   bfd_vma val;
diff --git a/sim/arm/wrapper.c b/sim/arm/wrapper.c
index 72a65242b9d..455f3205f97 100644
--- a/sim/arm/wrapper.c
+++ b/sim/arm/wrapper.c
@@ -429,7 +429,7 @@ tomem (struct ARMul_State *state,
 }
=20
 static int
-arm_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
+arm_reg_store (SIM_CPU *cpu, int rn, const unsigned char *memory, int leng=
th)
 {
   init ();
=20
diff --git a/sim/avr/interp.c b/sim/avr/interp.c
index 1b147c482d7..0aa7132cf77 100644
--- a/sim/avr/interp.c
+++ b/sim/avr/interp.c
@@ -1600,7 +1600,7 @@ sim_read (SIM_DESC sd, SIM_ADDR addr, void *buffer, i=
nt size)
 }
=20
 static int
-avr_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
+avr_reg_store (SIM_CPU *cpu, int rn, const unsigned char *memory, int leng=
th)
 {
   if (rn < 32 && length =3D=3D 1)
     {
diff --git a/sim/bfin/machs.c b/sim/bfin/machs.c
index f322b183b2e..035eb31a99d 100644
--- a/sim/bfin/machs.c
+++ b/sim/bfin/machs.c
@@ -1881,7 +1881,7 @@ bfin_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *=
buf, int len)
 }
=20
 static int
-bfin_reg_store (SIM_CPU *cpu, int rn, unsigned char *buf, int len)
+bfin_reg_store (SIM_CPU *cpu, int rn, const unsigned char *buf, int len)
 {
   bu32 value, *reg;
=20
diff --git a/sim/bpf/bpf.c b/sim/bpf/bpf.c
index 4a55acd4992..9db61ff56a9 100644
--- a/sim/bpf/bpf.c
+++ b/sim/bpf/bpf.c
@@ -61,7 +61,7 @@ bpfbf_fetch_register (SIM_CPU *current_cpu,
 int
 bpfbf_store_register (SIM_CPU *current_cpu,
                       int rn,
-                      unsigned char *buf,
+                      const unsigned char *buf,
                       int len)
 {
   if (rn =3D=3D 11)
diff --git a/sim/common/sim-cpu.h b/sim/common/sim-cpu.h
index 9e09a55bf81..2ad5667e3ab 100644
--- a/sim/common/sim-cpu.h
+++ b/sim/common/sim-cpu.h
@@ -31,7 +31,7 @@ typedef const char * (CPU_INSN_NAME_FN) (sim_cpu *, int);
 /* Types for register access functions.
    These routines implement the sim_{fetch,store}_register interface.  */
 typedef int (CPUREG_FETCH_FN) (sim_cpu *, int, unsigned char *, int);
-typedef int (CPUREG_STORE_FN) (sim_cpu *, int, unsigned char *, int);
+typedef int (CPUREG_STORE_FN) (sim_cpu *, int, const unsigned char *, int);
=20
 /* Types for PC access functions.
    Some simulators require a functional interface to access the program
diff --git a/sim/common/sim-reg.c b/sim/common/sim-reg.c
index 756ad26e4bd..54ce56206a4 100644
--- a/sim/common/sim-reg.c
+++ b/sim/common/sim-reg.c
@@ -45,7 +45,7 @@ sim_fetch_register (SIM_DESC sd, int rn, unsigned char *b=
uf, int length)
    cpus.  */
=20
 int
-sim_store_register (SIM_DESC sd, int rn, unsigned char *buf, int length)
+sim_store_register (SIM_DESC sd, int rn, const unsigned char *buf, int len=
gth)
 {
   SIM_CPU *cpu =3D STATE_CPU (sd, 0);
=20
diff --git a/sim/cr16/interp.c b/sim/cr16/interp.c
index cbdcdc6e793..6e27fade957 100644
--- a/sim/cr16/interp.c
+++ b/sim/cr16/interp.c
@@ -386,7 +386,7 @@ free_state (SIM_DESC sd)
 }
=20
 static int cr16_reg_fetch (SIM_CPU *, int, unsigned char *, int);
-static int cr16_reg_store (SIM_CPU *, int, unsigned char *, int);
+static int cr16_reg_store (SIM_CPU *, int, const unsigned char *, int);
=20
 SIM_DESC
 sim_open (SIM_OPEN_KIND kind, struct host_callback_struct *cb,
@@ -769,7 +769,7 @@ cr16_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *me=
mory, int length)
 }
=20
 static int
-cr16_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
+cr16_reg_store (SIM_CPU *cpu, int rn, const unsigned char *memory, int len=
gth)
 {
   SIM_DESC sd =3D CPU_STATE (cpu);
   int size;
diff --git a/sim/cris/cris-tmpl.c b/sim/cris/cris-tmpl.c
index 9f0c06e755e..a21a79aaa7c 100644
--- a/sim/cris/cris-tmpl.c
+++ b/sim/cris/cris-tmpl.c
@@ -90,7 +90,7 @@ MY (f_fetch_register) (SIM_CPU *current_cpu, int rn,
=20
 int
 MY (f_store_register) (SIM_CPU *current_cpu, int rn,
-		      unsigned char *buf, int len ATTRIBUTE_UNUSED)
+		      const unsigned char *buf, int len ATTRIBUTE_UNUSED)
 {
   XCONCAT3(crisv,BASENUM,f_h_gr_set) (current_cpu, rn, GETTSI (buf));
   return -1;
diff --git a/sim/cris/sim-if.c b/sim/cris/sim-if.c
index bedc0d08fc0..64fefd67bf2 100644
--- a/sim/cris/sim-if.c
+++ b/sim/cris/sim-if.c
@@ -933,7 +933,7 @@ sim_open (SIM_OPEN_KIND kind, host_callback *callback, =
struct bfd *abfd,
 	CPU_CRIS_MISC_PROFILE (cpu)->flags =3D STATE_TRACE_FLAGS (sd)[0];
=20
 	/* Set SP to the stack we allocated above.  */
-	(* CPU_REG_STORE (cpu)) (cpu, H_GR_SP, (unsigned char *) sp_init, 4);
+	(* CPU_REG_STORE (cpu)) (cpu, H_GR_SP, (const unsigned char *) sp_init, 4=
);
=20
 	/* Set the simulator environment data.  */
 	cpu->highest_mmapped_page =3D NULL;
diff --git a/sim/d10v/interp.c b/sim/d10v/interp.c
index c82bb4ce8c9..f17033f3b3e 100644
--- a/sim/d10v/interp.c
+++ b/sim/d10v/interp.c
@@ -744,7 +744,7 @@ free_state (SIM_DESC sd)
 }
=20
 static int d10v_reg_fetch (SIM_CPU *, int, unsigned char *, int);
-static int d10v_reg_store (SIM_CPU *, int, unsigned char *, int);
+static int d10v_reg_store (SIM_CPU *, int, const unsigned char *, int);
=20
 SIM_DESC
 sim_open (SIM_OPEN_KIND kind, host_callback *cb,
@@ -1293,7 +1293,7 @@ d10v_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *=
memory, int length)
 }
 =20
 static int
-d10v_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
+d10v_reg_store (SIM_CPU *cpu, int rn, const unsigned char *memory, int len=
gth)
 {
   SIM_DESC sd =3D CPU_STATE (cpu);
   int size;
diff --git a/sim/erc32/interf.c b/sim/erc32/interf.c
index fc4336c5f6f..9e0c5a27001 100644
--- a/sim/erc32/interf.c
+++ b/sim/erc32/interf.c
@@ -310,7 +310,7 @@ sim_create_inferior(SIM_DESC sd, bfd *abfd, char * cons=
t *argv,
 }
=20
 int
-sim_store_register(SIM_DESC sd, int regno, unsigned char *value, int lengt=
h)
+sim_store_register(SIM_DESC sd, int regno, const unsigned char *value, int=
 length)
 {
     int regval;
=20
diff --git a/sim/frv/frv.c b/sim/frv/frv.c
index eba01569d80..6cc95d4a2eb 100644
--- a/sim/frv/frv.c
+++ b/sim/frv/frv.c
@@ -89,7 +89,7 @@ frvbf_fetch_register (SIM_CPU *current_cpu, int rn, unsig=
ned char *buf, int len)
 /* The contents of BUF are in target byte order.  */
=20
 int
-frvbf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, in=
t len)
+frvbf_store_register (SIM_CPU *current_cpu, int rn, const unsigned char *b=
uf, int len)
 {
   if (SIM_FRV_GR0_REGNUM <=3D rn && rn <=3D SIM_FRV_GR63_REGNUM)
     {
diff --git a/sim/ft32/interp.c b/sim/ft32/interp.c
index 70212f45cca..65c7141a32c 100644
--- a/sim/ft32/interp.c
+++ b/sim/ft32/interp.c
@@ -745,7 +745,7 @@ ft32_lookup_register (SIM_CPU *cpu, int nr)
 static int
 ft32_reg_store (SIM_CPU *cpu,
 		int rn,
-		unsigned char *memory,
+		const unsigned char *memory,
 		int length)
 {
   if (0 <=3D rn && rn <=3D 32)
diff --git a/sim/h8300/compile.c b/sim/h8300/compile.c
index f49e83d6b19..ada7f72f873 100644
--- a/sim/h8300/compile.c
+++ b/sim/h8300/compile.c
@@ -4476,7 +4476,7 @@ sim_read (SIM_DESC sd, SIM_ADDR addr, void *buffer, i=
nt size)
 }
=20
 static int
-h8300_reg_store (SIM_CPU *cpu, int rn, unsigned char *value, int length)
+h8300_reg_store (SIM_CPU *cpu, int rn, const unsigned char *value, int len=
gth)
 {
   int longval;
   int shortval;
diff --git a/sim/iq2000/iq2000.c b/sim/iq2000/iq2000.c
index 9b1f4bd0179..d758867c27c 100644
--- a/sim/iq2000/iq2000.c
+++ b/sim/iq2000/iq2000.c
@@ -227,7 +227,7 @@ iq2000bf_fetch_register (SIM_CPU *cpu, int nr, unsigned=
 char *buf, int len)
 }
=20
 int
-iq2000bf_store_register (SIM_CPU *cpu, int nr, unsigned char *buf, int len)
+iq2000bf_store_register (SIM_CPU *cpu, int nr, const unsigned char *buf, i=
nt len)
 {
   if (nr >=3D GPR0_REGNUM
       && nr < (GPR0_REGNUM + NR_GPR)
diff --git a/sim/lm32/lm32.c b/sim/lm32/lm32.c
index 3ca8624f47b..e8e8386ee5e 100644
--- a/sim/lm32/lm32.c
+++ b/sim/lm32/lm32.c
@@ -52,7 +52,7 @@ lm32bf_fetch_register (SIM_CPU * current_cpu, int rn, uns=
igned char *buf,
 /* The contents of BUF are in target byte order.  */
=20
 int
-lm32bf_store_register (SIM_CPU * current_cpu, int rn, unsigned char *buf,
+lm32bf_store_register (SIM_CPU * current_cpu, int rn, const unsigned char =
*buf,
 		       int len)
 {
   if (rn < 32)
diff --git a/sim/m32c/gdb-if.c b/sim/m32c/gdb-if.c
index 802eae97851..a74dde947f6 100644
--- a/sim/m32c/gdb-if.c
+++ b/sim/m32c/gdb-if.c
@@ -403,7 +403,7 @@ sim_fetch_register (SIM_DESC sd, int regno, unsigned ch=
ar *buf, int length)
 }
=20
 int
-sim_store_register (SIM_DESC sd, int regno, unsigned char *buf, int length)
+sim_store_register (SIM_DESC sd, int regno, const unsigned char *buf, int =
length)
 {
   size_t size;
=20
diff --git a/sim/m32r/m32r.c b/sim/m32r/m32r.c
index 811c2b162c1..f8573690aac 100644
--- a/sim/m32r/m32r.c
+++ b/sim/m32r/m32r.c
@@ -98,7 +98,7 @@ m32rbf_fetch_register (SIM_CPU *current_cpu, int rn, unsi=
gned char *buf, int len
 /* The contents of BUF are in target byte order.  */
=20
 int
-m32rbf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, i=
nt len)
+m32rbf_store_register (SIM_CPU *current_cpu, int rn, const unsigned char *=
buf, int len)
 {
   int size =3D m32rbf_register_size (rn);
   if (len !=3D size)
diff --git a/sim/m32r/m32r2.c b/sim/m32r/m32r2.c
index 9c8daa5b8c6..a057a4c0e3f 100644
--- a/sim/m32r/m32r2.c
+++ b/sim/m32r/m32r2.c
@@ -38,7 +38,7 @@ m32r2f_fetch_register (SIM_CPU *current_cpu, int rn, unsi=
gned char *buf, int len
 /* The contents of BUF are in target byte order.  */
=20
 int
-m32r2f_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, i=
nt len)
+m32r2f_store_register (SIM_CPU *current_cpu, int rn, const unsigned char *=
buf, int len)
 {
   return m32rbf_store_register (current_cpu, rn, buf, len);
 }
diff --git a/sim/m32r/m32rx.c b/sim/m32r/m32rx.c
index 07098036d02..deafcbed446 100644
--- a/sim/m32r/m32rx.c
+++ b/sim/m32r/m32rx.c
@@ -38,7 +38,7 @@ m32rxf_fetch_register (SIM_CPU *current_cpu, int rn, unsi=
gned char *buf, int len
 /* The contents of BUF are in target byte order.  */
=20
 int
-m32rxf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, i=
nt len)
+m32rxf_store_register (SIM_CPU *current_cpu, int rn, const unsigned char *=
buf, int len)
 {
   return m32rbf_store_register (current_cpu, rn, buf, len);
 }
diff --git a/sim/m68hc11/interp.c b/sim/m68hc11/interp.c
index ab3c5a8e861..ab87068f858 100644
--- a/sim/m68hc11/interp.c
+++ b/sim/m68hc11/interp.c
@@ -392,7 +392,7 @@ m68hc11_pc_set (sim_cpu *cpu, sim_cia pc)
 }
=20
 static int m68hc11_reg_fetch (SIM_CPU *, int, unsigned char *, int);
-static int m68hc11_reg_store (SIM_CPU *, int, unsigned char *, int);
+static int m68hc11_reg_store (SIM_CPU *, int, const unsigned char *, int);
=20
 SIM_DESC
 sim_open (SIM_OPEN_KIND kind, host_callback *callback,
@@ -595,7 +595,7 @@ m68hc11_reg_fetch (SIM_CPU *cpu, int rn, unsigned char =
*memory, int length)
 }
=20
 static int
-m68hc11_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
+m68hc11_reg_store (SIM_CPU *cpu, int rn, const unsigned char *memory, int =
length)
 {
   uint16_t val;
=20
diff --git a/sim/mcore/interp.c b/sim/mcore/interp.c
index 082bc4e0767..8ca2eeec294 100644
--- a/sim/mcore/interp.c
+++ b/sim/mcore/interp.c
@@ -1242,7 +1242,7 @@ sim_engine_run (SIM_DESC sd,
 }
=20
 static int
-mcore_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
+mcore_reg_store (SIM_CPU *cpu, int rn, const unsigned char *memory, int le=
ngth)
 {
   if (rn < NUM_MCORE_REGS && rn >=3D 0)
     {
diff --git a/sim/microblaze/interp.c b/sim/microblaze/interp.c
index 6aa02632093..1435eccf6e2 100644
--- a/sim/microblaze/interp.c
+++ b/sim/microblaze/interp.c
@@ -321,7 +321,7 @@ sim_engine_run (SIM_DESC sd,
 }
=20
 static int
-microblaze_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int len=
gth)
+microblaze_reg_store (SIM_CPU *cpu, int rn, const unsigned char *memory, i=
nt length)
 {
   if (rn < NUM_REGS + NUM_SPECIAL && rn >=3D 0)
     {
diff --git a/sim/mips/interp.c b/sim/mips/interp.c
index 28421b3a831..5540d5c894a 100644
--- a/sim/mips/interp.c
+++ b/sim/mips/interp.c
@@ -337,7 +337,7 @@ mips_pc_set (sim_cpu *cpu, sim_cia pc)
 }
=20
 static int mips_reg_fetch (SIM_CPU *, int, unsigned char *, int);
-static int mips_reg_store (SIM_CPU *, int, unsigned char *, int);
+static int mips_reg_store (SIM_CPU *, int, const unsigned char *, int);
=20
 SIM_DESC
 sim_open (SIM_OPEN_KIND kind, host_callback *cb,
@@ -846,7 +846,7 @@ mips_sim_close (SIM_DESC sd, int quitting)
 }
=20
 static int
-mips_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
+mips_reg_store (SIM_CPU *cpu, int rn, const unsigned char *memory, int len=
gth)
 {
   /* NOTE: gdb (the client) stores registers in target byte order
      while the simulator uses host byte order */
diff --git a/sim/mn10300/interp.c b/sim/mn10300/interp.c
index 2e7fd163047..020fd04d67c 100644
--- a/sim/mn10300/interp.c
+++ b/sim/mn10300/interp.c
@@ -80,7 +80,7 @@ mn10300_pc_set (sim_cpu *cpu, sim_cia pc)
 }
=20
 static int mn10300_reg_fetch (SIM_CPU *, int, unsigned char *, int);
-static int mn10300_reg_store (SIM_CPU *, int, unsigned char *, int);
+static int mn10300_reg_store (SIM_CPU *, int, const unsigned char *, int);
=20
 /* These default values correspond to expected usage for the chip.  */
=20
@@ -344,9 +344,9 @@ mn10300_reg_fetch (SIM_CPU *cpu, int rn, unsigned char =
*memory, int length)
 }
 =20
 static int
-mn10300_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
+mn10300_reg_store (SIM_CPU *cpu, int rn, const unsigned char *memory, int =
length)
 {
-  uint8_t *a =3D memory;
+  const uint8_t *a =3D memory;
   State.regs[rn] =3D (a[3] << 24) + (a[2] << 16) + (a[1] << 8) + a[0];
   return length;
 }
diff --git a/sim/moxie/interp.c b/sim/moxie/interp.c
index d5d14bfe49d..325bd14e313 100644
--- a/sim/moxie/interp.c
+++ b/sim/moxie/interp.c
@@ -1132,7 +1132,7 @@ sim_engine_run (SIM_DESC sd,
 }
=20
 static int
-moxie_reg_store (SIM_CPU *scpu, int rn, unsigned char *memory, int length)
+moxie_reg_store (SIM_CPU *scpu, int rn, const unsigned char *memory, int l=
ength)
 {
   if (rn < NUM_MOXIE_REGS && rn >=3D 0)
     {
diff --git a/sim/msp430/msp430-sim.c b/sim/msp430/msp430-sim.c
index 2ca5e1716d2..d253f2e29f7 100644
--- a/sim/msp430/msp430-sim.c
+++ b/sim/msp430/msp430-sim.c
@@ -74,7 +74,7 @@ msp430_reg_fetch (SIM_CPU *cpu, int regno, unsigned char =
*buf, int len)
 }
=20
 static int
-msp430_reg_store (SIM_CPU *cpu, int regno, unsigned char *buf, int len)
+msp430_reg_store (SIM_CPU *cpu, int regno, const unsigned char *buf, int l=
en)
 {
   if (0 <=3D regno && regno < 16)
     {
diff --git a/sim/or1k/or1k-sim.h b/sim/or1k/or1k-sim.h
index c956a056369..045f17159b1 100644
--- a/sim/or1k/or1k-sim.h
+++ b/sim/or1k/or1k-sim.h
@@ -70,8 +70,8 @@ void or1k32bf_mtspr (sim_cpu *current_cpu, USI addr, USI =
val);
=20
 int or1k32bf_fetch_register (sim_cpu *current_cpu, int rn, unsigned char *=
buf,
 			     int len);
-int or1k32bf_store_register (sim_cpu *current_cpu, int rn, unsigned char *=
buf,
-			     int len);
+int or1k32bf_store_register (sim_cpu *current_cpu, int rn,
+			     const unsigned char *buf, int len);
 int or1k32bf_model_or1200_u_exec (sim_cpu *current_cpu, const IDESC *idesc,
 				  int unit_num, int referenced);
 int or1k32bf_model_or1200nd_u_exec (sim_cpu *current_cpu, const IDESC *ide=
sc,
diff --git a/sim/or1k/or1k.c b/sim/or1k/or1k.c
index bfab35461be..488d756e7c0 100644
--- a/sim/or1k/or1k.c
+++ b/sim/or1k/or1k.c
@@ -55,7 +55,7 @@ or1k32bf_fetch_register (sim_cpu *current_cpu, int rn, un=
signed char *buf,
 }
=20
 int
-or1k32bf_store_register (sim_cpu *current_cpu, int rn, unsigned char *buf,
+or1k32bf_store_register (sim_cpu *current_cpu, int rn, const unsigned char=
 *buf,
 			 int len)
 {
   if (rn < 32)
diff --git a/sim/ppc/gdb-sim.c b/sim/ppc/gdb-sim.c
index c6ae10e0a14..8cf3638f2bf 100644
--- a/sim/ppc/gdb-sim.c
+++ b/sim/ppc/gdb-sim.c
@@ -1284,7 +1284,8 @@ sim_fetch_register (SIM_DESC sd, int regno, unsigned =
char *buf, int length)
=20
=20
 int
-sim_store_register (SIM_DESC sd, int regno, unsigned char *buf, int length)
+sim_store_register (SIM_DESC sd, int regno, const unsigned char *buf,
+		    int length)
 {
   const char *regname =3D regnum2name (regno);
=20
diff --git a/sim/pru/interp.c b/sim/pru/interp.c
index fabedc99f6e..4b7de4c79ce 100644
--- a/sim/pru/interp.c
+++ b/sim/pru/interp.c
@@ -650,7 +650,7 @@ pru_pc_set (sim_cpu *cpu, sim_cia pc)
=20
 /* Implement callback for standard CPU_REG_STORE routine.  */
 static int
-pru_store_register (SIM_CPU *cpu, int rn, unsigned char *memory, int lengt=
h)
+pru_store_register (SIM_CPU *cpu, int rn, const unsigned char *memory, int=
 length)
 {
   if (rn < NUM_REGS && rn >=3D 0)
     {
diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 5932c0de979..1cf7111acff 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -1054,7 +1054,7 @@ reg_fetch (sim_cpu *cpu, int rn, unsigned char *buf, =
int len)
 }
=20
 static int
-reg_store (sim_cpu *cpu, int rn, unsigned char *buf, int len)
+reg_store (sim_cpu *cpu, int rn, const unsigned char *buf, int len)
 {
   if (len <=3D 0 || len > sizeof (unsigned_word))
     return -1;
diff --git a/sim/rl78/gdb-if.c b/sim/rl78/gdb-if.c
index 98bb0a4044b..ef6c75d1825 100644
--- a/sim/rl78/gdb-if.c
+++ b/sim/rl78/gdb-if.c
@@ -356,7 +356,7 @@ sim_fetch_register (SIM_DESC sd, int regno, unsigned ch=
ar *buf, int length)
    LENGTH must match the sim's internal notion of the register size.  */
=20
 int
-sim_store_register (SIM_DESC sd, int regno, unsigned char *buf, int length)
+sim_store_register (SIM_DESC sd, int regno, const unsigned char *buf, int =
length)
 {
   size_t size;
   SI val;
diff --git a/sim/rx/gdb-if.c b/sim/rx/gdb-if.c
index 7af37b94fcf..20bb9ef31be 100644
--- a/sim/rx/gdb-if.c
+++ b/sim/rx/gdb-if.c
@@ -532,7 +532,7 @@ sim_fetch_register (SIM_DESC sd, int regno, unsigned ch=
ar *buf, int length)
 }
=20
 int
-sim_store_register (SIM_DESC sd, int regno, unsigned char *buf, int length)
+sim_store_register (SIM_DESC sd, int regno, const unsigned char *buf, int =
length)
 {
   size_t size;
   DI val;
diff --git a/sim/sh/interp.c b/sim/sh/interp.c
index 6a33cce065a..21de3848aba 100644
--- a/sim/sh/interp.c
+++ b/sim/sh/interp.c
@@ -1913,7 +1913,7 @@ enum {
 };
=20
 static int
-sh_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
+sh_reg_store (SIM_CPU *cpu, int rn, const unsigned char *memory, int lengt=
h)
 {
   unsigned val;
=20
diff --git a/sim/v850/interp.c b/sim/v850/interp.c
index 88191481a86..d0fd132f8c8 100644
--- a/sim/v850/interp.c
+++ b/sim/v850/interp.c
@@ -185,7 +185,7 @@ v850_pc_set (sim_cpu *cpu, sim_cia pc)
 }
=20
 static int v850_reg_fetch (SIM_CPU *, int, unsigned char *, int);
-static int v850_reg_store (SIM_CPU *, int, unsigned char *, int);
+static int v850_reg_store (SIM_CPU *, int, const unsigned char *, int);
=20
 SIM_DESC
 sim_open (SIM_OPEN_KIND    kind,
@@ -320,7 +320,7 @@ v850_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *me=
mory, int length)
 }
=20
 static int
-v850_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
+v850_reg_store (SIM_CPU *cpu, int rn, const unsigned char *memory, int len=
gth)
 {
   State.regs[rn] =3D T2H_4 (*(uint32_t *) memory);
   return length;