From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1521) id E54773858423; Mon, 7 Nov 2022 16:45:36 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E54773858423 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1667839536; bh=jf9FFv+jCmJos4AkjZV5+2uVEu9cDpPE/zNPuJlsqI4=; h=From:To:Subject:Date:From; b=Wjdgb5fCWwcT13wpNWgzAuRC+mvmqPieZJFpoR1areV600gq8aYwz6aPcDMcucmHm 50MKv34F/drPzrVDgKopfWdaFAlsaoMLND5wdY6VvP48h6zrnzu+WyvKX2ulghPUaV mrcixZ3gkc5Q2f8Hr30/UNe5ti2lqirmKH0U2nds= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Michael Frysinger To: gdb-cvs@sourceware.org Subject: [binutils-gdb] sim: riscv: add missing AC_MSG_RESULT call X-Act-Checkin: binutils-gdb X-Git-Author: Mike Frysinger X-Git-Refname: refs/heads/master X-Git-Oldrev: 871aa3b9ee7b1067bffa05549190c6051cf06fe5 X-Git-Newrev: 4faede6126762a9704da4c79093cca15c15efafa Message-Id: <20221107164536.E54773858423@sourceware.org> Date: Mon, 7 Nov 2022 16:45:36 +0000 (GMT) List-Id: https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D4faede612676= 2a9704da4c79093cca15c15efafa commit 4faede6126762a9704da4c79093cca15c15efafa Author: Mike Frysinger Date: Mon Nov 7 23:44:36 2022 +0700 sim: riscv: add missing AC_MSG_RESULT call =20 Previous commit in here forgot to include this. Diff: --- sim/configure | 2 ++ sim/riscv/acinclude.m4 | 1 + 2 files changed, 3 insertions(+) diff --git a/sim/configure b/sim/configure index e25d60c0d90..1916e1d37f6 100755 --- a/sim/configure +++ b/sim/configure @@ -16279,6 +16279,8 @@ case $target in #( *) : ;; esac +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $SIM_RISCV_BITSIZE" >&5 +$as_echo "$SIM_RISCV_BITSIZE" >&6; } =20 =20 { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether sim rx should be= cycle accurate" >&5 diff --git a/sim/riscv/acinclude.m4 b/sim/riscv/acinclude.m4 index 29dcaebc61d..0a421f4d4d5 100644 --- a/sim/riscv/acinclude.m4 +++ b/sim/riscv/acinclude.m4 @@ -18,4 +18,5 @@ AC_MSG_CHECKING([riscv bitsize]) SIM_RISCV_BITSIZE=3D64 AS_CASE([$target], [riscv32*], [SIM_RISCV_BITSIZE=3D32]) +AC_MSG_RESULT([$SIM_RISCV_BITSIZE]) AC_SUBST(SIM_RISCV_BITSIZE)