From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1585) id 58129383F95C; Thu, 10 Nov 2022 00:45:45 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 58129383F95C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1668041145; bh=SinQ19mIvvaMoGs6S01Jq1Xz1emJq2hKCZ6Fdcdf5Y0=; h=From:To:Subject:Date:From; b=N6JqqaNvnGwlQtfKPwCJ4H5/q1yVBPZCg1zb0TO0z1G5PVbif3/uMD3qE/V6Wo2Jn +0AxL4eCE9uzhesjHZwl/yUUv3HEDkCTdic8p5xjGPkHcQWES3HJsKh01UQcEOWsc4 Q3YEhcykoxwMW4m0aMcy+rzplgiCwemFx8t+Iyj8= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Luis Machado To: gdb-cvs@sourceware.org Subject: [binutils-gdb] [gdb/aarch64] Use safer memory read routines X-Act-Checkin: binutils-gdb X-Git-Author: Luis Machado X-Git-Refname: refs/heads/master X-Git-Oldrev: 8a484e98aecc25737a1391d12d5881a170f2fe6a X-Git-Newrev: 94355de7751579b0182bd5821a3223939054f5d7 Message-Id: <20221110004545.58129383F95C@sourceware.org> Date: Thu, 10 Nov 2022 00:45:45 +0000 (GMT) List-Id: https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D94355de77515= 79b0182bd5821a3223939054f5d7 commit 94355de7751579b0182bd5821a3223939054f5d7 Author: Luis Machado Date: Mon Oct 31 13:26:20 2022 +0000 [gdb/aarch64] Use safer memory read routines =20 PR tdep/28796 =20 As reported, we are using some memory read routines that don't handle= read errors gracefully. Convert those to use the safe_* versions if availa= ble. =20 This allows the code to handle those read errors in a more sensible w= ay. =20 Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=3D28796 Diff: --- gdb/aarch64-tdep.c | 42 ++++++++++++++++++++++++++++++++++++------ 1 file changed, 36 insertions(+), 6 deletions(-) diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c index d9ddc84a140..07330356fdc 100644 --- a/gdb/aarch64-tdep.c +++ b/gdb/aarch64-tdep.c @@ -2940,8 +2940,18 @@ aarch64_software_single_step (struct regcache *regca= che) CORE_ADDR breaks[2] =3D { CORE_ADDR_MAX, CORE_ADDR_MAX }; CORE_ADDR loc =3D pc; CORE_ADDR closing_insn =3D 0; - uint32_t insn =3D read_memory_unsigned_integer (loc, insn_size, - byte_order_for_code); + + ULONGEST insn_from_memory; + if (!safe_read_memory_unsigned_integer (loc, insn_size, + byte_order_for_code, + &insn_from_memory)) + { + /* Assume we don't have a atomic sequence, as we couldn't read the + instruction in this location. */ + return {}; + } + + uint32_t insn =3D insn_from_memory; int index; int insn_count; int bc_insn_count =3D 0; /* Conditional branch instruction count. */ @@ -2958,9 +2968,17 @@ aarch64_software_single_step (struct regcache *regca= che) for (insn_count =3D 0; insn_count < atomic_sequence_length; ++insn_count) { loc +=3D insn_size; - insn =3D read_memory_unsigned_integer (loc, insn_size, - byte_order_for_code); =20 + if (!safe_read_memory_unsigned_integer (loc, insn_size, + byte_order_for_code, + &insn_from_memory)) + { + /* Assume we don't have a atomic sequence, as we couldn't read the + instruction in this location. */ + return {}; + } + + insn =3D insn_from_memory; if (aarch64_decode_insn (insn, &inst, 1, NULL) !=3D 0) return {}; /* Check if the instruction is a conditional branch. */ @@ -3259,9 +3277,15 @@ aarch64_displaced_step_copy_insn (struct gdbarch *gd= barch, struct regcache *regs) { enum bfd_endian byte_order_for_code =3D gdbarch_byte_order_for_code (gdb= arch); - uint32_t insn =3D read_memory_unsigned_integer (from, 4, byte_order_for_= code); struct aarch64_displaced_step_data dsd; aarch64_inst inst; + ULONGEST insn_from_memory; + + if (!safe_read_memory_unsigned_integer (from, 4, byte_order_for_code, + &insn_from_memory)) + return nullptr; + + uint32_t insn =3D insn_from_memory; =20 if (aarch64_decode_insn (insn, &inst, 1, NULL) !=3D 0) return NULL; @@ -3472,7 +3496,13 @@ aarch64_stack_frame_destroyed_p (struct gdbarch *gdb= arch, CORE_ADDR pc) return 0; =20 enum bfd_endian byte_order_for_code =3D gdbarch_byte_order_for_code (gdb= arch); - uint32_t insn =3D read_memory_unsigned_integer (pc, 4, byte_order_for_co= de); + + ULONGEST insn_from_memory; + if (!safe_read_memory_unsigned_integer (pc, 4, byte_order_for_code, + &insn_from_memory)) + return 0; + + uint32_t insn =3D insn_from_memory; =20 aarch64_inst inst; if (aarch64_decode_insn (insn, &inst, 1, nullptr) !=3D 0)