From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2059) id F2BB43858039; Sat, 12 Nov 2022 13:10:20 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org F2BB43858039 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1668258620; bh=WPYuObYwhDRlNnyud6yLw045UlQ2NWamUwn92MXcaRU=; h=From:To:Subject:Date:From; b=b33kwW9lDYv0mj6+vHLCuoraDW7s+eyWmeib+wnYLY1z2ThlC1xjFxuywANza4WPy vsIkfa33pu7E3D9R2jx83io8W8ypE+hJidYpLIC2wYmsWJnfwBn1VK3EFsoMOGj1Vt UgvdPRbab8eMtQwj9k83FRLwdxnoOV+dt8lew4yM= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Dimitar Dimitrov To: gdb-cvs@sourceware.org Subject: [binutils-gdb] sim: pru: Fix behaviour when loop count is zero X-Act-Checkin: binutils-gdb X-Git-Author: Dimitar Dimitrov X-Git-Refname: refs/heads/master X-Git-Oldrev: 7149607f6ae572fa198116b0d0fb69a3e0fde458 X-Git-Newrev: 7bee555bb712b74749b749d80566f9c0d2094312 Message-Id: <20221112131020.F2BB43858039@sourceware.org> Date: Sat, 12 Nov 2022 13:10:20 +0000 (GMT) List-Id: https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D7bee555bb712= b74749b749d80566f9c0d2094312 commit 7bee555bb712b74749b749d80566f9c0d2094312 Author: Dimitar Dimitrov Date: Fri Nov 11 20:14:13 2022 +0200 sim: pru: Fix behaviour when loop count is zero =20 If the counter for LOOP instruction is provided by a register with value zero, then the instruction must cause a PC jump directly to the loop end. But in that particular case simulator must not initialize its internal loop variables, because loop body will not be executed. Instead, simulator must obtain the loop's end address directly from the LOOP instruction. =20 Signed-off-by: Dimitar Dimitrov Diff: --- sim/pru/pru.isa | 4 ++-- sim/testsuite/pru/loop-zero.s | 41 +++++++++++++++++++++++++++++++++++++++= ++ 2 files changed, 43 insertions(+), 2 deletions(-) diff --git a/sim/pru/pru.isa b/sim/pru/pru.isa index b7d8b4af8b9..be8cdfd27fb 100644 --- a/sim/pru/pru.isa +++ b/sim/pru/pru.isa @@ -222,7 +222,7 @@ INSTRUCTION (loop, OP2 =3D (IO ? IMM8 + 1 : RS2_w0); if (OP2 =3D=3D 0) { - PC =3D LOOPEND; + PC =3D PC + LOOP_JMPOFFS; } else { @@ -237,7 +237,7 @@ INSTRUCTION (iloop, OP2 =3D (IO ? IMM8 + 1 : RS2_w0); if (OP2 =3D=3D 0) { - PC =3D LOOPEND; + PC =3D PC + LOOP_JMPOFFS; } else { diff --git a/sim/testsuite/pru/loop-zero.s b/sim/testsuite/pru/loop-zero.s new file mode 100644 index 00000000000..65330f27beb --- /dev/null +++ b/sim/testsuite/pru/loop-zero.s @@ -0,0 +1,41 @@ +# Check that loop insn works if register value is zero. +# mach: pru + +# Copyright (C) 2022 Free Software Foundation, Inc. +# Contributed by Dimitar Dimitrov +# +# This file is part of the GNU simulators. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +.include "testutils.inc" + + start + + ldi r25, 0 + ldi r27, 0 + ldi r28, 10 + + loop 1f, r25 + add r27, r27, 1 + add r28, r28, 1 +1: + + qbne F, r25, 0 + qbne F, r27, 0 + qbne F, r28, 10 + + pass + +F: fail