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From: Andrew Burgess <aburgess@sourceware.org> To: gdb-cvs@sourceware.org Subject: [binutils-gdb] gdb/riscv: correct dwarf to gdb register number mapping Date: Tue, 6 Dec 2022 10:19:27 +0000 (GMT) [thread overview] Message-ID: <20221206101927.9F62E38330DE@sourceware.org> (raw) https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=c8ea5e409b02cf7fa848e44af74b2e8246ad03f1 commit c8ea5e409b02cf7fa848e44af74b2e8246ad03f1 Author: Xiao Zeng <zengxiao@eswincomputing.com> Date: Tue Dec 6 14:59:43 2022 +0800 gdb/riscv: correct dwarf to gdb register number mapping According to the riscv psabi, the mapping relationship between the DWARF registers and the machine registers is as follows: DWARF Number | Register Name | Description 0 - 31 | x0 - x31 | Integer Registers 32 - 63 | f0 - f31 | Floating-point Registers This is not modelled quite right in riscv_dwarf_reg_to_regnum, the DWARF register numbers 31 and 63 are not handled correctly due to a use of '<' instead of '<='. This commit fixes this issue. Diff: --- gdb/riscv-tdep.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c index 0a050b272ff..a298623b449 100644 --- a/gdb/riscv-tdep.c +++ b/gdb/riscv-tdep.c @@ -3623,10 +3623,10 @@ riscv_add_reggroups (struct gdbarch *gdbarch) static int riscv_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) { - if (reg < RISCV_DWARF_REGNUM_X31) + if (reg <= RISCV_DWARF_REGNUM_X31) return RISCV_ZERO_REGNUM + (reg - RISCV_DWARF_REGNUM_X0); - else if (reg < RISCV_DWARF_REGNUM_F31) + else if (reg <= RISCV_DWARF_REGNUM_F31) return RISCV_FIRST_FP_REGNUM + (reg - RISCV_DWARF_REGNUM_F0); else if (reg >= RISCV_DWARF_FIRST_CSR && reg <= RISCV_DWARF_LAST_CSR)
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