From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1521) id 79A0A38582AC; Wed, 21 Dec 2022 05:07:30 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 79A0A38582AC DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1671599250; bh=I4WTF6iIDsxM34ZoIBj+68vXggmBXyooAVTTTMMzeGQ=; h=From:To:Subject:Date:From; b=ejSDgSgjRSTu7FOcYZLi6/DTdknOcLgIYWTV6gHK69o9LHBSyBAlTwNq1Tmnu2JU7 F/tJF5i+3XxSpp5rqgK8QTCRxa5gQT8w7ukyw5dY/VJMN+Nsiorn6E3uweNzTJIqMs KEulDEVbQUKdX4rVW0okYiQOp04gNo+s6O5rQKek= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Michael Frysinger To: gdb-cvs@sourceware.org Subject: [binutils-gdb] sim: ft32: invert sim_cpu storage X-Act-Checkin: binutils-gdb X-Git-Author: Mike Frysinger X-Git-Refname: refs/heads/master X-Git-Oldrev: 6adb1071134b5ca69d512dcfaf564774096d32dd X-Git-Newrev: 6780d3731ea7c24f50f4489da53e7ca6476fca42 Message-Id: <20221221050730.79A0A38582AC@sourceware.org> Date: Wed, 21 Dec 2022 05:07:30 +0000 (GMT) List-Id: https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D6780d3731ea7= c24f50f4489da53e7ca6476fca42 commit 6780d3731ea7c24f50f4489da53e7ca6476fca42 Author: Mike Frysinger Date: Sat Aug 13 00:07:45 2016 +0800 sim: ft32: invert sim_cpu storage Diff: --- sim/ft32/ft32-sim.h | 2 + sim/ft32/interp.c | 181 +++++++++++++++++++++++++++---------------------= ---- sim/ft32/sim-main.h | 11 +--- 3 files changed, 99 insertions(+), 95 deletions(-) diff --git a/sim/ft32/ft32-sim.h b/sim/ft32/ft32-sim.h index 27cb81c81e0..968ef346f45 100644 --- a/sim/ft32/ft32-sim.h +++ b/sim/ft32/ft32-sim.h @@ -40,4 +40,6 @@ struct ft32_cpu_state { int exception; }; =20 +#define FT32_SIM_CPU(cpu) ((struct ft32_cpu_state *) CPU_ARCH_DATA (cpu)) + #endif /* _FT32_SIM_H_ */ diff --git a/sim/ft32/interp.c b/sim/ft32/interp.c index 562585618fa..9324475709e 100644 --- a/sim/ft32/interp.c +++ b/sim/ft32/interp.c @@ -162,7 +162,8 @@ ft32_write_item (SIM_DESC sd, int dw, uint32_t ea, uint= 32_t v) static uint32_t cpu_mem_read (SIM_DESC sd, uint32_t dw, uint32_t ea) { sim_cpu *cpu =3D STATE_CPU (sd, 0); - uint32_t insnpc =3D cpu->state.pc; + struct ft32_cpu_state *ft32_cpu =3D FT32_SIM_CPU (cpu); + uint32_t insnpc =3D ft32_cpu->pc; uint32_t r; uint8_t byte[4]; =20 @@ -176,7 +177,7 @@ static uint32_t cpu_mem_read (SIM_DESC sd, uint32_t dw,= uint32_t ea) return getchar (); case 0x1fff4: /* Read the simulator cycle timer. */ - return cpu->state.cycles / 100; + return ft32_cpu->cycles / 100; default: sim_io_eprintf (sd, "Illegal IO read address %08x, pc %#x\n", ea, insnpc); @@ -189,6 +190,7 @@ static uint32_t cpu_mem_read (SIM_DESC sd, uint32_t dw,= uint32_t ea) static void cpu_mem_write (SIM_DESC sd, uint32_t dw, uint32_t ea, uint32_t= d) { sim_cpu *cpu =3D STATE_CPU (sd, 0); + struct ft32_cpu_state *ft32_cpu =3D FT32_SIM_CPU (cpu); ea &=3D 0x1ffff; if (ea & 0x10000) { @@ -201,23 +203,23 @@ static void cpu_mem_write (SIM_DESC sd, uint32_t dw, = uint32_t ea, uint32_t d) break; case 0x1fc80: /* Unlock the PM write port */ - cpu->state.pm_unlock =3D (d =3D=3D 0x1337f7d1); + ft32_cpu->pm_unlock =3D (d =3D=3D 0x1337f7d1); break; case 0x1fc84: /* Set the PM write address register */ - cpu->state.pm_addr =3D d; + ft32_cpu->pm_addr =3D d; break; case 0x1fc88: - if (cpu->state.pm_unlock) + if (ft32_cpu->pm_unlock) { /* Write to PM. */ - ft32_write_item (sd, dw, cpu->state.pm_addr, d); - cpu->state.pm_addr +=3D 4; + ft32_write_item (sd, dw, ft32_cpu->pm_addr, d); + ft32_cpu->pm_addr +=3D 4; } break; case 0x1fffc: /* Normal exit. */ - sim_engine_halt (sd, cpu, NULL, cpu->state.pc, sim_exited, cpu->state.r= egs[0]); + sim_engine_halt (sd, cpu, NULL, ft32_cpu->pc, sim_exited, ft32_cpu->reg= s[0]); break; case 0x1fff8: sim_io_printf (sd, "Debug write %08x\n", d); @@ -239,17 +241,19 @@ static void cpu_mem_write (SIM_DESC sd, uint32_t dw, = uint32_t ea, uint32_t d) static void ft32_push (SIM_DESC sd, uint32_t v) { sim_cpu *cpu =3D STATE_CPU (sd, 0); - cpu->state.regs[FT32_HARD_SP] -=3D 4; - cpu->state.regs[FT32_HARD_SP] &=3D 0xffff; - cpu_mem_write (sd, 2, cpu->state.regs[FT32_HARD_SP], v); + struct ft32_cpu_state *ft32_cpu =3D FT32_SIM_CPU (cpu); + ft32_cpu->regs[FT32_HARD_SP] -=3D 4; + ft32_cpu->regs[FT32_HARD_SP] &=3D 0xffff; + cpu_mem_write (sd, 2, ft32_cpu->regs[FT32_HARD_SP], v); } =20 static uint32_t ft32_pop (SIM_DESC sd) { sim_cpu *cpu =3D STATE_CPU (sd, 0); - uint32_t r =3D cpu_mem_read (sd, 2, cpu->state.regs[FT32_HARD_SP]); - cpu->state.regs[FT32_HARD_SP] +=3D 4; - cpu->state.regs[FT32_HARD_SP] &=3D 0xffff; + struct ft32_cpu_state *ft32_cpu =3D FT32_SIM_CPU (cpu); + uint32_t r =3D cpu_mem_read (sd, 2, ft32_cpu->regs[FT32_HARD_SP]); + ft32_cpu->regs[FT32_HARD_SP] +=3D 4; + ft32_cpu->regs[FT32_HARD_SP] &=3D 0xffff; return r; } =20 @@ -320,6 +324,7 @@ static void step_once (SIM_DESC sd) { sim_cpu *cpu =3D STATE_CPU (sd, 0); + struct ft32_cpu_state *ft32_cpu =3D FT32_SIM_CPU (cpu); address_word cia =3D CPU_PC_GET (cpu); uint32_t inst; uint32_t dw; @@ -346,13 +351,13 @@ step_once (SIM_DESC sd) unsigned int sc[2]; int isize; =20 - inst =3D ft32_read_item (sd, 2, cpu->state.pc); - cpu->state.cycles +=3D 1; + inst =3D ft32_read_item (sd, 2, ft32_cpu->pc); + ft32_cpu->cycles +=3D 1; =20 if ((STATE_ARCHITECTURE (sd)->mach =3D=3D bfd_mach_ft32b) - && ft32_decode_shortcode (cpu->state.pc, inst, sc)) + && ft32_decode_shortcode (ft32_cpu->pc, inst, sc)) { - if ((cpu->state.pc & 3) =3D=3D 0) + if ((ft32_cpu->pc & 3) =3D=3D 0) inst =3D sc[0]; else inst =3D sc[1]; @@ -365,7 +370,7 @@ step_once (SIM_DESC sd) if (inst =3D=3D 0x00340002) { sim_engine_halt (sd, cpu, NULL, - cpu->state.pc, + ft32_cpu->pc, sim_stopped, SIM_SIGTRAP); goto escape; } @@ -390,8 +395,8 @@ step_once (SIM_DESC sd) k15 -=3D 0x8000; al =3D (inst >> FT32_FLD_AL_BIT) & LSBS (FT32_FLD_AL_SIZ); =20 - r_1v =3D cpu->state.regs[r_1]; - rimmv =3D (rimm & 0x400) ? nsigned (10, rimm) : cpu->state.regs[rimm & 0= x1f]; + r_1v =3D ft32_cpu->regs[r_1]; + rimmv =3D (rimm & 0x400) ? nsigned (10, rimm) : ft32_cpu->regs[rimm & 0x= 1f]; =20 bit_pos =3D rimmv & 31; bit_len =3D 0xf & (rimmv >> 5); @@ -400,24 +405,24 @@ step_once (SIM_DESC sd) =20 upper =3D (inst >> 27); =20 - insnpc =3D cpu->state.pc; - cpu->state.pc +=3D isize; + insnpc =3D ft32_cpu->pc; + ft32_cpu->pc +=3D isize; switch (upper) { case FT32_PAT_TOC: case FT32_PAT_TOCI: { - int take =3D (cr =3D=3D 3) || ((1 & (cpu->state.regs[28 + cr] >> cb)) =3D= =3D cv); + int take =3D (cr =3D=3D 3) || ((1 & (ft32_cpu->regs[28 + cr] >> cb)) =3D= =3D cv); if (take) { - cpu->state.cycles +=3D 1; + ft32_cpu->cycles +=3D 1; if (bt) - ft32_push (sd, cpu->state.pc); /* this is a call. */ + ft32_push (sd, ft32_cpu->pc); /* this is a call. */ if (upper =3D=3D FT32_PAT_TOC) - cpu->state.pc =3D pa << 2; + ft32_cpu->pc =3D pa << 2; else - cpu->state.pc =3D cpu->state.regs[r_2]; - if (cpu->state.pc =3D=3D 0x8) + ft32_cpu->pc =3D ft32_cpu->regs[r_2]; + if (ft32_cpu->pc =3D=3D 0x8) goto escape; } } @@ -449,7 +454,7 @@ step_once (SIM_DESC sd) ILLEGAL (); } if (upper =3D=3D FT32_PAT_ALUOP) - cpu->state.regs[r_d] =3D result; + ft32_cpu->regs[r_d] =3D result; else { uint32_t dwmask =3D 0; @@ -492,7 +497,7 @@ step_once (SIM_DESC sd) greater =3D (sign =3D=3D overflow) & !zero; greatereq =3D (sign =3D=3D overflow); =20 - cpu->state.regs[r_d] =3D ( + ft32_cpu->regs[r_d] =3D ( (above << 6) | (greater << 5) | (greatereq << 4) | @@ -505,54 +510,54 @@ step_once (SIM_DESC sd) break; =20 case FT32_PAT_LDK: - cpu->state.regs[r_d] =3D k20; + ft32_cpu->regs[r_d] =3D k20; break; =20 case FT32_PAT_LPM: - cpu->state.regs[r_d] =3D ft32_read_item (sd, dw, pa << 2); - cpu->state.cycles +=3D 1; + ft32_cpu->regs[r_d] =3D ft32_read_item (sd, dw, pa << 2); + ft32_cpu->cycles +=3D 1; break; =20 case FT32_PAT_LPMI: - cpu->state.regs[r_d] =3D ft32_read_item (sd, dw, cpu->state.regs[r_1= ] + k15); - cpu->state.cycles +=3D 1; + ft32_cpu->regs[r_d] =3D ft32_read_item (sd, dw, ft32_cpu->regs[r_1] = + k15); + ft32_cpu->cycles +=3D 1; break; =20 case FT32_PAT_STA: - cpu_mem_write (sd, dw, aa, cpu->state.regs[r_d]); + cpu_mem_write (sd, dw, aa, ft32_cpu->regs[r_d]); break; =20 case FT32_PAT_STI: - cpu_mem_write (sd, dw, cpu->state.regs[r_d] + k15, cpu->state.regs[r= _1]); + cpu_mem_write (sd, dw, ft32_cpu->regs[r_d] + k15, ft32_cpu->regs[r_1= ]); break; =20 case FT32_PAT_LDA: - cpu->state.regs[r_d] =3D cpu_mem_read (sd, dw, aa); - cpu->state.cycles +=3D 1; + ft32_cpu->regs[r_d] =3D cpu_mem_read (sd, dw, aa); + ft32_cpu->cycles +=3D 1; break; =20 case FT32_PAT_LDI: - cpu->state.regs[r_d] =3D cpu_mem_read (sd, dw, cpu->state.regs[r_1] = + k15); - cpu->state.cycles +=3D 1; + ft32_cpu->regs[r_d] =3D cpu_mem_read (sd, dw, ft32_cpu->regs[r_1] + = k15); + ft32_cpu->cycles +=3D 1; break; =20 case FT32_PAT_EXA: { uint32_t tmp; tmp =3D cpu_mem_read (sd, dw, aa); - cpu_mem_write (sd, dw, aa, cpu->state.regs[r_d]); - cpu->state.regs[r_d] =3D tmp; - cpu->state.cycles +=3D 1; + cpu_mem_write (sd, dw, aa, ft32_cpu->regs[r_d]); + ft32_cpu->regs[r_d] =3D tmp; + ft32_cpu->cycles +=3D 1; } break; =20 case FT32_PAT_EXI: { uint32_t tmp; - tmp =3D cpu_mem_read (sd, dw, cpu->state.regs[r_1] + k15); - cpu_mem_write (sd, dw, cpu->state.regs[r_1] + k15, cpu->state.regs[r_d]); - cpu->state.regs[r_d] =3D tmp; - cpu->state.cycles +=3D 1; + tmp =3D cpu_mem_read (sd, dw, ft32_cpu->regs[r_1] + k15); + cpu_mem_write (sd, dw, ft32_cpu->regs[r_1] + k15, ft32_cpu->regs[r_d]); + ft32_cpu->regs[r_d] =3D tmp; + ft32_cpu->cycles +=3D 1; } break; =20 @@ -561,41 +566,41 @@ step_once (SIM_DESC sd) break; =20 case FT32_PAT_LINK: - ft32_push (sd, cpu->state.regs[r_d]); - cpu->state.regs[r_d] =3D cpu->state.regs[FT32_HARD_SP]; - cpu->state.regs[FT32_HARD_SP] -=3D k16; - cpu->state.regs[FT32_HARD_SP] &=3D 0xffff; + ft32_push (sd, ft32_cpu->regs[r_d]); + ft32_cpu->regs[r_d] =3D ft32_cpu->regs[FT32_HARD_SP]; + ft32_cpu->regs[FT32_HARD_SP] -=3D k16; + ft32_cpu->regs[FT32_HARD_SP] &=3D 0xffff; break; =20 case FT32_PAT_UNLINK: - cpu->state.regs[FT32_HARD_SP] =3D cpu->state.regs[r_d]; - cpu->state.regs[FT32_HARD_SP] &=3D 0xffff; - cpu->state.regs[r_d] =3D ft32_pop (sd); + ft32_cpu->regs[FT32_HARD_SP] =3D ft32_cpu->regs[r_d]; + ft32_cpu->regs[FT32_HARD_SP] &=3D 0xffff; + ft32_cpu->regs[r_d] =3D ft32_pop (sd); break; =20 case FT32_PAT_POP: - cpu->state.cycles +=3D 1; - cpu->state.regs[r_d] =3D ft32_pop (sd); + ft32_cpu->cycles +=3D 1; + ft32_cpu->regs[r_d] =3D ft32_pop (sd); break; =20 case FT32_PAT_RETURN: - cpu->state.pc =3D ft32_pop (sd); + ft32_cpu->pc =3D ft32_pop (sd); break; =20 case FT32_PAT_FFUOP: switch (al) { case 0x0: - cpu->state.regs[r_d] =3D r_1v / rimmv; + ft32_cpu->regs[r_d] =3D r_1v / rimmv; break; case 0x1: - cpu->state.regs[r_d] =3D r_1v % rimmv; + ft32_cpu->regs[r_d] =3D r_1v % rimmv; break; case 0x2: - cpu->state.regs[r_d] =3D ft32sdiv (r_1v, rimmv); + ft32_cpu->regs[r_d] =3D ft32sdiv (r_1v, rimmv); break; case 0x3: - cpu->state.regs[r_d] =3D ft32smod (r_1v, rimmv); + ft32_cpu->regs[r_d] =3D ft32smod (r_1v, rimmv); break; =20 case 0x4: @@ -607,7 +612,7 @@ step_once (SIM_DESC sd) while ((GET_BYTE (a + i) !=3D 0) && (GET_BYTE (a + i) =3D=3D GET_BYTE (b + i))) i++; - cpu->state.regs[r_d] =3D GET_BYTE (a + i) - GET_BYTE (b + i); + ft32_cpu->regs[r_d] =3D GET_BYTE (a + i) - GET_BYTE (b + i); } break; =20 @@ -615,7 +620,7 @@ step_once (SIM_DESC sd) { /* memcpy instruction. */ uint32_t src =3D r_1v; - uint32_t dst =3D cpu->state.regs[r_d]; + uint32_t dst =3D ft32_cpu->regs[r_d]; uint32_t i; for (i =3D 0; i < (rimmv & 0x7fff); i++) PUT_BYTE (dst + i, GET_BYTE (src + i)); @@ -628,46 +633,46 @@ step_once (SIM_DESC sd) uint32_t i; for (i =3D 0; GET_BYTE (src + i) !=3D 0; i++) ; - cpu->state.regs[r_d] =3D i; + ft32_cpu->regs[r_d] =3D i; } break; case 0x7: { /* memset instruction. */ - uint32_t dst =3D cpu->state.regs[r_d]; + uint32_t dst =3D ft32_cpu->regs[r_d]; uint32_t i; for (i =3D 0; i < (rimmv & 0x7fff); i++) PUT_BYTE (dst + i, r_1v); } break; case 0x8: - cpu->state.regs[r_d] =3D r_1v * rimmv; + ft32_cpu->regs[r_d] =3D r_1v * rimmv; break; case 0x9: - cpu->state.regs[r_d] =3D ((uint64_t)r_1v * (uint64_t)rimmv) >> 32; + ft32_cpu->regs[r_d] =3D ((uint64_t)r_1v * (uint64_t)rimmv) >> 32; break; case 0xa: { /* stpcpy instruction. */ uint32_t src =3D r_1v; - uint32_t dst =3D cpu->state.regs[r_d]; + uint32_t dst =3D ft32_cpu->regs[r_d]; uint32_t i; for (i =3D 0; GET_BYTE (src + i) !=3D 0; i++) PUT_BYTE (dst + i, GET_BYTE (src + i)); PUT_BYTE (dst + i, 0); - cpu->state.regs[r_d] =3D dst + i; + ft32_cpu->regs[r_d] =3D dst + i; } break; case 0xe: { /* streamout instruction. */ uint32_t i; - uint32_t src =3D cpu->state.regs[r_1]; + uint32_t src =3D ft32_cpu->regs[r_1]; for (i =3D 0; i < rimmv; i +=3D (1 << dw)) { cpu_mem_write (sd, dw, - cpu->state.regs[r_d], + ft32_cpu->regs[r_d], cpu_mem_read (sd, dw, src)); src +=3D (1 << dw); } @@ -683,7 +688,7 @@ step_once (SIM_DESC sd) sim_io_eprintf (sd, "Unhandled pattern %d at %08x\n", upper, insnpc); ILLEGAL (); } - cpu->state.num_i++; + ft32_cpu->num_i++; =20 escape: ; @@ -721,6 +726,8 @@ ft32_lookup_register (SIM_CPU *cpu, int nr) * 31 - cc */ =20 + struct ft32_cpu_state *ft32_cpu =3D FT32_SIM_CPU (cpu); + if ((nr < 0) || (nr > 32)) { sim_io_eprintf (CPU_STATE (cpu), "unknown register %i\n", nr); @@ -730,15 +737,15 @@ ft32_lookup_register (SIM_CPU *cpu, int nr) switch (nr) { case FT32_FP_REGNUM: - return &cpu->state.regs[FT32_HARD_FP]; + return &ft32_cpu->regs[FT32_HARD_FP]; case FT32_SP_REGNUM: - return &cpu->state.regs[FT32_HARD_SP]; + return &ft32_cpu->regs[FT32_HARD_SP]; case FT32_CC_REGNUM: - return &cpu->state.regs[FT32_HARD_CC]; + return &ft32_cpu->regs[FT32_HARD_CC]; case FT32_PC_REGNUM: - return &cpu->state.pc; + return &ft32_cpu->pc; default: - return &cpu->state.regs[nr - 2]; + return &ft32_cpu->regs[nr - 2]; } } =20 @@ -779,13 +786,13 @@ ft32_reg_fetch (SIM_CPU *cpu, static sim_cia ft32_pc_get (SIM_CPU *cpu) { - return cpu->state.pc; + return FT32_SIM_CPU (cpu)->pc; } =20 static void ft32_pc_set (SIM_CPU *cpu, sim_cia newpc) { - cpu->state.pc =3D newpc; + FT32_SIM_CPU (cpu)->pc =3D newpc; } =20 /* Cover function of sim_state_free to free the cpu buffers as well. */ @@ -814,7 +821,8 @@ sim_open (SIM_OPEN_KIND kind, current_target_byte_order =3D BFD_ENDIAN_LITTLE; =20 /* The cpu data is kept in a separately allocated chunk of memory. */ - if (sim_cpu_alloc_all (sd, 1) !=3D SIM_RC_OK) + if (sim_cpu_alloc_all_extra (sd, 1, sizeof (struct ft32_cpu_state)) + !=3D SIM_RC_OK) { free_state (sd); return 0; @@ -884,6 +892,7 @@ sim_create_inferior (SIM_DESC sd, { uint32_t addr; sim_cpu *cpu =3D STATE_CPU (sd, 0); + struct ft32_cpu_state *ft32_cpu =3D FT32_SIM_CPU (cpu); host_callback *cb =3D STATE_CALLBACK (sd); =20 /* Set the PC. */ @@ -911,10 +920,10 @@ sim_create_inferior (SIM_DESC sd, cb->argv =3D STATE_PROG_ARGV (sd); cb->envp =3D STATE_PROG_ENVP (sd); =20 - cpu->state.regs[FT32_HARD_SP] =3D addr; - cpu->state.num_i =3D 0; - cpu->state.cycles =3D 0; - cpu->state.next_tick_cycle =3D 100000; + ft32_cpu->regs[FT32_HARD_SP] =3D addr; + ft32_cpu->num_i =3D 0; + ft32_cpu->cycles =3D 0; + ft32_cpu->next_tick_cycle =3D 100000; =20 return SIM_RC_OK; } diff --git a/sim/ft32/sim-main.h b/sim/ft32/sim-main.h index 1c597372320..3a002efd359 100644 --- a/sim/ft32/sim-main.h +++ b/sim/ft32/sim-main.h @@ -21,19 +21,12 @@ #ifndef SIM_MAIN_H #define SIM_MAIN_H =20 +#define SIM_HAVE_COMMON_SIM_CPU + #include "sim-basics.h" #include "sim-base.h" #include "bfd.h" =20 #include "ft32-sim.h" =20 -struct _sim_cpu { - - /* The following are internal simulator state variables: */ - - struct ft32_cpu_state state; - - sim_cpu_base base; -}; - #endif