From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1521) id 4176E3857B9B; Fri, 23 Dec 2022 02:56:22 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 4176E3857B9B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1671764182; bh=R8A1L1UOCdmTjV6MzeegsWCyqvHxAR+oHWEYPr8UfCM=; h=From:To:Subject:Date:From; b=kO52XKxWIjAer8f/c+5s6GuExyHF5UwbDlmVoGiw6dOgjU8/ATYkmJY/1oidMg/pi +lX+G/pHMBe7qKRKeWGCD3H2ZlV0o8UcB1tQRfVKklQBPyaIzFtHBGHWKmVaHONx0k 1K2YKxYZZx0As5Hk9LDK3n1F3sOjDmVBjJPEYVOY= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Michael Frysinger To: gdb-cvs@sourceware.org Subject: [binutils-gdb] sim: mcore: replace custom "word" type with int32_t X-Act-Checkin: binutils-gdb X-Git-Author: Mike Frysinger X-Git-Refname: refs/heads/master X-Git-Oldrev: be2e4e65380f625f01648678798aaecf5a66bc48 X-Git-Newrev: 4c337f2dd3df1f97d9dc17ace5708f5cdc4512dc Message-Id: <20221223025622.4176E3857B9B@sourceware.org> Date: Fri, 23 Dec 2022 02:56:22 +0000 (GMT) List-Id: https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D4c337f2dd3df= 1f97d9dc17ace5708f5cdc4512dc commit 4c337f2dd3df1f97d9dc17ace5708f5cdc4512dc Author: Mike Frysinger Date: Thu Dec 22 21:53:51 2022 -0500 sim: mcore: replace custom "word" type with int32_t =20 This is a 32-bit architecture with 32-bit registers, so replace the custom "word" long int typedef with an explicit int32_t. This is a correctness fix since long will be 64-bits on most 64-bit hosts. Diff: --- sim/mcore/interp.c | 48 ++++++++++++++++++++++++------------------------ sim/mcore/sim-main.h | 15 ++++++--------- 2 files changed, 30 insertions(+), 33 deletions(-) diff --git a/sim/mcore/interp.c b/sim/mcore/interp.c index 40bd77d850d..8465f56d2d7 100644 --- a/sim/mcore/interp.c +++ b/sim/mcore/interp.c @@ -258,7 +258,7 @@ iu_carry (unsigned long a, unsigned long b, int cin) #ifdef WATCHFUNCTIONS =20 #define MAXWL 80 -word WL[MAXWL]; +int32_t WL[MAXWL]; char * WLstr[MAXWL]; =20 int ENDWL=3D0; @@ -267,7 +267,7 @@ int WLcyc[MAXWL]; int WLcnts[MAXWL]; int WLmax[MAXWL]; int WLmin[MAXWL]; -word WLendpc; +int32_t WLendpc; int WLbcyc; int WLW; #endif @@ -295,8 +295,8 @@ step_once (SIM_DESC sd, SIM_CPU *cpu) { struct mcore_sim_cpu *mcore_cpu =3D MCORE_SIM_CPU (cpu); int needfetch; - word ibuf; - word pc; + int32_t ibuf; + int32_t pc; unsigned short inst; int memops; int bonus_cycles; @@ -304,7 +304,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu) int w; int cycs; #ifdef WATCHFUNCTIONS - word WLhash; + int32_t WLhash; #endif =20 pc =3D CPU_PC_GET (cpu); @@ -330,7 +330,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu) =20 /* TODO: Unindent this block. */ { - word oldpc; + int32_t oldpc; =20 insts ++; =20 @@ -404,7 +404,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu) #endif =20 if (tracing) - fprintf (stderr, "%.4lx: inst =3D %.4x ", pc, inst); + fprintf (stderr, "%.4x: inst =3D %.4x ", pc, inst); =20 oldpc =3D pc; =20 @@ -498,7 +498,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu) break; case 0x4: /* ldq */ { - word addr =3D gr[RD]; + int32_t addr =3D gr[RD]; int regno =3D 4; /* always r4-r7 */ =20 bonus_cycles++; @@ -514,7 +514,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu) break; case 0x5: /* stq */ { - word addr =3D gr[RD]; + int32_t addr =3D gr[RD]; int regno =3D 4; /* always r4-r7 */ =20 memops +=3D 4; @@ -530,7 +530,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu) break; case 0x6: /* ldm */ { - word addr =3D gr[0]; + int32_t addr =3D gr[0]; int regno =3D RD; =20 /* bonus cycle is really only needed if @@ -549,7 +549,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu) break; case 0x7: /* stm */ { - word addr =3D gr[0]; + int32_t addr =3D gr[0]; int regno =3D RD; =20 /* this should be removed! */ @@ -580,7 +580,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu) case 0xC: /* jmp */ pc =3D gr[RD]; if (tracing && RD =3D=3D 15) - fprintf (stderr, "Func return, r2 =3D %lxx, r3 =3D %lx\n", + fprintf (stderr, "Func return, r2 =3D %xx, r3 =3D %x\n", gr[2], gr[3]); bonus_cycles++; needfetch =3D 1; @@ -593,7 +593,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu) break; case 0xE: /* ff1 */ { - word tmp, i; + int32_t tmp, i; tmp =3D gr[RD]; for (i =3D 0; !(tmp & 0x80000000) && i < 32; i++) tmp <<=3D 1; @@ -602,7 +602,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu) break; case 0xF: /* brev */ { - word tmp; + int32_t tmp; tmp =3D gr[RD]; tmp =3D ((tmp & 0xaaaaaaaa) >> 1) | ((tmp & 0x55555555) << 1); tmp =3D ((tmp & 0xcccccccc) >> 2) | ((tmp & 0x33333333) << 2); @@ -662,7 +662,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu) break; case 0x9: /* tstnbz */ { - word tmp =3D gr[RD]; + int32_t tmp =3D gr[RD]; NEW_C ((tmp & 0xFF000000) !=3D 0 && (tmp & 0x00FF0000) !=3D 0 && (tmp & 0x0000FF00) !=3D 0 && (tmp & 0x000000FF) !=3D 0); @@ -708,7 +708,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu) } bonus_cycles +=3D 2; /* min. is 3, so add 2, plus ticks above */ if (tracing) - fprintf (stderr, " mult %lx by %lx to give %lx", + fprintf (stderr, " mult %x by %x to give %x", gr[RD], gr[RS], gr[RD] * gr[RS]); gr[RD] =3D gr[RD] * gr[RS]; break; @@ -791,7 +791,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu) case 0x12: /* mov */ gr[RD] =3D gr[RS]; if (tracing) - fprintf (stderr, "MOV %lx into reg %d", gr[RD], RD); + fprintf (stderr, "MOV %x into reg %d", gr[RD], RD); break; =20 case 0x13: /* bgenr */ @@ -915,7 +915,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu) exe =3D 0; =20 /* unsigned divide */ - gr[RD] =3D (word) ((unsigned int) gr[RD] / (unsigned int)gr[1] ); + gr[RD] =3D (int32_t) ((unsigned int) gr[RD] / (unsigned int)gr[1] ); =20 /* compute bonus_cycles for divu */ for (r1nlz =3D 0; ((r1 & 0x80000000) =3D=3D 0) && (r1nlz < 32); r1nlz ++) @@ -1020,7 +1020,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu) unsigned long tmp =3D gr[RD]; if (imm =3D=3D 0) { - word cbit; + int32_t cbit; cbit =3D C_VALUE(); NEW_C (tmp); gr[RD] =3D (cbit << 31) | (tmp >> 1); @@ -1097,7 +1097,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu) case 0x7C: case 0x7D: case 0x7E: /* lrw */ gr[RX] =3D rlat ((pc + ((inst & 0xFF) << 2)) & 0xFFFFFFFC); if (tracing) - fprintf (stderr, "LRW of 0x%x from 0x%lx to reg %d", + fprintf (stderr, "LRW of 0x%x from 0x%x to reg %d", rlat ((pc + ((inst & 0xFF) << 2)) & 0xFFFFFFFC), (pc + ((inst & 0xFF) << 2)) & 0xFFFFFFFC, RX); memops++; @@ -1106,7 +1106,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu) gr[15] =3D pc; if (tracing) fprintf (stderr, - "func call: r2 =3D %lx r3 =3D %lx r4 =3D %lx r5 =3D %lx r6 =3D %lx = r7 =3D %lx\n", + "func call: r2 =3D %x r3 =3D %x r4 =3D %x r5 =3D %x r6 =3D %x r7 = =3D %x\n", gr[2], gr[3], gr[4], gr[5], gr[6], gr[7]); case 0x70: /* jmpi */ pc =3D rlat ((pc + ((inst & 0xFF) << 2)) & 0xFFFFFFFC); @@ -1121,7 +1121,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu) case 0x8C: case 0x8D: case 0x8E: case 0x8F: /* ld */ gr[RX] =3D rlat (gr[RD] + ((inst >> 2) & 0x003C)); if (tracing) - fprintf (stderr, "load reg %d from 0x%lx with 0x%lx", + fprintf (stderr, "load reg %d from 0x%x with 0x%x", RX, gr[RD] + ((inst >> 2) & 0x003C), gr[RX]); memops++; @@ -1132,7 +1132,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu) case 0x9C: case 0x9D: case 0x9E: case 0x9F: /* st */ wlat (gr[RD] + ((inst >> 2) & 0x003C), gr[RX]); if (tracing) - fprintf (stderr, "store reg %d (containing 0x%lx) to 0x%lx", + fprintf (stderr, "store reg %d (containing 0x%x) to 0x%x", RX, gr[RX], gr[RD] + ((inst >> 2) & 0x003C)); memops++; @@ -1472,7 +1472,7 @@ sim_create_inferior (SIM_DESC sd, struct bfd *prog_bf= d, } =20 /* Claim some memory for the pointers and strings. */ - pointers =3D hi_stack - sizeof(word) * (nenv+1+nargs+1); + pointers =3D hi_stack - sizeof(int32_t) * (nenv+1+nargs+1); pointers &=3D ~3; /* must be 4-byte aligned */ gr[0] =3D pointers; =20 diff --git a/sim/mcore/sim-main.h b/sim/mcore/sim-main.h index 23e7ae64b05..7290e02131e 100644 --- a/sim/mcore/sim-main.h +++ b/sim/mcore/sim-main.h @@ -20,9 +20,6 @@ along with this program. If not, see . */ #define SIM_MAIN_H =20 #include "sim-basics.h" - -typedef long int word; - #include "sim-base.h" #include "bfd.h" =20 @@ -39,10 +36,10 @@ typedef long int word; gdb/config/mcore/tm-mcore.h file in the REGISTER_NAMES macro. */ struct mcore_regset { - word gregs[16]; /* primary registers */ - word alt_gregs[16]; /* alt register file */ - word cregs[32]; /* control registers */ - word pc; + int32_t gregs[16]; /* primary registers */ + int32_t alt_gregs[16]; /* alt register file */ + int32_t cregs[32]; /* control registers */ + int32_t pc; }; #define LAST_VALID_CREG 32 /* only 0..12 implemented */ #define NUM_MCORE_REGS (16 + 16 + LAST_VALID_CREG + 1) @@ -52,11 +49,11 @@ struct mcore_sim_cpu { { struct mcore_regset regs; /* Used by the fetch/store reg helpers to access registers linearly. = */ - word asints[NUM_MCORE_REGS]; + int32_t asints[NUM_MCORE_REGS]; }; =20 /* Used to switch between gregs/alt_gregs based on the control state. */ - word *active_gregs; + int32_t *active_gregs; =20 int ticks; int stalls;