From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1521) id A71BC3858D32; Tue, 27 Dec 2022 05:38:50 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A71BC3858D32 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1672119530; bh=OIPsldaHUedmMIVjsh+zbAH2YTa9Z2IAbwGWN9VSCYc=; h=From:To:Subject:Date:From; b=HsONhs1QcsaYEswA9CayqfhHKQ/7fp9nbHA3daGMrwEYr8igJovDzqAJFBbV3G2y6 iiGZtLNKrNJdoaDj7eYzD3kRBm/L1BkFQDeyDXKi5zMiBFOtKKRvNtiVURzx1ax3uE 8BPwJ/nzEyR9+Sypadm1HzZJ7rF2/+BOgF6+2tXk= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Michael Frysinger To: gdb-cvs@sourceware.org Subject: [binutils-gdb] sim: mips: unify itable generation (a bit) X-Act-Checkin: binutils-gdb X-Git-Author: Mike Frysinger X-Git-Refname: refs/heads/master X-Git-Oldrev: 4c45662c0fd49bf25d3a014dec54224e9d11e90f X-Git-Newrev: 67c952d109873321b45b6de99cdbefbcd4249745 Message-Id: <20221227053850.A71BC3858D32@sourceware.org> Date: Tue, 27 Dec 2022 05:38:50 +0000 (GMT) List-Id: https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D67c952d10987= 3321b45b6de99cdbefbcd4249745 commit 67c952d109873321b45b6de99cdbefbcd4249745 Author: Mike Frysinger Date: Sun Dec 25 01:48:01 2022 -0500 sim: mips: unify itable generation (a bit) =20 The m16 & multi targets generate itable once even when all the other modules are generated multiple times. The default igen target will generate itable with everything else out of convenience. This means flags are passed which don't affect the generated itable there. =20 We can unify the itable generation by making sure the right -F/-M filter variables are passed down. Since there's already a dedicated rule & variable in the multi build mode, generalize that and switch the m16 & igen builds over too. =20 I spent a lot of time staring at this code, building for diff mips targets, and exploring all the shell code paths. I think this is safe, but only time (and users) will really tell. Diff: --- sim/configure | 4 ++++ sim/mips/Makefile.in | 54 +++++++++++++++++++----------------------------= ---- sim/mips/acinclude.m4 | 2 ++ 3 files changed, 26 insertions(+), 34 deletions(-) diff --git a/sim/configure b/sim/configure index 10458921d50..093142f3c03 100755 --- a/sim/configure +++ b/sim/configure @@ -16601,6 +16601,10 @@ __EOF__ =20 else SIM_MIPS_MULTI_SRC=3Ddoesnt-exist.c + SIM_MIPS_IGEN_ITABLE_FLAGS=3D'$(SIM_MIPS_IGEN_FLAGS)' + if test "x$SIM_MIPS_GEN" =3D x"M16"; then : + as_fn_append SIM_MIPS_IGEN_ITABLE_FLAGS ' $(SIM_MIPS_M16_FLAGS)' +fi =20 fi SIM_MIPS_IGEN_FLAGS=3D"-F ${sim_mips_igen_filter} ${sim_mips_igen_machine}" diff --git a/sim/mips/Makefile.in b/sim/mips/Makefile.in index 3861e4e5077..4cd59642119 100644 --- a/sim/mips/Makefile.in +++ b/sim/mips/Makefile.in @@ -92,7 +92,7 @@ IGEN_INCLUDE=3D\ # NB: Since these can be built by a number of generators, care # must be taken to ensure that they are only dependant on # one of those generators. -BUILT_SRC_FROM_GEN =3D \ +BUILT_SRC_FROM_IGEN_ITABLE =3D \ itable.h \ itable.c \ =20 @@ -100,8 +100,24 @@ SIM_IGEN_ALL =3D tmp-igen SIM_M16_ALL =3D tmp-m16 SIM_MULTI_ALL =3D tmp-multi =20 -$(BUILT_SRC_FROM_GEN): $(SIM_$(SIM_MIPS_GEN)_ALL) +$(BUILT_SRC_FROM_IGEN_ITABLE): tmp-itable =20 +tmp-itable: $(IGEN_INSN) $(IGEN_DC) $(IGEN) $(IGEN_INCLUDE) + $(ECHO_IGEN) $(IGEN_RUN) \ + $(IGEN_TRACE) \ + -I $(srcdir) \ + -Werror \ + -Wnodiscard \ + -Wnowidth \ + -Wnounimplemented \ + $(SIM_MIPS_IGEN_ITABLE_FLAGS) \ + -G gen-direct-access \ + -G gen-zero-r0 \ + -i $(IGEN_INSN) \ + -n itable.h -ht itable.h \ + -n itable.c -t itable.c \ + # + $(SILENCE) touch $@ =20 =20 BUILT_SRC_FROM_IGEN =3D \ @@ -145,8 +161,6 @@ tmp-igen: $(IGEN_INSN) $(IGEN_DC) $(IGEN) $(IGEN_INCLUD= E) -n model.c -m model.c \ -n support.h -hf support.h \ -n support.c -f support.c \ - -n itable.h -ht itable.h \ - -n itable.c -t itable.c \ -n engine.h -he engine.h \ -n engine.c -e engine.c \ -n irun.c -r irun.c @@ -228,25 +242,12 @@ tmp-m16: $(IGEN_INSN) $(IGEN_DC) $(IGEN) $(IGEN_INCLU= DE) -n m32_support.h -hf m32_support.h \ -n m32_support.c -f m32_support.c \ # - $(ECHO_IGEN) $(IGEN_RUN) \ - $(IGEN_TRACE) \ - -I $(srcdir) \ - -Werror \ - -Wnodiscard \ - -Wnowidth \ - $(SIM_MIPS_IGEN_FLAGS) $(SIM_MIPS_M16_FLAGS) \ - -G gen-direct-access \ - -G gen-zero-r0 \ - -i $(IGEN_INSN) \ - -n itable.h -ht itable.h \ - -n itable.c -t itable.c \ - # $(SILENCE) touch $@ =20 BUILT_SRC_FROM_MULTI =3D $(SIM_MIPS_MULTI_SRC) =20 $(BUILT_SRC_FROM_MULTI): tmp-multi -tmp-multi: tmp-mach-multi tmp-itable-multi tmp-run-multi +tmp-multi: tmp-mach-multi tmp-run-multi tmp-mach-multi: $(IGEN_INSN) $(IGEN_DC) $(IGEN) $(IGEN_INCLUDE) for t in $(SIM_MIPS_MULTI_IGEN_CONFIGS); do \ p=3D`echo $${t} | sed -e 's/:.*//'` ; \ @@ -292,21 +293,6 @@ tmp-mach-multi: $(IGEN_INSN) $(IGEN_DC) $(IGEN) $(IGEN= _INCLUDE) || exit; \ done $(SILENCE) touch $@ -tmp-itable-multi: $(IGEN_INSN) $(IGEN_DC) $(IGEN) $(IGEN_INCLUDE) - $(ECHO_IGEN) $(IGEN_RUN) \ - $(IGEN_TRACE) \ - -I $(srcdir) \ - -Werror \ - -Wnodiscard \ - -Wnowidth \ - $(SIM_MIPS_IGEN_ITABLE_FLAGS) \ - -G gen-direct-access \ - -G gen-zero-r0 \ - -i $(IGEN_INSN) \ - -n itable.h -ht itable.h \ - -n itable.c -t itable.c \ - # - $(SILENCE) touch $@ tmp-run-multi: $(srcdir)/m16run.c $(srcdir)/micromipsrun.c for t in $(SIM_MIPS_MULTI_IGEN_CONFIGS); do \ case $${t} in \ @@ -347,7 +333,7 @@ tmp-run-multi: $(srcdir)/m16run.c $(srcdir)/micromipsru= n.c $(SILENCE) touch $@ =20 clean-extra: - rm -f $(BUILT_SRC_FROM_GEN) + rm -f $(BUILT_SRC_FROM_IGEN_ITABLE) rm -f $(BUILT_SRC_FROM_IGEN) rm -f $(BUILT_SRC_FROM_M16) rm -f $(BUILT_SRC_FROM_MULTI) diff --git a/sim/mips/acinclude.m4 b/sim/mips/acinclude.m4 index 116dc1e6141..452dfc84514 100644 --- a/sim/mips/acinclude.m4 +++ b/sim/mips/acinclude.m4 @@ -321,6 +321,8 @@ __EOF__ ], [dnl dnl For clean-extra target. SIM_MIPS_MULTI_SRC=3Ddoesnt-exist.c + SIM_MIPS_IGEN_ITABLE_FLAGS=3D'$(SIM_MIPS_IGEN_FLAGS)' + AS_VAR_IF([SIM_MIPS_GEN], ["M16"], [AS_VAR_APPEND([SIM_MIPS_IGEN_ITABLE_= FLAGS], [' $(SIM_MIPS_M16_FLAGS)'])]) ]) SIM_MIPS_IGEN_FLAGS=3D"-F ${sim_mips_igen_filter} ${sim_mips_igen_machine}" SIM_MIPS_M16_FLAGS=3D"-F ${sim_mips_m16_filter} ${sim_mips_m16_machine}"