From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1521) id CA5E83858D32; Tue, 27 Dec 2022 05:39:00 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org CA5E83858D32 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1672119540; bh=zcGXK9MO6ueIamtKwSa6G7ipzTHgVOjr6FpJ2PWGQ4k=; h=From:To:Subject:Date:From; b=YwSbli60iTUCTnBANdaWRX8S9UGRpCGpMMRrTcJuNPsKSfFXsu8Rn0xn5SC6g2tmh eYLH1PDA7RN9eAN4LcMdU6sXBCnel/s9XEIKMKgLoCN6RtcBsWb7v6jKvP3DiJtqsJ hcZw6p1jMf/4blC+ic3KgxacFfQvix3DDzg7I02g= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Michael Frysinger To: gdb-cvs@sourceware.org Subject: [binutils-gdb] sim: mips: rename "igen" generation mode to "single" X-Act-Checkin: binutils-gdb X-Git-Author: Mike Frysinger X-Git-Refname: refs/heads/master X-Git-Oldrev: 49d3ce6c2e9c7b2d9f3c761a9e736bdaceb756e6 X-Git-Newrev: 07f60ed83166c163794b2f5987b217e22e1ef6b2 Message-Id: <20221227053900.CA5E83858D32@sourceware.org> Date: Tue, 27 Dec 2022 05:39:00 +0000 (GMT) List-Id: https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D07f60ed83166= c163794b2f5987b217e22e1ef6b2 commit 07f60ed83166c163794b2f5987b217e22e1ef6b2 Author: Mike Frysinger Date: Sun Dec 25 02:37:10 2022 -0500 sim: mips: rename "igen" generation mode to "single" =20 The naming in here has grown organically and is confusing to follow. Originally there was only one set of rules for generating code from the igen sources, so calling it "tmp-igen" and such made sense. But when other multigen modes were added ("m16" & "multi") which also used igen, it's not clear what's common igen and what's specific to this generation mode. So rename the set of rules from "igen" to "single" so it's easier to follow. Diff: --- sim/Makefile.in | 2 +- sim/configure | 50 +++++++++++++++++++++++++----------------------= --- sim/mips/Makefile.in | 18 +++++++++--------- sim/mips/acinclude.m4 | 50 +++++++++++++++++++++++++----------------------= --- 4 files changed, 60 insertions(+), 60 deletions(-) diff --git a/sim/Makefile.in b/sim/Makefile.in index 667b3192e5d..a1884d6b0fe 100644 --- a/sim/Makefile.in +++ b/sim/Makefile.in @@ -1114,12 +1114,12 @@ SIM_INLINE =3D @SIM_INLINE@ SIM_MIPS_BITSIZE =3D @SIM_MIPS_BITSIZE@ SIM_MIPS_FPU_BITSIZE =3D @SIM_MIPS_FPU_BITSIZE@ SIM_MIPS_GEN =3D @SIM_MIPS_GEN@ -SIM_MIPS_IGEN_FLAGS =3D @SIM_MIPS_IGEN_FLAGS@ SIM_MIPS_IGEN_ITABLE_FLAGS =3D @SIM_MIPS_IGEN_ITABLE_FLAGS@ SIM_MIPS_M16_FLAGS =3D @SIM_MIPS_M16_FLAGS@ SIM_MIPS_MULTI_IGEN_CONFIGS =3D @SIM_MIPS_MULTI_IGEN_CONFIGS@ SIM_MIPS_MULTI_OBJ =3D @SIM_MIPS_MULTI_OBJ@ SIM_MIPS_MULTI_SRC =3D @SIM_MIPS_MULTI_SRC@ +SIM_MIPS_SINGLE_FLAGS =3D @SIM_MIPS_SINGLE_FLAGS@ SIM_MIPS_SUBTARGET =3D @SIM_MIPS_SUBTARGET@ SIM_PRIMARY_TARGET =3D @SIM_PRIMARY_TARGET@ SIM_RISCV_BITSIZE =3D @SIM_RISCV_BITSIZE@ diff --git a/sim/configure b/sim/configure index 093142f3c03..b9626ce0ac3 100755 --- a/sim/configure +++ b/sim/configure @@ -647,7 +647,7 @@ SIM_MIPS_MULTI_IGEN_CONFIGS SIM_MIPS_IGEN_ITABLE_FLAGS SIM_MIPS_GEN SIM_MIPS_M16_FLAGS -SIM_MIPS_IGEN_FLAGS +SIM_MIPS_SINGLE_FLAGS SIM_MIPS_FPU_BITSIZE SIM_MIPS_BITSIZE SIM_MIPS_SUBTARGET @@ -16390,19 +16390,19 @@ esac $as_echo "$SIM_MIPS_FPU_BITSIZE" >&6; } =20 =20 -SIM_MIPS_GEN=3DIGEN -sim_mips_igen_machine=3D"-M mipsIV" +SIM_MIPS_GEN=3DSINGLE +sim_mips_single_machine=3D"-M mipsIV" sim_mips_m16_machine=3D"-M mips16,mipsIII" -sim_mips_igen_filter=3D"32,64,f" +sim_mips_single_filter=3D"32,64,f" sim_mips_m16_filter=3D"16" case ${target} in #( mips*tx39*) : - SIM_MIPS_GEN=3DIGEN - sim_mips_igen_filter=3D"32,f" - sim_mips_igen_machine=3D"-M r3900" ;; #( + SIM_MIPS_GEN=3DSINGLE + sim_mips_single_filter=3D"32,f" + sim_mips_single_machine=3D"-M r3900" ;; #( mips64vr41*) : SIM_MIPS_GEN=3DM16 - sim_mips_igen_machine=3D"-M vr4100" + sim_mips_single_machine=3D"-M vr4100" sim_mips_m16_machine=3D"-M vr4100" ;; #( mips64*) : SIM_MIPS_GEN=3DMULTI @@ -16429,36 +16429,36 @@ case ${target} in #( mips32r2:mips32r2,mips3d,mips16,mips16e,mdmx,dsp,dsp2,smartmips:32,f= :mipsisa32r2" sim_mips_multi_default=3Dmipsisa32r2 ;; #( mipsisa32r6*) : - SIM_MIPS_GEN=3DIGEN - sim_mips_igen_machine=3D"-M mips32r6" - sim_mips_igen_filter=3D"32,f" ;; #( + SIM_MIPS_GEN=3DSINGLE + sim_mips_single_machine=3D"-M mips32r6" + sim_mips_single_filter=3D"32,f" ;; #( mipsisa32*) : SIM_MIPS_GEN=3DM16 - sim_mips_igen_machine=3D"-M mips32,mips16,mips16e,smartmips" + sim_mips_single_machine=3D"-M mips32,mips16,mips16e,smartmips" sim_mips_m16_machine=3D"-M mips16,mips16e,mips32" - sim_mips_igen_filter=3D"32,f" ;; #( + sim_mips_single_filter=3D"32,f" ;; #( mipsisa64r2*) : SIM_MIPS_GEN=3DM16 - sim_mips_igen_machine=3D"-M mips64r2,mips3d,mips16,mips16e,mdmx,dsp,ds= p2" + sim_mips_single_machine=3D"-M mips64r2,mips3d,mips16,mips16e,mdmx,dsp,= dsp2" sim_mips_m16_machine=3D"-M mips16,mips16e,mips64r2" ;; #( mipsisa64r6*) : - SIM_MIPS_GEN=3DIGEN - sim_mips_igen_machine=3D"-M mips64r6" ;; #( + SIM_MIPS_GEN=3DSINGLE + sim_mips_single_machine=3D"-M mips64r6" ;; #( mipsisa64sb1*) : - SIM_MIPS_GEN=3DIGEN - sim_mips_igen_machine=3D"-M mips64,mips3d,sb1" ;; #( + SIM_MIPS_GEN=3DSINGLE + sim_mips_single_machine=3D"-M mips64,mips3d,sb1" ;; #( mipsisa64*) : SIM_MIPS_GEN=3DM16 - sim_mips_igen_machine=3D"-M mips64,mips3d,mips16,mips16e,mdmx" + sim_mips_single_machine=3D"-M mips64,mips3d,mips16,mips16e,mdmx" sim_mips_m16_machine=3D"-M mips16,mips16e,mips64" ;; #( mips*lsi*) : SIM_MIPS_GEN=3DM16 - sim_mips_igen_machine=3D"-M mipsIII,mips16" + sim_mips_single_machine=3D"-M mipsIII,mips16" sim_mips_m16_machine=3D"-M mips16,mipsIII" - sim_mips_igen_filter=3D"32,f" ;; #( + sim_mips_single_filter=3D"32,f" ;; #( mips*) : - SIM_MIPS_GEN=3DIGEN - sim_mips_igen_filter=3D"32,f" ;; #( + SIM_MIPS_GEN=3DSINGLE + sim_mips_single_filter=3D"32,f" ;; #( *) : ;; esac @@ -16601,13 +16601,13 @@ __EOF__ =20 else SIM_MIPS_MULTI_SRC=3Ddoesnt-exist.c - SIM_MIPS_IGEN_ITABLE_FLAGS=3D'$(SIM_MIPS_IGEN_FLAGS)' + SIM_MIPS_IGEN_ITABLE_FLAGS=3D'$(SIM_MIPS_SINGLE_FLAGS)' if test "x$SIM_MIPS_GEN" =3D x"M16"; then : as_fn_append SIM_MIPS_IGEN_ITABLE_FLAGS ' $(SIM_MIPS_M16_FLAGS)' fi =20 fi -SIM_MIPS_IGEN_FLAGS=3D"-F ${sim_mips_igen_filter} ${sim_mips_igen_machine}" +SIM_MIPS_SINGLE_FLAGS=3D"-F ${sim_mips_single_filter} ${sim_mips_single_ma= chine}" SIM_MIPS_M16_FLAGS=3D"-F ${sim_mips_m16_filter} ${sim_mips_m16_machine}" =20 =20 diff --git a/sim/mips/Makefile.in b/sim/mips/Makefile.in index 187f574f249..d9b489858c5 100644 --- a/sim/mips/Makefile.in +++ b/sim/mips/Makefile.in @@ -3,7 +3,7 @@ =20 ## COMMON_PRE_CONFIG_FRAG =20 -SIM_MIPS_IGEN_FLAGS =3D @SIM_MIPS_IGEN_FLAGS@ +SIM_MIPS_SINGLE_FLAGS =3D @SIM_MIPS_SINGLE_FLAGS@ SIM_MIPS_M16_FLAGS =3D @SIM_MIPS_M16_FLAGS@ SIM_MIPS_GEN =3D @SIM_MIPS_GEN@ SIM_MIPS_MULTI_IGEN_CONFIGS =3D @SIM_MIPS_MULTI_IGEN_CONFIGS@ @@ -15,7 +15,7 @@ arch =3D mips # Object files created by various simulator generators. =20 =20 -SIM_IGEN_OBJ =3D \ +SIM_SINGLE_OBJ =3D \ support.o \ itable.o \ semantics.o \ @@ -86,11 +86,11 @@ IGEN_INCLUDE=3D\ $(srcdir)/mips3264r2.igen \ $(srcdir)/mips3264r6.igen \ =20 -SIM_IGEN_ALL =3D tmp-igen +SIM_SINGLE_ALL =3D tmp-single SIM_M16_ALL =3D tmp-m16 SIM_MULTI_ALL =3D tmp-multi =20 -BUILT_SRC_FROM_IGEN =3D \ +BUILT_SRC_FROM_SINGLE =3D \ icache.h \ icache.c \ idecode.h \ @@ -105,15 +105,15 @@ BUILT_SRC_FROM_IGEN =3D \ engine.c \ irun.c \ =20 -$(BUILT_SRC_FROM_IGEN): tmp-igen +$(BUILT_SRC_FROM_SINGLE): tmp-single =20 -tmp-igen: $(IGEN_INSN) $(IGEN_DC) $(IGEN) $(IGEN_INCLUDE) +tmp-single: $(IGEN_INSN) $(IGEN_DC) $(IGEN) $(IGEN_INCLUDE) $(ECHO_IGEN) $(IGEN_RUN) \ $(IGEN_TRACE) \ -I $(srcdir) \ -Werror \ -Wnodiscard \ - $(SIM_MIPS_IGEN_FLAGS) \ + $(SIM_MIPS_SINGLE_FLAGS) \ -G gen-direct-access \ -G gen-zero-r0 \ -B 32 \ @@ -192,7 +192,7 @@ tmp-m16: $(IGEN_INSN) $(IGEN_DC) $(IGEN) $(IGEN_INCLUDE) -I $(srcdir) \ -Werror \ -Wnodiscard \ - $(SIM_MIPS_IGEN_FLAGS) \ + $(SIM_MIPS_SINGLE_FLAGS) \ -G gen-direct-access \ -G gen-zero-r0 \ -B 32 \ @@ -303,7 +303,7 @@ tmp-run-multi: $(srcdir)/m16run.c $(srcdir)/micromipsru= n.c $(SILENCE) touch $@ =20 clean-extra: - rm -f $(BUILT_SRC_FROM_IGEN) + rm -f $(BUILT_SRC_FROM_SINGLE) rm -f $(BUILT_SRC_FROM_M16) rm -f $(BUILT_SRC_FROM_MULTI) rm -f tmp-* diff --git a/sim/mips/acinclude.m4 b/sim/mips/acinclude.m4 index 452dfc84514..111dd87618e 100644 --- a/sim/mips/acinclude.m4 +++ b/sim/mips/acinclude.m4 @@ -59,19 +59,19 @@ AC_MSG_RESULT([$SIM_MIPS_FPU_BITSIZE]) AC_SUBST(SIM_MIPS_FPU_BITSIZE) =20 dnl Select the IGEN architecture. -SIM_MIPS_GEN=3DIGEN -sim_mips_igen_machine=3D"-M mipsIV" +SIM_MIPS_GEN=3DSINGLE +sim_mips_single_machine=3D"-M mipsIV" sim_mips_m16_machine=3D"-M mips16,mipsIII" -sim_mips_igen_filter=3D"32,64,f" +sim_mips_single_filter=3D"32,64,f" sim_mips_m16_filter=3D"16" AS_CASE([${target}], [mips*tx39*], [dnl - SIM_MIPS_GEN=3DIGEN - sim_mips_igen_filter=3D"32,f" - sim_mips_igen_machine=3D"-M r3900"], + SIM_MIPS_GEN=3DSINGLE + sim_mips_single_filter=3D"32,f" + sim_mips_single_machine=3D"-M r3900"], [mips64vr41*], [dnl SIM_MIPS_GEN=3DM16 - sim_mips_igen_machine=3D"-M vr4100" + sim_mips_single_machine=3D"-M vr4100" sim_mips_m16_machine=3D"-M vr4100"], [mips64*], [dnl SIM_MIPS_GEN=3DMULTI @@ -98,36 +98,36 @@ AS_CASE([${target}], mips32r2:mips32r2,mips3d,mips16,mips16e,mdmx,dsp,dsp2,smartmips:32,f= :mipsisa32r2" sim_mips_multi_default=3Dmipsisa32r2], [mipsisa32r6*], [dnl - SIM_MIPS_GEN=3DIGEN - sim_mips_igen_machine=3D"-M mips32r6" - sim_mips_igen_filter=3D"32,f"], + SIM_MIPS_GEN=3DSINGLE + sim_mips_single_machine=3D"-M mips32r6" + sim_mips_single_filter=3D"32,f"], [mipsisa32*], [dnl SIM_MIPS_GEN=3DM16 - sim_mips_igen_machine=3D"-M mips32,mips16,mips16e,smartmips" + sim_mips_single_machine=3D"-M mips32,mips16,mips16e,smartmips" sim_mips_m16_machine=3D"-M mips16,mips16e,mips32" - sim_mips_igen_filter=3D"32,f"], + sim_mips_single_filter=3D"32,f"], [mipsisa64r2*], [dnl SIM_MIPS_GEN=3DM16 - sim_mips_igen_machine=3D"-M mips64r2,mips3d,mips16,mips16e,mdmx,dsp,ds= p2" + sim_mips_single_machine=3D"-M mips64r2,mips3d,mips16,mips16e,mdmx,dsp,= dsp2" sim_mips_m16_machine=3D"-M mips16,mips16e,mips64r2"], [mipsisa64r6*], [dnl - SIM_MIPS_GEN=3DIGEN - sim_mips_igen_machine=3D"-M mips64r6"], + SIM_MIPS_GEN=3DSINGLE + sim_mips_single_machine=3D"-M mips64r6"], [mipsisa64sb1*], [dnl - SIM_MIPS_GEN=3DIGEN - sim_mips_igen_machine=3D"-M mips64,mips3d,sb1"], + SIM_MIPS_GEN=3DSINGLE + sim_mips_single_machine=3D"-M mips64,mips3d,sb1"], [mipsisa64*], [dnl SIM_MIPS_GEN=3DM16 - sim_mips_igen_machine=3D"-M mips64,mips3d,mips16,mips16e,mdmx" + sim_mips_single_machine=3D"-M mips64,mips3d,mips16,mips16e,mdmx" sim_mips_m16_machine=3D"-M mips16,mips16e,mips64"], [mips*lsi*], [dnl SIM_MIPS_GEN=3DM16 - sim_mips_igen_machine=3D"-M mipsIII,mips16" + sim_mips_single_machine=3D"-M mipsIII,mips16" sim_mips_m16_machine=3D"-M mips16,mipsIII" - sim_mips_igen_filter=3D"32,f"], + sim_mips_single_filter=3D"32,f"], [mips*], [dnl - SIM_MIPS_GEN=3DIGEN - sim_mips_igen_filter=3D"32,f"]) + SIM_MIPS_GEN=3DSINGLE + sim_mips_single_filter=3D"32,f"]) =20 dnl The MULTI generator can combine several simulation engines into one. dnl executable. A configuration which uses the MULTI should set two @@ -321,12 +321,12 @@ __EOF__ ], [dnl dnl For clean-extra target. SIM_MIPS_MULTI_SRC=3Ddoesnt-exist.c - SIM_MIPS_IGEN_ITABLE_FLAGS=3D'$(SIM_MIPS_IGEN_FLAGS)' + SIM_MIPS_IGEN_ITABLE_FLAGS=3D'$(SIM_MIPS_SINGLE_FLAGS)' AS_VAR_IF([SIM_MIPS_GEN], ["M16"], [AS_VAR_APPEND([SIM_MIPS_IGEN_ITABLE_= FLAGS], [' $(SIM_MIPS_M16_FLAGS)'])]) ]) -SIM_MIPS_IGEN_FLAGS=3D"-F ${sim_mips_igen_filter} ${sim_mips_igen_machine}" +SIM_MIPS_SINGLE_FLAGS=3D"-F ${sim_mips_single_filter} ${sim_mips_single_ma= chine}" SIM_MIPS_M16_FLAGS=3D"-F ${sim_mips_m16_filter} ${sim_mips_m16_machine}" -AC_SUBST(SIM_MIPS_IGEN_FLAGS) +AC_SUBST(SIM_MIPS_SINGLE_FLAGS) AC_SUBST(SIM_MIPS_M16_FLAGS) AC_SUBST(SIM_MIPS_GEN) AC_SUBST(SIM_MIPS_IGEN_ITABLE_FLAGS)