From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1521) id C0C2D3858C20; Tue, 10 Jan 2023 06:23:20 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C0C2D3858C20 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1673331800; bh=r0zByGNCWJbxdexZC7eLAhpLtadm7wI1uwmBH6bwTfs=; h=From:To:Subject:Date:From; b=hJLkgPS91UNSgMzYnrNSkJkRH+dlisiLJWWwhR3ZJmIg27AZ48KaDzMdTAx4gYS3T OpLeqGCJ1L7c5P752wijdyEMqjzUMwXyrfx9ZRViqg/bTj+jDfYwCAHxCyPOxakZ0W gyiufy42mj7Et+URerOsJdKsxy2WfxqHKxdZsVQQ= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Michael Frysinger To: gdb-cvs@sourceware.org Subject: [binutils-gdb] sim: d10v: move libsim.a creation to top-level X-Act-Checkin: binutils-gdb X-Git-Author: Mike Frysinger X-Git-Refname: refs/heads/master X-Git-Oldrev: eaa678ecc30ed6632d1315e99951eed741649d67 X-Git-Newrev: faf177dff014660285856c2c6bada1595f7268ba Message-Id: <20230110062320.C0C2D3858C20@sourceware.org> Date: Tue, 10 Jan 2023 06:23:20 +0000 (GMT) List-Id: https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3Dfaf177dff014= 660285856c2c6bada1595f7268ba commit faf177dff014660285856c2c6bada1595f7268ba Author: Mike Frysinger Date: Mon Dec 26 21:13:08 2022 -0500 sim: d10v: move libsim.a creation to top-level =20 The objects are still compiled in the subdir, but the creation of the archive itself is in the top-level. This is a required step before we can move compilation itself up, and makes it easier to review. =20 The downside is that each object compile is a recursive make instead of a single one. On my 4 core system, it adds ~100msec to the build per port, so it's not great, but it shouldn't be a big deal. This will go away of course once the top-level compiles objects. Diff: --- sim/Makefile.in | 232 ++++++++++++++++++++++++++++++-----------------= ---- sim/d10v/Makefile.in | 8 +- sim/d10v/local.mk | 21 +++++ 3 files changed, 157 insertions(+), 104 deletions(-) diff --git a/sim/Makefile.in b/sim/Makefile.in index e12fe8f5408..3705b4ea78d 100644 --- a/sim/Makefile.in +++ b/sim/Makefile.in @@ -174,79 +174,80 @@ TESTS =3D testsuite/common/bits32m0$(EXEEXT) \ =20 @SIM_ENABLE_ARCH_cris_TRUE@am__append_33 =3D $(cris_BUILD_OUTPUTS) @SIM_ENABLE_ARCH_cris_TRUE@am__append_34 =3D $(cris_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_d10v_TRUE@am__append_35 =3D d10v/run -@SIM_ENABLE_ARCH_d10v_TRUE@am__append_36 =3D d10v/simops.h -@SIM_ENABLE_ARCH_d10v_TRUE@am__append_37 =3D $(d10v_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_d10v_TRUE@am__append_38 =3D d10v/gencode -@SIM_ENABLE_ARCH_d10v_TRUE@am__append_39 =3D $(d10v_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_erc32_TRUE@am__append_40 =3D erc32/run erc32/sis -@SIM_ENABLE_ARCH_erc32_TRUE@am__append_41 =3D sim-%D-install-exec-local -@SIM_ENABLE_ARCH_erc32_TRUE@am__append_42 =3D sim-erc32-uninstall-local -@SIM_ENABLE_ARCH_examples_TRUE@am__append_43 =3D example-synacor/run -@SIM_ENABLE_ARCH_frv_TRUE@am__append_44 =3D frv/run -@SIM_ENABLE_ARCH_frv_TRUE@am__append_45 =3D frv/eng.h -@SIM_ENABLE_ARCH_frv_TRUE@am__append_46 =3D $(frv_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_d10v_TRUE@am__append_35 =3D d10v/libsim.a +@SIM_ENABLE_ARCH_d10v_TRUE@am__append_36 =3D d10v/run +@SIM_ENABLE_ARCH_d10v_TRUE@am__append_37 =3D d10v/simops.h +@SIM_ENABLE_ARCH_d10v_TRUE@am__append_38 =3D $(d10v_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_d10v_TRUE@am__append_39 =3D d10v/gencode +@SIM_ENABLE_ARCH_d10v_TRUE@am__append_40 =3D $(d10v_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_erc32_TRUE@am__append_41 =3D erc32/run erc32/sis +@SIM_ENABLE_ARCH_erc32_TRUE@am__append_42 =3D sim-%D-install-exec-local +@SIM_ENABLE_ARCH_erc32_TRUE@am__append_43 =3D sim-erc32-uninstall-local +@SIM_ENABLE_ARCH_examples_TRUE@am__append_44 =3D example-synacor/run +@SIM_ENABLE_ARCH_frv_TRUE@am__append_45 =3D frv/run +@SIM_ENABLE_ARCH_frv_TRUE@am__append_46 =3D frv/eng.h @SIM_ENABLE_ARCH_frv_TRUE@am__append_47 =3D $(frv_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_ft32_TRUE@am__append_48 =3D ft32/run -@SIM_ENABLE_ARCH_h8300_TRUE@am__append_49 =3D h8300/run -@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_50 =3D iq2000/run -@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_51 =3D iq2000/eng.h -@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_52 =3D $(iq2000_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_frv_TRUE@am__append_48 =3D $(frv_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_ft32_TRUE@am__append_49 =3D ft32/run +@SIM_ENABLE_ARCH_h8300_TRUE@am__append_50 =3D h8300/run +@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_51 =3D iq2000/run +@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_52 =3D iq2000/eng.h @SIM_ENABLE_ARCH_iq2000_TRUE@am__append_53 =3D $(iq2000_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_lm32_TRUE@am__append_54 =3D lm32/run -@SIM_ENABLE_ARCH_lm32_TRUE@am__append_55 =3D lm32_SIM_EXTRA_HW_DEVICES=3D"= $(lm32_SIM_EXTRA_HW_DEVICES)" -@SIM_ENABLE_ARCH_lm32_TRUE@am__append_56 =3D lm32/eng.h -@SIM_ENABLE_ARCH_lm32_TRUE@am__append_57 =3D $(lm32_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_54 =3D $(iq2000_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_lm32_TRUE@am__append_55 =3D lm32/run +@SIM_ENABLE_ARCH_lm32_TRUE@am__append_56 =3D lm32_SIM_EXTRA_HW_DEVICES=3D"= $(lm32_SIM_EXTRA_HW_DEVICES)" +@SIM_ENABLE_ARCH_lm32_TRUE@am__append_57 =3D lm32/eng.h @SIM_ENABLE_ARCH_lm32_TRUE@am__append_58 =3D $(lm32_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_m32c_TRUE@am__append_59 =3D m32c/run -@SIM_ENABLE_ARCH_m32c_TRUE@am__append_60 =3D $(m32c_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_m32c_TRUE@am__append_61 =3D m32c/opc2c -@SIM_ENABLE_ARCH_m32c_TRUE@am__append_62 =3D \ +@SIM_ENABLE_ARCH_lm32_TRUE@am__append_59 =3D $(lm32_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_m32c_TRUE@am__append_60 =3D m32c/run +@SIM_ENABLE_ARCH_m32c_TRUE@am__append_61 =3D $(m32c_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_m32c_TRUE@am__append_62 =3D m32c/opc2c +@SIM_ENABLE_ARCH_m32c_TRUE@am__append_63 =3D \ @SIM_ENABLE_ARCH_m32c_TRUE@ $(m32c_BUILD_OUTPUTS) \ @SIM_ENABLE_ARCH_m32c_TRUE@ m32c/m32c.c.log \ @SIM_ENABLE_ARCH_m32c_TRUE@ m32c/r8c.c.log =20 -@SIM_ENABLE_ARCH_m32r_TRUE@am__append_63 =3D m32r/run -@SIM_ENABLE_ARCH_m32r_TRUE@am__append_64 =3D m32r_SIM_EXTRA_HW_DEVICES=3D"= $(m32r_SIM_EXTRA_HW_DEVICES)" -@SIM_ENABLE_ARCH_m32r_TRUE@am__append_65 =3D \ +@SIM_ENABLE_ARCH_m32r_TRUE@am__append_64 =3D m32r/run +@SIM_ENABLE_ARCH_m32r_TRUE@am__append_65 =3D m32r_SIM_EXTRA_HW_DEVICES=3D"= $(m32r_SIM_EXTRA_HW_DEVICES)" +@SIM_ENABLE_ARCH_m32r_TRUE@am__append_66 =3D \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/eng.h \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/engx.h \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/eng2.h =20 -@SIM_ENABLE_ARCH_m32r_TRUE@am__append_66 =3D $(m32r_BUILD_OUTPUTS) @SIM_ENABLE_ARCH_m32r_TRUE@am__append_67 =3D $(m32r_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_68 =3D m68hc11/run -@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_69 =3D m68hc11_SIM_EXTRA_HW_DEVIC= ES=3D"$(m68hc11_SIM_EXTRA_HW_DEVICES)" -@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_70 =3D $(m68hc11_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_71 =3D m68hc11/gencode -@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_72 =3D $(m68hc11_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_mcore_TRUE@am__append_73 =3D mcore/run -@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_74 =3D microblaze/run -@SIM_ENABLE_ARCH_mips_TRUE@am__append_75 =3D mips/run -@SIM_ENABLE_ARCH_mips_TRUE@am__append_76 =3D mips_SIM_EXTRA_HW_DEVICES=3D"= $(mips_SIM_EXTRA_HW_DEVICES)" -@SIM_ENABLE_ARCH_mips_TRUE@am__append_77 =3D mips/itable.h \ +@SIM_ENABLE_ARCH_m32r_TRUE@am__append_68 =3D $(m32r_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_69 =3D m68hc11/run +@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_70 =3D m68hc11_SIM_EXTRA_HW_DEVIC= ES=3D"$(m68hc11_SIM_EXTRA_HW_DEVICES)" +@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_71 =3D $(m68hc11_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_72 =3D m68hc11/gencode +@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_73 =3D $(m68hc11_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_mcore_TRUE@am__append_74 =3D mcore/run +@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_75 =3D microblaze/run +@SIM_ENABLE_ARCH_mips_TRUE@am__append_76 =3D mips/run +@SIM_ENABLE_ARCH_mips_TRUE@am__append_77 =3D mips_SIM_EXTRA_HW_DEVICES=3D"= $(mips_SIM_EXTRA_HW_DEVICES)" +@SIM_ENABLE_ARCH_mips_TRUE@am__append_78 =3D mips/itable.h \ @SIM_ENABLE_ARCH_mips_TRUE@ $(SIM_MIPS_MULTI_SRC) -@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_78 = =3D \ +@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_79 = =3D \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ $(mips_BUILT_SR= C_FROM_GEN_MODE_SINGLE) \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/stamp-gen-= mode-single =20 -@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_79 =3D \ +@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_80 =3D \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ $(mips_BUILT_SRC_F= ROM_GEN_MODE_M16_M16) \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ $(mips_BUILT_SRC_F= ROM_GEN_MODE_M16_M32) \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/stamp-gen-mod= e-m16-m16 \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/stamp-gen-mod= e-m16-m32 =20 -@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_80 =3D= \ +@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_81 =3D= \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ $(SIM_MIPS_MULTI= _SRC) \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/stamp-gen-m= ode-multi-igen \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/stamp-gen-m= ode-multi-run =20 -@SIM_ENABLE_ARCH_mips_TRUE@am__append_81 =3D $(mips_BUILD_OUTPUTS) @SIM_ENABLE_ARCH_mips_TRUE@am__append_82 =3D $(mips_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_mips_TRUE@am__append_83 =3D mips/multi-include.h mips/mul= ti-run.c -@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_84 =3D mn10300/run -@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_85 =3D mn10300_SIM_EXTRA_HW_DEVIC= ES=3D"$(mn10300_SIM_EXTRA_HW_DEVICES)" -@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_86 =3D \ +@SIM_ENABLE_ARCH_mips_TRUE@am__append_83 =3D $(mips_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_mips_TRUE@am__append_84 =3D mips/multi-include.h mips/mul= ti-run.c +@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_85 =3D mn10300/run +@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_86 =3D mn10300_SIM_EXTRA_HW_DEVIC= ES=3D"$(mn10300_SIM_EXTRA_HW_DEVICES)" +@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_87 =3D \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/icache.h \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/idecode.h \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/semantics.h \ @@ -255,29 +256,29 @@ TESTS =3D testsuite/common/bits32m0$(EXEEXT) \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/itable.h \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/engine.h =20 -@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_87 =3D $(mn10300_BUILD_OUTPUTS) @SIM_ENABLE_ARCH_mn10300_TRUE@am__append_88 =3D $(mn10300_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_moxie_TRUE@am__append_89 =3D moxie/run -@SIM_ENABLE_ARCH_msp430_TRUE@am__append_90 =3D msp430/run -@SIM_ENABLE_ARCH_or1k_TRUE@am__append_91 =3D or1k/run -@SIM_ENABLE_ARCH_or1k_TRUE@am__append_92 =3D or1k/eng.h -@SIM_ENABLE_ARCH_or1k_TRUE@am__append_93 =3D $(or1k_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_89 =3D $(mn10300_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_moxie_TRUE@am__append_90 =3D moxie/run +@SIM_ENABLE_ARCH_msp430_TRUE@am__append_91 =3D msp430/run +@SIM_ENABLE_ARCH_or1k_TRUE@am__append_92 =3D or1k/run +@SIM_ENABLE_ARCH_or1k_TRUE@am__append_93 =3D or1k/eng.h @SIM_ENABLE_ARCH_or1k_TRUE@am__append_94 =3D $(or1k_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_ppc_TRUE@am__append_95 =3D ppc/run ppc/psim -@SIM_ENABLE_ARCH_pru_TRUE@am__append_96 =3D pru/run -@SIM_ENABLE_ARCH_riscv_TRUE@am__append_97 =3D riscv/run -@SIM_ENABLE_ARCH_rl78_TRUE@am__append_98 =3D rl78/run -@SIM_ENABLE_ARCH_rx_TRUE@am__append_99 =3D rx/run -@SIM_ENABLE_ARCH_sh_TRUE@am__append_100 =3D sh/run -@SIM_ENABLE_ARCH_sh_TRUE@am__append_101 =3D \ +@SIM_ENABLE_ARCH_or1k_TRUE@am__append_95 =3D $(or1k_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_ppc_TRUE@am__append_96 =3D ppc/run ppc/psim +@SIM_ENABLE_ARCH_pru_TRUE@am__append_97 =3D pru/run +@SIM_ENABLE_ARCH_riscv_TRUE@am__append_98 =3D riscv/run +@SIM_ENABLE_ARCH_rl78_TRUE@am__append_99 =3D rl78/run +@SIM_ENABLE_ARCH_rx_TRUE@am__append_100 =3D rx/run +@SIM_ENABLE_ARCH_sh_TRUE@am__append_101 =3D sh/run +@SIM_ENABLE_ARCH_sh_TRUE@am__append_102 =3D \ @SIM_ENABLE_ARCH_sh_TRUE@ sh/code.c \ @SIM_ENABLE_ARCH_sh_TRUE@ sh/ppi.c =20 -@SIM_ENABLE_ARCH_sh_TRUE@am__append_102 =3D $(sh_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_sh_TRUE@am__append_103 =3D sh/gencode -@SIM_ENABLE_ARCH_sh_TRUE@am__append_104 =3D $(sh_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_v850_TRUE@am__append_105 =3D v850/run -@SIM_ENABLE_ARCH_v850_TRUE@am__append_106 =3D \ +@SIM_ENABLE_ARCH_sh_TRUE@am__append_103 =3D $(sh_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_sh_TRUE@am__append_104 =3D sh/gencode +@SIM_ENABLE_ARCH_sh_TRUE@am__append_105 =3D $(sh_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_v850_TRUE@am__append_106 =3D v850/run +@SIM_ENABLE_ARCH_v850_TRUE@am__append_107 =3D \ @SIM_ENABLE_ARCH_v850_TRUE@ v850/icache.h \ @SIM_ENABLE_ARCH_v850_TRUE@ v850/idecode.h \ @SIM_ENABLE_ARCH_v850_TRUE@ v850/semantics.h \ @@ -286,8 +287,8 @@ TESTS =3D testsuite/common/bits32m0$(EXEEXT) \ @SIM_ENABLE_ARCH_v850_TRUE@ v850/itable.h \ @SIM_ENABLE_ARCH_v850_TRUE@ v850/engine.h =20 -@SIM_ENABLE_ARCH_v850_TRUE@am__append_107 =3D $(v850_BUILD_OUTPUTS) @SIM_ENABLE_ARCH_v850_TRUE@am__append_108 =3D $(v850_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_v850_TRUE@am__append_109 =3D $(v850_BUILD_OUTPUTS) subdir =3D . ACLOCAL_M4 =3D $(top_srcdir)/aclocal.m4 am__aclocal_m4_deps =3D $(top_srcdir)/../config/acx.m4 \ @@ -463,6 +464,18 @@ cris_libsim_a_AR =3D $(AR) $(ARFLAGS) @SIM_ENABLE_ARCH_cris_TRUE@ cris/traps.o am_cris_libsim_a_OBJECTS =3D cris_libsim_a_OBJECTS =3D $(am_cris_libsim_a_OBJECTS) +d10v_libsim_a_AR =3D $(AR) $(ARFLAGS) +@SIM_ENABLE_ARCH_d10v_TRUE@d10v_libsim_a_DEPENDENCIES =3D \ +@SIM_ENABLE_ARCH_d10v_TRUE@ $(common_libcommon_a_OBJECTS) \ +@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/interp.o $(patsubst \ +@SIM_ENABLE_ARCH_d10v_TRUE@ %,d10v/%,$(SIM_NEW_COMMON_OBJS)) \ +@SIM_ENABLE_ARCH_d10v_TRUE@ $(patsubst \ +@SIM_ENABLE_ARCH_d10v_TRUE@ %,d10v/dv-%.o,$(SIM_HW_DEVICES)) \ +@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/endian.o d10v/modules.o \ +@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/sim-resume.o d10v/simops.o \ +@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/table.o +am_d10v_libsim_a_OBJECTS =3D +d10v_libsim_a_OBJECTS =3D $(am_d10v_libsim_a_OBJECTS) igen_libigen_a_AR =3D $(AR) $(ARFLAGS) igen_libigen_a_LIBADD =3D @SIM_ENABLE_IGEN_TRUE@am_igen_libigen_a_OBJECTS =3D \ @@ -809,12 +822,12 @@ SOURCES =3D $(aarch64_libsim_a_SOURCES) $(arm_libsim_= a_SOURCES) \ $(avr_libsim_a_SOURCES) $(bfin_libsim_a_SOURCES) \ $(bpf_libsim_a_SOURCES) $(common_libcommon_a_SOURCES) \ $(cr16_libsim_a_SOURCES) $(cris_libsim_a_SOURCES) \ - $(igen_libigen_a_SOURCES) $(aarch64_run_SOURCES) \ - $(arm_run_SOURCES) $(avr_run_SOURCES) $(bfin_run_SOURCES) \ - $(bpf_run_SOURCES) $(cr16_gencode_SOURCES) $(cr16_run_SOURCES) \ - $(cris_run_SOURCES) $(cris_rvdummy_SOURCES) \ - $(d10v_gencode_SOURCES) $(d10v_run_SOURCES) \ - $(erc32_run_SOURCES) erc32/sis.c \ + $(d10v_libsim_a_SOURCES) $(igen_libigen_a_SOURCES) \ + $(aarch64_run_SOURCES) $(arm_run_SOURCES) $(avr_run_SOURCES) \ + $(bfin_run_SOURCES) $(bpf_run_SOURCES) $(cr16_gencode_SOURCES) \ + $(cr16_run_SOURCES) $(cris_run_SOURCES) \ + $(cris_rvdummy_SOURCES) $(d10v_gencode_SOURCES) \ + $(d10v_run_SOURCES) $(erc32_run_SOURCES) erc32/sis.c \ $(example_synacor_run_SOURCES) $(frv_run_SOURCES) \ $(ft32_run_SOURCES) $(h8300_run_SOURCES) \ $(igen_filter_SOURCES) $(igen_gen_SOURCES) \ @@ -1366,32 +1379,33 @@ srcroot =3D $(srcdir)/.. SUBDIRS =3D @subdirs@ $(SIM_SUBDIRS) AM_MAKEFLAGS =3D SIM_NEW_COMMON_OBJS_=3D"$(SIM_NEW_COMMON_OBJS)" \ $(am__append_3) $(am__append_16) $(am__append_30) \ - $(am__append_55) $(am__append_64) $(am__append_69) \ - $(am__append_76) $(am__append_85) + $(am__append_56) $(am__append_65) $(am__append_70) \ + $(am__append_77) $(am__append_86) pkginclude_HEADERS =3D $(am__append_1) noinst_LIBRARIES =3D common/libcommon.a $(am__append_5) $(am__append_8) \ $(am__append_10) $(am__append_12) $(am__append_14) \ - $(am__append_17) $(am__append_22) $(am__append_28) + $(am__append_17) $(am__append_22) $(am__append_28) \ + $(am__append_35) BUILT_SOURCES =3D $(am__append_19) $(am__append_24) $(am__append_32) \ - $(am__append_36) $(am__append_45) $(am__append_51) \ - $(am__append_56) $(am__append_65) $(am__append_77) \ - $(am__append_86) $(am__append_92) $(am__append_101) \ - $(am__append_106) + $(am__append_37) $(am__append_46) $(am__append_52) \ + $(am__append_57) $(am__append_66) $(am__append_78) \ + $(am__append_87) $(am__append_93) $(am__append_102) \ + $(am__append_107) CLEANFILES =3D common/version.c common/version.c-stamp \ testsuite/common/bits-gen testsuite/common/bits32m0.c \ testsuite/common/bits32m31.c testsuite/common/bits64m0.c \ testsuite/common/bits64m63.c -DISTCLEANFILES =3D $(am__append_83) +DISTCLEANFILES =3D $(am__append_84) MOSTLYCLEANFILES =3D core $(common_HW_CONFIG_H_TARGETS) $(patsubst \ %,%/stamp-hw,$(SIM_ENABLED_ARCHES)) \ $(common_GEN_MODULES_C_TARGETS) $(patsubst \ %,%/stamp-modules,$(SIM_ENABLED_ARCHES)) $(am__append_7) \ site-sim-config.exp testrun.log testrun.sum $(am__append_21) \ - $(am__append_27) $(am__append_34) $(am__append_39) \ - $(am__append_47) $(am__append_53) $(am__append_58) \ - $(am__append_62) $(am__append_67) $(am__append_72) \ - $(am__append_82) $(am__append_88) $(am__append_94) \ - $(am__append_104) $(am__append_108) + $(am__append_27) $(am__append_34) $(am__append_40) \ + $(am__append_48) $(am__append_54) $(am__append_59) \ + $(am__append_63) $(am__append_68) $(am__append_73) \ + $(am__append_83) $(am__append_89) $(am__append_95) \ + $(am__append_105) $(am__append_109) AM_CFLAGS =3D $(WERROR_CFLAGS) $(WARN_CFLAGS) AM_CPPFLAGS =3D $(INCGNU) -I$(srcroot)/include -I../bfd -I.. \ $(SIM_HW_CFLAGS) $(SIM_INLINE) -I$(srcdir)/common \ @@ -1403,14 +1417,14 @@ LINK_FOR_BUILD =3D $(CC_FOR_BUILD) $(CFLAGS_FOR_BUI= LD) $(LDFLAGS_FOR_BUILD) -o $@ SIM_ALL_RECURSIVE_DEPS =3D common/libcommon.a \ $(common_HW_CONFIG_H_TARGETS) $(common_GEN_MODULES_C_TARGETS) \ $(am__append_4) $(am__append_20) $(am__append_25) \ - $(am__append_33) $(am__append_37) $(am__append_46) \ - $(am__append_52) $(am__append_57) $(am__append_60) \ - $(am__append_66) $(am__append_70) $(am__append_81) \ - $(am__append_87) $(am__append_93) $(am__append_102) \ - $(am__append_107) + $(am__append_33) $(am__append_38) $(am__append_47) \ + $(am__append_53) $(am__append_58) $(am__append_61) \ + $(am__append_67) $(am__append_71) $(am__append_82) \ + $(am__append_88) $(am__append_94) $(am__append_103) \ + $(am__append_108) SIM_INSTALL_DATA_LOCAL_DEPS =3D=20 -SIM_INSTALL_EXEC_LOCAL_DEPS =3D $(am__append_41) -SIM_UNINSTALL_LOCAL_DEPS =3D $(am__append_42) +SIM_INSTALL_EXEC_LOCAL_DEPS =3D $(am__append_42) +SIM_UNINSTALL_LOCAL_DEPS =3D $(am__append_43) common_libcommon_a_SOURCES =3D \ common/callback.c \ common/portability.c \ @@ -1787,6 +1801,18 @@ testsuite_common_CPPFLAGS =3D \ @SIM_ENABLE_ARCH_cris_TRUE@ cris/mloopv32f.c \ @SIM_ENABLE_ARCH_cris_TRUE@ cris/stamp-mloop-v32f =20 +@SIM_ENABLE_ARCH_d10v_TRUE@d10v_libsim_a_SOURCES =3D=20 +@SIM_ENABLE_ARCH_d10v_TRUE@d10v_libsim_a_LIBADD =3D \ +@SIM_ENABLE_ARCH_d10v_TRUE@ $(common_libcommon_a_OBJECTS) \ +@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/interp.o \ +@SIM_ENABLE_ARCH_d10v_TRUE@ $(patsubst %,d10v/%,$(SIM_NEW_COMMON_OBJS)) \ +@SIM_ENABLE_ARCH_d10v_TRUE@ $(patsubst %,d10v/dv-%.o,$(SIM_HW_DEVICES)) \ +@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/endian.o \ +@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/modules.o \ +@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/sim-resume.o \ +@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/simops.o \ +@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/table.o + @SIM_ENABLE_ARCH_d10v_TRUE@d10v_run_SOURCES =3D=20 @SIM_ENABLE_ARCH_d10v_TRUE@d10v_run_LDADD =3D \ @SIM_ENABLE_ARCH_d10v_TRUE@ d10v/nrun.o \ @@ -1966,8 +1992,8 @@ testsuite_common_CPPFLAGS =3D \ @SIM_ENABLE_ARCH_mips_TRUE@mips_BUILD_OUTPUTS =3D \ @SIM_ENABLE_ARCH_mips_TRUE@ $(mips_BUILT_SRC_FROM_IGEN_ITABLE) \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/stamp-igen-itable \ -@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_78) $(am__append_79) \ -@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_80) +@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_79) $(am__append_80) \ +@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_81) @SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_TRACE =3D # -G omit-line-numbers # -G= trace-rule-selection -G trace-rule-rejection -G trace-entries # -G trace-a= ll @SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN =3D $(srcdir)/mips/mips.igen @SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN_INC =3D \ @@ -2396,6 +2422,14 @@ cris/libsim.a: $(cris_libsim_a_OBJECTS) $(cris_libsi= m_a_DEPENDENCIES) $(EXTRA_cr $(AM_V_at)-rm -f cris/libsim.a $(AM_V_AR)$(cris_libsim_a_AR) cris/libsim.a $(cris_libsim_a_OBJECTS) $(cr= is_libsim_a_LIBADD) $(AM_V_at)$(RANLIB) cris/libsim.a +d10v/$(am__dirstamp): + @$(MKDIR_P) d10v + @: > d10v/$(am__dirstamp) + +d10v/libsim.a: $(d10v_libsim_a_OBJECTS) $(d10v_libsim_a_DEPENDENCIES) $(EX= TRA_d10v_libsim_a_DEPENDENCIES) d10v/$(am__dirstamp) + $(AM_V_at)-rm -f d10v/libsim.a + $(AM_V_AR)$(d10v_libsim_a_AR) d10v/libsim.a $(d10v_libsim_a_OBJECTS) $(d1= 0v_libsim_a_LIBADD) + $(AM_V_at)$(RANLIB) d10v/libsim.a igen/$(am__dirstamp): @$(MKDIR_P) igen @: > igen/$(am__dirstamp) @@ -2502,9 +2536,6 @@ cris/rvdummy.$(OBJEXT): cris/$(am__dirstamp) \ cris/rvdummy$(EXEEXT): $(cris_rvdummy_OBJECTS) $(cris_rvdummy_DEPENDENCIES= ) $(EXTRA_cris_rvdummy_DEPENDENCIES) cris/$(am__dirstamp) @rm -f cris/rvdummy$(EXEEXT) $(AM_V_CCLD)$(LINK) $(cris_rvdummy_OBJECTS) $(cris_rvdummy_LDADD) $(LIBS) -d10v/$(am__dirstamp): - @$(MKDIR_P) d10v - @: > d10v/$(am__dirstamp) d10v/$(DEPDIR)/$(am__dirstamp): @$(MKDIR_P) d10v/$(DEPDIR) @: > d10v/$(DEPDIR)/$(am__dirstamp) @@ -3924,6 +3955,13 @@ testsuite/common/bits64m63.c: testsuite/common/bits-= gen$(EXEEXT) testsuite/commo @SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_GEN)cpu=3Dcrisv32f mach=3Dcrisv32 SUFFI= X=3Dv32 FLAGS=3D"with-scache with-profile=3Dfn" EXTRAFILES=3D"$(CGEN_CPU_SE= MSW)"; $(CGEN_GEN_CPU_DECODE) @SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change $= (srcdir)/cris/semv32-switch.c $(srcdir)/cris/semcrisv32f-switch.c @SIM_ENABLE_ARCH_cris_TRUE@cris/cpuv32.h cris/cpuv32.c cris/semcrisv32f-sw= itch.c cris/modelv32.c cris/decodev32.c cris/decodev32.h: @CGEN_MAINT@ cris= /cgen-cpu-decode-v32f +@SIM_ENABLE_ARCH_d10v_TRUE@$(d10v_libsim_a_OBJECTS) $(d10v_libsim_a_LIBADD= ): d10v/hw-config.h + +@SIM_ENABLE_ARCH_d10v_TRUE@d10v/%.o: d10v/%.c +@SIM_ENABLE_ARCH_d10v_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@= F) + +@SIM_ENABLE_ARCH_d10v_TRUE@d10v/%.o: common/%.c +@SIM_ENABLE_ARCH_d10v_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@= F) @SIM_ENABLE_ARCH_d10v_TRUE@d10v/modules.c: | $(d10v_BUILD_OUTPUTS) =20 # These rules are copied from automake, but tweaked to use FOR_BUILD varia= bles. diff --git a/sim/d10v/Makefile.in b/sim/d10v/Makefile.in index a2ccd4e1b77..6f209a2db1f 100644 --- a/sim/d10v/Makefile.in +++ b/sim/d10v/Makefile.in @@ -17,12 +17,6 @@ =20 ## COMMON_PRE_CONFIG_FRAG =20 -SIM_OBJS =3D \ - interp.o \ - $(SIM_NEW_COMMON_OBJS) \ - sim-resume.o \ - table.o \ - simops.o \ - endian.o +SIM_LIBSIM =3D =20 ## COMMON_POST_CONFIG_FRAG diff --git a/sim/d10v/local.mk b/sim/d10v/local.mk index 2556845ed1d..c9ca13f720c 100644 --- a/sim/d10v/local.mk +++ b/sim/d10v/local.mk @@ -16,6 +16,27 @@ ## You should have received a copy of the GNU General Public License ## along with this program. If not, see . =20 +%C%_libsim_a_SOURCES =3D +%C%_libsim_a_LIBADD =3D \ + $(common_libcommon_a_OBJECTS) \ + %D%/interp.o \ + $(patsubst %,%D%/%,$(SIM_NEW_COMMON_OBJS)) \ + $(patsubst %,%D%/dv-%.o,$(SIM_HW_DEVICES)) \ + %D%/endian.o \ + %D%/modules.o \ + %D%/sim-resume.o \ + %D%/simops.o \ + %D%/table.o +$(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-config.h + +noinst_LIBRARIES +=3D %D%/libsim.a + +%D%/%.o: %D%/%.c + $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F) + +%D%/%.o: common/%.c + $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F) + %C%_run_SOURCES =3D %C%_run_LDADD =3D \ %D%/nrun.o \