From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1521) id D31563858C27; Tue, 10 Jan 2023 06:23:25 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D31563858C27 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1673331805; bh=RShpyNPW5EbTeGYCwfhqsg/DXDa+Y2qgqNYx4+yyZGA=; h=From:To:Subject:Date:From; b=wNkXSNzDNuuRlq34I+V3I+tAv8gn2JXVR5yxJJpAMRG++nM180+4hIUAc8Wr69SA8 5LrM5B47yRtL6oRQgmlSwetxseEa1zJKKOPBqmDtuDhhKm1SNerytJUs3/EhCq+mzq 1SwirxHiiEpRIEFQsoWxxP/yz1XBTDWmu1Foh0lw= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Michael Frysinger To: gdb-cvs@sourceware.org Subject: [binutils-gdb] sim: erc32: move libsim.a creation to top-level X-Act-Checkin: binutils-gdb X-Git-Author: Mike Frysinger X-Git-Refname: refs/heads/master X-Git-Oldrev: faf177dff014660285856c2c6bada1595f7268ba X-Git-Newrev: 3f6c63ac49a994bb90732bc892cb630e163ad364 Message-Id: <20230110062325.D31563858C27@sourceware.org> Date: Tue, 10 Jan 2023 06:23:25 +0000 (GMT) List-Id: https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D3f6c63ac49a9= 94bb90732bc892cb630e163ad364 commit 3f6c63ac49a994bb90732bc892cb630e163ad364 Author: Mike Frysinger Date: Mon Dec 26 21:19:35 2022 -0500 sim: erc32: move libsim.a creation to top-level =20 The objects are still compiled in the subdir, but the creation of the archive itself is in the top-level. This is a required step before we can move compilation itself up, and makes it easier to review. =20 The downside is that each object compile is a recursive make instead of a single one. On my 4 core system, it adds ~100msec to the build per port, so it's not great, but it shouldn't be a big deal. This will go away of course once the top-level compiles objects. Diff: --- sim/Makefile.in | 219 ++++++++++++++++++++++++++++------------------= ---- sim/erc32/Makefile.in | 5 +- sim/erc32/local.mk | 24 +++++- 3 files changed, 148 insertions(+), 100 deletions(-) diff --git a/sim/Makefile.in b/sim/Makefile.in index 3705b4ea78d..0cb3dea3475 100644 --- a/sim/Makefile.in +++ b/sim/Makefile.in @@ -180,74 +180,75 @@ TESTS =3D testsuite/common/bits32m0$(EXEEXT) \ @SIM_ENABLE_ARCH_d10v_TRUE@am__append_38 =3D $(d10v_BUILD_OUTPUTS) @SIM_ENABLE_ARCH_d10v_TRUE@am__append_39 =3D d10v/gencode @SIM_ENABLE_ARCH_d10v_TRUE@am__append_40 =3D $(d10v_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_erc32_TRUE@am__append_41 =3D erc32/run erc32/sis -@SIM_ENABLE_ARCH_erc32_TRUE@am__append_42 =3D sim-%D-install-exec-local -@SIM_ENABLE_ARCH_erc32_TRUE@am__append_43 =3D sim-erc32-uninstall-local -@SIM_ENABLE_ARCH_examples_TRUE@am__append_44 =3D example-synacor/run -@SIM_ENABLE_ARCH_frv_TRUE@am__append_45 =3D frv/run -@SIM_ENABLE_ARCH_frv_TRUE@am__append_46 =3D frv/eng.h -@SIM_ENABLE_ARCH_frv_TRUE@am__append_47 =3D $(frv_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_erc32_TRUE@am__append_41 =3D erc32/libsim.a +@SIM_ENABLE_ARCH_erc32_TRUE@am__append_42 =3D erc32/run erc32/sis +@SIM_ENABLE_ARCH_erc32_TRUE@am__append_43 =3D sim-%D-install-exec-local +@SIM_ENABLE_ARCH_erc32_TRUE@am__append_44 =3D sim-erc32-uninstall-local +@SIM_ENABLE_ARCH_examples_TRUE@am__append_45 =3D example-synacor/run +@SIM_ENABLE_ARCH_frv_TRUE@am__append_46 =3D frv/run +@SIM_ENABLE_ARCH_frv_TRUE@am__append_47 =3D frv/eng.h @SIM_ENABLE_ARCH_frv_TRUE@am__append_48 =3D $(frv_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_ft32_TRUE@am__append_49 =3D ft32/run -@SIM_ENABLE_ARCH_h8300_TRUE@am__append_50 =3D h8300/run -@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_51 =3D iq2000/run -@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_52 =3D iq2000/eng.h -@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_53 =3D $(iq2000_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_frv_TRUE@am__append_49 =3D $(frv_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_ft32_TRUE@am__append_50 =3D ft32/run +@SIM_ENABLE_ARCH_h8300_TRUE@am__append_51 =3D h8300/run +@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_52 =3D iq2000/run +@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_53 =3D iq2000/eng.h @SIM_ENABLE_ARCH_iq2000_TRUE@am__append_54 =3D $(iq2000_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_lm32_TRUE@am__append_55 =3D lm32/run -@SIM_ENABLE_ARCH_lm32_TRUE@am__append_56 =3D lm32_SIM_EXTRA_HW_DEVICES=3D"= $(lm32_SIM_EXTRA_HW_DEVICES)" -@SIM_ENABLE_ARCH_lm32_TRUE@am__append_57 =3D lm32/eng.h -@SIM_ENABLE_ARCH_lm32_TRUE@am__append_58 =3D $(lm32_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_55 =3D $(iq2000_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_lm32_TRUE@am__append_56 =3D lm32/run +@SIM_ENABLE_ARCH_lm32_TRUE@am__append_57 =3D lm32_SIM_EXTRA_HW_DEVICES=3D"= $(lm32_SIM_EXTRA_HW_DEVICES)" +@SIM_ENABLE_ARCH_lm32_TRUE@am__append_58 =3D lm32/eng.h @SIM_ENABLE_ARCH_lm32_TRUE@am__append_59 =3D $(lm32_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_m32c_TRUE@am__append_60 =3D m32c/run -@SIM_ENABLE_ARCH_m32c_TRUE@am__append_61 =3D $(m32c_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_m32c_TRUE@am__append_62 =3D m32c/opc2c -@SIM_ENABLE_ARCH_m32c_TRUE@am__append_63 =3D \ +@SIM_ENABLE_ARCH_lm32_TRUE@am__append_60 =3D $(lm32_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_m32c_TRUE@am__append_61 =3D m32c/run +@SIM_ENABLE_ARCH_m32c_TRUE@am__append_62 =3D $(m32c_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_m32c_TRUE@am__append_63 =3D m32c/opc2c +@SIM_ENABLE_ARCH_m32c_TRUE@am__append_64 =3D \ @SIM_ENABLE_ARCH_m32c_TRUE@ $(m32c_BUILD_OUTPUTS) \ @SIM_ENABLE_ARCH_m32c_TRUE@ m32c/m32c.c.log \ @SIM_ENABLE_ARCH_m32c_TRUE@ m32c/r8c.c.log =20 -@SIM_ENABLE_ARCH_m32r_TRUE@am__append_64 =3D m32r/run -@SIM_ENABLE_ARCH_m32r_TRUE@am__append_65 =3D m32r_SIM_EXTRA_HW_DEVICES=3D"= $(m32r_SIM_EXTRA_HW_DEVICES)" -@SIM_ENABLE_ARCH_m32r_TRUE@am__append_66 =3D \ +@SIM_ENABLE_ARCH_m32r_TRUE@am__append_65 =3D m32r/run +@SIM_ENABLE_ARCH_m32r_TRUE@am__append_66 =3D m32r_SIM_EXTRA_HW_DEVICES=3D"= $(m32r_SIM_EXTRA_HW_DEVICES)" +@SIM_ENABLE_ARCH_m32r_TRUE@am__append_67 =3D \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/eng.h \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/engx.h \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/eng2.h =20 -@SIM_ENABLE_ARCH_m32r_TRUE@am__append_67 =3D $(m32r_BUILD_OUTPUTS) @SIM_ENABLE_ARCH_m32r_TRUE@am__append_68 =3D $(m32r_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_69 =3D m68hc11/run -@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_70 =3D m68hc11_SIM_EXTRA_HW_DEVIC= ES=3D"$(m68hc11_SIM_EXTRA_HW_DEVICES)" -@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_71 =3D $(m68hc11_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_72 =3D m68hc11/gencode -@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_73 =3D $(m68hc11_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_mcore_TRUE@am__append_74 =3D mcore/run -@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_75 =3D microblaze/run -@SIM_ENABLE_ARCH_mips_TRUE@am__append_76 =3D mips/run -@SIM_ENABLE_ARCH_mips_TRUE@am__append_77 =3D mips_SIM_EXTRA_HW_DEVICES=3D"= $(mips_SIM_EXTRA_HW_DEVICES)" -@SIM_ENABLE_ARCH_mips_TRUE@am__append_78 =3D mips/itable.h \ +@SIM_ENABLE_ARCH_m32r_TRUE@am__append_69 =3D $(m32r_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_70 =3D m68hc11/run +@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_71 =3D m68hc11_SIM_EXTRA_HW_DEVIC= ES=3D"$(m68hc11_SIM_EXTRA_HW_DEVICES)" +@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_72 =3D $(m68hc11_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_73 =3D m68hc11/gencode +@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_74 =3D $(m68hc11_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_mcore_TRUE@am__append_75 =3D mcore/run +@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_76 =3D microblaze/run +@SIM_ENABLE_ARCH_mips_TRUE@am__append_77 =3D mips/run +@SIM_ENABLE_ARCH_mips_TRUE@am__append_78 =3D mips_SIM_EXTRA_HW_DEVICES=3D"= $(mips_SIM_EXTRA_HW_DEVICES)" +@SIM_ENABLE_ARCH_mips_TRUE@am__append_79 =3D mips/itable.h \ @SIM_ENABLE_ARCH_mips_TRUE@ $(SIM_MIPS_MULTI_SRC) -@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_79 = =3D \ +@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_80 = =3D \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ $(mips_BUILT_SR= C_FROM_GEN_MODE_SINGLE) \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/stamp-gen-= mode-single =20 -@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_80 =3D \ +@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_81 =3D \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ $(mips_BUILT_SRC_F= ROM_GEN_MODE_M16_M16) \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ $(mips_BUILT_SRC_F= ROM_GEN_MODE_M16_M32) \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/stamp-gen-mod= e-m16-m16 \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/stamp-gen-mod= e-m16-m32 =20 -@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_81 =3D= \ +@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_82 =3D= \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ $(SIM_MIPS_MULTI= _SRC) \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/stamp-gen-m= ode-multi-igen \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/stamp-gen-m= ode-multi-run =20 -@SIM_ENABLE_ARCH_mips_TRUE@am__append_82 =3D $(mips_BUILD_OUTPUTS) @SIM_ENABLE_ARCH_mips_TRUE@am__append_83 =3D $(mips_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_mips_TRUE@am__append_84 =3D mips/multi-include.h mips/mul= ti-run.c -@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_85 =3D mn10300/run -@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_86 =3D mn10300_SIM_EXTRA_HW_DEVIC= ES=3D"$(mn10300_SIM_EXTRA_HW_DEVICES)" -@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_87 =3D \ +@SIM_ENABLE_ARCH_mips_TRUE@am__append_84 =3D $(mips_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_mips_TRUE@am__append_85 =3D mips/multi-include.h mips/mul= ti-run.c +@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_86 =3D mn10300/run +@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_87 =3D mn10300_SIM_EXTRA_HW_DEVIC= ES=3D"$(mn10300_SIM_EXTRA_HW_DEVICES)" +@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_88 =3D \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/icache.h \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/idecode.h \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/semantics.h \ @@ -256,29 +257,29 @@ TESTS =3D testsuite/common/bits32m0$(EXEEXT) \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/itable.h \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/engine.h =20 -@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_88 =3D $(mn10300_BUILD_OUTPUTS) @SIM_ENABLE_ARCH_mn10300_TRUE@am__append_89 =3D $(mn10300_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_moxie_TRUE@am__append_90 =3D moxie/run -@SIM_ENABLE_ARCH_msp430_TRUE@am__append_91 =3D msp430/run -@SIM_ENABLE_ARCH_or1k_TRUE@am__append_92 =3D or1k/run -@SIM_ENABLE_ARCH_or1k_TRUE@am__append_93 =3D or1k/eng.h -@SIM_ENABLE_ARCH_or1k_TRUE@am__append_94 =3D $(or1k_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_90 =3D $(mn10300_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_moxie_TRUE@am__append_91 =3D moxie/run +@SIM_ENABLE_ARCH_msp430_TRUE@am__append_92 =3D msp430/run +@SIM_ENABLE_ARCH_or1k_TRUE@am__append_93 =3D or1k/run +@SIM_ENABLE_ARCH_or1k_TRUE@am__append_94 =3D or1k/eng.h @SIM_ENABLE_ARCH_or1k_TRUE@am__append_95 =3D $(or1k_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_ppc_TRUE@am__append_96 =3D ppc/run ppc/psim -@SIM_ENABLE_ARCH_pru_TRUE@am__append_97 =3D pru/run -@SIM_ENABLE_ARCH_riscv_TRUE@am__append_98 =3D riscv/run -@SIM_ENABLE_ARCH_rl78_TRUE@am__append_99 =3D rl78/run -@SIM_ENABLE_ARCH_rx_TRUE@am__append_100 =3D rx/run -@SIM_ENABLE_ARCH_sh_TRUE@am__append_101 =3D sh/run -@SIM_ENABLE_ARCH_sh_TRUE@am__append_102 =3D \ +@SIM_ENABLE_ARCH_or1k_TRUE@am__append_96 =3D $(or1k_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_ppc_TRUE@am__append_97 =3D ppc/run ppc/psim +@SIM_ENABLE_ARCH_pru_TRUE@am__append_98 =3D pru/run +@SIM_ENABLE_ARCH_riscv_TRUE@am__append_99 =3D riscv/run +@SIM_ENABLE_ARCH_rl78_TRUE@am__append_100 =3D rl78/run +@SIM_ENABLE_ARCH_rx_TRUE@am__append_101 =3D rx/run +@SIM_ENABLE_ARCH_sh_TRUE@am__append_102 =3D sh/run +@SIM_ENABLE_ARCH_sh_TRUE@am__append_103 =3D \ @SIM_ENABLE_ARCH_sh_TRUE@ sh/code.c \ @SIM_ENABLE_ARCH_sh_TRUE@ sh/ppi.c =20 -@SIM_ENABLE_ARCH_sh_TRUE@am__append_103 =3D $(sh_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_sh_TRUE@am__append_104 =3D sh/gencode -@SIM_ENABLE_ARCH_sh_TRUE@am__append_105 =3D $(sh_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_v850_TRUE@am__append_106 =3D v850/run -@SIM_ENABLE_ARCH_v850_TRUE@am__append_107 =3D \ +@SIM_ENABLE_ARCH_sh_TRUE@am__append_104 =3D $(sh_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_sh_TRUE@am__append_105 =3D sh/gencode +@SIM_ENABLE_ARCH_sh_TRUE@am__append_106 =3D $(sh_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_v850_TRUE@am__append_107 =3D v850/run +@SIM_ENABLE_ARCH_v850_TRUE@am__append_108 =3D \ @SIM_ENABLE_ARCH_v850_TRUE@ v850/icache.h \ @SIM_ENABLE_ARCH_v850_TRUE@ v850/idecode.h \ @SIM_ENABLE_ARCH_v850_TRUE@ v850/semantics.h \ @@ -287,8 +288,8 @@ TESTS =3D testsuite/common/bits32m0$(EXEEXT) \ @SIM_ENABLE_ARCH_v850_TRUE@ v850/itable.h \ @SIM_ENABLE_ARCH_v850_TRUE@ v850/engine.h =20 -@SIM_ENABLE_ARCH_v850_TRUE@am__append_108 =3D $(v850_BUILD_OUTPUTS) @SIM_ENABLE_ARCH_v850_TRUE@am__append_109 =3D $(v850_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_v850_TRUE@am__append_110 =3D $(v850_BUILD_OUTPUTS) subdir =3D . ACLOCAL_M4 =3D $(top_srcdir)/aclocal.m4 am__aclocal_m4_deps =3D $(top_srcdir)/../config/acx.m4 \ @@ -476,6 +477,15 @@ d10v_libsim_a_AR =3D $(AR) $(ARFLAGS) @SIM_ENABLE_ARCH_d10v_TRUE@ d10v/table.o am_d10v_libsim_a_OBJECTS =3D d10v_libsim_a_OBJECTS =3D $(am_d10v_libsim_a_OBJECTS) +erc32_libsim_a_AR =3D $(AR) $(ARFLAGS) +@SIM_ENABLE_ARCH_erc32_TRUE@erc32_libsim_a_DEPENDENCIES =3D \ +@SIM_ENABLE_ARCH_erc32_TRUE@ $(common_libcommon_a_OBJECTS) \ +@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/erc32.o erc32/exec.o \ +@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/float.o erc32/func.o \ +@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/help.o erc32/interf.o \ +@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/modules.o +am_erc32_libsim_a_OBJECTS =3D +erc32_libsim_a_OBJECTS =3D $(am_erc32_libsim_a_OBJECTS) igen_libigen_a_AR =3D $(AR) $(ARFLAGS) igen_libigen_a_LIBADD =3D @SIM_ENABLE_IGEN_TRUE@am_igen_libigen_a_OBJECTS =3D \ @@ -822,12 +832,13 @@ SOURCES =3D $(aarch64_libsim_a_SOURCES) $(arm_libsim_= a_SOURCES) \ $(avr_libsim_a_SOURCES) $(bfin_libsim_a_SOURCES) \ $(bpf_libsim_a_SOURCES) $(common_libcommon_a_SOURCES) \ $(cr16_libsim_a_SOURCES) $(cris_libsim_a_SOURCES) \ - $(d10v_libsim_a_SOURCES) $(igen_libigen_a_SOURCES) \ - $(aarch64_run_SOURCES) $(arm_run_SOURCES) $(avr_run_SOURCES) \ - $(bfin_run_SOURCES) $(bpf_run_SOURCES) $(cr16_gencode_SOURCES) \ - $(cr16_run_SOURCES) $(cris_run_SOURCES) \ - $(cris_rvdummy_SOURCES) $(d10v_gencode_SOURCES) \ - $(d10v_run_SOURCES) $(erc32_run_SOURCES) erc32/sis.c \ + $(d10v_libsim_a_SOURCES) $(erc32_libsim_a_SOURCES) \ + $(igen_libigen_a_SOURCES) $(aarch64_run_SOURCES) \ + $(arm_run_SOURCES) $(avr_run_SOURCES) $(bfin_run_SOURCES) \ + $(bpf_run_SOURCES) $(cr16_gencode_SOURCES) $(cr16_run_SOURCES) \ + $(cris_run_SOURCES) $(cris_rvdummy_SOURCES) \ + $(d10v_gencode_SOURCES) $(d10v_run_SOURCES) \ + $(erc32_run_SOURCES) erc32/sis.c \ $(example_synacor_run_SOURCES) $(frv_run_SOURCES) \ $(ft32_run_SOURCES) $(h8300_run_SOURCES) \ $(igen_filter_SOURCES) $(igen_gen_SOURCES) \ @@ -1379,33 +1390,33 @@ srcroot =3D $(srcdir)/.. SUBDIRS =3D @subdirs@ $(SIM_SUBDIRS) AM_MAKEFLAGS =3D SIM_NEW_COMMON_OBJS_=3D"$(SIM_NEW_COMMON_OBJS)" \ $(am__append_3) $(am__append_16) $(am__append_30) \ - $(am__append_56) $(am__append_65) $(am__append_70) \ - $(am__append_77) $(am__append_86) + $(am__append_57) $(am__append_66) $(am__append_71) \ + $(am__append_78) $(am__append_87) pkginclude_HEADERS =3D $(am__append_1) noinst_LIBRARIES =3D common/libcommon.a $(am__append_5) $(am__append_8) \ $(am__append_10) $(am__append_12) $(am__append_14) \ $(am__append_17) $(am__append_22) $(am__append_28) \ - $(am__append_35) + $(am__append_35) $(am__append_41) BUILT_SOURCES =3D $(am__append_19) $(am__append_24) $(am__append_32) \ - $(am__append_37) $(am__append_46) $(am__append_52) \ - $(am__append_57) $(am__append_66) $(am__append_78) \ - $(am__append_87) $(am__append_93) $(am__append_102) \ - $(am__append_107) + $(am__append_37) $(am__append_47) $(am__append_53) \ + $(am__append_58) $(am__append_67) $(am__append_79) \ + $(am__append_88) $(am__append_94) $(am__append_103) \ + $(am__append_108) CLEANFILES =3D common/version.c common/version.c-stamp \ testsuite/common/bits-gen testsuite/common/bits32m0.c \ testsuite/common/bits32m31.c testsuite/common/bits64m0.c \ testsuite/common/bits64m63.c -DISTCLEANFILES =3D $(am__append_84) +DISTCLEANFILES =3D $(am__append_85) MOSTLYCLEANFILES =3D core $(common_HW_CONFIG_H_TARGETS) $(patsubst \ %,%/stamp-hw,$(SIM_ENABLED_ARCHES)) \ $(common_GEN_MODULES_C_TARGETS) $(patsubst \ %,%/stamp-modules,$(SIM_ENABLED_ARCHES)) $(am__append_7) \ site-sim-config.exp testrun.log testrun.sum $(am__append_21) \ $(am__append_27) $(am__append_34) $(am__append_40) \ - $(am__append_48) $(am__append_54) $(am__append_59) \ - $(am__append_63) $(am__append_68) $(am__append_73) \ - $(am__append_83) $(am__append_89) $(am__append_95) \ - $(am__append_105) $(am__append_109) + $(am__append_49) $(am__append_55) $(am__append_60) \ + $(am__append_64) $(am__append_69) $(am__append_74) \ + $(am__append_84) $(am__append_90) $(am__append_96) \ + $(am__append_106) $(am__append_110) AM_CFLAGS =3D $(WERROR_CFLAGS) $(WARN_CFLAGS) AM_CPPFLAGS =3D $(INCGNU) -I$(srcroot)/include -I../bfd -I.. \ $(SIM_HW_CFLAGS) $(SIM_INLINE) -I$(srcdir)/common \ @@ -1417,14 +1428,14 @@ LINK_FOR_BUILD =3D $(CC_FOR_BUILD) $(CFLAGS_FOR_BUI= LD) $(LDFLAGS_FOR_BUILD) -o $@ SIM_ALL_RECURSIVE_DEPS =3D common/libcommon.a \ $(common_HW_CONFIG_H_TARGETS) $(common_GEN_MODULES_C_TARGETS) \ $(am__append_4) $(am__append_20) $(am__append_25) \ - $(am__append_33) $(am__append_38) $(am__append_47) \ - $(am__append_53) $(am__append_58) $(am__append_61) \ - $(am__append_67) $(am__append_71) $(am__append_82) \ - $(am__append_88) $(am__append_94) $(am__append_103) \ - $(am__append_108) + $(am__append_33) $(am__append_38) $(am__append_48) \ + $(am__append_54) $(am__append_59) $(am__append_62) \ + $(am__append_68) $(am__append_72) $(am__append_83) \ + $(am__append_89) $(am__append_95) $(am__append_104) \ + $(am__append_109) SIM_INSTALL_DATA_LOCAL_DEPS =3D=20 -SIM_INSTALL_EXEC_LOCAL_DEPS =3D $(am__append_42) -SIM_UNINSTALL_LOCAL_DEPS =3D $(am__append_43) +SIM_INSTALL_EXEC_LOCAL_DEPS =3D $(am__append_43) +SIM_UNINSTALL_LOCAL_DEPS =3D $(am__append_44) common_libcommon_a_SOURCES =3D \ common/callback.c \ common/portability.c \ @@ -1825,6 +1836,17 @@ testsuite_common_CPPFLAGS =3D \ =20 @SIM_ENABLE_ARCH_d10v_TRUE@d10v_gencode_SOURCES =3D d10v/gencode.c @SIM_ENABLE_ARCH_d10v_TRUE@d10v_gencode_LDADD =3D d10v/d10v-opc.o +@SIM_ENABLE_ARCH_erc32_TRUE@erc32_libsim_a_SOURCES =3D=20 +@SIM_ENABLE_ARCH_erc32_TRUE@erc32_libsim_a_LIBADD =3D \ +@SIM_ENABLE_ARCH_erc32_TRUE@ $(common_libcommon_a_OBJECTS) \ +@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/erc32.o \ +@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/exec.o \ +@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/float.o \ +@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/func.o \ +@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/help.o \ +@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/interf.o \ +@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/modules.o + @SIM_ENABLE_ARCH_erc32_TRUE@erc32_run_SOURCES =3D=20 @SIM_ENABLE_ARCH_erc32_TRUE@erc32_run_LDADD =3D \ @SIM_ENABLE_ARCH_erc32_TRUE@ erc32/sis.o \ @@ -1992,8 +2014,8 @@ testsuite_common_CPPFLAGS =3D \ @SIM_ENABLE_ARCH_mips_TRUE@mips_BUILD_OUTPUTS =3D \ @SIM_ENABLE_ARCH_mips_TRUE@ $(mips_BUILT_SRC_FROM_IGEN_ITABLE) \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/stamp-igen-itable \ -@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_79) $(am__append_80) \ -@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_81) +@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_80) $(am__append_81) \ +@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_82) @SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_TRACE =3D # -G omit-line-numbers # -G= trace-rule-selection -G trace-rule-rejection -G trace-entries # -G trace-a= ll @SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN =3D $(srcdir)/mips/mips.igen @SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN_INC =3D \ @@ -2430,6 +2452,14 @@ d10v/libsim.a: $(d10v_libsim_a_OBJECTS) $(d10v_libsi= m_a_DEPENDENCIES) $(EXTRA_d1 $(AM_V_at)-rm -f d10v/libsim.a $(AM_V_AR)$(d10v_libsim_a_AR) d10v/libsim.a $(d10v_libsim_a_OBJECTS) $(d1= 0v_libsim_a_LIBADD) $(AM_V_at)$(RANLIB) d10v/libsim.a +erc32/$(am__dirstamp): + @$(MKDIR_P) erc32 + @: > erc32/$(am__dirstamp) + +erc32/libsim.a: $(erc32_libsim_a_OBJECTS) $(erc32_libsim_a_DEPENDENCIES) $= (EXTRA_erc32_libsim_a_DEPENDENCIES) erc32/$(am__dirstamp) + $(AM_V_at)-rm -f erc32/libsim.a + $(AM_V_AR)$(erc32_libsim_a_AR) erc32/libsim.a $(erc32_libsim_a_OBJECTS) $= (erc32_libsim_a_LIBADD) + $(AM_V_at)$(RANLIB) erc32/libsim.a igen/$(am__dirstamp): @$(MKDIR_P) igen @: > igen/$(am__dirstamp) @@ -2549,9 +2579,6 @@ d10v/gencode.$(OBJEXT): d10v/$(am__dirstamp) \ d10v/run$(EXEEXT): $(d10v_run_OBJECTS) $(d10v_run_DEPENDENCIES) $(EXTRA_d1= 0v_run_DEPENDENCIES) d10v/$(am__dirstamp) @rm -f d10v/run$(EXEEXT) $(AM_V_CCLD)$(LINK) $(d10v_run_OBJECTS) $(d10v_run_LDADD) $(LIBS) -erc32/$(am__dirstamp): - @$(MKDIR_P) erc32 - @: > erc32/$(am__dirstamp) =20 erc32/run$(EXEEXT): $(erc32_run_OBJECTS) $(erc32_run_DEPENDENCIES) $(EXTRA= _erc32_run_DEPENDENCIES) erc32/$(am__dirstamp) @rm -f erc32/run$(EXEEXT) @@ -3979,12 +4006,16 @@ testsuite/common/bits64m63.c: testsuite/common/bits= -gen$(EXEEXT) testsuite/commo =20 @SIM_ENABLE_ARCH_d10v_TRUE@d10v/table.c: d10v/gencode$(EXEEXT) @SIM_ENABLE_ARCH_d10v_TRUE@ $(AM_V_GEN)$< >$@ +@SIM_ENABLE_ARCH_erc32_TRUE@$(erc32_libsim_a_OBJECTS) $(erc32_libsim_a_LIB= ADD): erc32/hw-config.h + +@SIM_ENABLE_ARCH_erc32_TRUE@erc32/%.o: erc32/%.c +@SIM_ENABLE_ARCH_erc32_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(= @F) + +@SIM_ENABLE_ARCH_erc32_TRUE@erc32/%.o: common/%.c +@SIM_ENABLE_ARCH_erc32_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(= @F) =20 @SIM_ENABLE_ARCH_erc32_TRUE@erc32/sis$(EXEEXT): erc32/run$(EXEEXT) @SIM_ENABLE_ARCH_erc32_TRUE@ $(AM_V_GEN)ln $< $@ 2>/dev/null || $(LN_S) $<= $@ 2>/dev/null || cp -p $< $@ - -@SIM_ENABLE_ARCH_erc32_TRUE@erc32/%.o: erc32/%.c | erc32/libsim.a $(SIM_AL= L_RECURSIVE_DEPS) -@SIM_ENABLE_ARCH_erc32_TRUE@ $(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F) @SIM_ENABLE_ARCH_erc32_TRUE@sim-%D-install-exec-local: installdirs @SIM_ENABLE_ARCH_erc32_TRUE@ $(AM_V_at)$(MKDIR_P) $(DESTDIR)$(bindir) @SIM_ENABLE_ARCH_erc32_TRUE@ n=3D`echo sis | sed '$(program_transform_name= )'`; \ diff --git a/sim/erc32/Makefile.in b/sim/erc32/Makefile.in index d10eb0eb1a4..252427d4a38 100644 --- a/sim/erc32/Makefile.in +++ b/sim/erc32/Makefile.in @@ -18,10 +18,11 @@ =20 ## COMMON_PRE_CONFIG_FRAG =20 +SIM_LIBSIM =3D +SIM_RUN_OBJS =3D + READLINE_SRC =3D $(srcroot)/readline/readline =20 -SIM_OBJS =3D exec.o erc32.o func.o help.o float.o interf.o -SIM_RUN_OBJS =3D sis.o SIM_EXTRA_CFLAGS =3D $(READLINE_CFLAGS) =20 # UARTS run at about 115200 baud (simulator time). Add -DFAST_UART to diff --git a/sim/erc32/local.mk b/sim/erc32/local.mk index 65935fe082f..7c95128a166 100644 --- a/sim/erc32/local.mk +++ b/sim/erc32/local.mk @@ -17,6 +17,26 @@ ## You should have received a copy of the GNU General Public License ## along with this program. If not, see . =20 +%C%_libsim_a_SOURCES =3D +%C%_libsim_a_LIBADD =3D \ + $(common_libcommon_a_OBJECTS) \ + %D%/erc32.o \ + %D%/exec.o \ + %D%/float.o \ + %D%/func.o \ + %D%/help.o \ + %D%/interf.o \ + %D%/modules.o +$(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-config.h + +noinst_LIBRARIES +=3D %D%/libsim.a + +%D%/%.o: %D%/%.c + $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F) + +%D%/%.o: common/%.c + $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F) + %C%_run_SOURCES =3D %C%_run_LDADD =3D \ %D%/sis.o \ @@ -26,10 +46,6 @@ %D%/sis$(EXEEXT): %D%/run$(EXEEXT) $(AM_V_GEN)ln $< $@ 2>/dev/null || $(LN_S) $< $@ 2>/dev/null || cp -p $< = $@ =20 -## Helper targets for running make from the top-level due to run's sis.o. -%D%/%.o: %D%/%.c | %D%/libsim.a $(SIM_ALL_RECURSIVE_DEPS) - $(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F) - noinst_PROGRAMS +=3D %D%/run %D%/sis =20 %C%docdir =3D $(docdir)/%C%