From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1521) id 700E83858C2F; Tue, 10 Jan 2023 06:24:06 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 700E83858C2F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1673331846; bh=UnnntEcACyAsr30r8vm/GbZKXMDshMcV83tltaT9Il0=; h=From:To:Subject:Date:From; b=d76feUNK1FkX6NePoMyatjdOiAdygX+jTF6TAYH00hr9iDBRf+SBIEpJKhjiBl2qo tAlvmDPi6HRbtrvpzu36Y4KjFWL0D0dSB1q9vLknnvLtit/eqkI1UwyUsWxfQnrvCh PvpbNiZ7bgejaSqzvLyevs6bBDx29YrNlINQkBzg= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Michael Frysinger To: gdb-cvs@sourceware.org Subject: [binutils-gdb] sim: m32r: move libsim.a creation to top-level X-Act-Checkin: binutils-gdb X-Git-Author: Mike Frysinger X-Git-Refname: refs/heads/master X-Git-Oldrev: ba3a8498992008d2bfa1ee184b256ec53d55a9a1 X-Git-Newrev: 8136f0578d98d82ca3e305f3ac8c8662012f8f45 Message-Id: <20230110062406.700E83858C2F@sourceware.org> Date: Tue, 10 Jan 2023 06:24:06 +0000 (GMT) List-Id: https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D8136f0578d98= d82ca3e305f3ac8c8662012f8f45 commit 8136f0578d98d82ca3e305f3ac8c8662012f8f45 Author: Mike Frysinger Date: Mon Dec 26 21:58:02 2022 -0500 sim: m32r: move libsim.a creation to top-level =20 The objects are still compiled in the subdir, but the creation of the archive itself is in the top-level. This is a required step before we can move compilation itself up, and makes it easier to review. =20 The downside is that each object compile is a recursive make instead of a single one. On my 4 core system, it adds ~100msec to the build per port, so it's not great, but it shouldn't be a big deal. This will go away of course once the top-level compiles objects. Diff: --- sim/Makefile.in | 203 +++++++++++++++++++++++++++++++++++------------= ---- sim/m32r/Makefile.in | 14 +--- sim/m32r/local.mk | 46 ++++++++++++ 3 files changed, 186 insertions(+), 77 deletions(-) diff --git a/sim/Makefile.in b/sim/Makefile.in index 84e9a64c7a5..62873ec5b40 100644 --- a/sim/Makefile.in +++ b/sim/Makefile.in @@ -215,47 +215,48 @@ TESTS =3D testsuite/common/bits32m0$(EXEEXT) \ @SIM_ENABLE_ARCH_m32c_TRUE@ m32c/m32c.c.log \ @SIM_ENABLE_ARCH_m32c_TRUE@ m32c/r8c.c.log =20 -@SIM_ENABLE_ARCH_m32r_TRUE@am__append_72 =3D m32r/run -@SIM_ENABLE_ARCH_m32r_TRUE@am__append_73 =3D m32r_SIM_EXTRA_HW_DEVICES=3D"= $(m32r_SIM_EXTRA_HW_DEVICES)" -@SIM_ENABLE_ARCH_m32r_TRUE@am__append_74 =3D \ +@SIM_ENABLE_ARCH_m32r_TRUE@am__append_72 =3D m32r/libsim.a +@SIM_ENABLE_ARCH_m32r_TRUE@am__append_73 =3D m32r/run +@SIM_ENABLE_ARCH_m32r_TRUE@am__append_74 =3D m32r_SIM_EXTRA_HW_DEVICES=3D"= $(m32r_SIM_EXTRA_HW_DEVICES)" +@SIM_ENABLE_ARCH_m32r_TRUE@am__append_75 =3D \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/eng.h \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/engx.h \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/eng2.h =20 -@SIM_ENABLE_ARCH_m32r_TRUE@am__append_75 =3D $(m32r_BUILD_OUTPUTS) @SIM_ENABLE_ARCH_m32r_TRUE@am__append_76 =3D $(m32r_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_77 =3D m68hc11/run -@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_78 =3D m68hc11_SIM_EXTRA_HW_DEVIC= ES=3D"$(m68hc11_SIM_EXTRA_HW_DEVICES)" -@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_79 =3D $(m68hc11_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_80 =3D m68hc11/gencode -@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_81 =3D $(m68hc11_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_mcore_TRUE@am__append_82 =3D mcore/run -@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_83 =3D microblaze/run -@SIM_ENABLE_ARCH_mips_TRUE@am__append_84 =3D mips/run -@SIM_ENABLE_ARCH_mips_TRUE@am__append_85 =3D mips_SIM_EXTRA_HW_DEVICES=3D"= $(mips_SIM_EXTRA_HW_DEVICES)" -@SIM_ENABLE_ARCH_mips_TRUE@am__append_86 =3D mips/itable.h \ +@SIM_ENABLE_ARCH_m32r_TRUE@am__append_77 =3D $(m32r_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_78 =3D m68hc11/run +@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_79 =3D m68hc11_SIM_EXTRA_HW_DEVIC= ES=3D"$(m68hc11_SIM_EXTRA_HW_DEVICES)" +@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_80 =3D $(m68hc11_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_81 =3D m68hc11/gencode +@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_82 =3D $(m68hc11_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_mcore_TRUE@am__append_83 =3D mcore/run +@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_84 =3D microblaze/run +@SIM_ENABLE_ARCH_mips_TRUE@am__append_85 =3D mips/run +@SIM_ENABLE_ARCH_mips_TRUE@am__append_86 =3D mips_SIM_EXTRA_HW_DEVICES=3D"= $(mips_SIM_EXTRA_HW_DEVICES)" +@SIM_ENABLE_ARCH_mips_TRUE@am__append_87 =3D mips/itable.h \ @SIM_ENABLE_ARCH_mips_TRUE@ $(SIM_MIPS_MULTI_SRC) -@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_87 = =3D \ +@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_88 = =3D \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ $(mips_BUILT_SR= C_FROM_GEN_MODE_SINGLE) \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/stamp-gen-= mode-single =20 -@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_88 =3D \ +@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_89 =3D \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ $(mips_BUILT_SRC_F= ROM_GEN_MODE_M16_M16) \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ $(mips_BUILT_SRC_F= ROM_GEN_MODE_M16_M32) \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/stamp-gen-mod= e-m16-m16 \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/stamp-gen-mod= e-m16-m32 =20 -@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_89 =3D= \ +@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_90 =3D= \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ $(SIM_MIPS_MULTI= _SRC) \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/stamp-gen-m= ode-multi-igen \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/stamp-gen-m= ode-multi-run =20 -@SIM_ENABLE_ARCH_mips_TRUE@am__append_90 =3D $(mips_BUILD_OUTPUTS) @SIM_ENABLE_ARCH_mips_TRUE@am__append_91 =3D $(mips_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_mips_TRUE@am__append_92 =3D mips/multi-include.h mips/mul= ti-run.c -@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_93 =3D mn10300/run -@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_94 =3D mn10300_SIM_EXTRA_HW_DEVIC= ES=3D"$(mn10300_SIM_EXTRA_HW_DEVICES)" -@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_95 =3D \ +@SIM_ENABLE_ARCH_mips_TRUE@am__append_92 =3D $(mips_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_mips_TRUE@am__append_93 =3D mips/multi-include.h mips/mul= ti-run.c +@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_94 =3D mn10300/run +@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_95 =3D mn10300_SIM_EXTRA_HW_DEVIC= ES=3D"$(mn10300_SIM_EXTRA_HW_DEVICES)" +@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_96 =3D \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/icache.h \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/idecode.h \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/semantics.h \ @@ -264,29 +265,29 @@ TESTS =3D testsuite/common/bits32m0$(EXEEXT) \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/itable.h \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/engine.h =20 -@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_96 =3D $(mn10300_BUILD_OUTPUTS) @SIM_ENABLE_ARCH_mn10300_TRUE@am__append_97 =3D $(mn10300_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_moxie_TRUE@am__append_98 =3D moxie/run -@SIM_ENABLE_ARCH_msp430_TRUE@am__append_99 =3D msp430/run -@SIM_ENABLE_ARCH_or1k_TRUE@am__append_100 =3D or1k/run -@SIM_ENABLE_ARCH_or1k_TRUE@am__append_101 =3D or1k/eng.h -@SIM_ENABLE_ARCH_or1k_TRUE@am__append_102 =3D $(or1k_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_98 =3D $(mn10300_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_moxie_TRUE@am__append_99 =3D moxie/run +@SIM_ENABLE_ARCH_msp430_TRUE@am__append_100 =3D msp430/run +@SIM_ENABLE_ARCH_or1k_TRUE@am__append_101 =3D or1k/run +@SIM_ENABLE_ARCH_or1k_TRUE@am__append_102 =3D or1k/eng.h @SIM_ENABLE_ARCH_or1k_TRUE@am__append_103 =3D $(or1k_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_ppc_TRUE@am__append_104 =3D ppc/run ppc/psim -@SIM_ENABLE_ARCH_pru_TRUE@am__append_105 =3D pru/run -@SIM_ENABLE_ARCH_riscv_TRUE@am__append_106 =3D riscv/run -@SIM_ENABLE_ARCH_rl78_TRUE@am__append_107 =3D rl78/run -@SIM_ENABLE_ARCH_rx_TRUE@am__append_108 =3D rx/run -@SIM_ENABLE_ARCH_sh_TRUE@am__append_109 =3D sh/run -@SIM_ENABLE_ARCH_sh_TRUE@am__append_110 =3D \ +@SIM_ENABLE_ARCH_or1k_TRUE@am__append_104 =3D $(or1k_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_ppc_TRUE@am__append_105 =3D ppc/run ppc/psim +@SIM_ENABLE_ARCH_pru_TRUE@am__append_106 =3D pru/run +@SIM_ENABLE_ARCH_riscv_TRUE@am__append_107 =3D riscv/run +@SIM_ENABLE_ARCH_rl78_TRUE@am__append_108 =3D rl78/run +@SIM_ENABLE_ARCH_rx_TRUE@am__append_109 =3D rx/run +@SIM_ENABLE_ARCH_sh_TRUE@am__append_110 =3D sh/run +@SIM_ENABLE_ARCH_sh_TRUE@am__append_111 =3D \ @SIM_ENABLE_ARCH_sh_TRUE@ sh/code.c \ @SIM_ENABLE_ARCH_sh_TRUE@ sh/ppi.c =20 -@SIM_ENABLE_ARCH_sh_TRUE@am__append_111 =3D $(sh_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_sh_TRUE@am__append_112 =3D sh/gencode -@SIM_ENABLE_ARCH_sh_TRUE@am__append_113 =3D $(sh_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_v850_TRUE@am__append_114 =3D v850/run -@SIM_ENABLE_ARCH_v850_TRUE@am__append_115 =3D \ +@SIM_ENABLE_ARCH_sh_TRUE@am__append_112 =3D $(sh_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_sh_TRUE@am__append_113 =3D sh/gencode +@SIM_ENABLE_ARCH_sh_TRUE@am__append_114 =3D $(sh_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_v850_TRUE@am__append_115 =3D v850/run +@SIM_ENABLE_ARCH_v850_TRUE@am__append_116 =3D \ @SIM_ENABLE_ARCH_v850_TRUE@ v850/icache.h \ @SIM_ENABLE_ARCH_v850_TRUE@ v850/idecode.h \ @SIM_ENABLE_ARCH_v850_TRUE@ v850/semantics.h \ @@ -295,8 +296,8 @@ TESTS =3D testsuite/common/bits32m0$(EXEEXT) \ @SIM_ENABLE_ARCH_v850_TRUE@ v850/itable.h \ @SIM_ENABLE_ARCH_v850_TRUE@ v850/engine.h =20 -@SIM_ENABLE_ARCH_v850_TRUE@am__append_116 =3D $(v850_BUILD_OUTPUTS) @SIM_ENABLE_ARCH_v850_TRUE@am__append_117 =3D $(v850_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_v850_TRUE@am__append_118 =3D $(v850_BUILD_OUTPUTS) subdir =3D . ACLOCAL_M4 =3D $(top_srcdir)/aclocal.m4 am__aclocal_m4_deps =3D $(top_srcdir)/../config/acx.m4 \ @@ -618,6 +619,29 @@ m32c_libsim_a_AR =3D $(AR) $(ARFLAGS) @SIM_ENABLE_ARCH_m32c_TRUE@ m32c/trace.o am_m32c_libsim_a_OBJECTS =3D m32c_libsim_a_OBJECTS =3D $(am_m32c_libsim_a_OBJECTS) +m32r_libsim_a_AR =3D $(AR) $(ARFLAGS) +@SIM_ENABLE_ARCH_m32r_TRUE@m32r_libsim_a_DEPENDENCIES =3D \ +@SIM_ENABLE_ARCH_m32r_TRUE@ $(common_libcommon_a_OBJECTS) \ +@SIM_ENABLE_ARCH_m32r_TRUE@ $(patsubst \ +@SIM_ENABLE_ARCH_m32r_TRUE@ %,m32r/%,$(SIM_NEW_COMMON_OBJS)) \ +@SIM_ENABLE_ARCH_m32r_TRUE@ $(patsubst \ +@SIM_ENABLE_ARCH_m32r_TRUE@ %,m32r/dv-%.o,$(SIM_HW_DEVICES)) \ +@SIM_ENABLE_ARCH_m32r_TRUE@ $(patsubst \ +@SIM_ENABLE_ARCH_m32r_TRUE@ %,m32r/dv-%.o,$(m32r_SIM_EXTRA_HW_DEVICES)) \ +@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/modules.o m32r/cgen-run.o \ +@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cgen-scache.o \ +@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cgen-trace.o m32r/cgen-utils.o \ +@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/arch.o m32r/m32r.o m32r/cpu.o \ +@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/decode.o m32r/sem.o \ +@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/model.o m32r/mloop.o \ +@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/m32rx.o m32r/cpux.o \ +@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/decodex.o m32r/modelx.o \ +@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/mloopx.o m32r/m32r2.o \ +@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cpu2.o m32r/decode2.o \ +@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/model2.o m32r/mloop2.o \ +@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/sim-if.o m32r/traps.o +am_m32r_libsim_a_OBJECTS =3D +m32r_libsim_a_OBJECTS =3D $(am_m32r_libsim_a_OBJECTS) @SIM_ENABLE_IGEN_TRUE@am__EXEEXT_1 =3D $(IGEN) igen/filter$(EXEEXT) \ @SIM_ENABLE_IGEN_TRUE@ igen/gen$(EXEEXT) igen/ld-cache$(EXEEXT) \ @SIM_ENABLE_IGEN_TRUE@ igen/ld-decode$(EXEEXT) \ @@ -950,11 +974,12 @@ SOURCES =3D $(aarch64_libsim_a_SOURCES) $(arm_libsim_= a_SOURCES) \ $(ft32_libsim_a_SOURCES) $(h8300_libsim_a_SOURCES) \ $(igen_libigen_a_SOURCES) $(iq2000_libsim_a_SOURCES) \ $(lm32_libsim_a_SOURCES) $(m32c_libsim_a_SOURCES) \ - $(aarch64_run_SOURCES) $(arm_run_SOURCES) $(avr_run_SOURCES) \ - $(bfin_run_SOURCES) $(bpf_run_SOURCES) $(cr16_gencode_SOURCES) \ - $(cr16_run_SOURCES) $(cris_run_SOURCES) \ - $(cris_rvdummy_SOURCES) $(d10v_gencode_SOURCES) \ - $(d10v_run_SOURCES) $(erc32_run_SOURCES) erc32/sis.c \ + $(m32r_libsim_a_SOURCES) $(aarch64_run_SOURCES) \ + $(arm_run_SOURCES) $(avr_run_SOURCES) $(bfin_run_SOURCES) \ + $(bpf_run_SOURCES) $(cr16_gencode_SOURCES) $(cr16_run_SOURCES) \ + $(cris_run_SOURCES) $(cris_rvdummy_SOURCES) \ + $(d10v_gencode_SOURCES) $(d10v_run_SOURCES) \ + $(erc32_run_SOURCES) erc32/sis.c \ $(example_synacor_run_SOURCES) $(frv_run_SOURCES) \ $(ft32_run_SOURCES) $(h8300_run_SOURCES) \ $(igen_filter_SOURCES) $(igen_gen_SOURCES) \ @@ -1506,25 +1531,26 @@ srcroot =3D $(srcdir)/.. SUBDIRS =3D @subdirs@ $(SIM_SUBDIRS) AM_MAKEFLAGS =3D SIM_NEW_COMMON_OBJS_=3D"$(SIM_NEW_COMMON_OBJS)" \ $(am__append_3) $(am__append_16) $(am__append_30) \ - $(am__append_63) $(am__append_73) $(am__append_78) \ - $(am__append_85) $(am__append_94) + $(am__append_63) $(am__append_74) $(am__append_79) \ + $(am__append_86) $(am__append_95) pkginclude_HEADERS =3D $(am__append_1) noinst_LIBRARIES =3D common/libcommon.a $(am__append_5) $(am__append_8) \ $(am__append_10) $(am__append_12) $(am__append_14) \ $(am__append_17) $(am__append_22) $(am__append_28) \ $(am__append_35) $(am__append_41) $(am__append_45) \ $(am__append_47) $(am__append_52) $(am__append_54) \ - $(am__append_56) $(am__append_61) $(am__append_67) + $(am__append_56) $(am__append_61) $(am__append_67) \ + $(am__append_72) BUILT_SOURCES =3D $(am__append_19) $(am__append_24) $(am__append_32) \ $(am__append_37) $(am__append_49) $(am__append_58) \ - $(am__append_64) $(am__append_74) $(am__append_86) \ - $(am__append_95) $(am__append_101) $(am__append_110) \ - $(am__append_115) + $(am__append_64) $(am__append_75) $(am__append_87) \ + $(am__append_96) $(am__append_102) $(am__append_111) \ + $(am__append_116) CLEANFILES =3D common/version.c common/version.c-stamp \ testsuite/common/bits-gen testsuite/common/bits32m0.c \ testsuite/common/bits32m31.c testsuite/common/bits64m0.c \ testsuite/common/bits64m63.c -DISTCLEANFILES =3D $(am__append_92) +DISTCLEANFILES =3D $(am__append_93) MOSTLYCLEANFILES =3D core $(common_HW_CONFIG_H_TARGETS) $(patsubst \ %,%/stamp-hw,$(SIM_ENABLED_ARCHES)) \ $(common_GEN_MODULES_C_TARGETS) $(patsubst \ @@ -1532,9 +1558,9 @@ MOSTLYCLEANFILES =3D core $(common_HW_CONFIG_H_TARGET= S) $(patsubst \ site-sim-config.exp testrun.log testrun.sum $(am__append_21) \ $(am__append_27) $(am__append_34) $(am__append_40) \ $(am__append_51) $(am__append_60) $(am__append_66) \ - $(am__append_71) $(am__append_76) $(am__append_81) \ - $(am__append_91) $(am__append_97) $(am__append_103) \ - $(am__append_113) $(am__append_117) + $(am__append_71) $(am__append_77) $(am__append_82) \ + $(am__append_92) $(am__append_98) $(am__append_104) \ + $(am__append_114) $(am__append_118) AM_CFLAGS =3D $(WERROR_CFLAGS) $(WARN_CFLAGS) AM_CPPFLAGS =3D $(INCGNU) -I$(srcroot)/include -I../bfd -I.. \ $(SIM_HW_CFLAGS) $(SIM_INLINE) -I$(srcdir)/common \ @@ -1548,9 +1574,9 @@ SIM_ALL_RECURSIVE_DEPS =3D common/libcommon.a \ $(am__append_4) $(am__append_20) $(am__append_25) \ $(am__append_33) $(am__append_38) $(am__append_50) \ $(am__append_59) $(am__append_65) $(am__append_69) \ - $(am__append_75) $(am__append_79) $(am__append_90) \ - $(am__append_96) $(am__append_102) $(am__append_111) \ - $(am__append_116) + $(am__append_76) $(am__append_80) $(am__append_91) \ + $(am__append_97) $(am__append_103) $(am__append_112) \ + $(am__append_117) SIM_INSTALL_DATA_LOCAL_DEPS =3D=20 SIM_INSTALL_EXEC_LOCAL_DEPS =3D $(am__append_43) SIM_UNINSTALL_LOCAL_DEPS =3D $(am__append_44) @@ -2169,6 +2195,43 @@ testsuite_common_CPPFLAGS =3D \ # opc2c leaks memory, and therefore makes AddressSanitizer unhappy. Disab= le # leak detection while running it. @SIM_ENABLE_ARCH_m32c_TRUE@m32c_OPC2C_RUN =3D ASAN_OPTIONS=3Ddetect_leaks= =3D0 m32c/opc2c$(EXEEXT) +@SIM_ENABLE_ARCH_m32r_TRUE@m32r_libsim_a_SOURCES =3D=20 +@SIM_ENABLE_ARCH_m32r_TRUE@m32r_libsim_a_LIBADD =3D \ +@SIM_ENABLE_ARCH_m32r_TRUE@ $(common_libcommon_a_OBJECTS) \ +@SIM_ENABLE_ARCH_m32r_TRUE@ $(patsubst %,m32r/%,$(SIM_NEW_COMMON_OBJS)) \ +@SIM_ENABLE_ARCH_m32r_TRUE@ $(patsubst %,m32r/dv-%.o,$(SIM_HW_DEVICES)) \ +@SIM_ENABLE_ARCH_m32r_TRUE@ $(patsubst %,m32r/dv-%.o,$(m32r_SIM_EXTRA_HW_D= EVICES)) \ +@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/modules.o \ +@SIM_ENABLE_ARCH_m32r_TRUE@ \ +@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cgen-run.o \ +@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cgen-scache.o \ +@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cgen-trace.o \ +@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cgen-utils.o \ +@SIM_ENABLE_ARCH_m32r_TRUE@ \ +@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/arch.o \ +@SIM_ENABLE_ARCH_m32r_TRUE@ \ +@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/m32r.o \ +@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cpu.o \ +@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/decode.o \ +@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/sem.o \ +@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/model.o \ +@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/mloop.o \ +@SIM_ENABLE_ARCH_m32r_TRUE@ \ +@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/m32rx.o \ +@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cpux.o \ +@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/decodex.o \ +@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/modelx.o \ +@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/mloopx.o \ +@SIM_ENABLE_ARCH_m32r_TRUE@ \ +@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/m32r2.o \ +@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cpu2.o \ +@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/decode2.o \ +@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/model2.o \ +@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/mloop2.o \ +@SIM_ENABLE_ARCH_m32r_TRUE@ \ +@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/sim-if.o \ +@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/traps.o + @SIM_ENABLE_ARCH_m32r_TRUE@m32r_run_SOURCES =3D=20 @SIM_ENABLE_ARCH_m32r_TRUE@m32r_run_LDADD =3D \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/nrun.o \ @@ -2261,8 +2324,8 @@ testsuite_common_CPPFLAGS =3D \ @SIM_ENABLE_ARCH_mips_TRUE@mips_BUILD_OUTPUTS =3D \ @SIM_ENABLE_ARCH_mips_TRUE@ $(mips_BUILT_SRC_FROM_IGEN_ITABLE) \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/stamp-igen-itable \ -@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_87) $(am__append_88) \ -@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_89) +@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_88) $(am__append_89) \ +@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_90) @SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_TRACE =3D # -G omit-line-numbers # -G= trace-rule-selection -G trace-rule-rejection -G trace-entries # -G trace-a= ll @SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN =3D $(srcdir)/mips/mips.igen @SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN_INC =3D \ @@ -2805,6 +2868,14 @@ m32c/libsim.a: $(m32c_libsim_a_OBJECTS) $(m32c_libsi= m_a_DEPENDENCIES) $(EXTRA_m3 $(AM_V_at)-rm -f m32c/libsim.a $(AM_V_AR)$(m32c_libsim_a_AR) m32c/libsim.a $(m32c_libsim_a_OBJECTS) $(m3= 2c_libsim_a_LIBADD) $(AM_V_at)$(RANLIB) m32c/libsim.a +m32r/$(am__dirstamp): + @$(MKDIR_P) m32r + @: > m32r/$(am__dirstamp) + +m32r/libsim.a: $(m32r_libsim_a_OBJECTS) $(m32r_libsim_a_DEPENDENCIES) $(EX= TRA_m32r_libsim_a_DEPENDENCIES) m32r/$(am__dirstamp) + $(AM_V_at)-rm -f m32r/libsim.a + $(AM_V_AR)$(m32r_libsim_a_AR) m32r/libsim.a $(m32r_libsim_a_OBJECTS) $(m3= 2r_libsim_a_LIBADD) + $(AM_V_at)$(RANLIB) m32r/libsim.a =20 clean-checkPROGRAMS: @list=3D'$(check_PROGRAMS)'; test -n "$$list" || exit 0; \ @@ -2962,9 +3033,6 @@ m32c/opc2c.$(OBJEXT): m32c/$(am__dirstamp) \ m32c/run$(EXEEXT): $(m32c_run_OBJECTS) $(m32c_run_DEPENDENCIES) $(EXTRA_m3= 2c_run_DEPENDENCIES) m32c/$(am__dirstamp) @rm -f m32c/run$(EXEEXT) $(AM_V_CCLD)$(LINK) $(m32c_run_OBJECTS) $(m32c_run_LDADD) $(LIBS) -m32r/$(am__dirstamp): - @$(MKDIR_P) m32r - @: > m32r/$(am__dirstamp) =20 m32r/run$(EXEEXT): $(m32r_run_OBJECTS) $(m32r_run_DEPENDENCIES) $(EXTRA_m3= 2r_run_DEPENDENCIES) m32r/$(am__dirstamp) @rm -f m32r/run$(EXEEXT) @@ -4433,6 +4501,13 @@ testsuite/common/bits64m63.c: testsuite/common/bits-= gen$(EXEEXT) testsuite/commo @SIM_ENABLE_ARCH_m32c_TRUE@m32c/r8c.c: m32c/r8c.opc m32c/opc2c$(EXEEXT) @SIM_ENABLE_ARCH_m32c_TRUE@ $(AM_V_GEN)$(m32c_OPC2C_RUN) -l $@.log $< > $@= .tmp @SIM_ENABLE_ARCH_m32c_TRUE@ $(AM_V_at)mv $@.tmp $@ +@SIM_ENABLE_ARCH_m32r_TRUE@$(m32r_libsim_a_OBJECTS) $(m32r_libsim_a_LIBADD= ): m32r/hw-config.h + +@SIM_ENABLE_ARCH_m32r_TRUE@m32r/%.o: m32r/%.c +@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@= F) + +@SIM_ENABLE_ARCH_m32r_TRUE@m32r/%.o: common/%.c +@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@= F) @SIM_ENABLE_ARCH_m32r_TRUE@m32r/modules.c: | $(m32r_BUILD_OUTPUTS) =20 @SIM_ENABLE_ARCH_m32r_TRUE@m32r/mloop.c m32r/eng.h: m32r/stamp-mloop ; @tr= ue diff --git a/sim/m32r/Makefile.in b/sim/m32r/Makefile.in index 644d8de7dd1..08cda449ca1 100644 --- a/sim/m32r/Makefile.in +++ b/sim/m32r/Makefile.in @@ -21,19 +21,7 @@ =20 arch =3D m32r =20 -M32R_OBJS =3D m32r.o cpu.o decode.o sem.o model.o mloop.o -M32RX_OBJS =3D m32rx.o cpux.o decodex.o modelx.o mloopx.o -M32R2_OBJS =3D m32r2.o cpu2.o decode2.o model2.o mloop2.o - -SIM_OBJS =3D \ - $(SIM_NEW_COMMON_OBJS) \ - cgen-utils.o cgen-trace.o cgen-scache.o \ - cgen-run.o \ - sim-if.o arch.o \ - $(M32R_OBJS) \ - $(M32RX_OBJS) \ - $(M32R2_OBJS) \ - traps.o +SIM_LIBSIM =3D =20 # Some modules don't build cleanly yet. cpu.o cpu2.o cpux.o m32r.o m32r2.o m32rx.o mloop.o mloop2.o mloopx.o sem.o= sim-if.o traps.o: SIM_WERROR_CFLAGS =3D diff --git a/sim/m32r/local.mk b/sim/m32r/local.mk index 9814ae5c6c1..afecaf6c8bc 100644 --- a/sim/m32r/local.mk +++ b/sim/m32r/local.mk @@ -16,6 +16,52 @@ ## You should have received a copy of the GNU General Public License ## along with this program. If not, see . =20 +%C%_libsim_a_SOURCES =3D +%C%_libsim_a_LIBADD =3D \ + $(common_libcommon_a_OBJECTS) \ + $(patsubst %,%D%/%,$(SIM_NEW_COMMON_OBJS)) \ + $(patsubst %,%D%/dv-%.o,$(SIM_HW_DEVICES)) \ + $(patsubst %,%D%/dv-%.o,$(%C%_SIM_EXTRA_HW_DEVICES)) \ + %D%/modules.o \ + \ + %D%/cgen-run.o \ + %D%/cgen-scache.o \ + %D%/cgen-trace.o \ + %D%/cgen-utils.o \ + \ + %D%/arch.o \ + \ + %D%/m32r.o \ + %D%/cpu.o \ + %D%/decode.o \ + %D%/sem.o \ + %D%/model.o \ + %D%/mloop.o \ + \ + %D%/m32rx.o \ + %D%/cpux.o \ + %D%/decodex.o \ + %D%/modelx.o \ + %D%/mloopx.o \ + \ + %D%/m32r2.o \ + %D%/cpu2.o \ + %D%/decode2.o \ + %D%/model2.o \ + %D%/mloop2.o \ + \ + %D%/sim-if.o \ + %D%/traps.o +$(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-config.h + +noinst_LIBRARIES +=3D %D%/libsim.a + +%D%/%.o: %D%/%.c + $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F) + +%D%/%.o: common/%.c + $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F) + %C%_run_SOURCES =3D %C%_run_LDADD =3D \ %D%/nrun.o \