From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1521) id 176353858CDB; Tue, 10 Jan 2023 06:24:52 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 176353858CDB DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1673331892; bh=sf40s5xGjNYOEKqIxEw7I47qW1Ro+L4IW+PeV0WItPI=; h=From:To:Subject:Date:From; b=defzHEOlxZ3rAR5VMOLxJiHlkZ96H8aFWSVMjDHwPplSOtfNN/5LbRRpN1RwtN0IJ 7CrENOtakF+EDPGzeQksozXmeS9bnfw9CiODIi6wbYy7sj3z95XMh96J8VOKpaE1JY J5FIUqYJHukxXQlRUUFNmzenqx1LyYNW/fBGMbJY= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Michael Frysinger To: gdb-cvs@sourceware.org Subject: [binutils-gdb] sim: pru: move libsim.a creation to top-level X-Act-Checkin: binutils-gdb X-Git-Author: Mike Frysinger X-Git-Refname: refs/heads/master X-Git-Oldrev: 4d998e1559ab9728597971325738a246857f8f6c X-Git-Newrev: 3373e27fe1b5513d95e03629355447c82a5e6937 Message-Id: <20230110062452.176353858CDB@sourceware.org> Date: Tue, 10 Jan 2023 06:24:52 +0000 (GMT) List-Id: https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D3373e27fe1b5= 513d95e03629355447c82a5e6937 commit 3373e27fe1b5513d95e03629355447c82a5e6937 Author: Mike Frysinger Date: Mon Dec 26 22:21:51 2022 -0500 sim: pru: move libsim.a creation to top-level =20 The objects are still compiled in the subdir, but the creation of the archive itself is in the top-level. This is a required step before we can move compilation itself up, and makes it easier to review. =20 The downside is that each object compile is a recursive make instead of a single one. On my 4 core system, it adds ~100msec to the build per port, so it's not great, but it shouldn't be a big deal. This will go away of course once the top-level compiles objects. Diff: --- sim/Makefile.in | 88 +++++++++++++++++++++++++++++++++++++------------= ---- sim/pru/Makefile.in | 5 +-- sim/pru/local.mk | 18 +++++++++++ 3 files changed, 80 insertions(+), 31 deletions(-) diff --git a/sim/Makefile.in b/sim/Makefile.in index 16f3dd68521..bdb407f8446 100644 --- a/sim/Makefile.in +++ b/sim/Makefile.in @@ -310,20 +310,21 @@ TESTS =3D testsuite/common/bits32m0$(EXEEXT) \ @SIM_ENABLE_ARCH_or1k_TRUE@am__append_114 =3D $(or1k_BUILD_OUTPUTS) @SIM_ENABLE_ARCH_or1k_TRUE@am__append_115 =3D $(or1k_BUILD_OUTPUTS) @SIM_ENABLE_ARCH_ppc_TRUE@am__append_116 =3D ppc/run ppc/psim -@SIM_ENABLE_ARCH_pru_TRUE@am__append_117 =3D pru/run -@SIM_ENABLE_ARCH_riscv_TRUE@am__append_118 =3D riscv/run -@SIM_ENABLE_ARCH_rl78_TRUE@am__append_119 =3D rl78/run -@SIM_ENABLE_ARCH_rx_TRUE@am__append_120 =3D rx/run -@SIM_ENABLE_ARCH_sh_TRUE@am__append_121 =3D sh/run -@SIM_ENABLE_ARCH_sh_TRUE@am__append_122 =3D \ +@SIM_ENABLE_ARCH_pru_TRUE@am__append_117 =3D pru/libsim.a +@SIM_ENABLE_ARCH_pru_TRUE@am__append_118 =3D pru/run +@SIM_ENABLE_ARCH_riscv_TRUE@am__append_119 =3D riscv/run +@SIM_ENABLE_ARCH_rl78_TRUE@am__append_120 =3D rl78/run +@SIM_ENABLE_ARCH_rx_TRUE@am__append_121 =3D rx/run +@SIM_ENABLE_ARCH_sh_TRUE@am__append_122 =3D sh/run +@SIM_ENABLE_ARCH_sh_TRUE@am__append_123 =3D \ @SIM_ENABLE_ARCH_sh_TRUE@ sh/code.c \ @SIM_ENABLE_ARCH_sh_TRUE@ sh/ppi.c =20 -@SIM_ENABLE_ARCH_sh_TRUE@am__append_123 =3D $(sh_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_sh_TRUE@am__append_124 =3D sh/gencode -@SIM_ENABLE_ARCH_sh_TRUE@am__append_125 =3D $(sh_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_v850_TRUE@am__append_126 =3D v850/run -@SIM_ENABLE_ARCH_v850_TRUE@am__append_127 =3D \ +@SIM_ENABLE_ARCH_sh_TRUE@am__append_124 =3D $(sh_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_sh_TRUE@am__append_125 =3D sh/gencode +@SIM_ENABLE_ARCH_sh_TRUE@am__append_126 =3D $(sh_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_v850_TRUE@am__append_127 =3D v850/run +@SIM_ENABLE_ARCH_v850_TRUE@am__append_128 =3D \ @SIM_ENABLE_ARCH_v850_TRUE@ v850/icache.h \ @SIM_ENABLE_ARCH_v850_TRUE@ v850/idecode.h \ @SIM_ENABLE_ARCH_v850_TRUE@ v850/semantics.h \ @@ -332,8 +333,8 @@ TESTS =3D testsuite/common/bits32m0$(EXEEXT) \ @SIM_ENABLE_ARCH_v850_TRUE@ v850/itable.h \ @SIM_ENABLE_ARCH_v850_TRUE@ v850/engine.h =20 -@SIM_ENABLE_ARCH_v850_TRUE@am__append_128 =3D $(v850_BUILD_OUTPUTS) @SIM_ENABLE_ARCH_v850_TRUE@am__append_129 =3D $(v850_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_v850_TRUE@am__append_130 =3D $(v850_BUILD_OUTPUTS) subdir =3D . ACLOCAL_M4 =3D $(top_srcdir)/aclocal.m4 am__aclocal_m4_deps =3D $(top_srcdir)/../config/acx.m4 \ @@ -799,6 +800,17 @@ or1k_libsim_a_AR =3D $(AR) $(ARFLAGS) @SIM_ENABLE_ARCH_or1k_TRUE@ or1k/sim-if.o or1k/traps.o am_or1k_libsim_a_OBJECTS =3D or1k_libsim_a_OBJECTS =3D $(am_or1k_libsim_a_OBJECTS) +pru_libsim_a_AR =3D $(AR) $(ARFLAGS) +@SIM_ENABLE_ARCH_pru_TRUE@pru_libsim_a_DEPENDENCIES =3D \ +@SIM_ENABLE_ARCH_pru_TRUE@ $(common_libcommon_a_OBJECTS) \ +@SIM_ENABLE_ARCH_pru_TRUE@ $(patsubst \ +@SIM_ENABLE_ARCH_pru_TRUE@ %,pru/%,$(SIM_NEW_COMMON_OBJS)) \ +@SIM_ENABLE_ARCH_pru_TRUE@ $(patsubst \ +@SIM_ENABLE_ARCH_pru_TRUE@ %,pru/dv-%.o,$(SIM_HW_DEVICES)) \ +@SIM_ENABLE_ARCH_pru_TRUE@ pru/interp.o pru/modules.o \ +@SIM_ENABLE_ARCH_pru_TRUE@ pru/sim-resume.o +am_pru_libsim_a_OBJECTS =3D +pru_libsim_a_OBJECTS =3D $(am_pru_libsim_a_OBJECTS) @SIM_ENABLE_IGEN_TRUE@am__EXEEXT_1 =3D $(IGEN) igen/filter$(EXEEXT) \ @SIM_ENABLE_IGEN_TRUE@ igen/gen$(EXEEXT) igen/ld-cache$(EXEEXT) \ @SIM_ENABLE_IGEN_TRUE@ igen/ld-decode$(EXEEXT) \ @@ -1134,12 +1146,12 @@ SOURCES =3D $(aarch64_libsim_a_SOURCES) $(arm_libsi= m_a_SOURCES) \ $(mcore_libsim_a_SOURCES) $(microblaze_libsim_a_SOURCES) \ $(mips_libsim_a_SOURCES) $(mn10300_libsim_a_SOURCES) \ $(moxie_libsim_a_SOURCES) $(msp430_libsim_a_SOURCES) \ - $(or1k_libsim_a_SOURCES) $(aarch64_run_SOURCES) \ - $(arm_run_SOURCES) $(avr_run_SOURCES) $(bfin_run_SOURCES) \ - $(bpf_run_SOURCES) $(cr16_gencode_SOURCES) $(cr16_run_SOURCES) \ - $(cris_run_SOURCES) $(cris_rvdummy_SOURCES) \ - $(d10v_gencode_SOURCES) $(d10v_run_SOURCES) \ - $(erc32_run_SOURCES) erc32/sis.c \ + $(or1k_libsim_a_SOURCES) $(pru_libsim_a_SOURCES) \ + $(aarch64_run_SOURCES) $(arm_run_SOURCES) $(avr_run_SOURCES) \ + $(bfin_run_SOURCES) $(bpf_run_SOURCES) $(cr16_gencode_SOURCES) \ + $(cr16_run_SOURCES) $(cris_run_SOURCES) \ + $(cris_rvdummy_SOURCES) $(d10v_gencode_SOURCES) \ + $(d10v_run_SOURCES) $(erc32_run_SOURCES) erc32/sis.c \ $(example_synacor_run_SOURCES) $(frv_run_SOURCES) \ $(ft32_run_SOURCES) $(h8300_run_SOURCES) \ $(igen_filter_SOURCES) $(igen_gen_SOURCES) \ @@ -1702,12 +1714,13 @@ noinst_LIBRARIES =3D common/libcommon.a $(am__appen= d_5) $(am__append_8) \ $(am__append_56) $(am__append_61) $(am__append_67) \ $(am__append_72) $(am__append_78) $(am__append_84) \ $(am__append_86) $(am__append_91) $(am__append_101) \ - $(am__append_107) $(am__append_109) $(am__append_111) + $(am__append_107) $(am__append_109) $(am__append_111) \ + $(am__append_117) BUILT_SOURCES =3D $(am__append_19) $(am__append_24) $(am__append_32) \ $(am__append_37) $(am__append_49) $(am__append_58) \ $(am__append_64) $(am__append_75) $(am__append_94) \ - $(am__append_104) $(am__append_113) $(am__append_122) \ - $(am__append_127) + $(am__append_104) $(am__append_113) $(am__append_123) \ + $(am__append_128) CLEANFILES =3D common/version.c common/version.c-stamp \ testsuite/common/bits-gen testsuite/common/bits32m0.c \ testsuite/common/bits32m31.c testsuite/common/bits64m0.c \ @@ -1722,7 +1735,7 @@ MOSTLYCLEANFILES =3D core $(common_HW_CONFIG_H_TARGET= S) $(patsubst \ $(am__append_51) $(am__append_60) $(am__append_66) \ $(am__append_71) $(am__append_77) $(am__append_83) \ $(am__append_99) $(am__append_106) $(am__append_115) \ - $(am__append_125) $(am__append_129) + $(am__append_126) $(am__append_130) AM_CFLAGS =3D $(WERROR_CFLAGS) $(WARN_CFLAGS) AM_CPPFLAGS =3D $(INCGNU) -I$(srcroot)/include -I../bfd -I.. \ $(SIM_HW_CFLAGS) $(SIM_INLINE) -I$(srcdir)/common \ @@ -1737,8 +1750,8 @@ SIM_ALL_RECURSIVE_DEPS =3D common/libcommon.a \ $(am__append_33) $(am__append_38) $(am__append_50) \ $(am__append_59) $(am__append_65) $(am__append_69) \ $(am__append_76) $(am__append_81) $(am__append_98) \ - $(am__append_105) $(am__append_114) $(am__append_123) \ - $(am__append_128) + $(am__append_105) $(am__append_114) $(am__append_124) \ + $(am__append_129) SIM_INSTALL_DATA_LOCAL_DEPS =3D=20 SIM_INSTALL_EXEC_LOCAL_DEPS =3D $(am__append_43) SIM_UNINSTALL_LOCAL_DEPS =3D $(am__append_44) @@ -2687,6 +2700,15 @@ testsuite_common_CPPFLAGS =3D \ =20 @SIM_ENABLE_ARCH_ppc_TRUE@ppcdocdir =3D $(docdir)/ppc @SIM_ENABLE_ARCH_ppc_TRUE@ppcdoc_DATA =3D ppc/BUGS ppc/INSTALL ppc/README = ppc/RUN +@SIM_ENABLE_ARCH_pru_TRUE@pru_libsim_a_SOURCES =3D=20 +@SIM_ENABLE_ARCH_pru_TRUE@pru_libsim_a_LIBADD =3D \ +@SIM_ENABLE_ARCH_pru_TRUE@ $(common_libcommon_a_OBJECTS) \ +@SIM_ENABLE_ARCH_pru_TRUE@ $(patsubst %,pru/%,$(SIM_NEW_COMMON_OBJS)) \ +@SIM_ENABLE_ARCH_pru_TRUE@ $(patsubst %,pru/dv-%.o,$(SIM_HW_DEVICES)) \ +@SIM_ENABLE_ARCH_pru_TRUE@ pru/interp.o \ +@SIM_ENABLE_ARCH_pru_TRUE@ pru/modules.o \ +@SIM_ENABLE_ARCH_pru_TRUE@ pru/sim-resume.o + @SIM_ENABLE_ARCH_pru_TRUE@pru_run_SOURCES =3D=20 @SIM_ENABLE_ARCH_pru_TRUE@pru_run_LDADD =3D \ @SIM_ENABLE_ARCH_pru_TRUE@ pru/nrun.o \ @@ -3214,6 +3236,14 @@ or1k/libsim.a: $(or1k_libsim_a_OBJECTS) $(or1k_libsi= m_a_DEPENDENCIES) $(EXTRA_or $(AM_V_at)-rm -f or1k/libsim.a $(AM_V_AR)$(or1k_libsim_a_AR) or1k/libsim.a $(or1k_libsim_a_OBJECTS) $(or= 1k_libsim_a_LIBADD) $(AM_V_at)$(RANLIB) or1k/libsim.a +pru/$(am__dirstamp): + @$(MKDIR_P) pru + @: > pru/$(am__dirstamp) + +pru/libsim.a: $(pru_libsim_a_OBJECTS) $(pru_libsim_a_DEPENDENCIES) $(EXTRA= _pru_libsim_a_DEPENDENCIES) pru/$(am__dirstamp) + $(AM_V_at)-rm -f pru/libsim.a + $(AM_V_AR)$(pru_libsim_a_AR) pru/libsim.a $(pru_libsim_a_OBJECTS) $(pru_l= ibsim_a_LIBADD) + $(AM_V_at)$(RANLIB) pru/libsim.a =20 clean-checkPROGRAMS: @list=3D'$(check_PROGRAMS)'; test -n "$$list" || exit 0; \ @@ -3431,9 +3461,6 @@ ppc/psim.$(OBJEXT): ppc/$(am__dirstamp) ppc/$(DEPDIR)= /$(am__dirstamp) ppc/run$(EXEEXT): $(ppc_run_OBJECTS) $(ppc_run_DEPENDENCIES) $(EXTRA_ppc_r= un_DEPENDENCIES) ppc/$(am__dirstamp) @rm -f ppc/run$(EXEEXT) $(AM_V_CCLD)$(LINK) $(ppc_run_OBJECTS) $(ppc_run_LDADD) $(LIBS) -pru/$(am__dirstamp): - @$(MKDIR_P) pru - @: > pru/$(am__dirstamp) =20 pru/run$(EXEEXT): $(pru_run_OBJECTS) $(pru_run_DEPENDENCIES) $(EXTRA_pru_r= un_DEPENDENCIES) pru/$(am__dirstamp) @rm -f pru/run$(EXEEXT) @@ -5219,6 +5246,13 @@ testsuite/common/bits64m63.c: testsuite/common/bits-= gen$(EXEEXT) testsuite/commo @SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_GEN)$(srcdir)/ppc/spreg-gen.py --header = $@.tmp @SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change $@= .tmp $(srcdir)/ppc/spreg.h @SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)touch $(srcdir)/ppc/spreg.h +@SIM_ENABLE_ARCH_pru_TRUE@$(pru_libsim_a_OBJECTS) $(pru_libsim_a_LIBADD): = pru/hw-config.h + +@SIM_ENABLE_ARCH_pru_TRUE@pru/%.o: pru/%.c +@SIM_ENABLE_ARCH_pru_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F) + +@SIM_ENABLE_ARCH_pru_TRUE@pru/%.o: common/%.c +@SIM_ENABLE_ARCH_pru_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F) =20 @SIM_ENABLE_ARCH_rl78_TRUE@rl78/%.o: rl78/%.c | rl78/libsim.a $(SIM_ALL_RE= CURSIVE_DEPS) @SIM_ENABLE_ARCH_rl78_TRUE@ $(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F) diff --git a/sim/pru/Makefile.in b/sim/pru/Makefile.in index b81d0967e7a..9b2f2f0498a 100644 --- a/sim/pru/Makefile.in +++ b/sim/pru/Makefile.in @@ -19,9 +19,6 @@ =20 ## COMMON_PRE_CONFIG_FRAG =20 -SIM_OBJS =3D \ - $(SIM_NEW_COMMON_OBJS) \ - interp.o \ - sim-resume.o +SIM_LIBSIM =3D =20 ## COMMON_POST_CONFIG_FRAG diff --git a/sim/pru/local.mk b/sim/pru/local.mk index 5992f0ce161..0c3018cbeb2 100644 --- a/sim/pru/local.mk +++ b/sim/pru/local.mk @@ -16,6 +16,24 @@ ## You should have received a copy of the GNU General Public License ## along with this program. If not, see . =20 +%C%_libsim_a_SOURCES =3D +%C%_libsim_a_LIBADD =3D \ + $(common_libcommon_a_OBJECTS) \ + $(patsubst %,%D%/%,$(SIM_NEW_COMMON_OBJS)) \ + $(patsubst %,%D%/dv-%.o,$(SIM_HW_DEVICES)) \ + %D%/interp.o \ + %D%/modules.o \ + %D%/sim-resume.o +$(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-config.h + +noinst_LIBRARIES +=3D %D%/libsim.a + +%D%/%.o: %D%/%.c + $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F) + +%D%/%.o: common/%.c + $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F) + %C%_run_SOURCES =3D %C%_run_LDADD =3D \ %D%/nrun.o \