From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1521) id 7EA343858D1E; Sun, 15 Jan 2023 01:42:19 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 7EA343858D1E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1673746940; bh=JCLhc91SNkL9gbR5jAAHV0Lxy0nQU0h9gYcFvXHU7RU=; h=From:To:Subject:Date:From; b=ZgxcQKClccqATtAcQZmihdeNjBfYsG68b8k81PUeIsyxzmrQqLPY7nPDGhFr8aMWK QQG1FYn01/szj+oavmTZ7lWcqozsdHkb9H5fT13IWLhivswEagbdupSa+zz7yNo1kH Lp+ma6qBntKcXjL7NbaP7Uw92XEBmwB/9hzlm4uY= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Michael Frysinger To: gdb-cvs@sourceware.org Subject: [binutils-gdb] sim: build: drop AM_MAKEFLAGS settings X-Act-Checkin: binutils-gdb X-Git-Author: Mike Frysinger X-Git-Refname: refs/heads/master X-Git-Oldrev: 936b119d439cd67b691f5ee6eac6a8a8cb40c960 X-Git-Newrev: 068b723abc3f642f2fa5408908049d3d21a98588 Message-Id: <20230115014220.7EA343858D1E@sourceware.org> Date: Sun, 15 Jan 2023 01:42:19 +0000 (GMT) List-Id: https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D068b723abc3f= 642f2fa5408908049d3d21a98588 commit 068b723abc3f642f2fa5408908049d3d21a98588 Author: Mike Frysinger Date: Sun Jan 1 23:02:28 2023 -0500 sim: build: drop AM_MAKEFLAGS settings =20 We don't have any recursive builds anymore, so we can drop this logic. Diff: --- sim/Makefile.am | 1 - sim/Makefile.in | 334 +++++++++++++++++++++++++----------------------= ---- sim/bfin/local.mk | 1 - sim/common/local.mk | 4 - sim/cris/local.mk | 1 - sim/lm32/local.mk | 1 - sim/m32r/local.mk | 1 - sim/m68hc11/local.mk | 1 - sim/mips/local.mk | 1 - sim/mn10300/local.mk | 1 - 10 files changed, 161 insertions(+), 185 deletions(-) diff --git a/sim/Makefile.am b/sim/Makefile.am index 29086d22d68..0e9fc3c67a9 100644 --- a/sim/Makefile.am +++ b/sim/Makefile.am @@ -27,7 +27,6 @@ srcroot =3D $(srcdir)/.. SUBDIRS =3D @subdirs@ =20 SIM_PRIMARY_TARGET =3D @SIM_PRIMARY_TARGET@ -AM_MAKEFLAGS =3D =20 ## We don't set some of these vars here, but we need to define them so the= y may ## be used consistently in local.mk files we include below. diff --git a/sim/Makefile.in b/sim/Makefile.in index 14db403586f..c2669fd1505 100644 --- a/sim/Makefile.in +++ b/sim/Makefile.in @@ -131,111 +131,105 @@ EXTRA_PROGRAMS =3D $(am__EXEEXT_2) testsuite/common= /bits-gen$(EXEEXT) \ @SIM_ENABLE_HW_TRUE@ $(SIM_COMMON_HW_OBJS) \ @SIM_ENABLE_HW_TRUE@ $(SIM_HW_SOCKSER) =20 -@SIM_ENABLE_HW_TRUE@am__append_3 =3D SIM_HW_DEVICES_=3D"$(SIM_HW_DEVICES)" -@SIM_ENABLE_IGEN_TRUE@am__append_4 =3D $(IGEN) -@SIM_ENABLE_IGEN_TRUE@am__append_5 =3D igen/libigen.a +@SIM_ENABLE_IGEN_TRUE@am__append_3 =3D $(IGEN) +@SIM_ENABLE_IGEN_TRUE@am__append_4 =3D igen/libigen.a +@SIM_ENABLE_IGEN_TRUE@am__append_5 =3D $(igen_IGEN_TOOLS) @SIM_ENABLE_IGEN_TRUE@am__append_6 =3D $(igen_IGEN_TOOLS) -@SIM_ENABLE_IGEN_TRUE@am__append_7 =3D $(igen_IGEN_TOOLS) TESTS =3D testsuite/common/bits32m0$(EXEEXT) \ testsuite/common/bits32m31$(EXEEXT) \ testsuite/common/bits64m0$(EXEEXT) \ testsuite/common/bits64m63$(EXEEXT) \ testsuite/common/alu-tst$(EXEEXT) -@SIM_ENABLE_ARCH_aarch64_TRUE@am__append_8 =3D aarch64/libsim.a -@SIM_ENABLE_ARCH_aarch64_TRUE@am__append_9 =3D aarch64/run -@SIM_ENABLE_ARCH_arm_TRUE@am__append_10 =3D arm/libsim.a -@SIM_ENABLE_ARCH_arm_TRUE@am__append_11 =3D arm/run -@SIM_ENABLE_ARCH_avr_TRUE@am__append_12 =3D avr/libsim.a -@SIM_ENABLE_ARCH_avr_TRUE@am__append_13 =3D avr/run -@SIM_ENABLE_ARCH_bfin_TRUE@am__append_14 =3D bfin/libsim.a -@SIM_ENABLE_ARCH_bfin_TRUE@am__append_15 =3D bfin/run -@SIM_ENABLE_ARCH_bfin_TRUE@am__append_16 =3D bfin_SIM_EXTRA_HW_DEVICES=3D"= $(bfin_SIM_EXTRA_HW_DEVICES)" -@SIM_ENABLE_ARCH_bpf_TRUE@am__append_17 =3D bpf/libsim.a -@SIM_ENABLE_ARCH_bpf_TRUE@am__append_18 =3D bpf/run -@SIM_ENABLE_ARCH_bpf_TRUE@am__append_19 =3D \ +@SIM_ENABLE_ARCH_aarch64_TRUE@am__append_7 =3D aarch64/libsim.a +@SIM_ENABLE_ARCH_aarch64_TRUE@am__append_8 =3D aarch64/run +@SIM_ENABLE_ARCH_arm_TRUE@am__append_9 =3D arm/libsim.a +@SIM_ENABLE_ARCH_arm_TRUE@am__append_10 =3D arm/run +@SIM_ENABLE_ARCH_avr_TRUE@am__append_11 =3D avr/libsim.a +@SIM_ENABLE_ARCH_avr_TRUE@am__append_12 =3D avr/run +@SIM_ENABLE_ARCH_bfin_TRUE@am__append_13 =3D bfin/libsim.a +@SIM_ENABLE_ARCH_bfin_TRUE@am__append_14 =3D bfin/run +@SIM_ENABLE_ARCH_bpf_TRUE@am__append_15 =3D bpf/libsim.a +@SIM_ENABLE_ARCH_bpf_TRUE@am__append_16 =3D bpf/run +@SIM_ENABLE_ARCH_bpf_TRUE@am__append_17 =3D \ @SIM_ENABLE_ARCH_bpf_TRUE@ bpf/eng-le.h \ @SIM_ENABLE_ARCH_bpf_TRUE@ bpf/eng-be.h =20 -@SIM_ENABLE_ARCH_bpf_TRUE@am__append_20 =3D $(bpf_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_bpf_TRUE@am__append_21 =3D $(bpf_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_cr16_TRUE@am__append_22 =3D cr16/libsim.a -@SIM_ENABLE_ARCH_cr16_TRUE@am__append_23 =3D cr16/run -@SIM_ENABLE_ARCH_cr16_TRUE@am__append_24 =3D cr16/simops.h +@SIM_ENABLE_ARCH_bpf_TRUE@am__append_18 =3D $(bpf_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_bpf_TRUE@am__append_19 =3D $(bpf_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_cr16_TRUE@am__append_20 =3D cr16/libsim.a +@SIM_ENABLE_ARCH_cr16_TRUE@am__append_21 =3D cr16/run +@SIM_ENABLE_ARCH_cr16_TRUE@am__append_22 =3D cr16/simops.h +@SIM_ENABLE_ARCH_cr16_TRUE@am__append_23 =3D $(cr16_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_cr16_TRUE@am__append_24 =3D cr16/gencode @SIM_ENABLE_ARCH_cr16_TRUE@am__append_25 =3D $(cr16_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_cr16_TRUE@am__append_26 =3D cr16/gencode -@SIM_ENABLE_ARCH_cr16_TRUE@am__append_27 =3D $(cr16_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_cris_TRUE@am__append_28 =3D cris/libsim.a -@SIM_ENABLE_ARCH_cris_TRUE@am__append_29 =3D cris/run -@SIM_ENABLE_ARCH_cris_TRUE@am__append_30 =3D cris_SIM_EXTRA_HW_DEVICES=3D"= $(cris_SIM_EXTRA_HW_DEVICES)" -@SIM_ENABLE_ARCH_cris_TRUE@am__append_31 =3D cris/rvdummy -@SIM_ENABLE_ARCH_cris_TRUE@am__append_32 =3D \ +@SIM_ENABLE_ARCH_cris_TRUE@am__append_26 =3D cris/libsim.a +@SIM_ENABLE_ARCH_cris_TRUE@am__append_27 =3D cris/run +@SIM_ENABLE_ARCH_cris_TRUE@am__append_28 =3D cris/rvdummy +@SIM_ENABLE_ARCH_cris_TRUE@am__append_29 =3D \ @SIM_ENABLE_ARCH_cris_TRUE@ cris/engv10.h \ @SIM_ENABLE_ARCH_cris_TRUE@ cris/engv32.h =20 -@SIM_ENABLE_ARCH_cris_TRUE@am__append_33 =3D $(cris_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_cris_TRUE@am__append_34 =3D $(cris_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_d10v_TRUE@am__append_35 =3D d10v/libsim.a -@SIM_ENABLE_ARCH_d10v_TRUE@am__append_36 =3D d10v/run -@SIM_ENABLE_ARCH_d10v_TRUE@am__append_37 =3D d10v/simops.h -@SIM_ENABLE_ARCH_d10v_TRUE@am__append_38 =3D $(d10v_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_d10v_TRUE@am__append_39 =3D d10v/gencode -@SIM_ENABLE_ARCH_d10v_TRUE@am__append_40 =3D $(d10v_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_erc32_TRUE@am__append_41 =3D erc32/libsim.a -@SIM_ENABLE_ARCH_erc32_TRUE@am__append_42 =3D erc32/run erc32/sis -@SIM_ENABLE_ARCH_erc32_TRUE@am__append_43 =3D sim-%D-install-exec-local -@SIM_ENABLE_ARCH_erc32_TRUE@am__append_44 =3D sim-erc32-uninstall-local -@SIM_ENABLE_ARCH_examples_TRUE@am__append_45 =3D example-synacor/libsim.a -@SIM_ENABLE_ARCH_examples_TRUE@am__append_46 =3D example-synacor/run -@SIM_ENABLE_ARCH_frv_TRUE@am__append_47 =3D frv/libsim.a -@SIM_ENABLE_ARCH_frv_TRUE@am__append_48 =3D frv/run -@SIM_ENABLE_ARCH_frv_TRUE@am__append_49 =3D frv/eng.h -@SIM_ENABLE_ARCH_frv_TRUE@am__append_50 =3D $(frv_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_frv_TRUE@am__append_51 =3D $(frv_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_ft32_TRUE@am__append_52 =3D ft32/libsim.a -@SIM_ENABLE_ARCH_ft32_TRUE@am__append_53 =3D ft32/run -@SIM_ENABLE_ARCH_h8300_TRUE@am__append_54 =3D h8300/libsim.a -@SIM_ENABLE_ARCH_h8300_TRUE@am__append_55 =3D h8300/run -@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_56 =3D iq2000/libsim.a -@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_57 =3D iq2000/run -@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_58 =3D iq2000/eng.h -@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_59 =3D $(iq2000_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_60 =3D $(iq2000_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_lm32_TRUE@am__append_61 =3D lm32/libsim.a -@SIM_ENABLE_ARCH_lm32_TRUE@am__append_62 =3D lm32/run -@SIM_ENABLE_ARCH_lm32_TRUE@am__append_63 =3D lm32_SIM_EXTRA_HW_DEVICES=3D"= $(lm32_SIM_EXTRA_HW_DEVICES)" -@SIM_ENABLE_ARCH_lm32_TRUE@am__append_64 =3D lm32/eng.h -@SIM_ENABLE_ARCH_lm32_TRUE@am__append_65 =3D $(lm32_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_lm32_TRUE@am__append_66 =3D $(lm32_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_m32c_TRUE@am__append_67 =3D m32c/libsim.a -@SIM_ENABLE_ARCH_m32c_TRUE@am__append_68 =3D m32c/run -@SIM_ENABLE_ARCH_m32c_TRUE@am__append_69 =3D $(m32c_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_m32c_TRUE@am__append_70 =3D m32c/opc2c -@SIM_ENABLE_ARCH_m32c_TRUE@am__append_71 =3D \ +@SIM_ENABLE_ARCH_cris_TRUE@am__append_30 =3D $(cris_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_cris_TRUE@am__append_31 =3D $(cris_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_d10v_TRUE@am__append_32 =3D d10v/libsim.a +@SIM_ENABLE_ARCH_d10v_TRUE@am__append_33 =3D d10v/run +@SIM_ENABLE_ARCH_d10v_TRUE@am__append_34 =3D d10v/simops.h +@SIM_ENABLE_ARCH_d10v_TRUE@am__append_35 =3D $(d10v_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_d10v_TRUE@am__append_36 =3D d10v/gencode +@SIM_ENABLE_ARCH_d10v_TRUE@am__append_37 =3D $(d10v_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_erc32_TRUE@am__append_38 =3D erc32/libsim.a +@SIM_ENABLE_ARCH_erc32_TRUE@am__append_39 =3D erc32/run erc32/sis +@SIM_ENABLE_ARCH_erc32_TRUE@am__append_40 =3D sim-%D-install-exec-local +@SIM_ENABLE_ARCH_erc32_TRUE@am__append_41 =3D sim-erc32-uninstall-local +@SIM_ENABLE_ARCH_examples_TRUE@am__append_42 =3D example-synacor/libsim.a +@SIM_ENABLE_ARCH_examples_TRUE@am__append_43 =3D example-synacor/run +@SIM_ENABLE_ARCH_frv_TRUE@am__append_44 =3D frv/libsim.a +@SIM_ENABLE_ARCH_frv_TRUE@am__append_45 =3D frv/run +@SIM_ENABLE_ARCH_frv_TRUE@am__append_46 =3D frv/eng.h +@SIM_ENABLE_ARCH_frv_TRUE@am__append_47 =3D $(frv_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_frv_TRUE@am__append_48 =3D $(frv_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_ft32_TRUE@am__append_49 =3D ft32/libsim.a +@SIM_ENABLE_ARCH_ft32_TRUE@am__append_50 =3D ft32/run +@SIM_ENABLE_ARCH_h8300_TRUE@am__append_51 =3D h8300/libsim.a +@SIM_ENABLE_ARCH_h8300_TRUE@am__append_52 =3D h8300/run +@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_53 =3D iq2000/libsim.a +@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_54 =3D iq2000/run +@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_55 =3D iq2000/eng.h +@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_56 =3D $(iq2000_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_57 =3D $(iq2000_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_lm32_TRUE@am__append_58 =3D lm32/libsim.a +@SIM_ENABLE_ARCH_lm32_TRUE@am__append_59 =3D lm32/run +@SIM_ENABLE_ARCH_lm32_TRUE@am__append_60 =3D lm32/eng.h +@SIM_ENABLE_ARCH_lm32_TRUE@am__append_61 =3D $(lm32_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_lm32_TRUE@am__append_62 =3D $(lm32_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_m32c_TRUE@am__append_63 =3D m32c/libsim.a +@SIM_ENABLE_ARCH_m32c_TRUE@am__append_64 =3D m32c/run +@SIM_ENABLE_ARCH_m32c_TRUE@am__append_65 =3D $(m32c_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_m32c_TRUE@am__append_66 =3D m32c/opc2c +@SIM_ENABLE_ARCH_m32c_TRUE@am__append_67 =3D \ @SIM_ENABLE_ARCH_m32c_TRUE@ $(m32c_BUILD_OUTPUTS) \ @SIM_ENABLE_ARCH_m32c_TRUE@ m32c/m32c.c.log \ @SIM_ENABLE_ARCH_m32c_TRUE@ m32c/r8c.c.log =20 -@SIM_ENABLE_ARCH_m32r_TRUE@am__append_72 =3D m32r/libsim.a -@SIM_ENABLE_ARCH_m32r_TRUE@am__append_73 =3D m32r/run -@SIM_ENABLE_ARCH_m32r_TRUE@am__append_74 =3D m32r_SIM_EXTRA_HW_DEVICES=3D"= $(m32r_SIM_EXTRA_HW_DEVICES)" -@SIM_ENABLE_ARCH_m32r_TRUE@am__append_75 =3D \ +@SIM_ENABLE_ARCH_m32r_TRUE@am__append_68 =3D m32r/libsim.a +@SIM_ENABLE_ARCH_m32r_TRUE@am__append_69 =3D m32r/run +@SIM_ENABLE_ARCH_m32r_TRUE@am__append_70 =3D \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/eng.h \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/engx.h \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/eng2.h =20 -@SIM_ENABLE_ARCH_m32r_TRUE@am__append_76 =3D $(m32r_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_m32r_TRUE@am__append_77 =3D $(m32r_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_78 =3D m68hc11/libsim.a -@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_79 =3D m68hc11/run -@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_80 =3D m68hc11_SIM_EXTRA_HW_DEVIC= ES=3D"$(m68hc11_SIM_EXTRA_HW_DEVICES)" -@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_81 =3D $(m68hc11_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_82 =3D m68hc11/gencode -@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_83 =3D $(m68hc11_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_mcore_TRUE@am__append_84 =3D mcore/libsim.a -@SIM_ENABLE_ARCH_mcore_TRUE@am__append_85 =3D mcore/run -@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_86 =3D microblaze/libsim.a -@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_87 =3D microblaze/run -@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_88 = =3D \ +@SIM_ENABLE_ARCH_m32r_TRUE@am__append_71 =3D $(m32r_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_m32r_TRUE@am__append_72 =3D $(m32r_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_73 =3D m68hc11/libsim.a +@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_74 =3D m68hc11/run +@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_75 =3D $(m68hc11_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_76 =3D m68hc11/gencode +@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_77 =3D $(m68hc11_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_mcore_TRUE@am__append_78 =3D mcore/libsim.a +@SIM_ENABLE_ARCH_mcore_TRUE@am__append_79 =3D mcore/run +@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_80 =3D microblaze/libsim.a +@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_81 =3D microblaze/run +@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_82 = =3D \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/support.o \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/itable.o \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/semantics.= o \ @@ -244,7 +238,7 @@ TESTS =3D testsuite/common/bits32m0$(EXEEXT) \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/engine.o \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/irun.o =20 -@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_89 =3D \ +@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_83 =3D \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m16_support.o= \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m16_semantics= .o \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m16_idecode.o= \ @@ -258,38 +252,36 @@ TESTS =3D testsuite/common/bits32m0$(EXEEXT) \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/itable.o \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m16run.o =20 -@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_90 =3D= \ +@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_84 =3D= \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ $(SIM_MIPS_MULTI= _OBJ) \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/itable.o \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/multi-run.o =20 -@SIM_ENABLE_ARCH_mips_TRUE@am__append_91 =3D mips/libsim.a -@SIM_ENABLE_ARCH_mips_TRUE@am__append_92 =3D mips/run -@SIM_ENABLE_ARCH_mips_TRUE@am__append_93 =3D mips_SIM_EXTRA_HW_DEVICES=3D"= $(mips_SIM_EXTRA_HW_DEVICES)" -@SIM_ENABLE_ARCH_mips_TRUE@am__append_94 =3D mips/itable.h \ +@SIM_ENABLE_ARCH_mips_TRUE@am__append_85 =3D mips/libsim.a +@SIM_ENABLE_ARCH_mips_TRUE@am__append_86 =3D mips/run +@SIM_ENABLE_ARCH_mips_TRUE@am__append_87 =3D mips/itable.h \ @SIM_ENABLE_ARCH_mips_TRUE@ $(SIM_MIPS_MULTI_SRC) -@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_95 = =3D \ +@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_88 = =3D \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ $(mips_BUILT_SR= C_FROM_GEN_MODE_SINGLE) \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/stamp-gen-= mode-single =20 -@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_96 =3D \ +@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_89 =3D \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ $(mips_BUILT_SRC_F= ROM_GEN_MODE_M16_M16) \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ $(mips_BUILT_SRC_F= ROM_GEN_MODE_M16_M32) \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/stamp-gen-mod= e-m16-m16 \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/stamp-gen-mod= e-m16-m32 =20 -@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_97 =3D= \ +@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_90 =3D= \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ $(SIM_MIPS_MULTI= _SRC) \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/stamp-gen-m= ode-multi-igen \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/stamp-gen-m= ode-multi-run =20 -@SIM_ENABLE_ARCH_mips_TRUE@am__append_98 =3D $(mips_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_mips_TRUE@am__append_99 =3D $(mips_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_mips_TRUE@am__append_100 =3D mips/multi-include.h mips/mu= lti-run.c -@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_101 =3D mn10300/libsim.a -@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_102 =3D mn10300/run -@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_103 =3D mn10300_SIM_EXTRA_HW_DEVI= CES=3D"$(mn10300_SIM_EXTRA_HW_DEVICES)" -@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_104 =3D \ +@SIM_ENABLE_ARCH_mips_TRUE@am__append_91 =3D $(mips_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_mips_TRUE@am__append_92 =3D $(mips_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_mips_TRUE@am__append_93 =3D mips/multi-include.h mips/mul= ti-run.c +@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_94 =3D mn10300/libsim.a +@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_95 =3D mn10300/run +@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_96 =3D \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/icache.h \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/idecode.h \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/semantics.h \ @@ -298,38 +290,38 @@ TESTS =3D testsuite/common/bits32m0$(EXEEXT) \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/itable.h \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/engine.h =20 -@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_105 =3D $(mn10300_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_106 =3D $(mn10300_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_moxie_TRUE@am__append_107 =3D moxie/libsim.a -@SIM_ENABLE_ARCH_moxie_TRUE@am__append_108 =3D moxie/run -@SIM_ENABLE_ARCH_msp430_TRUE@am__append_109 =3D msp430/libsim.a -@SIM_ENABLE_ARCH_msp430_TRUE@am__append_110 =3D msp430/run -@SIM_ENABLE_ARCH_or1k_TRUE@am__append_111 =3D or1k/libsim.a -@SIM_ENABLE_ARCH_or1k_TRUE@am__append_112 =3D or1k/run -@SIM_ENABLE_ARCH_or1k_TRUE@am__append_113 =3D or1k/eng.h -@SIM_ENABLE_ARCH_or1k_TRUE@am__append_114 =3D $(or1k_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_or1k_TRUE@am__append_115 =3D $(or1k_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_ppc_TRUE@am__append_116 =3D ppc/run ppc/psim -@SIM_ENABLE_ARCH_pru_TRUE@am__append_117 =3D pru/libsim.a -@SIM_ENABLE_ARCH_pru_TRUE@am__append_118 =3D pru/run -@SIM_ENABLE_ARCH_riscv_TRUE@am__append_119 =3D riscv/libsim.a -@SIM_ENABLE_ARCH_riscv_TRUE@am__append_120 =3D riscv/run -@SIM_ENABLE_ARCH_rl78_TRUE@am__append_121 =3D rl78/libsim.a -@SIM_ENABLE_ARCH_rl78_TRUE@am__append_122 =3D rl78/run -@SIM_ENABLE_ARCH_rx_TRUE@am__append_123 =3D rx/libsim.a -@SIM_ENABLE_ARCH_rx_TRUE@am__append_124 =3D rx/run -@SIM_ENABLE_ARCH_sh_TRUE@am__append_125 =3D sh/libsim.a -@SIM_ENABLE_ARCH_sh_TRUE@am__append_126 =3D sh/run -@SIM_ENABLE_ARCH_sh_TRUE@am__append_127 =3D \ +@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_97 =3D $(mn10300_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_98 =3D $(mn10300_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_moxie_TRUE@am__append_99 =3D moxie/libsim.a +@SIM_ENABLE_ARCH_moxie_TRUE@am__append_100 =3D moxie/run +@SIM_ENABLE_ARCH_msp430_TRUE@am__append_101 =3D msp430/libsim.a +@SIM_ENABLE_ARCH_msp430_TRUE@am__append_102 =3D msp430/run +@SIM_ENABLE_ARCH_or1k_TRUE@am__append_103 =3D or1k/libsim.a +@SIM_ENABLE_ARCH_or1k_TRUE@am__append_104 =3D or1k/run +@SIM_ENABLE_ARCH_or1k_TRUE@am__append_105 =3D or1k/eng.h +@SIM_ENABLE_ARCH_or1k_TRUE@am__append_106 =3D $(or1k_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_or1k_TRUE@am__append_107 =3D $(or1k_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_ppc_TRUE@am__append_108 =3D ppc/run ppc/psim +@SIM_ENABLE_ARCH_pru_TRUE@am__append_109 =3D pru/libsim.a +@SIM_ENABLE_ARCH_pru_TRUE@am__append_110 =3D pru/run +@SIM_ENABLE_ARCH_riscv_TRUE@am__append_111 =3D riscv/libsim.a +@SIM_ENABLE_ARCH_riscv_TRUE@am__append_112 =3D riscv/run +@SIM_ENABLE_ARCH_rl78_TRUE@am__append_113 =3D rl78/libsim.a +@SIM_ENABLE_ARCH_rl78_TRUE@am__append_114 =3D rl78/run +@SIM_ENABLE_ARCH_rx_TRUE@am__append_115 =3D rx/libsim.a +@SIM_ENABLE_ARCH_rx_TRUE@am__append_116 =3D rx/run +@SIM_ENABLE_ARCH_sh_TRUE@am__append_117 =3D sh/libsim.a +@SIM_ENABLE_ARCH_sh_TRUE@am__append_118 =3D sh/run +@SIM_ENABLE_ARCH_sh_TRUE@am__append_119 =3D \ @SIM_ENABLE_ARCH_sh_TRUE@ sh/code.c \ @SIM_ENABLE_ARCH_sh_TRUE@ sh/ppi.c =20 -@SIM_ENABLE_ARCH_sh_TRUE@am__append_128 =3D $(sh_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_sh_TRUE@am__append_129 =3D sh/gencode -@SIM_ENABLE_ARCH_sh_TRUE@am__append_130 =3D $(sh_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_v850_TRUE@am__append_131 =3D v850/libsim.a -@SIM_ENABLE_ARCH_v850_TRUE@am__append_132 =3D v850/run -@SIM_ENABLE_ARCH_v850_TRUE@am__append_133 =3D \ +@SIM_ENABLE_ARCH_sh_TRUE@am__append_120 =3D $(sh_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_sh_TRUE@am__append_121 =3D sh/gencode +@SIM_ENABLE_ARCH_sh_TRUE@am__append_122 =3D $(sh_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_v850_TRUE@am__append_123 =3D v850/libsim.a +@SIM_ENABLE_ARCH_v850_TRUE@am__append_124 =3D v850/run +@SIM_ENABLE_ARCH_v850_TRUE@am__append_125 =3D \ @SIM_ENABLE_ARCH_v850_TRUE@ v850/icache.h \ @SIM_ENABLE_ARCH_v850_TRUE@ v850/idecode.h \ @SIM_ENABLE_ARCH_v850_TRUE@ v850/semantics.h \ @@ -338,8 +330,8 @@ TESTS =3D testsuite/common/bits32m0$(EXEEXT) \ @SIM_ENABLE_ARCH_v850_TRUE@ v850/itable.h \ @SIM_ENABLE_ARCH_v850_TRUE@ v850/engine.h =20 -@SIM_ENABLE_ARCH_v850_TRUE@am__append_134 =3D $(v850_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_v850_TRUE@am__append_135 =3D $(v850_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_v850_TRUE@am__append_126 =3D $(v850_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_v850_TRUE@am__append_127 =3D $(v850_BUILD_OUTPUTS) subdir =3D . ACLOCAL_M4 =3D $(top_srcdir)/aclocal.m4 am__aclocal_m4_deps =3D $(top_srcdir)/../config/acx.m4 \ @@ -716,8 +708,8 @@ am__DEPENDENCIES_1 =3D @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__DEPENDENCIES_= 2 =3D $(am__DEPENDENCIES_1) \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/itable.o \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/multi-run.o -@SIM_ENABLE_ARCH_mips_TRUE@am__DEPENDENCIES_3 =3D $(am__append_88) \ -@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_89) \ +@SIM_ENABLE_ARCH_mips_TRUE@am__DEPENDENCIES_3 =3D $(am__append_82) \ +@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_83) \ @SIM_ENABLE_ARCH_mips_TRUE@ $(am__DEPENDENCIES_2) @SIM_ENABLE_ARCH_mips_TRUE@mips_libsim_a_DEPENDENCIES =3D \ @SIM_ENABLE_ARCH_mips_TRUE@ $(common_libcommon_a_OBJECTS) \ @@ -1746,43 +1738,39 @@ GNULIB_PARENT_DIR =3D .. srccom =3D $(srcdir)/common srcroot =3D $(srcdir)/.. SUBDIRS =3D @subdirs@ -AM_MAKEFLAGS =3D SIM_NEW_COMMON_OBJS_=3D"$(SIM_NEW_COMMON_OBJS)" \ - $(am__append_3) $(am__append_16) $(am__append_30) \ - $(am__append_63) $(am__append_74) $(am__append_80) \ - $(am__append_93) $(am__append_103) pkginclude_HEADERS =3D $(am__append_1) -noinst_LIBRARIES =3D common/libcommon.a $(am__append_5) $(am__append_8) \ - $(am__append_10) $(am__append_12) $(am__append_14) \ - $(am__append_17) $(am__append_22) $(am__append_28) \ - $(am__append_35) $(am__append_41) $(am__append_45) \ - $(am__append_47) $(am__append_52) $(am__append_54) \ - $(am__append_56) $(am__append_61) $(am__append_67) \ - $(am__append_72) $(am__append_78) $(am__append_84) \ - $(am__append_86) $(am__append_91) $(am__append_101) \ - $(am__append_107) $(am__append_109) $(am__append_111) \ - $(am__append_117) $(am__append_119) $(am__append_121) \ - $(am__append_123) $(am__append_125) $(am__append_131) -BUILT_SOURCES =3D $(am__append_19) $(am__append_24) $(am__append_32) \ - $(am__append_37) $(am__append_49) $(am__append_58) \ - $(am__append_64) $(am__append_75) $(am__append_94) \ - $(am__append_104) $(am__append_113) $(am__append_127) \ - $(am__append_133) +noinst_LIBRARIES =3D common/libcommon.a $(am__append_4) $(am__append_7) \ + $(am__append_9) $(am__append_11) $(am__append_13) \ + $(am__append_15) $(am__append_20) $(am__append_26) \ + $(am__append_32) $(am__append_38) $(am__append_42) \ + $(am__append_44) $(am__append_49) $(am__append_51) \ + $(am__append_53) $(am__append_58) $(am__append_63) \ + $(am__append_68) $(am__append_73) $(am__append_78) \ + $(am__append_80) $(am__append_85) $(am__append_94) \ + $(am__append_99) $(am__append_101) $(am__append_103) \ + $(am__append_109) $(am__append_111) $(am__append_113) \ + $(am__append_115) $(am__append_117) $(am__append_123) +BUILT_SOURCES =3D $(am__append_17) $(am__append_22) $(am__append_29) \ + $(am__append_34) $(am__append_46) $(am__append_55) \ + $(am__append_60) $(am__append_70) $(am__append_87) \ + $(am__append_96) $(am__append_105) $(am__append_119) \ + $(am__append_125) CLEANFILES =3D common/version.c common/version.c-stamp \ testsuite/common/bits-gen testsuite/common/bits32m0.c \ testsuite/common/bits32m31.c testsuite/common/bits64m0.c \ testsuite/common/bits64m63.c -DISTCLEANFILES =3D $(am__append_100) +DISTCLEANFILES =3D $(am__append_93) MOSTLYCLEANFILES =3D core $(SIM_ENABLED_ARCHES:%=3D%/*.o) \ $(common_HW_CONFIG_H_TARGETS) $(patsubst \ %,%/stamp-hw,$(SIM_ENABLED_ARCHES)) \ $(common_GEN_MODULES_C_TARGETS) $(patsubst \ - %,%/stamp-modules,$(SIM_ENABLED_ARCHES)) $(am__append_7) \ - site-sim-config.exp testrun.log testrun.sum $(am__append_21) \ - $(am__append_27) $(am__append_34) $(am__append_40) \ - $(am__append_51) $(am__append_60) $(am__append_66) \ - $(am__append_71) $(am__append_77) $(am__append_83) \ - $(am__append_99) $(am__append_106) $(am__append_115) \ - $(am__append_130) $(am__append_135) + %,%/stamp-modules,$(SIM_ENABLED_ARCHES)) $(am__append_6) \ + site-sim-config.exp testrun.log testrun.sum $(am__append_19) \ + $(am__append_25) $(am__append_31) $(am__append_37) \ + $(am__append_48) $(am__append_57) $(am__append_62) \ + $(am__append_67) $(am__append_72) $(am__append_77) \ + $(am__append_92) $(am__append_98) $(am__append_107) \ + $(am__append_122) $(am__append_127) AM_CFLAGS =3D \ $(WERROR_CFLAGS) \ $(WARN_CFLAGS) \ @@ -1799,15 +1787,15 @@ COMPILE_FOR_BUILD =3D $(CC_FOR_BUILD) $(AM_CPPFLAGS= _FOR_BUILD) $(CPPFLAGS_FOR_BUIL LINK_FOR_BUILD =3D $(CC_FOR_BUILD) $(CFLAGS_FOR_BUILD) $(LDFLAGS_FOR_BUILD= ) -o $@ SIM_ALL_RECURSIVE_DEPS =3D common/libcommon.a \ $(common_HW_CONFIG_H_TARGETS) $(common_GEN_MODULES_C_TARGETS) \ - $(am__append_4) $(am__append_20) $(am__append_25) \ - $(am__append_33) $(am__append_38) $(am__append_50) \ - $(am__append_59) $(am__append_65) $(am__append_69) \ - $(am__append_76) $(am__append_81) $(am__append_98) \ - $(am__append_105) $(am__append_114) $(am__append_128) \ - $(am__append_134) + $(am__append_3) $(am__append_18) $(am__append_23) \ + $(am__append_30) $(am__append_35) $(am__append_47) \ + $(am__append_56) $(am__append_61) $(am__append_65) \ + $(am__append_71) $(am__append_75) $(am__append_91) \ + $(am__append_97) $(am__append_106) $(am__append_120) \ + $(am__append_126) SIM_INSTALL_DATA_LOCAL_DEPS =3D=20 -SIM_INSTALL_EXEC_LOCAL_DEPS =3D $(am__append_43) -SIM_UNINSTALL_LOCAL_DEPS =3D $(am__append_44) +SIM_INSTALL_EXEC_LOCAL_DEPS =3D $(am__append_40) +SIM_UNINSTALL_LOCAL_DEPS =3D $(am__append_41) SIM_DEPBASE =3D $(@D)/$(DEPDIR)/$(@F:.o=3D) SIM_COMPILE =3D \ $(AM_V_CC)$(COMPILE) -MT $@ -MD -MP -MF $(SIM_DEPBASE).Tpo -c -o $@ $< &&= \ @@ -2579,8 +2567,8 @@ testsuite_common_CPPFLAGS =3D \ @SIM_ENABLE_ARCH_mips_TRUE@ -DWITH_TARGET_WORD_BITSIZE=3D@SIM_MIPS_BITSIZE= @ -DWITH_TARGET_WORD_MSB=3DWITH_TARGET_WORD_BITSIZE-1 \ @SIM_ENABLE_ARCH_mips_TRUE@ -DWITH_FLOATING_POINT=3DHARD_FLOATING_POINT -D= WITH_TARGET_FLOATING_POINT_BITSIZE=3D@SIM_MIPS_FPU_BITSIZE@ =20 -@SIM_ENABLE_ARCH_mips_TRUE@mips_GEN_OBJ =3D $(am__append_88) \ -@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_89) $(am__append_90) +@SIM_ENABLE_ARCH_mips_TRUE@mips_GEN_OBJ =3D $(am__append_82) \ +@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_83) $(am__append_84) @SIM_ENABLE_ARCH_mips_TRUE@mips_libsim_a_SOURCES =3D=20 @SIM_ENABLE_ARCH_mips_TRUE@mips_libsim_a_LIBADD =3D \ @SIM_ENABLE_ARCH_mips_TRUE@ $(common_libcommon_a_OBJECTS) \ @@ -2649,8 +2637,8 @@ testsuite_common_CPPFLAGS =3D \ @SIM_ENABLE_ARCH_mips_TRUE@mips_BUILD_OUTPUTS =3D \ @SIM_ENABLE_ARCH_mips_TRUE@ $(mips_BUILT_SRC_FROM_IGEN_ITABLE) \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/stamp-igen-itable \ -@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_95) $(am__append_96) \ -@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_97) +@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_88) $(am__append_89) \ +@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_90) @SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_TRACE =3D # -G omit-line-numbers # -G= trace-rule-selection -G trace-rule-rejection -G trace-entries # -G trace-a= ll @SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN =3D $(srcdir)/mips/mips.igen @SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN_INC =3D \ diff --git a/sim/bfin/local.mk b/sim/bfin/local.mk index 90b697e9dcb..17a5047fa24 100644 --- a/sim/bfin/local.mk +++ b/sim/bfin/local.mk @@ -78,7 +78,6 @@ noinst_PROGRAMS +=3D %D%/run bfin_wdog \ bfin_wp \ eth_phy -AM_MAKEFLAGS +=3D %C%_SIM_EXTRA_HW_DEVICES=3D"$(%C%_SIM_EXTRA_HW_DEVICES)" =20 %D%/linux-fixed-code.h: @MAINT@ $(srcdir)/%D%/linux-fixed-code.s %D%/local= .mk %D%/$(am__dirstamp) $(AM_V_GEN)$(AS_FOR_TARGET_BFIN) $(srcdir)/%D%/linux-fixed-code.s -o %D%/= linux-fixed-code.o diff --git a/sim/common/local.mk b/sim/common/local.mk index 0ed18359ae4..2c68f668d37 100644 --- a/sim/common/local.mk +++ b/sim/common/local.mk @@ -106,16 +106,12 @@ SIM_NEW_COMMON_OBJS =3D \ sim-utils.o \ sim-watch.o =20 -AM_MAKEFLAGS +=3D SIM_NEW_COMMON_OBJS_=3D"$(SIM_NEW_COMMON_OBJS)" - SIM_HW_DEVICES =3D cfi core pal glue =20 if SIM_ENABLE_HW SIM_NEW_COMMON_OBJS +=3D \ $(SIM_COMMON_HW_OBJS) \ $(SIM_HW_SOCKSER) - -AM_MAKEFLAGS +=3D SIM_HW_DEVICES_=3D"$(SIM_HW_DEVICES)" endif =20 # FIXME This is one very simple-minded way of generating the file hw-confi= g.h. diff --git a/sim/cris/local.mk b/sim/cris/local.mk index 78f40e03ec4..ef78c63062c 100644 --- a/sim/cris/local.mk +++ b/sim/cris/local.mk @@ -59,7 +59,6 @@ noinst_LIBRARIES +=3D %D%/libsim.a noinst_PROGRAMS +=3D %D%/run =20 %C%_SIM_EXTRA_HW_DEVICES =3D rv cris cris_900000xx -AM_MAKEFLAGS +=3D %C%_SIM_EXTRA_HW_DEVICES=3D"$(%C%_SIM_EXTRA_HW_DEVICES)" =20 ## rvdummy is just used for testing -- it runs on the same host as `run`. ## It does nothing if --enable-sim-hardware isn't active. diff --git a/sim/lm32/local.mk b/sim/lm32/local.mk index f3e0567d73b..1c286245cca 100644 --- a/sim/lm32/local.mk +++ b/sim/lm32/local.mk @@ -56,7 +56,6 @@ noinst_LIBRARIES +=3D %D%/libsim.a noinst_PROGRAMS +=3D %D%/run =20 %C%_SIM_EXTRA_HW_DEVICES =3D lm32cpu lm32timer lm32uart -AM_MAKEFLAGS +=3D %C%_SIM_EXTRA_HW_DEVICES=3D"$(%C%_SIM_EXTRA_HW_DEVICES)" =20 ## List all generated headers to help Automake dependency tracking. BUILT_SOURCES +=3D %D%/eng.h diff --git a/sim/m32r/local.mk b/sim/m32r/local.mk index 31178a3b034..78c8a87a42e 100644 --- a/sim/m32r/local.mk +++ b/sim/m32r/local.mk @@ -82,7 +82,6 @@ noinst_LIBRARIES +=3D %D%/libsim.a noinst_PROGRAMS +=3D %D%/run =20 %C%_SIM_EXTRA_HW_DEVICES =3D m32r_cache m32r_uart -AM_MAKEFLAGS +=3D %C%_SIM_EXTRA_HW_DEVICES=3D"$(%C%_SIM_EXTRA_HW_DEVICES)" =20 ## List all generated headers to help Automake dependency tracking. BUILT_SOURCES +=3D \ diff --git a/sim/m68hc11/local.mk b/sim/m68hc11/local.mk index da4c25913d8..8f881d5b854 100644 --- a/sim/m68hc11/local.mk +++ b/sim/m68hc11/local.mk @@ -57,7 +57,6 @@ noinst_LIBRARIES +=3D %D%/libsim.a noinst_PROGRAMS +=3D %D%/run =20 %C%_SIM_EXTRA_HW_DEVICES =3D m68hc11 m68hc11sio m68hc11eepr m68hc11tim m68= hc11spi nvram -AM_MAKEFLAGS +=3D %C%_SIM_EXTRA_HW_DEVICES=3D"$(%C%_SIM_EXTRA_HW_DEVICES)" =20 %C%_BUILD_OUTPUTS =3D \ %D%/gencode$(EXEEXT) \ diff --git a/sim/mips/local.mk b/sim/mips/local.mk index 136eebaacaf..e54a0ef6102 100644 --- a/sim/mips/local.mk +++ b/sim/mips/local.mk @@ -86,7 +86,6 @@ noinst_LIBRARIES +=3D %D%/libsim.a noinst_PROGRAMS +=3D %D%/run =20 %C%_SIM_EXTRA_HW_DEVICES =3D tx3904cpu tx3904irc tx3904tmr tx3904sio -AM_MAKEFLAGS +=3D %C%_SIM_EXTRA_HW_DEVICES=3D"$(%C%_SIM_EXTRA_HW_DEVICES)" =20 ## List all generated headers to help Automake dependency tracking. BUILT_SOURCES +=3D %D%/itable.h diff --git a/sim/mn10300/local.mk b/sim/mn10300/local.mk index 61c7f9188ea..0c5d1bf59be 100644 --- a/sim/mn10300/local.mk +++ b/sim/mn10300/local.mk @@ -53,7 +53,6 @@ noinst_LIBRARIES +=3D %D%/libsim.a noinst_PROGRAMS +=3D %D%/run =20 %C%_SIM_EXTRA_HW_DEVICES =3D mn103cpu mn103int mn103tim mn103ser mn103iop -AM_MAKEFLAGS +=3D %C%_SIM_EXTRA_HW_DEVICES=3D"$(%C%_SIM_EXTRA_HW_DEVICES)" =20 ## List all generated headers to help Automake dependency tracking. BUILT_SOURCES +=3D \