From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1521) id 9F4F93858D1E; Sun, 15 Jan 2023 01:51:27 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9F4F93858D1E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1673747487; bh=XF7c7x8kp9zjqtxXsz8A/MJCHcCThX1/1wbleDru3X0=; h=From:To:Subject:Date:From; b=L+vWNyePbqymcyFq8WMYRaeEqSXLQJStz/wdYPra8CkPc7vWxkbtPi44g5u8gNn2l o9HJM0SUjpYss/xLHck95/ER6LIrSBUSIoebpVyR+9SeI1tyKC+/woPSW9JedIzkps 0dWCWV57IA8cLac3FRB5Gfi/GiAvGC0b+DcgBB70= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Michael Frysinger To: gdb-cvs@sourceware.org Subject: [binutils-gdb] sim: build: drop most recursive build deps X-Act-Checkin: binutils-gdb X-Git-Author: Mike Frysinger X-Git-Refname: refs/heads/master X-Git-Oldrev: eac2fbdc4ba9116693f838d82edb844cccce8dd9 X-Git-Newrev: ee3134d0288c9d9d4f4a9fe325d4864a556edc63 Message-Id: <20230115015127.9F4F93858D1E@sourceware.org> Date: Sun, 15 Jan 2023 01:51:27 +0000 (GMT) List-Id: https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3Dee3134d0288c= 9d9d4f4a9fe325d4864a556edc63 commit ee3134d0288c9d9d4f4a9fe325d4864a556edc63 Author: Mike Frysinger Date: Mon Jan 2 14:34:52 2023 -0500 sim: build: drop most recursive build deps =20 Now that we build these objects in the top dir & generate modules.c there, we don't need to generate them all first -- we can let the normal dependency graph take care of building things in parallel. Diff: --- sim/Makefile.in | 281 +++++++++++++++++++++++++----------------------= ---- sim/bpf/local.mk | 3 +- sim/cr16/local.mk | 3 +- sim/cris/local.mk | 3 +- sim/d10v/local.mk | 3 +- sim/frv/local.mk | 3 +- sim/iq2000/local.mk | 3 +- sim/lm32/local.mk | 3 +- sim/m32c/local.mk | 3 +- sim/m32r/local.mk | 3 +- sim/m68hc11/local.mk | 3 +- sim/mips/local.mk | 3 +- sim/mn10300/local.mk | 3 +- sim/or1k/local.mk | 3 +- sim/sh/local.mk | 3 +- sim/v850/local.mk | 3 +- 16 files changed, 153 insertions(+), 173 deletions(-) diff --git a/sim/Makefile.in b/sim/Makefile.in index ddc98822614..80cfbccb566 100644 --- a/sim/Makefile.in +++ b/sim/Makefile.in @@ -154,81 +154,71 @@ TESTS =3D testsuite/common/bits32m0$(EXEEXT) \ @SIM_ENABLE_ARCH_bpf_TRUE@ bpf/eng-be.h =20 @SIM_ENABLE_ARCH_bpf_TRUE@am__append_17 =3D $(bpf_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_bpf_TRUE@am__append_18 =3D $(bpf_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_cr16_TRUE@am__append_19 =3D cr16/libsim.a -@SIM_ENABLE_ARCH_cr16_TRUE@am__append_20 =3D cr16/run -@SIM_ENABLE_ARCH_cr16_TRUE@am__append_21 =3D cr16/simops.h +@SIM_ENABLE_ARCH_cr16_TRUE@am__append_18 =3D cr16/libsim.a +@SIM_ENABLE_ARCH_cr16_TRUE@am__append_19 =3D cr16/run +@SIM_ENABLE_ARCH_cr16_TRUE@am__append_20 =3D cr16/simops.h +@SIM_ENABLE_ARCH_cr16_TRUE@am__append_21 =3D cr16/gencode @SIM_ENABLE_ARCH_cr16_TRUE@am__append_22 =3D $(cr16_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_cr16_TRUE@am__append_23 =3D cr16/gencode -@SIM_ENABLE_ARCH_cr16_TRUE@am__append_24 =3D $(cr16_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_cris_TRUE@am__append_25 =3D cris/libsim.a -@SIM_ENABLE_ARCH_cris_TRUE@am__append_26 =3D cris/run -@SIM_ENABLE_ARCH_cris_TRUE@am__append_27 =3D cris/rvdummy -@SIM_ENABLE_ARCH_cris_TRUE@am__append_28 =3D \ +@SIM_ENABLE_ARCH_cris_TRUE@am__append_23 =3D cris/libsim.a +@SIM_ENABLE_ARCH_cris_TRUE@am__append_24 =3D cris/run +@SIM_ENABLE_ARCH_cris_TRUE@am__append_25 =3D cris/rvdummy +@SIM_ENABLE_ARCH_cris_TRUE@am__append_26 =3D \ @SIM_ENABLE_ARCH_cris_TRUE@ cris/engv10.h \ @SIM_ENABLE_ARCH_cris_TRUE@ cris/engv32.h =20 -@SIM_ENABLE_ARCH_cris_TRUE@am__append_29 =3D $(cris_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_cris_TRUE@am__append_30 =3D $(cris_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_d10v_TRUE@am__append_31 =3D d10v/libsim.a -@SIM_ENABLE_ARCH_d10v_TRUE@am__append_32 =3D d10v/run -@SIM_ENABLE_ARCH_d10v_TRUE@am__append_33 =3D d10v/simops.h -@SIM_ENABLE_ARCH_d10v_TRUE@am__append_34 =3D $(d10v_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_d10v_TRUE@am__append_35 =3D d10v/gencode -@SIM_ENABLE_ARCH_d10v_TRUE@am__append_36 =3D $(d10v_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_erc32_TRUE@am__append_37 =3D erc32/libsim.a -@SIM_ENABLE_ARCH_erc32_TRUE@am__append_38 =3D erc32/run erc32/sis -@SIM_ENABLE_ARCH_erc32_TRUE@am__append_39 =3D sim-%D-install-exec-local -@SIM_ENABLE_ARCH_erc32_TRUE@am__append_40 =3D sim-erc32-uninstall-local -@SIM_ENABLE_ARCH_examples_TRUE@am__append_41 =3D example-synacor/libsim.a -@SIM_ENABLE_ARCH_examples_TRUE@am__append_42 =3D example-synacor/run -@SIM_ENABLE_ARCH_frv_TRUE@am__append_43 =3D frv/libsim.a -@SIM_ENABLE_ARCH_frv_TRUE@am__append_44 =3D frv/run -@SIM_ENABLE_ARCH_frv_TRUE@am__append_45 =3D frv/eng.h -@SIM_ENABLE_ARCH_frv_TRUE@am__append_46 =3D $(frv_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_frv_TRUE@am__append_47 =3D $(frv_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_ft32_TRUE@am__append_48 =3D ft32/libsim.a -@SIM_ENABLE_ARCH_ft32_TRUE@am__append_49 =3D ft32/run -@SIM_ENABLE_ARCH_h8300_TRUE@am__append_50 =3D h8300/libsim.a -@SIM_ENABLE_ARCH_h8300_TRUE@am__append_51 =3D h8300/run -@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_52 =3D iq2000/libsim.a -@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_53 =3D iq2000/run -@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_54 =3D iq2000/eng.h -@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_55 =3D $(iq2000_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_56 =3D $(iq2000_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_lm32_TRUE@am__append_57 =3D lm32/libsim.a -@SIM_ENABLE_ARCH_lm32_TRUE@am__append_58 =3D lm32/run -@SIM_ENABLE_ARCH_lm32_TRUE@am__append_59 =3D lm32/eng.h -@SIM_ENABLE_ARCH_lm32_TRUE@am__append_60 =3D $(lm32_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_lm32_TRUE@am__append_61 =3D $(lm32_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_m32c_TRUE@am__append_62 =3D m32c/libsim.a -@SIM_ENABLE_ARCH_m32c_TRUE@am__append_63 =3D m32c/run -@SIM_ENABLE_ARCH_m32c_TRUE@am__append_64 =3D $(m32c_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_m32c_TRUE@am__append_65 =3D m32c/opc2c -@SIM_ENABLE_ARCH_m32c_TRUE@am__append_66 =3D \ +@SIM_ENABLE_ARCH_cris_TRUE@am__append_27 =3D $(cris_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_d10v_TRUE@am__append_28 =3D d10v/libsim.a +@SIM_ENABLE_ARCH_d10v_TRUE@am__append_29 =3D d10v/run +@SIM_ENABLE_ARCH_d10v_TRUE@am__append_30 =3D d10v/simops.h +@SIM_ENABLE_ARCH_d10v_TRUE@am__append_31 =3D d10v/gencode +@SIM_ENABLE_ARCH_d10v_TRUE@am__append_32 =3D $(d10v_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_erc32_TRUE@am__append_33 =3D erc32/libsim.a +@SIM_ENABLE_ARCH_erc32_TRUE@am__append_34 =3D erc32/run erc32/sis +@SIM_ENABLE_ARCH_erc32_TRUE@am__append_35 =3D sim-%D-install-exec-local +@SIM_ENABLE_ARCH_erc32_TRUE@am__append_36 =3D sim-erc32-uninstall-local +@SIM_ENABLE_ARCH_examples_TRUE@am__append_37 =3D example-synacor/libsim.a +@SIM_ENABLE_ARCH_examples_TRUE@am__append_38 =3D example-synacor/run +@SIM_ENABLE_ARCH_frv_TRUE@am__append_39 =3D frv/libsim.a +@SIM_ENABLE_ARCH_frv_TRUE@am__append_40 =3D frv/run +@SIM_ENABLE_ARCH_frv_TRUE@am__append_41 =3D frv/eng.h +@SIM_ENABLE_ARCH_frv_TRUE@am__append_42 =3D $(frv_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_ft32_TRUE@am__append_43 =3D ft32/libsim.a +@SIM_ENABLE_ARCH_ft32_TRUE@am__append_44 =3D ft32/run +@SIM_ENABLE_ARCH_h8300_TRUE@am__append_45 =3D h8300/libsim.a +@SIM_ENABLE_ARCH_h8300_TRUE@am__append_46 =3D h8300/run +@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_47 =3D iq2000/libsim.a +@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_48 =3D iq2000/run +@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_49 =3D iq2000/eng.h +@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_50 =3D $(iq2000_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_lm32_TRUE@am__append_51 =3D lm32/libsim.a +@SIM_ENABLE_ARCH_lm32_TRUE@am__append_52 =3D lm32/run +@SIM_ENABLE_ARCH_lm32_TRUE@am__append_53 =3D lm32/eng.h +@SIM_ENABLE_ARCH_lm32_TRUE@am__append_54 =3D $(lm32_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_m32c_TRUE@am__append_55 =3D m32c/libsim.a +@SIM_ENABLE_ARCH_m32c_TRUE@am__append_56 =3D m32c/run +@SIM_ENABLE_ARCH_m32c_TRUE@am__append_57 =3D m32c/opc2c +@SIM_ENABLE_ARCH_m32c_TRUE@am__append_58 =3D \ @SIM_ENABLE_ARCH_m32c_TRUE@ $(m32c_BUILD_OUTPUTS) \ @SIM_ENABLE_ARCH_m32c_TRUE@ m32c/m32c.c.log \ @SIM_ENABLE_ARCH_m32c_TRUE@ m32c/r8c.c.log =20 -@SIM_ENABLE_ARCH_m32r_TRUE@am__append_67 =3D m32r/libsim.a -@SIM_ENABLE_ARCH_m32r_TRUE@am__append_68 =3D m32r/run -@SIM_ENABLE_ARCH_m32r_TRUE@am__append_69 =3D \ +@SIM_ENABLE_ARCH_m32r_TRUE@am__append_59 =3D m32r/libsim.a +@SIM_ENABLE_ARCH_m32r_TRUE@am__append_60 =3D m32r/run +@SIM_ENABLE_ARCH_m32r_TRUE@am__append_61 =3D \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/eng.h \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/engx.h \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/eng2.h =20 -@SIM_ENABLE_ARCH_m32r_TRUE@am__append_70 =3D $(m32r_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_m32r_TRUE@am__append_71 =3D $(m32r_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_72 =3D m68hc11/libsim.a -@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_73 =3D m68hc11/run -@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_74 =3D $(m68hc11_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_75 =3D m68hc11/gencode -@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_76 =3D $(m68hc11_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_mcore_TRUE@am__append_77 =3D mcore/libsim.a -@SIM_ENABLE_ARCH_mcore_TRUE@am__append_78 =3D mcore/run -@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_79 =3D microblaze/libsim.a -@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_80 =3D microblaze/run -@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_81 = =3D \ +@SIM_ENABLE_ARCH_m32r_TRUE@am__append_62 =3D $(m32r_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_63 =3D m68hc11/libsim.a +@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_64 =3D m68hc11/run +@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_65 =3D m68hc11/gencode +@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_66 =3D $(m68hc11_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_mcore_TRUE@am__append_67 =3D mcore/libsim.a +@SIM_ENABLE_ARCH_mcore_TRUE@am__append_68 =3D mcore/run +@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_69 =3D microblaze/libsim.a +@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_70 =3D microblaze/run +@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_71 = =3D \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/support.o \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/itable.o \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/semantics.= o \ @@ -237,7 +227,7 @@ TESTS =3D testsuite/common/bits32m0$(EXEEXT) \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/engine.o \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/irun.o =20 -@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_82 =3D \ +@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_72 =3D \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m16_support.o= \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m16_semantics= .o \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m16_idecode.o= \ @@ -251,36 +241,35 @@ TESTS =3D testsuite/common/bits32m0$(EXEEXT) \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/itable.o \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m16run.o =20 -@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_83 =3D= \ +@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_73 =3D= \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ $(SIM_MIPS_MULTI= _OBJ) \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/itable.o \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/multi-run.o =20 -@SIM_ENABLE_ARCH_mips_TRUE@am__append_84 =3D mips/libsim.a -@SIM_ENABLE_ARCH_mips_TRUE@am__append_85 =3D mips/run -@SIM_ENABLE_ARCH_mips_TRUE@am__append_86 =3D mips/itable.h \ +@SIM_ENABLE_ARCH_mips_TRUE@am__append_74 =3D mips/libsim.a +@SIM_ENABLE_ARCH_mips_TRUE@am__append_75 =3D mips/run +@SIM_ENABLE_ARCH_mips_TRUE@am__append_76 =3D mips/itable.h \ @SIM_ENABLE_ARCH_mips_TRUE@ $(SIM_MIPS_MULTI_SRC) -@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_87 = =3D \ +@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_77 = =3D \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ $(mips_BUILT_SR= C_FROM_GEN_MODE_SINGLE) \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/stamp-gen-= mode-single =20 -@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_88 =3D \ +@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_78 =3D \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ $(mips_BUILT_SRC_F= ROM_GEN_MODE_M16_M16) \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ $(mips_BUILT_SRC_F= ROM_GEN_MODE_M16_M32) \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/stamp-gen-mod= e-m16-m16 \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/stamp-gen-mod= e-m16-m32 =20 -@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_89 =3D= \ +@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_79 =3D= \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ $(SIM_MIPS_MULTI= _SRC) \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/stamp-gen-m= ode-multi-igen \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/stamp-gen-m= ode-multi-run =20 -@SIM_ENABLE_ARCH_mips_TRUE@am__append_90 =3D $(mips_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_mips_TRUE@am__append_91 =3D $(mips_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_mips_TRUE@am__append_92 =3D mips/multi-include.h mips/mul= ti-run.c -@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_93 =3D mn10300/libsim.a -@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_94 =3D mn10300/run -@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_95 =3D \ +@SIM_ENABLE_ARCH_mips_TRUE@am__append_80 =3D $(mips_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_mips_TRUE@am__append_81 =3D mips/multi-include.h mips/mul= ti-run.c +@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_82 =3D mn10300/libsim.a +@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_83 =3D mn10300/run +@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_84 =3D \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/icache.h \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/idecode.h \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/semantics.h \ @@ -289,38 +278,35 @@ TESTS =3D testsuite/common/bits32m0$(EXEEXT) \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/itable.h \ @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/engine.h =20 -@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_96 =3D $(mn10300_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_97 =3D $(mn10300_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_moxie_TRUE@am__append_98 =3D moxie/libsim.a -@SIM_ENABLE_ARCH_moxie_TRUE@am__append_99 =3D moxie/run -@SIM_ENABLE_ARCH_msp430_TRUE@am__append_100 =3D msp430/libsim.a -@SIM_ENABLE_ARCH_msp430_TRUE@am__append_101 =3D msp430/run -@SIM_ENABLE_ARCH_or1k_TRUE@am__append_102 =3D or1k/libsim.a -@SIM_ENABLE_ARCH_or1k_TRUE@am__append_103 =3D or1k/run -@SIM_ENABLE_ARCH_or1k_TRUE@am__append_104 =3D or1k/eng.h -@SIM_ENABLE_ARCH_or1k_TRUE@am__append_105 =3D $(or1k_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_or1k_TRUE@am__append_106 =3D $(or1k_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_ppc_TRUE@am__append_107 =3D ppc/run ppc/psim -@SIM_ENABLE_ARCH_pru_TRUE@am__append_108 =3D pru/libsim.a -@SIM_ENABLE_ARCH_pru_TRUE@am__append_109 =3D pru/run -@SIM_ENABLE_ARCH_riscv_TRUE@am__append_110 =3D riscv/libsim.a -@SIM_ENABLE_ARCH_riscv_TRUE@am__append_111 =3D riscv/run -@SIM_ENABLE_ARCH_rl78_TRUE@am__append_112 =3D rl78/libsim.a -@SIM_ENABLE_ARCH_rl78_TRUE@am__append_113 =3D rl78/run -@SIM_ENABLE_ARCH_rx_TRUE@am__append_114 =3D rx/libsim.a -@SIM_ENABLE_ARCH_rx_TRUE@am__append_115 =3D rx/run -@SIM_ENABLE_ARCH_sh_TRUE@am__append_116 =3D sh/libsim.a -@SIM_ENABLE_ARCH_sh_TRUE@am__append_117 =3D sh/run -@SIM_ENABLE_ARCH_sh_TRUE@am__append_118 =3D \ +@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_85 =3D $(mn10300_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_moxie_TRUE@am__append_86 =3D moxie/libsim.a +@SIM_ENABLE_ARCH_moxie_TRUE@am__append_87 =3D moxie/run +@SIM_ENABLE_ARCH_msp430_TRUE@am__append_88 =3D msp430/libsim.a +@SIM_ENABLE_ARCH_msp430_TRUE@am__append_89 =3D msp430/run +@SIM_ENABLE_ARCH_or1k_TRUE@am__append_90 =3D or1k/libsim.a +@SIM_ENABLE_ARCH_or1k_TRUE@am__append_91 =3D or1k/run +@SIM_ENABLE_ARCH_or1k_TRUE@am__append_92 =3D or1k/eng.h +@SIM_ENABLE_ARCH_or1k_TRUE@am__append_93 =3D $(or1k_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_ppc_TRUE@am__append_94 =3D ppc/run ppc/psim +@SIM_ENABLE_ARCH_pru_TRUE@am__append_95 =3D pru/libsim.a +@SIM_ENABLE_ARCH_pru_TRUE@am__append_96 =3D pru/run +@SIM_ENABLE_ARCH_riscv_TRUE@am__append_97 =3D riscv/libsim.a +@SIM_ENABLE_ARCH_riscv_TRUE@am__append_98 =3D riscv/run +@SIM_ENABLE_ARCH_rl78_TRUE@am__append_99 =3D rl78/libsim.a +@SIM_ENABLE_ARCH_rl78_TRUE@am__append_100 =3D rl78/run +@SIM_ENABLE_ARCH_rx_TRUE@am__append_101 =3D rx/libsim.a +@SIM_ENABLE_ARCH_rx_TRUE@am__append_102 =3D rx/run +@SIM_ENABLE_ARCH_sh_TRUE@am__append_103 =3D sh/libsim.a +@SIM_ENABLE_ARCH_sh_TRUE@am__append_104 =3D sh/run +@SIM_ENABLE_ARCH_sh_TRUE@am__append_105 =3D \ @SIM_ENABLE_ARCH_sh_TRUE@ sh/code.c \ @SIM_ENABLE_ARCH_sh_TRUE@ sh/ppi.c =20 -@SIM_ENABLE_ARCH_sh_TRUE@am__append_119 =3D $(sh_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_sh_TRUE@am__append_120 =3D sh/gencode -@SIM_ENABLE_ARCH_sh_TRUE@am__append_121 =3D $(sh_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_v850_TRUE@am__append_122 =3D v850/libsim.a -@SIM_ENABLE_ARCH_v850_TRUE@am__append_123 =3D v850/run -@SIM_ENABLE_ARCH_v850_TRUE@am__append_124 =3D \ +@SIM_ENABLE_ARCH_sh_TRUE@am__append_106 =3D sh/gencode +@SIM_ENABLE_ARCH_sh_TRUE@am__append_107 =3D $(sh_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_v850_TRUE@am__append_108 =3D v850/libsim.a +@SIM_ENABLE_ARCH_v850_TRUE@am__append_109 =3D v850/run +@SIM_ENABLE_ARCH_v850_TRUE@am__append_110 =3D \ @SIM_ENABLE_ARCH_v850_TRUE@ v850/icache.h \ @SIM_ENABLE_ARCH_v850_TRUE@ v850/idecode.h \ @SIM_ENABLE_ARCH_v850_TRUE@ v850/semantics.h \ @@ -329,8 +315,7 @@ TESTS =3D testsuite/common/bits32m0$(EXEEXT) \ @SIM_ENABLE_ARCH_v850_TRUE@ v850/itable.h \ @SIM_ENABLE_ARCH_v850_TRUE@ v850/engine.h =20 -@SIM_ENABLE_ARCH_v850_TRUE@am__append_125 =3D $(v850_BUILD_OUTPUTS) -@SIM_ENABLE_ARCH_v850_TRUE@am__append_126 =3D $(v850_BUILD_OUTPUTS) +@SIM_ENABLE_ARCH_v850_TRUE@am__append_111 =3D $(v850_BUILD_OUTPUTS) subdir =3D . ACLOCAL_M4 =3D $(top_srcdir)/aclocal.m4 am__aclocal_m4_deps =3D $(top_srcdir)/../config/acx.m4 \ @@ -709,8 +694,8 @@ am__DEPENDENCIES_1 =3D @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__DEPENDENCIES_= 2 =3D $(am__DEPENDENCIES_1) \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/itable.o \ @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/multi-run.o -@SIM_ENABLE_ARCH_mips_TRUE@am__DEPENDENCIES_3 =3D $(am__append_81) \ -@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_82) \ +@SIM_ENABLE_ARCH_mips_TRUE@am__DEPENDENCIES_3 =3D $(am__append_71) \ +@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_72) \ @SIM_ENABLE_ARCH_mips_TRUE@ $(am__DEPENDENCIES_2) @SIM_ENABLE_ARCH_mips_TRUE@mips_libsim_a_DEPENDENCIES =3D mips/interp.o \ @SIM_ENABLE_ARCH_mips_TRUE@ $(am__DEPENDENCIES_3) $(patsubst \ @@ -1732,36 +1717,36 @@ SUBDIRS =3D @subdirs@ pkginclude_HEADERS =3D $(am__append_1) noinst_LIBRARIES =3D common/libcommon.a $(am__append_3) $(am__append_6) \ $(am__append_8) $(am__append_10) $(am__append_12) \ - $(am__append_14) $(am__append_19) $(am__append_25) \ - $(am__append_31) $(am__append_37) $(am__append_41) \ - $(am__append_43) $(am__append_48) $(am__append_50) \ - $(am__append_52) $(am__append_57) $(am__append_62) \ - $(am__append_67) $(am__append_72) $(am__append_77) \ - $(am__append_79) $(am__append_84) $(am__append_93) \ - $(am__append_98) $(am__append_100) $(am__append_102) \ - $(am__append_108) $(am__append_110) $(am__append_112) \ - $(am__append_114) $(am__append_116) $(am__append_122) -BUILT_SOURCES =3D $(am__append_16) $(am__append_21) $(am__append_28) \ - $(am__append_33) $(am__append_45) $(am__append_54) \ - $(am__append_59) $(am__append_69) $(am__append_86) \ - $(am__append_95) $(am__append_104) $(am__append_118) \ - $(am__append_124) + $(am__append_14) $(am__append_18) $(am__append_23) \ + $(am__append_28) $(am__append_33) $(am__append_37) \ + $(am__append_39) $(am__append_43) $(am__append_45) \ + $(am__append_47) $(am__append_51) $(am__append_55) \ + $(am__append_59) $(am__append_63) $(am__append_67) \ + $(am__append_69) $(am__append_74) $(am__append_82) \ + $(am__append_86) $(am__append_88) $(am__append_90) \ + $(am__append_95) $(am__append_97) $(am__append_99) \ + $(am__append_101) $(am__append_103) $(am__append_108) +BUILT_SOURCES =3D $(am__append_16) $(am__append_20) $(am__append_26) \ + $(am__append_30) $(am__append_41) $(am__append_49) \ + $(am__append_53) $(am__append_61) $(am__append_76) \ + $(am__append_84) $(am__append_92) $(am__append_105) \ + $(am__append_110) CLEANFILES =3D common/version.c common/version.c-stamp \ testsuite/common/bits-gen testsuite/common/bits32m0.c \ testsuite/common/bits32m31.c testsuite/common/bits64m0.c \ testsuite/common/bits64m63.c -DISTCLEANFILES =3D $(am__append_92) +DISTCLEANFILES =3D $(am__append_81) MOSTLYCLEANFILES =3D core $(SIM_ENABLED_ARCHES:%=3D%/*.o) \ $(SIM_ENABLED_ARCHES:%=3D%/hw-config.h) \ $(SIM_ENABLED_ARCHES:%=3D%/stamp-hw) \ $(common_GEN_MODULES_C_TARGETS) $(patsubst \ %,%/stamp-modules,$(SIM_ENABLED_ARCHES)) $(am__append_5) \ - site-sim-config.exp testrun.log testrun.sum $(am__append_18) \ - $(am__append_24) $(am__append_30) $(am__append_36) \ - $(am__append_47) $(am__append_56) $(am__append_61) \ - $(am__append_66) $(am__append_71) $(am__append_76) \ - $(am__append_91) $(am__append_97) $(am__append_106) \ - $(am__append_121) $(am__append_126) + site-sim-config.exp testrun.log testrun.sum $(am__append_17) \ + $(am__append_22) $(am__append_27) $(am__append_32) \ + $(am__append_42) $(am__append_50) $(am__append_54) \ + $(am__append_58) $(am__append_62) $(am__append_66) \ + $(am__append_80) $(am__append_85) $(am__append_93) \ + $(am__append_107) $(am__append_111) AM_CFLAGS =3D \ $(WERROR_CFLAGS) \ $(WARN_CFLAGS) \ @@ -1777,15 +1762,10 @@ AM_CPPFLAGS_FOR_BUILD =3D -I$(srcroot)/include $(SI= M_HW_CFLAGS) \ COMPILE_FOR_BUILD =3D $(CC_FOR_BUILD) $(AM_CPPFLAGS_FOR_BUILD) $(CPPFLAGS_= FOR_BUILD) $(CFLAGS_FOR_BUILD) LINK_FOR_BUILD =3D $(CC_FOR_BUILD) $(CFLAGS_FOR_BUILD) $(LDFLAGS_FOR_BUILD= ) -o $@ SIM_ALL_RECURSIVE_DEPS =3D common/libcommon.a \ - $(common_GEN_MODULES_C_TARGETS) $(am__append_17) \ - $(am__append_22) $(am__append_29) $(am__append_34) \ - $(am__append_46) $(am__append_55) $(am__append_60) \ - $(am__append_64) $(am__append_70) $(am__append_74) \ - $(am__append_90) $(am__append_96) $(am__append_105) \ - $(am__append_119) $(am__append_125) + $(common_GEN_MODULES_C_TARGETS) SIM_INSTALL_DATA_LOCAL_DEPS =3D=20 -SIM_INSTALL_EXEC_LOCAL_DEPS =3D $(am__append_39) -SIM_UNINSTALL_LOCAL_DEPS =3D $(am__append_40) +SIM_INSTALL_EXEC_LOCAL_DEPS =3D $(am__append_35) +SIM_UNINSTALL_LOCAL_DEPS =3D $(am__append_36) SIM_DEPBASE =3D $(@D)/$(DEPDIR)/$(@F:.o=3D) SIM_COMPILE =3D \ $(AM_V_CC)$(COMPILE) -MT $@ -MD -MP -MF $(SIM_DEPBASE).Tpo -c -o $@ $< &&= \ @@ -2576,8 +2556,8 @@ testsuite_common_CPPFLAGS =3D \ @SIM_ENABLE_ARCH_mips_TRUE@ -DWITH_TARGET_WORD_BITSIZE=3D@SIM_MIPS_BITSIZE= @ -DWITH_TARGET_WORD_MSB=3DWITH_TARGET_WORD_BITSIZE-1 \ @SIM_ENABLE_ARCH_mips_TRUE@ -DWITH_FLOATING_POINT=3DHARD_FLOATING_POINT -D= WITH_TARGET_FLOATING_POINT_BITSIZE=3D@SIM_MIPS_FPU_BITSIZE@ =20 -@SIM_ENABLE_ARCH_mips_TRUE@mips_GEN_OBJ =3D $(am__append_81) \ -@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_82) $(am__append_83) +@SIM_ENABLE_ARCH_mips_TRUE@mips_GEN_OBJ =3D $(am__append_71) \ +@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_72) $(am__append_73) @SIM_ENABLE_ARCH_mips_TRUE@mips_libsim_a_SOURCES =3D \ @SIM_ENABLE_ARCH_mips_TRUE@ $(common_libcommon_a_SOURCES) =20 @@ -2647,8 +2627,8 @@ testsuite_common_CPPFLAGS =3D \ @SIM_ENABLE_ARCH_mips_TRUE@mips_BUILD_OUTPUTS =3D \ @SIM_ENABLE_ARCH_mips_TRUE@ $(mips_BUILT_SRC_FROM_IGEN_ITABLE) \ @SIM_ENABLE_ARCH_mips_TRUE@ mips/stamp-igen-itable \ -@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_87) $(am__append_88) \ -@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_89) +@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_77) $(am__append_78) \ +@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_79) @SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_TRACE =3D # -G omit-line-numbers # -G= trace-rule-selection -G trace-rule-rejection -G trace-entries # -G trace-a= ll @SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN =3D $(srcdir)/mips/mips.igen @SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN_INC =3D \ @@ -4707,6 +4687,7 @@ testsuite/common/bits64m63.c: testsuite/common/bits-g= en$(EXEEXT) testsuite/commo =20 @SIM_ENABLE_ARCH_bpf_TRUE@bpf/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_bpf_TRUE@-@am__include@ bpf/$(DEPDIR)/*.Po + @SIM_ENABLE_ARCH_bpf_TRUE@bpf/modules.c: | $(bpf_BUILD_OUTPUTS) =20 @SIM_ENABLE_ARCH_bpf_TRUE@bpf/mloop-le.c bpf/eng-le.h: bpf/stamp-mloop-le = ; @true @@ -4759,6 +4740,7 @@ testsuite/common/bits64m63.c: testsuite/common/bits-g= en$(EXEEXT) testsuite/commo =20 @SIM_ENABLE_ARCH_cr16_TRUE@cr16/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_cr16_TRUE@-@am__include@ cr16/$(DEPDIR)/*.Po + @SIM_ENABLE_ARCH_cr16_TRUE@cr16/modules.c: | $(cr16_BUILD_OUTPUTS) =20 # These rules are copied from automake, but tweaked to use FOR_BUILD varia= bles. @@ -4780,6 +4762,7 @@ testsuite/common/bits64m63.c: testsuite/common/bits-g= en$(EXEEXT) testsuite/commo =20 @SIM_ENABLE_ARCH_cris_TRUE@cris/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_cris_TRUE@-@am__include@ cris/$(DEPDIR)/*.Po + @SIM_ENABLE_ARCH_cris_TRUE@cris/modules.c: | $(cris_BUILD_OUTPUTS) =20 @SIM_ENABLE_ARCH_cris_TRUE@cris/mloopv10f.c cris/engv10.h: cris/stamp-mloo= p-v10f ; @true @@ -4821,6 +4804,7 @@ testsuite/common/bits64m63.c: testsuite/common/bits-g= en$(EXEEXT) testsuite/commo =20 @SIM_ENABLE_ARCH_d10v_TRUE@d10v/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_d10v_TRUE@-@am__include@ d10v/$(DEPDIR)/*.Po + @SIM_ENABLE_ARCH_d10v_TRUE@d10v/modules.c: | $(d10v_BUILD_OUTPUTS) =20 # These rules are copied from automake, but tweaked to use FOR_BUILD varia= bles. @@ -4859,6 +4843,7 @@ testsuite/common/bits64m63.c: testsuite/common/bits-g= en$(EXEEXT) testsuite/commo =20 @SIM_ENABLE_ARCH_frv_TRUE@frv/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_frv_TRUE@-@am__include@ frv/$(DEPDIR)/*.Po + @SIM_ENABLE_ARCH_frv_TRUE@frv/modules.c: | $(frv_BUILD_OUTPUTS) =20 @SIM_ENABLE_ARCH_frv_TRUE@frv/mloop.c frv/eng.h: frv/stamp-mloop ; @true @@ -4892,6 +4877,7 @@ testsuite/common/bits64m63.c: testsuite/common/bits-g= en$(EXEEXT) testsuite/commo =20 @SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_iq2000_TRUE@-@am__include@ iq2000/$(DEPDIR)/*.Po + @SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/modules.c: | $(iq2000_BUILD_OUTPUTS) =20 @SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/mloop.c iq2000/eng.h: iq2000/stamp-mlo= op ; @true @@ -4917,6 +4903,7 @@ testsuite/common/bits64m63.c: testsuite/common/bits-g= en$(EXEEXT) testsuite/commo =20 @SIM_ENABLE_ARCH_lm32_TRUE@lm32/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_lm32_TRUE@-@am__include@ lm32/$(DEPDIR)/*.Po + @SIM_ENABLE_ARCH_lm32_TRUE@lm32/modules.c: | $(lm32_BUILD_OUTPUTS) =20 @SIM_ENABLE_ARCH_lm32_TRUE@lm32/mloop.c lm32/eng.h: lm32/stamp-mloop ; @tr= ue @@ -4942,6 +4929,7 @@ testsuite/common/bits64m63.c: testsuite/common/bits-g= en$(EXEEXT) testsuite/commo =20 @SIM_ENABLE_ARCH_m32c_TRUE@m32c/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_m32c_TRUE@-@am__include@ m32c/$(DEPDIR)/*.Po + @SIM_ENABLE_ARCH_m32c_TRUE@m32c/modules.c: | $(m32c_BUILD_OUTPUTS) =20 # These rules are copied from automake, but tweaked to use FOR_BUILD varia= bles. @@ -4963,6 +4951,7 @@ testsuite/common/bits64m63.c: testsuite/common/bits-g= en$(EXEEXT) testsuite/commo =20 @SIM_ENABLE_ARCH_m32r_TRUE@m32r/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_m32r_TRUE@-@am__include@ m32r/$(DEPDIR)/*.Po + @SIM_ENABLE_ARCH_m32r_TRUE@m32r/modules.c: | $(m32r_BUILD_OUTPUTS) =20 @SIM_ENABLE_ARCH_m32r_TRUE@m32r/mloop.c m32r/eng.h: m32r/stamp-mloop ; @tr= ue @@ -5016,6 +5005,7 @@ testsuite/common/bits64m63.c: testsuite/common/bits-g= en$(EXEEXT) testsuite/commo =20 @SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_m68hc11_TRUE@-@am__include@ m68hc11/$(DEPDIR)/*.Po + @SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11/modules.c: | $(m68hc11_BUILD_OUTPUTS) =20 # These rules are copied from automake, but tweaked to use FOR_BUILD varia= bles. @@ -5043,6 +5033,7 @@ testsuite/common/bits64m63.c: testsuite/common/bits-g= en$(EXEEXT) testsuite/commo =20 @SIM_ENABLE_ARCH_mips_TRUE@mips/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_mips_TRUE@-@am__include@ mips/$(DEPDIR)/*.Po + @SIM_ENABLE_ARCH_mips_TRUE@mips/modules.c: | $(mips_BUILD_OUTPUTS) =20 @SIM_ENABLE_ARCH_mips_TRUE@$(mips_BUILT_SRC_FROM_IGEN_ITABLE): mips/stamp-= igen-itable @@ -5246,6 +5237,7 @@ testsuite/common/bits64m63.c: testsuite/common/bits-g= en$(EXEEXT) testsuite/commo =20 @SIM_ENABLE_ARCH_mn10300_TRUE@mn10300/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_mn10300_TRUE@-@am__include@ mn10300/$(DEPDIR)/*.Po + @SIM_ENABLE_ARCH_mn10300_TRUE@mn10300/modules.c: | $(mn10300_BUILD_OUTPUTS) =20 @SIM_ENABLE_ARCH_mn10300_TRUE@$(mn10300_BUILT_SRC_FROM_IGEN): mn10300/stam= p-igen @@ -5299,6 +5291,7 @@ testsuite/common/bits64m63.c: testsuite/common/bits-g= en$(EXEEXT) testsuite/commo =20 @SIM_ENABLE_ARCH_or1k_TRUE@or1k/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_or1k_TRUE@-@am__include@ or1k/$(DEPDIR)/*.Po + @SIM_ENABLE_ARCH_or1k_TRUE@or1k/modules.c: | $(or1k_BUILD_OUTPUTS) =20 @SIM_ENABLE_ARCH_or1k_TRUE@or1k/mloop.c or1k/eng.h: or1k/stamp-mloop ; @tr= ue @@ -5356,6 +5349,7 @@ testsuite/common/bits64m63.c: testsuite/common/bits-g= en$(EXEEXT) testsuite/commo =20 @SIM_ENABLE_ARCH_sh_TRUE@sh/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_sh_TRUE@-@am__include@ sh/$(DEPDIR)/*.Po + @SIM_ENABLE_ARCH_sh_TRUE@sh/modules.c: | $(sh_BUILD_OUTPUTS) =20 # These rules are copied from automake, but tweaked to use FOR_BUILD varia= bles. @@ -5378,6 +5372,7 @@ testsuite/common/bits64m63.c: testsuite/common/bits-g= en$(EXEEXT) testsuite/commo =20 @SIM_ENABLE_ARCH_v850_TRUE@v850/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_v850_TRUE@-@am__include@ v850/$(DEPDIR)/*.Po + @SIM_ENABLE_ARCH_v850_TRUE@v850/modules.c: | $(v850_BUILD_OUTPUTS) =20 @SIM_ENABLE_ARCH_v850_TRUE@$(v850_BUILT_SRC_FROM_IGEN): v850/stamp-igen diff --git a/sim/bpf/local.mk b/sim/bpf/local.mk index 4218999c7e7..80bf775104f 100644 --- a/sim/bpf/local.mk +++ b/sim/bpf/local.mk @@ -73,8 +73,7 @@ BUILT_SOURCES +=3D \ %D%/mloop-be.c \ %D%/stamp-mloop-be =20 -## This makes sure build tools are available before building the arch-subd= irs. -SIM_ALL_RECURSIVE_DEPS +=3D $(%C%_BUILD_OUTPUTS) +## Generating modules.c requires all sources to scan. %D%/modules.c: | $(%C%_BUILD_OUTPUTS) =20 %D%/mloop-le.c %D%/eng-le.h: %D%/stamp-mloop-le ; @true diff --git a/sim/cr16/local.mk b/sim/cr16/local.mk index 19446381c9f..cb5ae553594 100644 --- a/sim/cr16/local.mk +++ b/sim/cr16/local.mk @@ -47,8 +47,7 @@ BUILT_SOURCES +=3D %D%/simops.h %D%/gencode$(EXEEXT) \ %D%/table.c =20 -## This makes sure build tools are available before building the arch-subd= irs. -SIM_ALL_RECURSIVE_DEPS +=3D $(%C%_BUILD_OUTPUTS) +## Generating modules.c requires all sources to scan. %D%/modules.c: | $(%C%_BUILD_OUTPUTS) =20 %C%_gencode_SOURCES =3D %D%/gencode.c diff --git a/sim/cris/local.mk b/sim/cris/local.mk index 14c8644fe07..3976f6836ef 100644 --- a/sim/cris/local.mk +++ b/sim/cris/local.mk @@ -77,8 +77,7 @@ BUILT_SOURCES +=3D \ %D%/mloopv32f.c \ %D%/stamp-mloop-v32f =20 -## This makes sure build tools are available before building the arch-subd= irs. -SIM_ALL_RECURSIVE_DEPS +=3D $(%C%_BUILD_OUTPUTS) +## Generating modules.c requires all sources to scan. %D%/modules.c: | $(%C%_BUILD_OUTPUTS) =20 ## FIXME: What is mono and what does "Use of `mono' is wip" mean (other diff --git a/sim/d10v/local.mk b/sim/d10v/local.mk index 967d4e7e543..63ddb6ea0c5 100644 --- a/sim/d10v/local.mk +++ b/sim/d10v/local.mk @@ -48,8 +48,7 @@ BUILT_SOURCES +=3D %D%/simops.h %D%/gencode$(EXEEXT) \ %D%/table.c =20 -## This makes sure build tools are available before building the arch-subd= irs. -SIM_ALL_RECURSIVE_DEPS +=3D $(%C%_BUILD_OUTPUTS) +## Generating modules.c requires all sources to scan. %D%/modules.c: | $(%C%_BUILD_OUTPUTS) =20 %C%_gencode_SOURCES =3D %D%/gencode.c diff --git a/sim/frv/local.mk b/sim/frv/local.mk index c1a10045a70..7d572fccb6a 100644 --- a/sim/frv/local.mk +++ b/sim/frv/local.mk @@ -83,8 +83,7 @@ BUILT_SOURCES +=3D %D%/eng.h %D%/mloop.c \ %D%/stamp-mloop =20 -## This makes sure build tools are available before building the arch-subd= irs. -SIM_ALL_RECURSIVE_DEPS +=3D $(%C%_BUILD_OUTPUTS) +## Generating modules.c requires all sources to scan. %D%/modules.c: | $(%C%_BUILD_OUTPUTS) =20 ## FIXME: Use of `mono' is wip. diff --git a/sim/iq2000/local.mk b/sim/iq2000/local.mk index fa498e48595..77804fe69ab 100644 --- a/sim/iq2000/local.mk +++ b/sim/iq2000/local.mk @@ -58,8 +58,7 @@ BUILT_SOURCES +=3D %D%/eng.h %D%/mloop.c \ %D%/stamp-mloop =20 -## This makes sure build tools are available before building the arch-subd= irs. -SIM_ALL_RECURSIVE_DEPS +=3D $(%C%_BUILD_OUTPUTS) +## Generating modules.c requires all sources to scan. %D%/modules.c: | $(%C%_BUILD_OUTPUTS) =20 ## FIXME: Use of `mono' is wip. diff --git a/sim/lm32/local.mk b/sim/lm32/local.mk index 4fecaca6a38..40f8d524c95 100644 --- a/sim/lm32/local.mk +++ b/sim/lm32/local.mk @@ -63,8 +63,7 @@ BUILT_SOURCES +=3D %D%/eng.h %D%/mloop.c \ %D%/stamp-mloop =20 -## This makes sure build tools are available before building the arch-subd= irs. -SIM_ALL_RECURSIVE_DEPS +=3D $(%C%_BUILD_OUTPUTS) +## Generating modules.c requires all sources to scan. %D%/modules.c: | $(%C%_BUILD_OUTPUTS) =20 ## FIXME: Use of `mono' is wip. diff --git a/sim/m32c/local.mk b/sim/m32c/local.mk index 7093e248c7e..a6d22424929 100644 --- a/sim/m32c/local.mk +++ b/sim/m32c/local.mk @@ -53,8 +53,7 @@ noinst_PROGRAMS +=3D %D%/run %D%/m32c.c \ %D%/r8c.c =20 -## This makes sure build tools are available before building the arch-subd= irs. -SIM_ALL_RECURSIVE_DEPS +=3D $(%C%_BUILD_OUTPUTS) +## Generating modules.c requires all sources to scan. %D%/modules.c: | $(%C%_BUILD_OUTPUTS) =20 %C%_opc2c_SOURCES =3D %D%/opc2c.c diff --git a/sim/m32r/local.mk b/sim/m32r/local.mk index 6a6a6d99912..24ef10ef2bc 100644 --- a/sim/m32r/local.mk +++ b/sim/m32r/local.mk @@ -96,8 +96,7 @@ BUILT_SOURCES +=3D \ %D%/mloop2.c \ %D%/stamp-mloop-2 =20 -## This makes sure build tools are available before building the arch-subd= irs. -SIM_ALL_RECURSIVE_DEPS +=3D $(%C%_BUILD_OUTPUTS) +## Generating modules.c requires all sources to scan. %D%/modules.c: | $(%C%_BUILD_OUTPUTS) =20 ## FIXME: Use of `mono' is wip. diff --git a/sim/m68hc11/local.mk b/sim/m68hc11/local.mk index d5faae40ed5..e094918a321 100644 --- a/sim/m68hc11/local.mk +++ b/sim/m68hc11/local.mk @@ -63,8 +63,7 @@ noinst_PROGRAMS +=3D %D%/run %D%/m68hc11int.c \ %D%/m68hc12int.c =20 -## This makes sure build tools are available before building the arch-subd= irs. -SIM_ALL_RECURSIVE_DEPS +=3D $(%C%_BUILD_OUTPUTS) +## Generating modules.c requires all sources to scan. %D%/modules.c: | $(%C%_BUILD_OUTPUTS) =20 %C%_gencode_SOURCES =3D %D%/gencode.c diff --git a/sim/mips/local.mk b/sim/mips/local.mk index 942997240c8..5f32eee573f 100644 --- a/sim/mips/local.mk +++ b/sim/mips/local.mk @@ -154,8 +154,7 @@ if SIM_MIPS_GEN_MODE_MULTI %D%/stamp-gen-mode-multi-run endif =20 -## This makes sure build tools are available before building the arch-subd= irs. -SIM_ALL_RECURSIVE_DEPS +=3D $(%C%_BUILD_OUTPUTS) +## Generating modules.c requires all sources to scan. %D%/modules.c: | $(%C%_BUILD_OUTPUTS) =20 $(%C%_BUILT_SRC_FROM_IGEN_ITABLE): %D%/stamp-igen-itable diff --git a/sim/mn10300/local.mk b/sim/mn10300/local.mk index 2abd093e834..1eae112642d 100644 --- a/sim/mn10300/local.mk +++ b/sim/mn10300/local.mk @@ -83,8 +83,7 @@ BUILT_SOURCES +=3D \ $(%C%_BUILT_SRC_FROM_IGEN) \ %D%/stamp-igen =20 -## This makes sure build tools are available before building the arch-subd= irs. -SIM_ALL_RECURSIVE_DEPS +=3D $(%C%_BUILD_OUTPUTS) +## Generating modules.c requires all sources to scan. %D%/modules.c: | $(%C%_BUILD_OUTPUTS) =20 $(%C%_BUILT_SRC_FROM_IGEN): %D%/stamp-igen diff --git a/sim/or1k/local.mk b/sim/or1k/local.mk index 71a34db21d8..a5989d51dda 100644 --- a/sim/or1k/local.mk +++ b/sim/or1k/local.mk @@ -65,8 +65,7 @@ BUILT_SOURCES +=3D %D%/eng.h %D%/mloop.c \ %D%/stamp-mloop =20 -## This makes sure build tools are available before building the arch-subd= irs. -SIM_ALL_RECURSIVE_DEPS +=3D $(%C%_BUILD_OUTPUTS) +## Generating modules.c requires all sources to scan. %D%/modules.c: | $(%C%_BUILD_OUTPUTS) =20 ## FIXME: Use of `mono' is wip. diff --git a/sim/sh/local.mk b/sim/sh/local.mk index b197fa4c7c3..4f6a4c5e661 100644 --- a/sim/sh/local.mk +++ b/sim/sh/local.mk @@ -49,8 +49,7 @@ BUILT_SOURCES +=3D \ %D%/gencode$(EXEEXT) \ %D%/table.c =20 -## This makes sure build tools are available before building the arch-subd= irs. -SIM_ALL_RECURSIVE_DEPS +=3D $(%C%_BUILD_OUTPUTS) +## Generating modules.c requires all sources to scan. %D%/modules.c: | $(%C%_BUILD_OUTPUTS) =20 %C%_gencode_SOURCES =3D %D%/gencode.c diff --git a/sim/v850/local.mk b/sim/v850/local.mk index 68f61f89505..973e83c4278 100644 --- a/sim/v850/local.mk +++ b/sim/v850/local.mk @@ -78,8 +78,7 @@ BUILT_SOURCES +=3D \ $(%C%_BUILT_SRC_FROM_IGEN) \ %D%/stamp-igen =20 -## This makes sure build tools are available before building the arch-subd= irs. -SIM_ALL_RECURSIVE_DEPS +=3D $(%C%_BUILD_OUTPUTS) +## Generating modules.c requires all sources to scan. %D%/modules.c: | $(%C%_BUILD_OUTPUTS) =20 $(%C%_BUILT_SRC_FROM_IGEN): %D%/stamp-igen