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From: Michael Frysinger <vapier@sourceware.org>
To: gdb-cvs@sourceware.org
Subject: [binutils-gdb] sim: igen: simplify build logic a little
X-Act-Checkin: binutils-gdb
X-Git-Author: Mike Frysinger <vapier@gentoo.org>
X-Git-Refname: refs/heads/master
X-Git-Oldrev: eaa13962f22acfe8bff388e2bc4d7335ec3fe802
X-Git-Newrev: 9a7472d7c599453405484f2df5206e56b7618fb3
Message-Id: <20230115071030.CE2393858D1E@sourceware.org>
Date: Sun, 15 Jan 2023 07:10:30 +0000 (GMT)
List-Id: <gdb-cvs.sourceware.org>

https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D9a7472d7c599=
453405484f2df5206e56b7618fb3

commit 9a7472d7c599453405484f2df5206e56b7618fb3
Author: Mike Frysinger <vapier@gentoo.org>
Date:   Sat Jan 14 21:55:31 2023 -0500

    sim: igen: simplify build logic a little
   =20
    Now that all ports (that use igen) build in the top-level and depend
    on igen, we can move the conditional logic out of configure.  We also
    switch from noinst_LIBRARIES to EXTRA_LIBRARIES so that the library
    is only built when needed (i.e. the igen tool is used).

Diff:
---
 sim/Makefile.am   |   3 +-
 sim/Makefile.in   | 564 ++++++++++++++++++++++++++------------------------=
----
 sim/configure     |  50 +----
 sim/configure.ac  |  10 +-
 sim/igen/local.mk |   2 +-
 5 files changed, 275 insertions(+), 354 deletions(-)

diff --git a/sim/Makefile.am b/sim/Makefile.am
index 0e9fc3c67a9..3693eb18d49 100644
--- a/sim/Makefile.am
+++ b/sim/Makefile.am
@@ -33,6 +33,7 @@ SIM_PRIMARY_TARGET =3D @SIM_PRIMARY_TARGET@
 pkginclude_HEADERS =3D
 check_PROGRAMS =3D
 noinst_PROGRAMS =3D
+EXTRA_LIBRARIES =3D
 noinst_LIBRARIES =3D
 EXTRA_PROGRAMS =3D
 BUILT_SOURCES =3D
@@ -101,9 +102,7 @@ SIM_COMPILE =3D \
 	$(am__mv) $(SIM_DEPBASE).Tpo $(SIM_DEPBASE).Po
=20
 include common/local.mk
-if SIM_ENABLE_IGEN
 include igen/local.mk
-endif
 include testsuite/local.mk
=20
 ## Arch includes must come after common/local.mk.
diff --git a/sim/Makefile.in b/sim/Makefile.in
index 1ac885f6d1f..3f8713339b4 100644
--- a/sim/Makefile.in
+++ b/sim/Makefile.in
@@ -107,22 +107,22 @@ POST_UNINSTALL =3D :
 build_triplet =3D @build@
 host_triplet =3D @host@
 target_triplet =3D @target@
-check_PROGRAMS =3D $(am__EXEEXT_8) $(am__EXEEXT_9)
-noinst_PROGRAMS =3D $(am__EXEEXT_10) $(am__EXEEXT_11) $(am__EXEEXT_12) \
-	$(am__EXEEXT_13) $(am__EXEEXT_14) $(am__EXEEXT_15) \
-	$(am__EXEEXT_16) $(am__EXEEXT_17) $(am__EXEEXT_18) \
-	$(am__EXEEXT_19) $(am__EXEEXT_20) $(am__EXEEXT_21) \
-	$(am__EXEEXT_22) $(am__EXEEXT_23) $(am__EXEEXT_24) \
-	$(am__EXEEXT_25) $(am__EXEEXT_26) $(am__EXEEXT_27) \
-	$(am__EXEEXT_28) $(am__EXEEXT_29) $(am__EXEEXT_30) \
-	$(am__EXEEXT_31) $(am__EXEEXT_32) $(am__EXEEXT_33) \
-	$(am__EXEEXT_34) $(am__EXEEXT_35) $(am__EXEEXT_36) \
-	$(am__EXEEXT_37) $(am__EXEEXT_38) $(am__EXEEXT_39) \
-	$(am__EXEEXT_40) $(am__EXEEXT_41)
-EXTRA_PROGRAMS =3D $(am__EXEEXT_2) testsuite/common/bits-gen$(EXEEXT) \
-	testsuite/common/fpu-tst$(EXEEXT) $(am__EXEEXT_3) \
-	$(am__EXEEXT_4) $(am__EXEEXT_5) $(am__EXEEXT_6) \
-	$(am__EXEEXT_7)
+check_PROGRAMS =3D $(am__EXEEXT_7) $(am__EXEEXT_8)
+noinst_PROGRAMS =3D $(am__EXEEXT_9) $(am__EXEEXT_10) $(am__EXEEXT_11) \
+	$(am__EXEEXT_12) $(am__EXEEXT_13) $(am__EXEEXT_14) \
+	$(am__EXEEXT_15) $(am__EXEEXT_16) $(am__EXEEXT_17) \
+	$(am__EXEEXT_18) $(am__EXEEXT_19) $(am__EXEEXT_20) \
+	$(am__EXEEXT_21) $(am__EXEEXT_22) $(am__EXEEXT_23) \
+	$(am__EXEEXT_24) $(am__EXEEXT_25) $(am__EXEEXT_26) \
+	$(am__EXEEXT_27) $(am__EXEEXT_28) $(am__EXEEXT_29) \
+	$(am__EXEEXT_30) $(am__EXEEXT_31) $(am__EXEEXT_32) \
+	$(am__EXEEXT_33) $(am__EXEEXT_34) $(am__EXEEXT_35) \
+	$(am__EXEEXT_36) $(am__EXEEXT_37) $(am__EXEEXT_38) \
+	$(am__EXEEXT_39) $(am__EXEEXT_40)
+EXTRA_PROGRAMS =3D $(am__EXEEXT_1) testsuite/common/bits-gen$(EXEEXT) \
+	testsuite/common/fpu-tst$(EXEEXT) $(am__EXEEXT_2) \
+	$(am__EXEEXT_3) $(am__EXEEXT_4) $(am__EXEEXT_5) \
+	$(am__EXEEXT_6)
 @ENABLE_SIM_TRUE@am__append_1 =3D \
 @ENABLE_SIM_TRUE@	$(srcroot)/include/sim/callback.h \
 @ENABLE_SIM_TRUE@	$(srcroot)/include/sim/sim.h
@@ -131,94 +131,91 @@ EXTRA_PROGRAMS =3D $(am__EXEEXT_2) testsuite/common/b=
its-gen$(EXEEXT) \
 @SIM_ENABLE_HW_TRUE@	$(SIM_COMMON_HW_OBJS) \
 @SIM_ENABLE_HW_TRUE@	$(SIM_HW_SOCKSER)
=20
-@SIM_ENABLE_IGEN_TRUE@am__append_3 =3D igen/libigen.a
-@SIM_ENABLE_IGEN_TRUE@am__append_4 =3D $(igen_IGEN_TOOLS)
-@SIM_ENABLE_IGEN_TRUE@am__append_5 =3D $(igen_IGEN_TOOLS)
 TESTS =3D testsuite/common/bits32m0$(EXEEXT) \
 	testsuite/common/bits32m31$(EXEEXT) \
 	testsuite/common/bits64m0$(EXEEXT) \
 	testsuite/common/bits64m63$(EXEEXT) \
 	testsuite/common/alu-tst$(EXEEXT)
-@SIM_ENABLE_ARCH_aarch64_TRUE@am__append_6 =3D aarch64/libsim.a
-@SIM_ENABLE_ARCH_aarch64_TRUE@am__append_7 =3D aarch64/run
-@SIM_ENABLE_ARCH_arm_TRUE@am__append_8 =3D arm/libsim.a
-@SIM_ENABLE_ARCH_arm_TRUE@am__append_9 =3D arm/run
-@SIM_ENABLE_ARCH_avr_TRUE@am__append_10 =3D avr/libsim.a
-@SIM_ENABLE_ARCH_avr_TRUE@am__append_11 =3D avr/run
-@SIM_ENABLE_ARCH_bfin_TRUE@am__append_12 =3D bfin/libsim.a
-@SIM_ENABLE_ARCH_bfin_TRUE@am__append_13 =3D bfin/run
-@SIM_ENABLE_ARCH_bpf_TRUE@am__append_14 =3D bpf/libsim.a
-@SIM_ENABLE_ARCH_bpf_TRUE@am__append_15 =3D bpf/run
-@SIM_ENABLE_ARCH_bpf_TRUE@am__append_16 =3D \
+@SIM_ENABLE_ARCH_aarch64_TRUE@am__append_3 =3D aarch64/libsim.a
+@SIM_ENABLE_ARCH_aarch64_TRUE@am__append_4 =3D aarch64/run
+@SIM_ENABLE_ARCH_arm_TRUE@am__append_5 =3D arm/libsim.a
+@SIM_ENABLE_ARCH_arm_TRUE@am__append_6 =3D arm/run
+@SIM_ENABLE_ARCH_avr_TRUE@am__append_7 =3D avr/libsim.a
+@SIM_ENABLE_ARCH_avr_TRUE@am__append_8 =3D avr/run
+@SIM_ENABLE_ARCH_bfin_TRUE@am__append_9 =3D bfin/libsim.a
+@SIM_ENABLE_ARCH_bfin_TRUE@am__append_10 =3D bfin/run
+@SIM_ENABLE_ARCH_bpf_TRUE@am__append_11 =3D bpf/libsim.a
+@SIM_ENABLE_ARCH_bpf_TRUE@am__append_12 =3D bpf/run
+@SIM_ENABLE_ARCH_bpf_TRUE@am__append_13 =3D \
 @SIM_ENABLE_ARCH_bpf_TRUE@	bpf/eng-le.h \
 @SIM_ENABLE_ARCH_bpf_TRUE@	bpf/eng-be.h
=20
-@SIM_ENABLE_ARCH_bpf_TRUE@am__append_17 =3D $(bpf_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_cr16_TRUE@am__append_18 =3D cr16/libsim.a
-@SIM_ENABLE_ARCH_cr16_TRUE@am__append_19 =3D cr16/run
-@SIM_ENABLE_ARCH_cr16_TRUE@am__append_20 =3D cr16/simops.h
-@SIM_ENABLE_ARCH_cr16_TRUE@am__append_21 =3D cr16/gencode
-@SIM_ENABLE_ARCH_cr16_TRUE@am__append_22 =3D $(cr16_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_cris_TRUE@am__append_23 =3D cris/libsim.a
-@SIM_ENABLE_ARCH_cris_TRUE@am__append_24 =3D cris/run
-@SIM_ENABLE_ARCH_cris_TRUE@am__append_25 =3D cris/rvdummy
-@SIM_ENABLE_ARCH_cris_TRUE@am__append_26 =3D \
+@SIM_ENABLE_ARCH_bpf_TRUE@am__append_14 =3D $(bpf_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_cr16_TRUE@am__append_15 =3D cr16/libsim.a
+@SIM_ENABLE_ARCH_cr16_TRUE@am__append_16 =3D cr16/run
+@SIM_ENABLE_ARCH_cr16_TRUE@am__append_17 =3D cr16/simops.h
+@SIM_ENABLE_ARCH_cr16_TRUE@am__append_18 =3D cr16/gencode
+@SIM_ENABLE_ARCH_cr16_TRUE@am__append_19 =3D $(cr16_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_cris_TRUE@am__append_20 =3D cris/libsim.a
+@SIM_ENABLE_ARCH_cris_TRUE@am__append_21 =3D cris/run
+@SIM_ENABLE_ARCH_cris_TRUE@am__append_22 =3D cris/rvdummy
+@SIM_ENABLE_ARCH_cris_TRUE@am__append_23 =3D \
 @SIM_ENABLE_ARCH_cris_TRUE@	cris/engv10.h \
 @SIM_ENABLE_ARCH_cris_TRUE@	cris/engv32.h
=20
-@SIM_ENABLE_ARCH_cris_TRUE@am__append_27 =3D $(cris_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_d10v_TRUE@am__append_28 =3D d10v/libsim.a
-@SIM_ENABLE_ARCH_d10v_TRUE@am__append_29 =3D d10v/run
-@SIM_ENABLE_ARCH_d10v_TRUE@am__append_30 =3D d10v/simops.h
-@SIM_ENABLE_ARCH_d10v_TRUE@am__append_31 =3D d10v/gencode
-@SIM_ENABLE_ARCH_d10v_TRUE@am__append_32 =3D $(d10v_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_erc32_TRUE@am__append_33 =3D erc32/libsim.a
-@SIM_ENABLE_ARCH_erc32_TRUE@am__append_34 =3D erc32/run erc32/sis
-@SIM_ENABLE_ARCH_erc32_TRUE@am__append_35 =3D sim-%D-install-exec-local
-@SIM_ENABLE_ARCH_erc32_TRUE@am__append_36 =3D sim-erc32-uninstall-local
-@SIM_ENABLE_ARCH_examples_TRUE@am__append_37 =3D example-synacor/libsim.a
-@SIM_ENABLE_ARCH_examples_TRUE@am__append_38 =3D example-synacor/run
-@SIM_ENABLE_ARCH_frv_TRUE@am__append_39 =3D frv/libsim.a
-@SIM_ENABLE_ARCH_frv_TRUE@am__append_40 =3D frv/run
-@SIM_ENABLE_ARCH_frv_TRUE@am__append_41 =3D frv/eng.h
-@SIM_ENABLE_ARCH_frv_TRUE@am__append_42 =3D $(frv_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_ft32_TRUE@am__append_43 =3D ft32/libsim.a
-@SIM_ENABLE_ARCH_ft32_TRUE@am__append_44 =3D ft32/run
-@SIM_ENABLE_ARCH_h8300_TRUE@am__append_45 =3D h8300/libsim.a
-@SIM_ENABLE_ARCH_h8300_TRUE@am__append_46 =3D h8300/run
-@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_47 =3D iq2000/libsim.a
-@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_48 =3D iq2000/run
-@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_49 =3D iq2000/eng.h
-@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_50 =3D $(iq2000_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_lm32_TRUE@am__append_51 =3D lm32/libsim.a
-@SIM_ENABLE_ARCH_lm32_TRUE@am__append_52 =3D lm32/run
-@SIM_ENABLE_ARCH_lm32_TRUE@am__append_53 =3D lm32/eng.h
-@SIM_ENABLE_ARCH_lm32_TRUE@am__append_54 =3D $(lm32_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_m32c_TRUE@am__append_55 =3D m32c/libsim.a
-@SIM_ENABLE_ARCH_m32c_TRUE@am__append_56 =3D m32c/run
-@SIM_ENABLE_ARCH_m32c_TRUE@am__append_57 =3D m32c/opc2c
-@SIM_ENABLE_ARCH_m32c_TRUE@am__append_58 =3D \
+@SIM_ENABLE_ARCH_cris_TRUE@am__append_24 =3D $(cris_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_d10v_TRUE@am__append_25 =3D d10v/libsim.a
+@SIM_ENABLE_ARCH_d10v_TRUE@am__append_26 =3D d10v/run
+@SIM_ENABLE_ARCH_d10v_TRUE@am__append_27 =3D d10v/simops.h
+@SIM_ENABLE_ARCH_d10v_TRUE@am__append_28 =3D d10v/gencode
+@SIM_ENABLE_ARCH_d10v_TRUE@am__append_29 =3D $(d10v_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_erc32_TRUE@am__append_30 =3D erc32/libsim.a
+@SIM_ENABLE_ARCH_erc32_TRUE@am__append_31 =3D erc32/run erc32/sis
+@SIM_ENABLE_ARCH_erc32_TRUE@am__append_32 =3D sim-%D-install-exec-local
+@SIM_ENABLE_ARCH_erc32_TRUE@am__append_33 =3D sim-erc32-uninstall-local
+@SIM_ENABLE_ARCH_examples_TRUE@am__append_34 =3D example-synacor/libsim.a
+@SIM_ENABLE_ARCH_examples_TRUE@am__append_35 =3D example-synacor/run
+@SIM_ENABLE_ARCH_frv_TRUE@am__append_36 =3D frv/libsim.a
+@SIM_ENABLE_ARCH_frv_TRUE@am__append_37 =3D frv/run
+@SIM_ENABLE_ARCH_frv_TRUE@am__append_38 =3D frv/eng.h
+@SIM_ENABLE_ARCH_frv_TRUE@am__append_39 =3D $(frv_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_ft32_TRUE@am__append_40 =3D ft32/libsim.a
+@SIM_ENABLE_ARCH_ft32_TRUE@am__append_41 =3D ft32/run
+@SIM_ENABLE_ARCH_h8300_TRUE@am__append_42 =3D h8300/libsim.a
+@SIM_ENABLE_ARCH_h8300_TRUE@am__append_43 =3D h8300/run
+@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_44 =3D iq2000/libsim.a
+@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_45 =3D iq2000/run
+@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_46 =3D iq2000/eng.h
+@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_47 =3D $(iq2000_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_lm32_TRUE@am__append_48 =3D lm32/libsim.a
+@SIM_ENABLE_ARCH_lm32_TRUE@am__append_49 =3D lm32/run
+@SIM_ENABLE_ARCH_lm32_TRUE@am__append_50 =3D lm32/eng.h
+@SIM_ENABLE_ARCH_lm32_TRUE@am__append_51 =3D $(lm32_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_m32c_TRUE@am__append_52 =3D m32c/libsim.a
+@SIM_ENABLE_ARCH_m32c_TRUE@am__append_53 =3D m32c/run
+@SIM_ENABLE_ARCH_m32c_TRUE@am__append_54 =3D m32c/opc2c
+@SIM_ENABLE_ARCH_m32c_TRUE@am__append_55 =3D \
 @SIM_ENABLE_ARCH_m32c_TRUE@	$(m32c_BUILD_OUTPUTS) \
 @SIM_ENABLE_ARCH_m32c_TRUE@	m32c/m32c.c.log \
 @SIM_ENABLE_ARCH_m32c_TRUE@	m32c/r8c.c.log
=20
-@SIM_ENABLE_ARCH_m32r_TRUE@am__append_59 =3D m32r/libsim.a
-@SIM_ENABLE_ARCH_m32r_TRUE@am__append_60 =3D m32r/run
-@SIM_ENABLE_ARCH_m32r_TRUE@am__append_61 =3D \
+@SIM_ENABLE_ARCH_m32r_TRUE@am__append_56 =3D m32r/libsim.a
+@SIM_ENABLE_ARCH_m32r_TRUE@am__append_57 =3D m32r/run
+@SIM_ENABLE_ARCH_m32r_TRUE@am__append_58 =3D \
 @SIM_ENABLE_ARCH_m32r_TRUE@	m32r/eng.h \
 @SIM_ENABLE_ARCH_m32r_TRUE@	m32r/engx.h \
 @SIM_ENABLE_ARCH_m32r_TRUE@	m32r/eng2.h
=20
-@SIM_ENABLE_ARCH_m32r_TRUE@am__append_62 =3D $(m32r_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_63 =3D m68hc11/libsim.a
-@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_64 =3D m68hc11/run
-@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_65 =3D m68hc11/gencode
-@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_66 =3D $(m68hc11_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_mcore_TRUE@am__append_67 =3D mcore/libsim.a
-@SIM_ENABLE_ARCH_mcore_TRUE@am__append_68 =3D mcore/run
-@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_69 =3D microblaze/libsim.a
-@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_70 =3D microblaze/run
-@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_71 =
=3D \
+@SIM_ENABLE_ARCH_m32r_TRUE@am__append_59 =3D $(m32r_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_60 =3D m68hc11/libsim.a
+@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_61 =3D m68hc11/run
+@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_62 =3D m68hc11/gencode
+@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_63 =3D $(m68hc11_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_mcore_TRUE@am__append_64 =3D mcore/libsim.a
+@SIM_ENABLE_ARCH_mcore_TRUE@am__append_65 =3D mcore/run
+@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_66 =3D microblaze/libsim.a
+@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_67 =3D microblaze/run
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_68 =
=3D \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@	mips/support.o \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@	mips/itable.o \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@	mips/semantics.=
o \
@@ -227,7 +224,7 @@ TESTS =3D testsuite/common/bits32m0$(EXEEXT) \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@	mips/engine.o \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@	mips/irun.o
=20
-@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_72 =3D \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_69 =3D \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	mips/m16_support.o=
 \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	mips/m16_semantics=
.o \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	mips/m16_idecode.o=
 \
@@ -241,35 +238,35 @@ TESTS =3D testsuite/common/bits32m0$(EXEEXT) \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	mips/itable.o \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	mips/m16run.o
=20
-@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_73 =3D=
 \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_70 =3D=
 \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@	$(SIM_MIPS_MULTI=
_OBJ) \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@	mips/itable.o \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@	mips/multi-run.o
=20
-@SIM_ENABLE_ARCH_mips_TRUE@am__append_74 =3D mips/libsim.a
-@SIM_ENABLE_ARCH_mips_TRUE@am__append_75 =3D mips/run
-@SIM_ENABLE_ARCH_mips_TRUE@am__append_76 =3D mips/itable.h \
+@SIM_ENABLE_ARCH_mips_TRUE@am__append_71 =3D mips/libsim.a
+@SIM_ENABLE_ARCH_mips_TRUE@am__append_72 =3D mips/run
+@SIM_ENABLE_ARCH_mips_TRUE@am__append_73 =3D mips/itable.h \
 @SIM_ENABLE_ARCH_mips_TRUE@	$(SIM_MIPS_MULTI_SRC)
-@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_77 =
=3D \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_74 =
=3D \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@	$(mips_BUILT_SR=
C_FROM_GEN_MODE_SINGLE) \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@	mips/stamp-gen-=
mode-single
=20
-@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_78 =3D \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_75 =3D \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	$(mips_BUILT_SRC_F=
ROM_GEN_MODE_M16_M16) \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	$(mips_BUILT_SRC_F=
ROM_GEN_MODE_M16_M32) \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	mips/stamp-gen-mod=
e-m16-m16 \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	mips/stamp-gen-mod=
e-m16-m32
=20
-@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_79 =3D=
 \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_76 =3D=
 \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@	$(SIM_MIPS_MULTI=
_SRC) \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@	mips/stamp-gen-m=
ode-multi-igen \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@	mips/stamp-gen-m=
ode-multi-run
=20
-@SIM_ENABLE_ARCH_mips_TRUE@am__append_80 =3D $(mips_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_mips_TRUE@am__append_81 =3D mips/multi-include.h mips/mul=
ti-run.c
-@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_82 =3D mn10300/libsim.a
-@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_83 =3D mn10300/run
-@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_84 =3D \
+@SIM_ENABLE_ARCH_mips_TRUE@am__append_77 =3D $(mips_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_mips_TRUE@am__append_78 =3D mips/multi-include.h mips/mul=
ti-run.c
+@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_79 =3D mn10300/libsim.a
+@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_80 =3D mn10300/run
+@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_81 =3D \
 @SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/icache.h \
 @SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/idecode.h \
 @SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/semantics.h \
@@ -278,36 +275,36 @@ TESTS =3D testsuite/common/bits32m0$(EXEEXT) \
 @SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/itable.h \
 @SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/engine.h
=20
-@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_85 =3D $(mn10300_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_moxie_TRUE@am__append_86 =3D moxie/libsim.a
-@SIM_ENABLE_ARCH_moxie_TRUE@am__append_87 =3D moxie/run
-@SIM_ENABLE_ARCH_msp430_TRUE@am__append_88 =3D msp430/libsim.a
-@SIM_ENABLE_ARCH_msp430_TRUE@am__append_89 =3D msp430/run
-@SIM_ENABLE_ARCH_or1k_TRUE@am__append_90 =3D or1k/libsim.a
-@SIM_ENABLE_ARCH_or1k_TRUE@am__append_91 =3D or1k/run
-@SIM_ENABLE_ARCH_or1k_TRUE@am__append_92 =3D or1k/eng.h
-@SIM_ENABLE_ARCH_or1k_TRUE@am__append_93 =3D $(or1k_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_ppc_TRUE@am__append_94 =3D common/libcommon.a
-@SIM_ENABLE_ARCH_ppc_TRUE@am__append_95 =3D ppc/run ppc/psim
-@SIM_ENABLE_ARCH_pru_TRUE@am__append_96 =3D pru/libsim.a
-@SIM_ENABLE_ARCH_pru_TRUE@am__append_97 =3D pru/run
-@SIM_ENABLE_ARCH_riscv_TRUE@am__append_98 =3D riscv/libsim.a
-@SIM_ENABLE_ARCH_riscv_TRUE@am__append_99 =3D riscv/run
-@SIM_ENABLE_ARCH_rl78_TRUE@am__append_100 =3D rl78/libsim.a
-@SIM_ENABLE_ARCH_rl78_TRUE@am__append_101 =3D rl78/run
-@SIM_ENABLE_ARCH_rx_TRUE@am__append_102 =3D rx/libsim.a
-@SIM_ENABLE_ARCH_rx_TRUE@am__append_103 =3D rx/run
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_104 =3D sh/libsim.a
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_105 =3D sh/run
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_106 =3D \
+@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_82 =3D $(mn10300_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_moxie_TRUE@am__append_83 =3D moxie/libsim.a
+@SIM_ENABLE_ARCH_moxie_TRUE@am__append_84 =3D moxie/run
+@SIM_ENABLE_ARCH_msp430_TRUE@am__append_85 =3D msp430/libsim.a
+@SIM_ENABLE_ARCH_msp430_TRUE@am__append_86 =3D msp430/run
+@SIM_ENABLE_ARCH_or1k_TRUE@am__append_87 =3D or1k/libsim.a
+@SIM_ENABLE_ARCH_or1k_TRUE@am__append_88 =3D or1k/run
+@SIM_ENABLE_ARCH_or1k_TRUE@am__append_89 =3D or1k/eng.h
+@SIM_ENABLE_ARCH_or1k_TRUE@am__append_90 =3D $(or1k_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_ppc_TRUE@am__append_91 =3D common/libcommon.a
+@SIM_ENABLE_ARCH_ppc_TRUE@am__append_92 =3D ppc/run ppc/psim
+@SIM_ENABLE_ARCH_pru_TRUE@am__append_93 =3D pru/libsim.a
+@SIM_ENABLE_ARCH_pru_TRUE@am__append_94 =3D pru/run
+@SIM_ENABLE_ARCH_riscv_TRUE@am__append_95 =3D riscv/libsim.a
+@SIM_ENABLE_ARCH_riscv_TRUE@am__append_96 =3D riscv/run
+@SIM_ENABLE_ARCH_rl78_TRUE@am__append_97 =3D rl78/libsim.a
+@SIM_ENABLE_ARCH_rl78_TRUE@am__append_98 =3D rl78/run
+@SIM_ENABLE_ARCH_rx_TRUE@am__append_99 =3D rx/libsim.a
+@SIM_ENABLE_ARCH_rx_TRUE@am__append_100 =3D rx/run
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_101 =3D sh/libsim.a
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_102 =3D sh/run
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_103 =3D \
 @SIM_ENABLE_ARCH_sh_TRUE@	sh/code.c \
 @SIM_ENABLE_ARCH_sh_TRUE@	sh/ppi.c
=20
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_107 =3D sh/gencode
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_108 =3D $(sh_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_v850_TRUE@am__append_109 =3D v850/libsim.a
-@SIM_ENABLE_ARCH_v850_TRUE@am__append_110 =3D v850/run
-@SIM_ENABLE_ARCH_v850_TRUE@am__append_111 =3D \
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_104 =3D sh/gencode
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_105 =3D $(sh_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_v850_TRUE@am__append_106 =3D v850/libsim.a
+@SIM_ENABLE_ARCH_v850_TRUE@am__append_107 =3D v850/run
+@SIM_ENABLE_ARCH_v850_TRUE@am__append_108 =3D \
 @SIM_ENABLE_ARCH_v850_TRUE@	v850/icache.h \
 @SIM_ENABLE_ARCH_v850_TRUE@	v850/idecode.h \
 @SIM_ENABLE_ARCH_v850_TRUE@	v850/semantics.h \
@@ -316,7 +313,7 @@ TESTS =3D testsuite/common/bits32m0$(EXEEXT) \
 @SIM_ENABLE_ARCH_v850_TRUE@	v850/itable.h \
 @SIM_ENABLE_ARCH_v850_TRUE@	v850/engine.h
=20
-@SIM_ENABLE_ARCH_v850_TRUE@am__append_112 =3D $(v850_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_v850_TRUE@am__append_109 =3D $(v850_BUILD_OUTPUTS)
 subdir =3D .
 ACLOCAL_M4 =3D $(top_srcdir)/aclocal.m4
 am__aclocal_m4_deps =3D $(top_srcdir)/../config/acx.m4 \
@@ -592,22 +589,14 @@ h8300_libsim_a_OBJECTS =3D $(am_h8300_libsim_a_OBJECT=
S) \
 	$(nodist_h8300_libsim_a_OBJECTS)
 igen_libigen_a_AR =3D $(AR) $(ARFLAGS)
 igen_libigen_a_LIBADD =3D
-@SIM_ENABLE_IGEN_TRUE@am_igen_libigen_a_OBJECTS =3D  \
-@SIM_ENABLE_IGEN_TRUE@	igen/table.$(OBJEXT) igen/lf.$(OBJEXT) \
-@SIM_ENABLE_IGEN_TRUE@	igen/misc.$(OBJEXT) \
-@SIM_ENABLE_IGEN_TRUE@	igen/filter_host.$(OBJEXT) \
-@SIM_ENABLE_IGEN_TRUE@	igen/ld-decode.$(OBJEXT) \
-@SIM_ENABLE_IGEN_TRUE@	igen/ld-cache.$(OBJEXT) \
-@SIM_ENABLE_IGEN_TRUE@	igen/filter.$(OBJEXT) \
-@SIM_ENABLE_IGEN_TRUE@	igen/ld-insn.$(OBJEXT) \
-@SIM_ENABLE_IGEN_TRUE@	igen/gen-model.$(OBJEXT) \
-@SIM_ENABLE_IGEN_TRUE@	igen/gen-itable.$(OBJEXT) \
-@SIM_ENABLE_IGEN_TRUE@	igen/gen-icache.$(OBJEXT) \
-@SIM_ENABLE_IGEN_TRUE@	igen/gen-semantics.$(OBJEXT) \
-@SIM_ENABLE_IGEN_TRUE@	igen/gen-idecode.$(OBJEXT) \
-@SIM_ENABLE_IGEN_TRUE@	igen/gen-support.$(OBJEXT) \
-@SIM_ENABLE_IGEN_TRUE@	igen/gen-engine.$(OBJEXT) \
-@SIM_ENABLE_IGEN_TRUE@	igen/gen.$(OBJEXT)
+am_igen_libigen_a_OBJECTS =3D igen/table.$(OBJEXT) igen/lf.$(OBJEXT) \
+	igen/misc.$(OBJEXT) igen/filter_host.$(OBJEXT) \
+	igen/ld-decode.$(OBJEXT) igen/ld-cache.$(OBJEXT) \
+	igen/filter.$(OBJEXT) igen/ld-insn.$(OBJEXT) \
+	igen/gen-model.$(OBJEXT) igen/gen-itable.$(OBJEXT) \
+	igen/gen-icache.$(OBJEXT) igen/gen-semantics.$(OBJEXT) \
+	igen/gen-idecode.$(OBJEXT) igen/gen-support.$(OBJEXT) \
+	igen/gen-engine.$(OBJEXT) igen/gen.$(OBJEXT)
 igen_libigen_a_OBJECTS =3D $(am_igen_libigen_a_OBJECTS)
 iq2000_libsim_a_AR =3D $(AR) $(ARFLAGS)
 @SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_libsim_a_DEPENDENCIES =3D  \
@@ -737,8 +726,8 @@ am__DEPENDENCIES_1 =3D
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__DEPENDENCIES_=
2 =3D $(am__DEPENDENCIES_1) \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@	mips/itable.o \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@	mips/multi-run.o
-@SIM_ENABLE_ARCH_mips_TRUE@am__DEPENDENCIES_3 =3D $(am__append_71) \
-@SIM_ENABLE_ARCH_mips_TRUE@	$(am__append_72) \
+@SIM_ENABLE_ARCH_mips_TRUE@am__DEPENDENCIES_3 =3D $(am__append_68) \
+@SIM_ENABLE_ARCH_mips_TRUE@	$(am__append_69) \
 @SIM_ENABLE_ARCH_mips_TRUE@	$(am__DEPENDENCIES_2)
 @SIM_ENABLE_ARCH_mips_TRUE@mips_libsim_a_DEPENDENCIES =3D mips/interp.o \
 @SIM_ENABLE_ARCH_mips_TRUE@	$(am__DEPENDENCIES_3) $(patsubst \
@@ -894,59 +883,56 @@ v850_libsim_a_AR =3D $(AR) $(ARFLAGS)
 @SIM_ENABLE_ARCH_v850_TRUE@	v850/modules.$(OBJEXT)
 v850_libsim_a_OBJECTS =3D $(am_v850_libsim_a_OBJECTS) \
 	$(nodist_v850_libsim_a_OBJECTS)
-@SIM_ENABLE_IGEN_TRUE@am__EXEEXT_1 =3D $(IGEN) igen/filter$(EXEEXT) \
-@SIM_ENABLE_IGEN_TRUE@	igen/gen$(EXEEXT) igen/ld-cache$(EXEEXT) \
-@SIM_ENABLE_IGEN_TRUE@	igen/ld-decode$(EXEEXT) \
-@SIM_ENABLE_IGEN_TRUE@	igen/ld-insn$(EXEEXT) \
-@SIM_ENABLE_IGEN_TRUE@	igen/table$(EXEEXT)
-@SIM_ENABLE_IGEN_TRUE@am__EXEEXT_2 =3D $(am__EXEEXT_1)
-@SIM_ENABLE_ARCH_cr16_TRUE@am__EXEEXT_3 =3D cr16/gencode$(EXEEXT)
-@SIM_ENABLE_ARCH_d10v_TRUE@am__EXEEXT_4 =3D d10v/gencode$(EXEEXT)
-@SIM_ENABLE_ARCH_m32c_TRUE@am__EXEEXT_5 =3D m32c/opc2c$(EXEEXT)
-@SIM_ENABLE_ARCH_m68hc11_TRUE@am__EXEEXT_6 =3D m68hc11/gencode$(EXEEXT)
-@SIM_ENABLE_ARCH_sh_TRUE@am__EXEEXT_7 =3D sh/gencode$(EXEEXT)
-am__EXEEXT_8 =3D testsuite/common/bits32m0$(EXEEXT) \
+am__EXEEXT_1 =3D $(IGEN) igen/filter$(EXEEXT) igen/gen$(EXEEXT) \
+	igen/ld-cache$(EXEEXT) igen/ld-decode$(EXEEXT) \
+	igen/ld-insn$(EXEEXT) igen/table$(EXEEXT)
+@SIM_ENABLE_ARCH_cr16_TRUE@am__EXEEXT_2 =3D cr16/gencode$(EXEEXT)
+@SIM_ENABLE_ARCH_d10v_TRUE@am__EXEEXT_3 =3D d10v/gencode$(EXEEXT)
+@SIM_ENABLE_ARCH_m32c_TRUE@am__EXEEXT_4 =3D m32c/opc2c$(EXEEXT)
+@SIM_ENABLE_ARCH_m68hc11_TRUE@am__EXEEXT_5 =3D m68hc11/gencode$(EXEEXT)
+@SIM_ENABLE_ARCH_sh_TRUE@am__EXEEXT_6 =3D sh/gencode$(EXEEXT)
+am__EXEEXT_7 =3D testsuite/common/bits32m0$(EXEEXT) \
 	testsuite/common/bits32m31$(EXEEXT) \
 	testsuite/common/bits64m0$(EXEEXT) \
 	testsuite/common/bits64m63$(EXEEXT) \
 	testsuite/common/alu-tst$(EXEEXT)
-@SIM_ENABLE_ARCH_cris_TRUE@am__EXEEXT_9 =3D cris/rvdummy$(EXEEXT)
-@SIM_ENABLE_ARCH_aarch64_TRUE@am__EXEEXT_10 =3D aarch64/run$(EXEEXT)
-@SIM_ENABLE_ARCH_arm_TRUE@am__EXEEXT_11 =3D arm/run$(EXEEXT)
-@SIM_ENABLE_ARCH_avr_TRUE@am__EXEEXT_12 =3D avr/run$(EXEEXT)
-@SIM_ENABLE_ARCH_bfin_TRUE@am__EXEEXT_13 =3D bfin/run$(EXEEXT)
-@SIM_ENABLE_ARCH_bpf_TRUE@am__EXEEXT_14 =3D bpf/run$(EXEEXT)
-@SIM_ENABLE_ARCH_cr16_TRUE@am__EXEEXT_15 =3D cr16/run$(EXEEXT)
-@SIM_ENABLE_ARCH_cris_TRUE@am__EXEEXT_16 =3D cris/run$(EXEEXT)
-@SIM_ENABLE_ARCH_d10v_TRUE@am__EXEEXT_17 =3D d10v/run$(EXEEXT)
-@SIM_ENABLE_ARCH_erc32_TRUE@am__EXEEXT_18 =3D erc32/run$(EXEEXT) \
+@SIM_ENABLE_ARCH_cris_TRUE@am__EXEEXT_8 =3D cris/rvdummy$(EXEEXT)
+@SIM_ENABLE_ARCH_aarch64_TRUE@am__EXEEXT_9 =3D aarch64/run$(EXEEXT)
+@SIM_ENABLE_ARCH_arm_TRUE@am__EXEEXT_10 =3D arm/run$(EXEEXT)
+@SIM_ENABLE_ARCH_avr_TRUE@am__EXEEXT_11 =3D avr/run$(EXEEXT)
+@SIM_ENABLE_ARCH_bfin_TRUE@am__EXEEXT_12 =3D bfin/run$(EXEEXT)
+@SIM_ENABLE_ARCH_bpf_TRUE@am__EXEEXT_13 =3D bpf/run$(EXEEXT)
+@SIM_ENABLE_ARCH_cr16_TRUE@am__EXEEXT_14 =3D cr16/run$(EXEEXT)
+@SIM_ENABLE_ARCH_cris_TRUE@am__EXEEXT_15 =3D cris/run$(EXEEXT)
+@SIM_ENABLE_ARCH_d10v_TRUE@am__EXEEXT_16 =3D d10v/run$(EXEEXT)
+@SIM_ENABLE_ARCH_erc32_TRUE@am__EXEEXT_17 =3D erc32/run$(EXEEXT) \
 @SIM_ENABLE_ARCH_erc32_TRUE@	erc32/sis$(EXEEXT)
-@SIM_ENABLE_ARCH_examples_TRUE@am__EXEEXT_19 =3D  \
+@SIM_ENABLE_ARCH_examples_TRUE@am__EXEEXT_18 =3D  \
 @SIM_ENABLE_ARCH_examples_TRUE@	example-synacor/run$(EXEEXT)
-@SIM_ENABLE_ARCH_frv_TRUE@am__EXEEXT_20 =3D frv/run$(EXEEXT)
-@SIM_ENABLE_ARCH_ft32_TRUE@am__EXEEXT_21 =3D ft32/run$(EXEEXT)
-@SIM_ENABLE_ARCH_h8300_TRUE@am__EXEEXT_22 =3D h8300/run$(EXEEXT)
-@SIM_ENABLE_ARCH_iq2000_TRUE@am__EXEEXT_23 =3D iq2000/run$(EXEEXT)
-@SIM_ENABLE_ARCH_lm32_TRUE@am__EXEEXT_24 =3D lm32/run$(EXEEXT)
-@SIM_ENABLE_ARCH_m32c_TRUE@am__EXEEXT_25 =3D m32c/run$(EXEEXT)
-@SIM_ENABLE_ARCH_m32r_TRUE@am__EXEEXT_26 =3D m32r/run$(EXEEXT)
-@SIM_ENABLE_ARCH_m68hc11_TRUE@am__EXEEXT_27 =3D m68hc11/run$(EXEEXT)
-@SIM_ENABLE_ARCH_mcore_TRUE@am__EXEEXT_28 =3D mcore/run$(EXEEXT)
-@SIM_ENABLE_ARCH_microblaze_TRUE@am__EXEEXT_29 =3D  \
+@SIM_ENABLE_ARCH_frv_TRUE@am__EXEEXT_19 =3D frv/run$(EXEEXT)
+@SIM_ENABLE_ARCH_ft32_TRUE@am__EXEEXT_20 =3D ft32/run$(EXEEXT)
+@SIM_ENABLE_ARCH_h8300_TRUE@am__EXEEXT_21 =3D h8300/run$(EXEEXT)
+@SIM_ENABLE_ARCH_iq2000_TRUE@am__EXEEXT_22 =3D iq2000/run$(EXEEXT)
+@SIM_ENABLE_ARCH_lm32_TRUE@am__EXEEXT_23 =3D lm32/run$(EXEEXT)
+@SIM_ENABLE_ARCH_m32c_TRUE@am__EXEEXT_24 =3D m32c/run$(EXEEXT)
+@SIM_ENABLE_ARCH_m32r_TRUE@am__EXEEXT_25 =3D m32r/run$(EXEEXT)
+@SIM_ENABLE_ARCH_m68hc11_TRUE@am__EXEEXT_26 =3D m68hc11/run$(EXEEXT)
+@SIM_ENABLE_ARCH_mcore_TRUE@am__EXEEXT_27 =3D mcore/run$(EXEEXT)
+@SIM_ENABLE_ARCH_microblaze_TRUE@am__EXEEXT_28 =3D  \
 @SIM_ENABLE_ARCH_microblaze_TRUE@	microblaze/run$(EXEEXT)
-@SIM_ENABLE_ARCH_mips_TRUE@am__EXEEXT_30 =3D mips/run$(EXEEXT)
-@SIM_ENABLE_ARCH_mn10300_TRUE@am__EXEEXT_31 =3D mn10300/run$(EXEEXT)
-@SIM_ENABLE_ARCH_moxie_TRUE@am__EXEEXT_32 =3D moxie/run$(EXEEXT)
-@SIM_ENABLE_ARCH_msp430_TRUE@am__EXEEXT_33 =3D msp430/run$(EXEEXT)
-@SIM_ENABLE_ARCH_or1k_TRUE@am__EXEEXT_34 =3D or1k/run$(EXEEXT)
-@SIM_ENABLE_ARCH_ppc_TRUE@am__EXEEXT_35 =3D ppc/run$(EXEEXT) \
+@SIM_ENABLE_ARCH_mips_TRUE@am__EXEEXT_29 =3D mips/run$(EXEEXT)
+@SIM_ENABLE_ARCH_mn10300_TRUE@am__EXEEXT_30 =3D mn10300/run$(EXEEXT)
+@SIM_ENABLE_ARCH_moxie_TRUE@am__EXEEXT_31 =3D moxie/run$(EXEEXT)
+@SIM_ENABLE_ARCH_msp430_TRUE@am__EXEEXT_32 =3D msp430/run$(EXEEXT)
+@SIM_ENABLE_ARCH_or1k_TRUE@am__EXEEXT_33 =3D or1k/run$(EXEEXT)
+@SIM_ENABLE_ARCH_ppc_TRUE@am__EXEEXT_34 =3D ppc/run$(EXEEXT) \
 @SIM_ENABLE_ARCH_ppc_TRUE@	ppc/psim$(EXEEXT)
-@SIM_ENABLE_ARCH_pru_TRUE@am__EXEEXT_36 =3D pru/run$(EXEEXT)
-@SIM_ENABLE_ARCH_riscv_TRUE@am__EXEEXT_37 =3D riscv/run$(EXEEXT)
-@SIM_ENABLE_ARCH_rl78_TRUE@am__EXEEXT_38 =3D rl78/run$(EXEEXT)
-@SIM_ENABLE_ARCH_rx_TRUE@am__EXEEXT_39 =3D rx/run$(EXEEXT)
-@SIM_ENABLE_ARCH_sh_TRUE@am__EXEEXT_40 =3D sh/run$(EXEEXT)
-@SIM_ENABLE_ARCH_v850_TRUE@am__EXEEXT_41 =3D v850/run$(EXEEXT)
+@SIM_ENABLE_ARCH_pru_TRUE@am__EXEEXT_35 =3D pru/run$(EXEEXT)
+@SIM_ENABLE_ARCH_riscv_TRUE@am__EXEEXT_36 =3D riscv/run$(EXEEXT)
+@SIM_ENABLE_ARCH_rl78_TRUE@am__EXEEXT_37 =3D rl78/run$(EXEEXT)
+@SIM_ENABLE_ARCH_rx_TRUE@am__EXEEXT_38 =3D rx/run$(EXEEXT)
+@SIM_ENABLE_ARCH_sh_TRUE@am__EXEEXT_39 =3D sh/run$(EXEEXT)
+@SIM_ENABLE_ARCH_v850_TRUE@am__EXEEXT_40 =3D v850/run$(EXEEXT)
 PROGRAMS =3D $(noinst_PROGRAMS)
 am_aarch64_run_OBJECTS =3D
 aarch64_run_OBJECTS =3D $(am_aarch64_run_OBJECTS)
@@ -1032,31 +1018,25 @@ h8300_run_OBJECTS =3D $(am_h8300_run_OBJECTS)
 @SIM_ENABLE_ARCH_h8300_TRUE@	$(am__DEPENDENCIES_4)
 am_igen_filter_OBJECTS =3D
 igen_filter_OBJECTS =3D $(am_igen_filter_OBJECTS)
-@SIM_ENABLE_IGEN_TRUE@igen_filter_DEPENDENCIES =3D igen/filter-main.o \
-@SIM_ENABLE_IGEN_TRUE@	igen/libigen.a
+igen_filter_DEPENDENCIES =3D igen/filter-main.o igen/libigen.a
 am_igen_gen_OBJECTS =3D
 igen_gen_OBJECTS =3D $(am_igen_gen_OBJECTS)
-@SIM_ENABLE_IGEN_TRUE@igen_gen_DEPENDENCIES =3D igen/gen-main.o \
-@SIM_ENABLE_IGEN_TRUE@	igen/libigen.a
-@SIM_ENABLE_IGEN_TRUE@am_igen_igen_OBJECTS =3D igen/igen.$(OBJEXT)
+igen_gen_DEPENDENCIES =3D igen/gen-main.o igen/libigen.a
+am_igen_igen_OBJECTS =3D igen/igen.$(OBJEXT)
 igen_igen_OBJECTS =3D $(am_igen_igen_OBJECTS)
-@SIM_ENABLE_IGEN_TRUE@igen_igen_DEPENDENCIES =3D igen/libigen.a
+igen_igen_DEPENDENCIES =3D igen/libigen.a
 am_igen_ld_cache_OBJECTS =3D
 igen_ld_cache_OBJECTS =3D $(am_igen_ld_cache_OBJECTS)
-@SIM_ENABLE_IGEN_TRUE@igen_ld_cache_DEPENDENCIES =3D  \
-@SIM_ENABLE_IGEN_TRUE@	igen/ld-cache-main.o igen/libigen.a
+igen_ld_cache_DEPENDENCIES =3D igen/ld-cache-main.o igen/libigen.a
 am_igen_ld_decode_OBJECTS =3D
 igen_ld_decode_OBJECTS =3D $(am_igen_ld_decode_OBJECTS)
-@SIM_ENABLE_IGEN_TRUE@igen_ld_decode_DEPENDENCIES =3D  \
-@SIM_ENABLE_IGEN_TRUE@	igen/ld-decode-main.o igen/libigen.a
+igen_ld_decode_DEPENDENCIES =3D igen/ld-decode-main.o igen/libigen.a
 am_igen_ld_insn_OBJECTS =3D
 igen_ld_insn_OBJECTS =3D $(am_igen_ld_insn_OBJECTS)
-@SIM_ENABLE_IGEN_TRUE@igen_ld_insn_DEPENDENCIES =3D igen/ld-insn-main.o \
-@SIM_ENABLE_IGEN_TRUE@	igen/libigen.a
+igen_ld_insn_DEPENDENCIES =3D igen/ld-insn-main.o igen/libigen.a
 am_igen_table_OBJECTS =3D
 igen_table_OBJECTS =3D $(am_igen_table_OBJECTS)
-@SIM_ENABLE_IGEN_TRUE@igen_table_DEPENDENCIES =3D igen/table-main.o \
-@SIM_ENABLE_IGEN_TRUE@	igen/libigen.a
+igen_table_DEPENDENCIES =3D igen/table-main.o igen/libigen.a
 am_iq2000_run_OBJECTS =3D
 iq2000_run_OBJECTS =3D $(am_iq2000_run_OBJECTS)
 @SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_run_DEPENDENCIES =3D iq2000/nrun.o \
@@ -1801,38 +1781,39 @@ srccom =3D $(srcdir)/common
 srcroot =3D $(srcdir)/..
 SUBDIRS =3D @subdirs@
 pkginclude_HEADERS =3D $(am__append_1)
-noinst_LIBRARIES =3D common/libcommon.a $(am__append_3) $(am__append_6) \
-	$(am__append_8) $(am__append_10) $(am__append_12) \
-	$(am__append_14) $(am__append_18) $(am__append_23) \
-	$(am__append_28) $(am__append_33) $(am__append_37) \
-	$(am__append_39) $(am__append_43) $(am__append_45) \
-	$(am__append_47) $(am__append_51) $(am__append_55) \
-	$(am__append_59) $(am__append_63) $(am__append_67) \
-	$(am__append_69) $(am__append_74) $(am__append_82) \
-	$(am__append_86) $(am__append_88) $(am__append_90) \
-	$(am__append_96) $(am__append_98) $(am__append_100) \
-	$(am__append_102) $(am__append_104) $(am__append_109)
-BUILT_SOURCES =3D $(am__append_16) $(am__append_20) $(am__append_26) \
-	$(am__append_30) $(am__append_41) $(am__append_49) \
-	$(am__append_53) $(am__append_61) $(am__append_76) \
-	$(am__append_84) $(am__append_92) $(am__append_106) \
-	$(am__append_111)
+EXTRA_LIBRARIES =3D igen/libigen.a
+noinst_LIBRARIES =3D common/libcommon.a $(am__append_3) $(am__append_5) \
+	$(am__append_7) $(am__append_9) $(am__append_11) \
+	$(am__append_15) $(am__append_20) $(am__append_25) \
+	$(am__append_30) $(am__append_34) $(am__append_36) \
+	$(am__append_40) $(am__append_42) $(am__append_44) \
+	$(am__append_48) $(am__append_52) $(am__append_56) \
+	$(am__append_60) $(am__append_64) $(am__append_66) \
+	$(am__append_71) $(am__append_79) $(am__append_83) \
+	$(am__append_85) $(am__append_87) $(am__append_93) \
+	$(am__append_95) $(am__append_97) $(am__append_99) \
+	$(am__append_101) $(am__append_106)
+BUILT_SOURCES =3D $(am__append_13) $(am__append_17) $(am__append_23) \
+	$(am__append_27) $(am__append_38) $(am__append_46) \
+	$(am__append_50) $(am__append_58) $(am__append_73) \
+	$(am__append_81) $(am__append_89) $(am__append_103) \
+	$(am__append_108)
 CLEANFILES =3D common/version.c common/version.c-stamp \
 	testsuite/common/bits-gen testsuite/common/bits32m0.c \
 	testsuite/common/bits32m31.c testsuite/common/bits64m0.c \
 	testsuite/common/bits64m63.c
-DISTCLEANFILES =3D $(am__append_81)
+DISTCLEANFILES =3D $(am__append_78)
 MOSTLYCLEANFILES =3D core $(SIM_ENABLED_ARCHES:%=3D%/*.o) \
 	$(SIM_ENABLED_ARCHES:%=3D%/hw-config.h) \
 	$(SIM_ENABLED_ARCHES:%=3D%/stamp-hw) \
 	$(SIM_ENABLED_ARCHES:%=3D%/modules.c) \
-	$(SIM_ENABLED_ARCHES:%=3D%/stamp-modules) $(am__append_5) \
-	site-sim-config.exp testrun.log testrun.sum $(am__append_17) \
-	$(am__append_22) $(am__append_27) $(am__append_32) \
-	$(am__append_42) $(am__append_50) $(am__append_54) \
-	$(am__append_58) $(am__append_62) $(am__append_66) \
-	$(am__append_80) $(am__append_85) $(am__append_93) \
-	$(am__append_108) $(am__append_112)
+	$(SIM_ENABLED_ARCHES:%=3D%/stamp-modules) $(igen_IGEN_TOOLS) \
+	site-sim-config.exp testrun.log testrun.sum $(am__append_14) \
+	$(am__append_19) $(am__append_24) $(am__append_29) \
+	$(am__append_39) $(am__append_47) $(am__append_51) \
+	$(am__append_55) $(am__append_59) $(am__append_63) \
+	$(am__append_77) $(am__append_82) $(am__append_90) \
+	$(am__append_105) $(am__append_109)
 AM_CFLAGS =3D \
 	$(WERROR_CFLAGS) \
 	$(WARN_CFLAGS) \
@@ -1847,10 +1828,10 @@ AM_CPPFLAGS_FOR_BUILD =3D -I$(srcroot)/include $(SI=
M_HW_CFLAGS) \
 	$(SIM_INLINE) -I$(srcdir)/common
 COMPILE_FOR_BUILD =3D $(CC_FOR_BUILD) $(AM_CPPFLAGS_FOR_BUILD) $(CPPFLAGS_=
FOR_BUILD) $(CFLAGS_FOR_BUILD)
 LINK_FOR_BUILD =3D $(CC_FOR_BUILD) $(CFLAGS_FOR_BUILD) $(LDFLAGS_FOR_BUILD=
) -o $@
-SIM_ALL_RECURSIVE_DEPS =3D $(am__append_94)
+SIM_ALL_RECURSIVE_DEPS =3D $(am__append_91)
 SIM_INSTALL_DATA_LOCAL_DEPS =3D=20
-SIM_INSTALL_EXEC_LOCAL_DEPS =3D $(am__append_35)
-SIM_UNINSTALL_LOCAL_DEPS =3D $(am__append_36)
+SIM_INSTALL_EXEC_LOCAL_DEPS =3D $(am__append_32)
+SIM_UNINSTALL_LOCAL_DEPS =3D $(am__append_33)
 SIM_DEPBASE =3D $(@D)/$(DEPDIR)/$(@F:.o=3D)
 SIM_COMPILE =3D \
 	$(AM_V_CC)$(COMPILE) -MT $@ -MD -MP -MF $(SIM_DEPBASE).Tpo -c -o $@ $< &&=
 \
@@ -1961,48 +1942,48 @@ CGEN_GEN_CPU_DESC =3D \
=20
 # igen leaks memory, and therefore makes AddressSanitizer unhappy.  Disable
 # leak detection while running it.
-@SIM_ENABLE_IGEN_TRUE@IGEN =3D igen/igen$(EXEEXT)
-@SIM_ENABLE_IGEN_TRUE@IGEN_RUN =3D ASAN_OPTIONS=3Ddetect_leaks=3D0 $(IGEN)=
 $(IGEN_FLAGS_SMP)
-@SIM_ENABLE_IGEN_TRUE@igen_libigen_a_SOURCES =3D \
-@SIM_ENABLE_IGEN_TRUE@	igen/table.c \
-@SIM_ENABLE_IGEN_TRUE@	igen/lf.c \
-@SIM_ENABLE_IGEN_TRUE@	igen/misc.c \
-@SIM_ENABLE_IGEN_TRUE@	igen/filter_host.c \
-@SIM_ENABLE_IGEN_TRUE@	igen/ld-decode.c \
-@SIM_ENABLE_IGEN_TRUE@	igen/ld-cache.c \
-@SIM_ENABLE_IGEN_TRUE@	igen/filter.c \
-@SIM_ENABLE_IGEN_TRUE@	igen/ld-insn.c \
-@SIM_ENABLE_IGEN_TRUE@	igen/gen-model.c \
-@SIM_ENABLE_IGEN_TRUE@	igen/gen-itable.c \
-@SIM_ENABLE_IGEN_TRUE@	igen/gen-icache.c \
-@SIM_ENABLE_IGEN_TRUE@	igen/gen-semantics.c \
-@SIM_ENABLE_IGEN_TRUE@	igen/gen-idecode.c \
-@SIM_ENABLE_IGEN_TRUE@	igen/gen-support.c \
-@SIM_ENABLE_IGEN_TRUE@	igen/gen-engine.c \
-@SIM_ENABLE_IGEN_TRUE@	igen/gen.c
-
-@SIM_ENABLE_IGEN_TRUE@igen_igen_SOURCES =3D igen/igen.c
-@SIM_ENABLE_IGEN_TRUE@igen_igen_LDADD =3D igen/libigen.a
-@SIM_ENABLE_IGEN_TRUE@igen_filter_SOURCES =3D=20
-@SIM_ENABLE_IGEN_TRUE@igen_filter_LDADD =3D igen/filter-main.o igen/libige=
n.a
-@SIM_ENABLE_IGEN_TRUE@igen_gen_SOURCES =3D=20
-@SIM_ENABLE_IGEN_TRUE@igen_gen_LDADD =3D igen/gen-main.o igen/libigen.a
-@SIM_ENABLE_IGEN_TRUE@igen_ld_cache_SOURCES =3D=20
-@SIM_ENABLE_IGEN_TRUE@igen_ld_cache_LDADD =3D igen/ld-cache-main.o igen/li=
bigen.a
-@SIM_ENABLE_IGEN_TRUE@igen_ld_decode_SOURCES =3D=20
-@SIM_ENABLE_IGEN_TRUE@igen_ld_decode_LDADD =3D igen/ld-decode-main.o igen/=
libigen.a
-@SIM_ENABLE_IGEN_TRUE@igen_ld_insn_SOURCES =3D=20
-@SIM_ENABLE_IGEN_TRUE@igen_ld_insn_LDADD =3D igen/ld-insn-main.o igen/libi=
gen.a
-@SIM_ENABLE_IGEN_TRUE@igen_table_SOURCES =3D=20
-@SIM_ENABLE_IGEN_TRUE@igen_table_LDADD =3D igen/table-main.o igen/libigen.a
-@SIM_ENABLE_IGEN_TRUE@igen_IGEN_TOOLS =3D \
-@SIM_ENABLE_IGEN_TRUE@	$(IGEN) \
-@SIM_ENABLE_IGEN_TRUE@	igen/filter \
-@SIM_ENABLE_IGEN_TRUE@	igen/gen \
-@SIM_ENABLE_IGEN_TRUE@	igen/ld-cache \
-@SIM_ENABLE_IGEN_TRUE@	igen/ld-decode \
-@SIM_ENABLE_IGEN_TRUE@	igen/ld-insn \
-@SIM_ENABLE_IGEN_TRUE@	igen/table
+IGEN =3D igen/igen$(EXEEXT)
+IGEN_RUN =3D ASAN_OPTIONS=3Ddetect_leaks=3D0 $(IGEN) $(IGEN_FLAGS_SMP)
+igen_libigen_a_SOURCES =3D \
+	igen/table.c \
+	igen/lf.c \
+	igen/misc.c \
+	igen/filter_host.c \
+	igen/ld-decode.c \
+	igen/ld-cache.c \
+	igen/filter.c \
+	igen/ld-insn.c \
+	igen/gen-model.c \
+	igen/gen-itable.c \
+	igen/gen-icache.c \
+	igen/gen-semantics.c \
+	igen/gen-idecode.c \
+	igen/gen-support.c \
+	igen/gen-engine.c \
+	igen/gen.c
+
+igen_igen_SOURCES =3D igen/igen.c
+igen_igen_LDADD =3D igen/libigen.a
+igen_filter_SOURCES =3D=20
+igen_filter_LDADD =3D igen/filter-main.o igen/libigen.a
+igen_gen_SOURCES =3D=20
+igen_gen_LDADD =3D igen/gen-main.o igen/libigen.a
+igen_ld_cache_SOURCES =3D=20
+igen_ld_cache_LDADD =3D igen/ld-cache-main.o igen/libigen.a
+igen_ld_decode_SOURCES =3D=20
+igen_ld_decode_LDADD =3D igen/ld-decode-main.o igen/libigen.a
+igen_ld_insn_SOURCES =3D=20
+igen_ld_insn_LDADD =3D igen/ld-insn-main.o igen/libigen.a
+igen_table_SOURCES =3D=20
+igen_table_LDADD =3D igen/table-main.o igen/libigen.a
+igen_IGEN_TOOLS =3D \
+	$(IGEN) \
+	igen/filter \
+	igen/gen \
+	igen/ld-cache \
+	igen/ld-decode \
+	igen/ld-insn \
+	igen/table
=20
 EXTRA_DEJAGNU_SITE_CONFIG =3D site-sim-config.exp
=20
@@ -2680,8 +2661,8 @@ testsuite_common_CPPFLAGS =3D \
 @SIM_ENABLE_ARCH_mips_TRUE@	-DWITH_TARGET_WORD_BITSIZE=3D@SIM_MIPS_BITSIZE=
@ -DWITH_TARGET_WORD_MSB=3DWITH_TARGET_WORD_BITSIZE-1 \
 @SIM_ENABLE_ARCH_mips_TRUE@	-DWITH_FLOATING_POINT=3DHARD_FLOATING_POINT -D=
WITH_TARGET_FLOATING_POINT_BITSIZE=3D@SIM_MIPS_FPU_BITSIZE@
=20
-@SIM_ENABLE_ARCH_mips_TRUE@mips_GEN_OBJ =3D $(am__append_71) \
-@SIM_ENABLE_ARCH_mips_TRUE@	$(am__append_72) $(am__append_73)
+@SIM_ENABLE_ARCH_mips_TRUE@mips_GEN_OBJ =3D $(am__append_68) \
+@SIM_ENABLE_ARCH_mips_TRUE@	$(am__append_69) $(am__append_70)
 @SIM_ENABLE_ARCH_mips_TRUE@nodist_mips_libsim_a_SOURCES =3D \
 @SIM_ENABLE_ARCH_mips_TRUE@	mips/modules.c
=20
@@ -2753,8 +2734,8 @@ testsuite_common_CPPFLAGS =3D \
 @SIM_ENABLE_ARCH_mips_TRUE@mips_BUILD_OUTPUTS =3D  \
 @SIM_ENABLE_ARCH_mips_TRUE@	$(mips_BUILT_SRC_FROM_IGEN_ITABLE) \
 @SIM_ENABLE_ARCH_mips_TRUE@	mips/stamp-igen-itable \
-@SIM_ENABLE_ARCH_mips_TRUE@	$(am__append_77) $(am__append_78) \
-@SIM_ENABLE_ARCH_mips_TRUE@	$(am__append_79)
+@SIM_ENABLE_ARCH_mips_TRUE@	$(am__append_74) $(am__append_75) \
+@SIM_ENABLE_ARCH_mips_TRUE@	$(am__append_76)
 @SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_TRACE =3D # -G omit-line-numbers # -G=
 trace-rule-selection -G trace-rule-rejection -G trace-entries # -G trace-a=
ll
 @SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN =3D $(srcdir)/mips/mips.igen
 @SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN_INC =3D \
@@ -3441,11 +3422,6 @@ igen/gen-engine.$(OBJEXT): igen/$(am__dirstamp) \
 	igen/$(DEPDIR)/$(am__dirstamp)
 igen/gen.$(OBJEXT): igen/$(am__dirstamp) \
 	igen/$(DEPDIR)/$(am__dirstamp)
-
-@SIM_ENABLE_IGEN_FALSE@igen/libigen.a: $(igen_libigen_a_OBJECTS) $(igen_li=
bigen_a_DEPENDENCIES) $(EXTRA_igen_libigen_a_DEPENDENCIES) igen/$(am__dirst=
amp)
-@SIM_ENABLE_IGEN_FALSE@	$(AM_V_at)-rm -f igen/libigen.a
-@SIM_ENABLE_IGEN_FALSE@	$(AM_V_AR)$(igen_libigen_a_AR) igen/libigen.a $(ig=
en_libigen_a_OBJECTS) $(igen_libigen_a_LIBADD)
-@SIM_ENABLE_IGEN_FALSE@	$(AM_V_at)$(RANLIB) igen/libigen.a
 iq2000/$(am__dirstamp):
 	@$(MKDIR_P) iq2000
 	@: > iq2000/$(am__dirstamp)
@@ -3783,10 +3759,6 @@ igen/gen$(EXEEXT): $(igen_gen_OBJECTS) $(igen_gen_DE=
PENDENCIES) $(EXTRA_igen_gen
 igen/igen.$(OBJEXT): igen/$(am__dirstamp) \
 	igen/$(DEPDIR)/$(am__dirstamp)
=20
-@SIM_ENABLE_IGEN_FALSE@igen/igen$(EXEEXT): $(igen_igen_OBJECTS) $(igen_ige=
n_DEPENDENCIES) $(EXTRA_igen_igen_DEPENDENCIES) igen/$(am__dirstamp)
-@SIM_ENABLE_IGEN_FALSE@	@rm -f igen/igen$(EXEEXT)
-@SIM_ENABLE_IGEN_FALSE@	$(AM_V_CCLD)$(LINK) $(igen_igen_OBJECTS) $(igen_ig=
en_LDADD) $(LIBS)
-
 igen/ld-cache$(EXEEXT): $(igen_ld_cache_OBJECTS) $(igen_ld_cache_DEPENDENC=
IES) $(EXTRA_igen_ld_cache_DEPENDENCIES) igen/$(am__dirstamp)
 	@rm -f igen/ld-cache$(EXEEXT)
 	$(AM_V_CCLD)$(LINK) $(igen_ld_cache_OBJECTS) $(igen_ld_cache_LDADD) $(LIB=
S)
@@ -4894,24 +4866,24 @@ common/version.c-stamp: $(srcroot)/gdb/version.in $=
(srcroot)/bfd/version.h $(src
 .PRECIOUS: %/stamp-modules
=20
 # Alias for developers.
-@SIM_ENABLE_IGEN_TRUE@igen: $(IGEN)
+igen: $(IGEN)
=20
 # These rules are copied from automake, but tweaked to use FOR_BUILD varia=
bles.
-@SIM_ENABLE_IGEN_TRUE@igen/libigen.a: $(igen_libigen_a_OBJECTS) $(igen_lib=
igen_a_DEPENDENCIES) $(EXTRA_igen_libigen_a_DEPENDENCIES) igen/$(am__dirsta=
mp)
-@SIM_ENABLE_IGEN_TRUE@	$(AM_V_at)-rm -f $@
-@SIM_ENABLE_IGEN_TRUE@	$(AM_V_AR)$(AR_FOR_BUILD) $(ARFLAGS) $@ $(igen_libi=
gen_a_OBJECTS) $(igen_libigen_a_LIBADD)
-@SIM_ENABLE_IGEN_TRUE@	$(AM_V_at)$(RANLIB_FOR_BUILD) $@
+igen/libigen.a: $(igen_libigen_a_OBJECTS) $(igen_libigen_a_DEPENDENCIES) $=
(EXTRA_igen_libigen_a_DEPENDENCIES) igen/$(am__dirstamp)
+	$(AM_V_at)-rm -f $@
+	$(AM_V_AR)$(AR_FOR_BUILD) $(ARFLAGS) $@ $(igen_libigen_a_OBJECTS) $(igen_=
libigen_a_LIBADD)
+	$(AM_V_at)$(RANLIB_FOR_BUILD) $@
=20
-@SIM_ENABLE_IGEN_TRUE@igen/igen$(EXEEXT): $(igen_igen_OBJECTS) $(igen_igen=
_DEPENDENCIES) igen/$(am__dirstamp)
-@SIM_ENABLE_IGEN_TRUE@	$(AM_V_CCLD)$(LINK_FOR_BUILD) $(igen_igen_OBJECTS) =
$(igen_igen_LDADD)
+igen/igen$(EXEEXT): $(igen_igen_OBJECTS) $(igen_igen_DEPENDENCIES) igen/$(=
am__dirstamp)
+	$(AM_V_CCLD)$(LINK_FOR_BUILD) $(igen_igen_OBJECTS) $(igen_igen_LDADD)
=20
 # igen is a build-time only tool.  Override the default rules for it.
-@SIM_ENABLE_IGEN_TRUE@igen/%.o: igen/%.c
-@SIM_ENABLE_IGEN_TRUE@	$(AM_V_CC)$(COMPILE_FOR_BUILD) -c $< -o $@
+igen/%.o: igen/%.c
+	$(AM_V_CC)$(COMPILE_FOR_BUILD) -c $< -o $@
=20
 # Build some of the files in standalone mode for developers of igen itself.
-@SIM_ENABLE_IGEN_TRUE@igen/%-main.o: igen/%.c
-@SIM_ENABLE_IGEN_TRUE@	$(AM_V_CC)$(COMPILE_FOR_BUILD) -DMAIN -c $< -o $@
+igen/%-main.o: igen/%.c
+	$(AM_V_CC)$(COMPILE_FOR_BUILD) -DMAIN -c $< -o $@
=20
 site-sim-config.exp: Makefile
 	$(AM_V_GEN)( \
diff --git a/sim/configure b/sim/configure
index 3867d1ed5c4..70f7c23acdb 100755
--- a/sim/configure
+++ b/sim/configure
@@ -668,8 +668,6 @@ cgendir
 CGEN_MAINT
 ENABLE_SIM_FALSE
 ENABLE_SIM_TRUE
-SIM_ENABLE_IGEN_FALSE
-SIM_ENABLE_IGEN_TRUE
 SIM_ENABLE_ARCH_examples_FALSE
 SIM_ENABLE_ARCH_examples_TRUE
 CC_FOR_TARGET_EXAMPLE_SYNACOR
@@ -12444,7 +12442,7 @@ else
   lt_dlunknown=3D0; lt_dlno_uscore=3D1; lt_dlneed_uscore=3D2
   lt_status=3D$lt_dlunknown
   cat > conftest.$ac_ext <<_LT_EOF
-#line 12447 "configure"
+#line 12445 "configure"
 #include "confdefs.h"
=20
 #if HAVE_DLFCN_H
@@ -12550,7 +12548,7 @@ else
   lt_dlunknown=3D0; lt_dlno_uscore=3D1; lt_dlneed_uscore=3D2
   lt_status=3D$lt_dlunknown
   cat > conftest.$ac_ext <<_LT_EOF
-#line 12553 "configure"
+#line 12551 "configure"
 #include "confdefs.h"
=20
 #if HAVE_DLFCN_H
@@ -14269,7 +14267,6 @@ ENABLE_SIM=3Dno
=20
=20
 if test "${enable_sim}" !=3D no; then
-  sim_igen=3Dno
   for targ in `echo $target $enable_targets | sed 's/,/ /g'`
   do
       sim_enable_arch_aarch64=3Dfalse
@@ -14285,7 +14282,6 @@ if test "${enable_sim}" !=3D no; then
=20
=20
       sim_enable_arch_aarch64=3Dtrue
-
       ;;
   esac
   { $as_echo "$as_me:${as_lineno-$LINENO}: checking where to find the targ=
et cc" >&5
@@ -14450,7 +14446,6 @@ fi
=20
=20
       sim_enable_arch_arm=3Dtrue
-
       ;;
   esac
=20
@@ -14488,7 +14483,6 @@ fi
=20
=20
       sim_enable_arch_avr=3Dtrue
-
       ;;
   esac
=20
@@ -14526,7 +14520,6 @@ fi
=20
=20
       sim_enable_arch_bfin=3Dtrue
-
       ;;
   esac
=20
@@ -14564,7 +14557,6 @@ fi
=20
=20
       sim_enable_arch_bpf=3Dtrue
-
       ;;
   esac
=20
@@ -14602,7 +14594,6 @@ fi
=20
=20
       sim_enable_arch_cr16=3Dtrue
-
       ;;
   esac
=20
@@ -14640,7 +14631,6 @@ fi
=20
=20
       sim_enable_arch_cris=3Dtrue
-
       ;;
   esac
=20
@@ -14678,7 +14668,6 @@ fi
=20
=20
       sim_enable_arch_d10v=3Dtrue
-
       ;;
   esac
=20
@@ -14716,7 +14705,6 @@ fi
=20
=20
       sim_enable_arch_frv=3Dtrue
-
       ;;
   esac
=20
@@ -14754,7 +14742,6 @@ fi
=20
=20
       sim_enable_arch_ft32=3Dtrue
-
       ;;
   esac
=20
@@ -14792,7 +14779,6 @@ fi
=20
=20
       sim_enable_arch_h8300=3Dtrue
-
       ;;
   esac
=20
@@ -14830,7 +14816,6 @@ fi
=20
=20
       sim_enable_arch_iq2000=3Dtrue
-
       ;;
   esac
=20
@@ -14868,7 +14853,6 @@ fi
=20
=20
       sim_enable_arch_lm32=3Dtrue
-
       ;;
   esac
=20
@@ -14906,7 +14890,6 @@ fi
=20
=20
       sim_enable_arch_m32c=3Dtrue
-
       ;;
   esac
=20
@@ -14944,7 +14927,6 @@ fi
=20
=20
       sim_enable_arch_m32r=3Dtrue
-
       ;;
   esac
=20
@@ -14982,7 +14964,6 @@ fi
=20
=20
       sim_enable_arch_m68hc11=3Dtrue
-
       ;;
   esac
=20
@@ -15020,7 +15001,6 @@ fi
=20
=20
       sim_enable_arch_mcore=3Dtrue
-
       ;;
   esac
=20
@@ -15058,7 +15038,6 @@ fi
=20
=20
       sim_enable_arch_microblaze=3Dtrue
-
       ;;
   esac
=20
@@ -15096,7 +15075,6 @@ fi
=20
=20
       sim_enable_arch_mips=3Dtrue
-      sim_igen=3Dyes
       ;;
   esac
=20
@@ -15134,7 +15112,6 @@ fi
=20
=20
       sim_enable_arch_mn10300=3Dtrue
-      sim_igen=3Dyes
       ;;
   esac
=20
@@ -15172,7 +15149,6 @@ fi
=20
=20
       sim_enable_arch_moxie=3Dtrue
-
       ;;
   esac
=20
@@ -15210,7 +15186,6 @@ fi
=20
=20
       sim_enable_arch_msp430=3Dtrue
-
       ;;
   esac
=20
@@ -15248,7 +15223,6 @@ fi
=20
=20
       sim_enable_arch_or1k=3Dtrue
-
       ;;
   esac
=20
@@ -15290,7 +15264,6 @@ subdirs=3D"$subdirs ppc"
=20
=20
       sim_enable_arch_ppc=3Dtrue
-
       ;;
   esac
=20
@@ -15328,7 +15301,6 @@ fi
=20
=20
       sim_enable_arch_pru=3Dtrue
-
       ;;
   esac
=20
@@ -15366,7 +15338,6 @@ fi
=20
=20
       sim_enable_arch_riscv=3Dtrue
-
       ;;
   esac
=20
@@ -15404,7 +15375,6 @@ fi
=20
=20
       sim_enable_arch_rl78=3Dtrue
-
       ;;
   esac
=20
@@ -15442,7 +15412,6 @@ fi
=20
=20
       sim_enable_arch_rx=3Dtrue
-
       ;;
   esac
=20
@@ -15480,7 +15449,6 @@ fi
=20
=20
       sim_enable_arch_sh=3Dtrue
-
       ;;
   esac
=20
@@ -15518,7 +15486,6 @@ fi
=20
=20
       sim_enable_arch_erc32=3Dtrue
-
       ;;
   esac
=20
@@ -15556,7 +15523,6 @@ fi
=20
=20
       sim_enable_arch_v850=3Dtrue
-      sim_igen=3Dyes
       ;;
   esac
=20
@@ -15610,14 +15576,6 @@ else
 fi
=20
 fi
- if test "$sim_igen" =3D "yes"; then
-  SIM_ENABLE_IGEN_TRUE=3D
-  SIM_ENABLE_IGEN_FALSE=3D'#'
-else
-  SIM_ENABLE_IGEN_TRUE=3D'#'
-  SIM_ENABLE_IGEN_FALSE=3D
-fi
-
  if test "$ENABLE_SIM" =3D "yes"; then
   ENABLE_SIM_TRUE=3D
   ENABLE_SIM_FALSE=3D'#'
@@ -16744,10 +16702,6 @@ if test -z "${SIM_ENABLE_ARCH_examples_TRUE}" && t=
est -z "${SIM_ENABLE_ARCH_exam
   as_fn_error $? "conditional \"SIM_ENABLE_ARCH_examples\" was never defin=
ed.
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
-if test -z "${SIM_ENABLE_IGEN_TRUE}" && test -z "${SIM_ENABLE_IGEN_FALSE}"=
; then
-  as_fn_error $? "conditional \"SIM_ENABLE_IGEN\" was never defined.
-Usually this means the macro was only invoked conditionally." "$LINENO" 5
-fi
 if test -z "${ENABLE_SIM_TRUE}" && test -z "${ENABLE_SIM_FALSE}"; then
   as_fn_error $? "conditional \"ENABLE_SIM\" was never defined.
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
diff --git a/sim/configure.ac b/sim/configure.ac
index b4ea1e7de9b..ecda34a6b3f 100644
--- a/sim/configure.ac
+++ b/sim/configure.ac
@@ -68,7 +68,6 @@ dnl Enable a particular arch subdir.
 dnl arg[1] is the matching target triple.
 dnl arg[2] is the arch subdir name.
 dnl arg[3] is whether the arch has a dedicated configure script.
-dnl arg[4] is any additional shell code to run for this arch.
 m4_define([SIM_TARGET], [dnl
   sim_enable_arch_$2=3Dfalse
   case "${targ}" in
@@ -78,7 +77,6 @@ m4_define([SIM_TARGET], [dnl
       fi
       SIM_BUILD_TARGET($2, $3)
       sim_enable_arch_$2=3Dtrue
-      $4
       ;;
   esac
   SIM_AC_TOOLCHAIN_FOR_TARGET($2)
@@ -93,7 +91,6 @@ dnl
 dnl NB: Target matching is aligned with gdb/configure.tgt.  Changes must b=
e kept
 dnl in sync with that file.
 if test "${enable_sim}" !=3D no; then
-  sim_igen=3Dno
   for targ in `echo $target $enable_targets | sed 's/,/ /g'`
   do
     SIM_TARGET([aarch64*-*-*], [aarch64])
@@ -114,8 +111,8 @@ if test "${enable_sim}" !=3D no; then
     SIM_TARGET([m68hc11-*-*|m6811-*-*], [m68hc11])
     SIM_TARGET([mcore-*-*], [mcore])
     SIM_TARGET([microblaze*-*-*], [microblaze])
-    SIM_TARGET([mips*-*-*], [mips], [], [sim_igen=3Dyes])
-    SIM_TARGET([mn10300*-*-*], [mn10300], [], [sim_igen=3Dyes])
+    SIM_TARGET([mips*-*-*], [mips])
+    SIM_TARGET([mn10300*-*-*], [mn10300])
     SIM_TARGET([moxie-*-*], [moxie])
     SIM_TARGET([msp430*-*-*], [msp430])
     SIM_TARGET([or1k*-*-*], [or1k])
@@ -126,7 +123,7 @@ if test "${enable_sim}" !=3D no; then
     SIM_TARGET([rx-*-*], [rx])
     SIM_TARGET([sh*-*-*], [sh])
     SIM_TARGET([sparc-*-*], [erc32])
-    SIM_TARGET([v850*-*-*], [v850], [], [sim_igen=3Dyes])
+    SIM_TARGET([v850*-*-*], [v850])
   done
=20
   if test "x${enable_example_sims}" =3D xyes; then
@@ -135,7 +132,6 @@ if test "${enable_sim}" !=3D no; then
   fi
   AM_CONDITIONAL([SIM_ENABLE_ARCH_examples], [test "${enable_example_sims}=
" =3D "yes"])
 fi
-AM_CONDITIONAL([SIM_ENABLE_IGEN], [test "$sim_igen" =3D "yes"])
 AM_CONDITIONAL([ENABLE_SIM], [test "$ENABLE_SIM" =3D "yes"])
=20
 dnl Standard (and optional) simulator options.
diff --git a/sim/igen/local.mk b/sim/igen/local.mk
index 0126a2cdb7e..75b9cebd8f7 100644
--- a/sim/igen/local.mk
+++ b/sim/igen/local.mk
@@ -27,7 +27,7 @@ IGEN_RUN =3D ASAN_OPTIONS=3Ddetect_leaks=3D0 $(IGEN) $(IG=
EN_FLAGS_SMP)
 # Alias for developers.
 igen: $(IGEN)
=20
-noinst_LIBRARIES +=3D %D%/libigen.a
+EXTRA_LIBRARIES +=3D %D%/libigen.a
 %C%_libigen_a_SOURCES =3D \
 	%D%/table.c \
 	%D%/lf.c \