From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1521) id 45C093858D38; Mon, 16 Jan 2023 01:56:41 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 45C093858D38 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1673834201; bh=pd7BpHTGDYNPzf4h/v2pVnrBH2Qp3rtj3R/sBqLi0Uk=; h=From:To:Subject:Date:From; b=ESF+cwJLriSh5NUDjVE8FLPYKJzl0iiQb5OjadmsmNmtu8JsAtgF0Pvjrc8jXJgZi u5Jsh2ivzUcqqKyHaxRqn/gB8Y42ZlMWoMiCVAp+4bueXu0XFGYs3cfG+d6Ff9HGOa Ijci+4fiSj96cAx7H0pc1Jg9cMym8Txcxhof7ojI= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Michael Frysinger To: gdb-cvs@sourceware.org Subject: [binutils-gdb] sim: modules.c: fix generation after recent refactors X-Act-Checkin: binutils-gdb X-Git-Author: Mike Frysinger X-Git-Refname: refs/heads/master X-Git-Oldrev: 8cf531c3dbf593dd3159950dc3fa1bba2c00ac5e X-Git-Newrev: 109a0a7e902f23e7167f89abbc0d8fa0ccca6594 Message-Id: <20230116015641.45C093858D38@sourceware.org> Date: Mon, 16 Jan 2023 01:56:41 +0000 (GMT) List-Id: https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D109a0a7e902f= 23e7167f89abbc0d8fa0ccca6594 commit 109a0a7e902f23e7167f89abbc0d8fa0ccca6594 Author: Mike Frysinger Date: Sun Jan 15 20:48:28 2023 -0500 sim: modules.c: fix generation after recent refactors =20 Add explicit arch-specific modules.c rules to keep the build from generating an incorrect common/modules.c. Otherwise the pattern rules would cascade such that it'd look for $arch/modules.o which turned into common/modules.c which triggered the gen rule. =20 My local testing of this code didn't catch this bug because of how Automake manages .Po (dependency files) in incremental builds -- it was adding extra rules that override the pattern rules which caused the build to generate correct modules.c files. But when building from a cold cache, the pattern rules would force common/modules.c to be used leading to crashes at runtime. Diff: --- sim/Makefile.in | 62 ++++++++++++++++++++++++++++++++++++++++= ++++ sim/aarch64/local.mk | 3 +++ sim/arm/local.mk | 3 +++ sim/avr/local.mk | 3 +++ sim/bfin/local.mk | 3 +++ sim/bpf/local.mk | 3 +++ sim/cr16/local.mk | 3 +++ sim/cris/local.mk | 3 +++ sim/d10v/local.mk | 3 +++ sim/erc32/local.mk | 3 +++ sim/example-synacor/local.mk | 3 +++ sim/frv/local.mk | 3 +++ sim/ft32/local.mk | 3 +++ sim/h8300/local.mk | 3 +++ sim/iq2000/local.mk | 3 +++ sim/lm32/local.mk | 3 +++ sim/m32c/local.mk | 3 +++ sim/m32r/local.mk | 3 +++ sim/m68hc11/local.mk | 3 +++ sim/mcore/local.mk | 3 +++ sim/microblaze/local.mk | 3 +++ sim/mips/local.mk | 3 +++ sim/mn10300/local.mk | 3 +++ sim/moxie/local.mk | 3 +++ sim/msp430/local.mk | 3 +++ sim/or1k/local.mk | 3 +++ sim/pru/local.mk | 3 +++ sim/riscv/local.mk | 3 +++ sim/rl78/local.mk | 3 +++ sim/rx/local.mk | 3 +++ sim/sh/local.mk | 3 +++ sim/v850/local.mk | 3 +++ 32 files changed, 155 insertions(+) diff --git a/sim/Makefile.in b/sim/Makefile.in index 57abd19b7c8..150c8a3bc69 100644 --- a/sim/Makefile.in +++ b/sim/Makefile.in @@ -4980,18 +4980,26 @@ testsuite/common/bits64m63.c: testsuite/common/bits= -gen$(EXEEXT) testsuite/commo $(AM_V_at)mv $@.tmp $@ @SIM_ENABLE_ARCH_aarch64_TRUE@$(aarch64_libsim_a_OBJECTS) $(aarch64_libsim= _a_LIBADD): aarch64/hw-config.h =20 +@SIM_ENABLE_ARCH_aarch64_TRUE@aarch64/modules.o: aarch64/modules.c + @SIM_ENABLE_ARCH_aarch64_TRUE@aarch64/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_aarch64_TRUE@-@am__include@ aarch64/$(DEPDIR)/*.Po @SIM_ENABLE_ARCH_arm_TRUE@$(arm_libsim_a_OBJECTS) $(arm_libsim_a_LIBADD): = arm/hw-config.h =20 +@SIM_ENABLE_ARCH_arm_TRUE@arm/modules.o: arm/modules.c + @SIM_ENABLE_ARCH_arm_TRUE@arm/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_arm_TRUE@-@am__include@ arm/$(DEPDIR)/*.Po @SIM_ENABLE_ARCH_avr_TRUE@$(avr_libsim_a_OBJECTS) $(avr_libsim_a_LIBADD): = avr/hw-config.h =20 +@SIM_ENABLE_ARCH_avr_TRUE@avr/modules.o: avr/modules.c + @SIM_ENABLE_ARCH_avr_TRUE@avr/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_avr_TRUE@-@am__include@ avr/$(DEPDIR)/*.Po @SIM_ENABLE_ARCH_bfin_TRUE@$(bfin_libsim_a_OBJECTS) $(bfin_libsim_a_LIBADD= ): bfin/hw-config.h =20 +@SIM_ENABLE_ARCH_bfin_TRUE@bfin/modules.o: bfin/modules.c + @SIM_ENABLE_ARCH_bfin_TRUE@bfin/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_bfin_TRUE@-@am__include@ bfin/$(DEPDIR)/*.Po =20 @@ -5014,6 +5022,8 @@ testsuite/common/bits64m63.c: testsuite/common/bits-g= en$(EXEEXT) testsuite/commo @SIM_ENABLE_ARCH_bfin_TRUE@ $(AM_V_at)touch $(srcdir)/bfin/linux-fixed-cod= e.h @SIM_ENABLE_ARCH_bpf_TRUE@$(bpf_libsim_a_OBJECTS) $(bpf_libsim_a_LIBADD): = bpf/hw-config.h =20 +@SIM_ENABLE_ARCH_bpf_TRUE@bpf/modules.o: bpf/modules.c + @SIM_ENABLE_ARCH_bpf_TRUE@bpf/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_bpf_TRUE@-@am__include@ bpf/$(DEPDIR)/*.Po =20 @@ -5067,6 +5077,8 @@ testsuite/common/bits64m63.c: testsuite/common/bits-g= en$(EXEEXT) testsuite/commo @SIM_ENABLE_ARCH_bpf_TRUE@bpf/sem-be.c bpf/decode-be.c bpf/decode-be.h: @C= GEN_MAINT@ bpf/cgen-decode-be @SIM_ENABLE_ARCH_cr16_TRUE@$(cr16_libsim_a_OBJECTS) $(cr16_libsim_a_LIBADD= ): cr16/hw-config.h =20 +@SIM_ENABLE_ARCH_cr16_TRUE@cr16/modules.o: cr16/modules.c + @SIM_ENABLE_ARCH_cr16_TRUE@cr16/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_cr16_TRUE@-@am__include@ cr16/$(DEPDIR)/*.Po =20 @@ -5089,6 +5101,8 @@ testsuite/common/bits64m63.c: testsuite/common/bits-g= en$(EXEEXT) testsuite/commo @SIM_ENABLE_ARCH_cr16_TRUE@ $(AM_V_GEN)$< >$@ @SIM_ENABLE_ARCH_cris_TRUE@$(cris_libsim_a_OBJECTS) $(cris_libsim_a_LIBADD= ): cris/hw-config.h =20 +@SIM_ENABLE_ARCH_cris_TRUE@cris/modules.o: cris/modules.c + @SIM_ENABLE_ARCH_cris_TRUE@cris/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_cris_TRUE@-@am__include@ cris/$(DEPDIR)/*.Po =20 @@ -5131,6 +5145,8 @@ testsuite/common/bits64m63.c: testsuite/common/bits-g= en$(EXEEXT) testsuite/commo @SIM_ENABLE_ARCH_cris_TRUE@cris/cpuv32.h cris/cpuv32.c cris/semcrisv32f-sw= itch.c cris/modelv32.c cris/decodev32.c cris/decodev32.h: @CGEN_MAINT@ cris= /cgen-cpu-decode-v32f @SIM_ENABLE_ARCH_d10v_TRUE@$(d10v_libsim_a_OBJECTS) $(d10v_libsim_a_LIBADD= ): d10v/hw-config.h =20 +@SIM_ENABLE_ARCH_d10v_TRUE@d10v/modules.o: d10v/modules.c + @SIM_ENABLE_ARCH_d10v_TRUE@d10v/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_d10v_TRUE@-@am__include@ d10v/$(DEPDIR)/*.Po =20 @@ -5153,6 +5169,8 @@ testsuite/common/bits64m63.c: testsuite/common/bits-g= en$(EXEEXT) testsuite/commo @SIM_ENABLE_ARCH_d10v_TRUE@ $(AM_V_GEN)$< >$@ @SIM_ENABLE_ARCH_erc32_TRUE@$(erc32_libsim_a_OBJECTS) $(erc32_libsim_a_LIB= ADD): erc32/hw-config.h =20 +@SIM_ENABLE_ARCH_erc32_TRUE@erc32/modules.o: erc32/modules.c + @SIM_ENABLE_ARCH_erc32_TRUE@erc32/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_erc32_TRUE@-@am__include@ erc32/$(DEPDIR)/*.Po =20 @@ -5166,10 +5184,14 @@ testsuite/common/bits64m63.c: testsuite/common/bits= -gen$(EXEEXT) testsuite/commo @SIM_ENABLE_ARCH_erc32_TRUE@ rm -f $(DESTDIR)$(bindir)/sis @SIM_ENABLE_ARCH_examples_TRUE@$(example_synacor_libsim_a_OBJECTS) $(examp= le_synacor_libsim_a_LIBADD): example-synacor/hw-config.h =20 +@SIM_ENABLE_ARCH_examples_TRUE@example-synacor/modules.o: example-synacor/= modules.c + @SIM_ENABLE_ARCH_examples_TRUE@example-synacor/%.o: common/%.c ; $(SIM_COM= PILE) @SIM_ENABLE_ARCH_examples_TRUE@-@am__include@ example-synacor/$(DEPDIR)/*.= Po @SIM_ENABLE_ARCH_frv_TRUE@$(frv_libsim_a_OBJECTS) $(frv_libsim_a_LIBADD): = frv/hw-config.h =20 +@SIM_ENABLE_ARCH_frv_TRUE@frv/modules.o: frv/modules.c + @SIM_ENABLE_ARCH_frv_TRUE@frv/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_frv_TRUE@-@am__include@ frv/$(DEPDIR)/*.Po =20 @@ -5196,14 +5218,20 @@ testsuite/common/bits64m63.c: testsuite/common/bits= -gen$(EXEEXT) testsuite/commo @SIM_ENABLE_ARCH_frv_TRUE@frv/cpu.h frv/sem.c frv/model.c frv/decode.c frv= /decode.h: @CGEN_MAINT@ frv/cgen-cpu-decode @SIM_ENABLE_ARCH_ft32_TRUE@$(ft32_libsim_a_OBJECTS) $(ft32_libsim_a_LIBADD= ): ft32/hw-config.h =20 +@SIM_ENABLE_ARCH_ft32_TRUE@ft32/modules.o: ft32/modules.c + @SIM_ENABLE_ARCH_ft32_TRUE@ft32/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_ft32_TRUE@-@am__include@ ft32/$(DEPDIR)/*.Po @SIM_ENABLE_ARCH_h8300_TRUE@$(h8300_libsim_a_OBJECTS) $(h8300_libsim_a_LIB= ADD): h8300/hw-config.h =20 +@SIM_ENABLE_ARCH_h8300_TRUE@h8300/modules.o: h8300/modules.c + @SIM_ENABLE_ARCH_h8300_TRUE@h8300/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_h8300_TRUE@-@am__include@ h8300/$(DEPDIR)/*.Po @SIM_ENABLE_ARCH_iq2000_TRUE@$(iq2000_libsim_a_OBJECTS) $(iq2000_libsim_a_= LIBADD): iq2000/hw-config.h =20 +@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/modules.o: iq2000/modules.c + @SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_iq2000_TRUE@-@am__include@ iq2000/$(DEPDIR)/*.Po =20 @@ -5230,6 +5258,8 @@ testsuite/common/bits64m63.c: testsuite/common/bits-g= en$(EXEEXT) testsuite/commo @SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/cpu.h iq2000/sem.c iq2000/sem-switch.c= iq2000/model.c iq2000/decode.c iq2000/decode.h: @CGEN_MAINT@ iq2000/cgen-c= pu-decode @SIM_ENABLE_ARCH_lm32_TRUE@$(lm32_libsim_a_OBJECTS) $(lm32_libsim_a_LIBADD= ): lm32/hw-config.h =20 +@SIM_ENABLE_ARCH_lm32_TRUE@lm32/modules.o: lm32/modules.c + @SIM_ENABLE_ARCH_lm32_TRUE@lm32/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_lm32_TRUE@-@am__include@ lm32/$(DEPDIR)/*.Po =20 @@ -5256,6 +5286,8 @@ testsuite/common/bits64m63.c: testsuite/common/bits-g= en$(EXEEXT) testsuite/commo @SIM_ENABLE_ARCH_lm32_TRUE@lm32/cpu.h lm32/sem.c lm32/sem-switch.c lm32/mo= del.c lm32/decode.c lm32/decode.h: @CGEN_MAINT@ lm32/cgen-cpu-decode @SIM_ENABLE_ARCH_m32c_TRUE@$(m32c_libsim_a_OBJECTS) $(m32c_libsim_a_LIBADD= ): m32c/hw-config.h =20 +@SIM_ENABLE_ARCH_m32c_TRUE@m32c/modules.o: m32c/modules.c + @SIM_ENABLE_ARCH_m32c_TRUE@m32c/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_m32c_TRUE@-@am__include@ m32c/$(DEPDIR)/*.Po =20 @@ -5278,6 +5310,8 @@ testsuite/common/bits64m63.c: testsuite/common/bits-g= en$(EXEEXT) testsuite/commo @SIM_ENABLE_ARCH_m32c_TRUE@ $(AM_V_at)mv $@.tmp $@ @SIM_ENABLE_ARCH_m32r_TRUE@$(m32r_libsim_a_OBJECTS) $(m32r_libsim_a_LIBADD= ): m32r/hw-config.h =20 +@SIM_ENABLE_ARCH_m32r_TRUE@m32r/modules.o: m32r/modules.c + @SIM_ENABLE_ARCH_m32r_TRUE@m32r/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_m32r_TRUE@-@am__include@ m32r/$(DEPDIR)/*.Po =20 @@ -5332,6 +5366,8 @@ testsuite/common/bits64m63.c: testsuite/common/bits-g= en$(EXEEXT) testsuite/commo @SIM_ENABLE_ARCH_m32r_TRUE@m32r/cpu2.h m32r/sem2-switch.c m32r/model2.c m3= 2r/decode2.c m32r/decode2.h: @CGEN_MAINT@ m32r/cgen-cpu-decode-2 @SIM_ENABLE_ARCH_m68hc11_TRUE@$(m68hc11_libsim_a_OBJECTS) $(m68hc11_libsim= _a_LIBADD): m68hc11/hw-config.h =20 +@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11/modules.o: m68hc11/modules.c + @SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_m68hc11_TRUE@-@am__include@ m68hc11/$(DEPDIR)/*.Po =20 @@ -5352,14 +5388,20 @@ testsuite/common/bits64m63.c: testsuite/common/bits= -gen$(EXEEXT) testsuite/commo @SIM_ENABLE_ARCH_m68hc11_TRUE@ $(AM_V_GEN)$< -m6812 >$@ @SIM_ENABLE_ARCH_mcore_TRUE@$(mcore_libsim_a_OBJECTS) $(mcore_libsim_a_LIB= ADD): mcore/hw-config.h =20 +@SIM_ENABLE_ARCH_mcore_TRUE@mcore/modules.o: mcore/modules.c + @SIM_ENABLE_ARCH_mcore_TRUE@mcore/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_mcore_TRUE@-@am__include@ mcore/$(DEPDIR)/*.Po @SIM_ENABLE_ARCH_microblaze_TRUE@$(microblaze_libsim_a_OBJECTS) $(microbla= ze_libsim_a_LIBADD): microblaze/hw-config.h =20 +@SIM_ENABLE_ARCH_microblaze_TRUE@microblaze/modules.o: microblaze/modules.c + @SIM_ENABLE_ARCH_microblaze_TRUE@microblaze/%.o: common/%.c ; $(SIM_COMPIL= E) @SIM_ENABLE_ARCH_microblaze_TRUE@-@am__include@ microblaze/$(DEPDIR)/*.Po @SIM_ENABLE_ARCH_mips_TRUE@$(mips_libsim_a_OBJECTS) $(mips_libsim_a_LIBADD= ): mips/hw-config.h =20 +@SIM_ENABLE_ARCH_mips_TRUE@mips/modules.o: mips/modules.c + @SIM_ENABLE_ARCH_mips_TRUE@mips/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_mips_TRUE@-@am__include@ mips/$(DEPDIR)/*.Po =20 @@ -5564,6 +5606,8 @@ testsuite/common/bits64m63.c: testsuite/common/bits-g= en$(EXEEXT) testsuite/commo @SIM_ENABLE_ARCH_mips_TRUE@ $(AM_V_at)touch $@ @SIM_ENABLE_ARCH_mn10300_TRUE@$(mn10300_libsim_a_OBJECTS) $(mn10300_libsim= _a_LIBADD): mn10300/hw-config.h =20 +@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300/modules.o: mn10300/modules.c + @SIM_ENABLE_ARCH_mn10300_TRUE@mn10300/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_mn10300_TRUE@-@am__include@ mn10300/$(DEPDIR)/*.Po =20 @@ -5598,6 +5642,8 @@ testsuite/common/bits64m63.c: testsuite/common/bits-g= en$(EXEEXT) testsuite/commo @SIM_ENABLE_ARCH_mn10300_TRUE@ $(AM_V_at)touch $@ @SIM_ENABLE_ARCH_moxie_TRUE@$(moxie_libsim_a_OBJECTS) $(moxie_libsim_a_LIB= ADD): moxie/hw-config.h =20 +@SIM_ENABLE_ARCH_moxie_TRUE@moxie/modules.o: moxie/modules.c + @SIM_ENABLE_ARCH_moxie_TRUE@moxie/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_moxie_TRUE@-@am__include@ moxie/$(DEPDIR)/*.Po =20 @@ -5614,10 +5660,14 @@ testsuite/common/bits64m63.c: testsuite/common/bits= -gen$(EXEEXT) testsuite/commo @SIM_ENABLE_ARCH_moxie_TRUE@ fi @SIM_ENABLE_ARCH_msp430_TRUE@$(msp430_libsim_a_OBJECTS) $(msp430_libsim_a_= LIBADD): msp430/hw-config.h =20 +@SIM_ENABLE_ARCH_msp430_TRUE@msp430/modules.o: msp430/modules.c + @SIM_ENABLE_ARCH_msp430_TRUE@msp430/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_msp430_TRUE@-@am__include@ msp430/$(DEPDIR)/*.Po @SIM_ENABLE_ARCH_or1k_TRUE@$(or1k_libsim_a_OBJECTS) $(or1k_libsim_a_LIBADD= ): or1k/hw-config.h =20 +@SIM_ENABLE_ARCH_or1k_TRUE@or1k/modules.o: or1k/modules.c + @SIM_ENABLE_ARCH_or1k_TRUE@or1k/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_or1k_TRUE@-@am__include@ or1k/$(DEPDIR)/*.Po =20 @@ -5662,22 +5712,32 @@ testsuite/common/bits64m63.c: testsuite/common/bits= -gen$(EXEEXT) testsuite/commo @SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)touch $(srcdir)/ppc/spreg.h @SIM_ENABLE_ARCH_pru_TRUE@$(pru_libsim_a_OBJECTS) $(pru_libsim_a_LIBADD): = pru/hw-config.h =20 +@SIM_ENABLE_ARCH_pru_TRUE@pru/modules.o: pru/modules.c + @SIM_ENABLE_ARCH_pru_TRUE@pru/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_pru_TRUE@-@am__include@ pru/$(DEPDIR)/*.Po @SIM_ENABLE_ARCH_riscv_TRUE@$(riscv_libsim_a_OBJECTS) $(riscv_libsim_a_LIB= ADD): riscv/hw-config.h =20 +@SIM_ENABLE_ARCH_riscv_TRUE@riscv/modules.o: riscv/modules.c + @SIM_ENABLE_ARCH_riscv_TRUE@riscv/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_riscv_TRUE@-@am__include@ riscv/$(DEPDIR)/*.Po @SIM_ENABLE_ARCH_rl78_TRUE@$(rl78_libsim_a_OBJECTS) $(rl78_libsim_a_LIBADD= ): rl78/hw-config.h =20 +@SIM_ENABLE_ARCH_rl78_TRUE@rl78/modules.o: rl78/modules.c + @SIM_ENABLE_ARCH_rl78_TRUE@rl78/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_rl78_TRUE@-@am__include@ rl78/$(DEPDIR)/*.Po @SIM_ENABLE_ARCH_rx_TRUE@$(rx_libsim_a_OBJECTS) $(rx_libsim_a_LIBADD): rx/= hw-config.h =20 +@SIM_ENABLE_ARCH_rx_TRUE@rx/modules.o: rx/modules.c + @SIM_ENABLE_ARCH_rx_TRUE@rx/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_rx_TRUE@-@am__include@ rx/$(DEPDIR)/*.Po @SIM_ENABLE_ARCH_sh_TRUE@$(sh_libsim_a_OBJECTS) $(sh_libsim_a_LIBADD): sh/= hw-config.h =20 +@SIM_ENABLE_ARCH_sh_TRUE@sh/modules.o: sh/modules.c + @SIM_ENABLE_ARCH_sh_TRUE@sh/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_sh_TRUE@-@am__include@ sh/$(DEPDIR)/*.Po =20 @@ -5701,6 +5761,8 @@ testsuite/common/bits64m63.c: testsuite/common/bits-g= en$(EXEEXT) testsuite/commo @SIM_ENABLE_ARCH_sh_TRUE@ $(AM_V_GEN)$< -s >$@ @SIM_ENABLE_ARCH_v850_TRUE@$(v850_libsim_a_OBJECTS) $(v850_libsim_a_LIBADD= ): v850/hw-config.h =20 +@SIM_ENABLE_ARCH_v850_TRUE@v850/modules.o: v850/modules.c + @SIM_ENABLE_ARCH_v850_TRUE@v850/%.o: common/%.c ; $(SIM_COMPILE) @SIM_ENABLE_ARCH_v850_TRUE@-@am__include@ v850/$(DEPDIR)/*.Po =20 diff --git a/sim/aarch64/local.mk b/sim/aarch64/local.mk index 113055b126d..b0a1f8f5545 100644 --- a/sim/aarch64/local.mk +++ b/sim/aarch64/local.mk @@ -32,6 +32,9 @@ $(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-co= nfig.h =20 noinst_LIBRARIES +=3D %D%/libsim.a =20 +## Override wildcards that trigger common/modules.c to be (incorrectly) us= ed. +%D%/modules.o: %D%/modules.c + %D%/%.o: common/%.c ; $(SIM_COMPILE) -@am__include@ %D%/$(DEPDIR)/*.Po =20 diff --git a/sim/arm/local.mk b/sim/arm/local.mk index 0c2b1a386dc..2939dd868c0 100644 --- a/sim/arm/local.mk +++ b/sim/arm/local.mk @@ -34,6 +34,9 @@ $(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-co= nfig.h =20 noinst_LIBRARIES +=3D %D%/libsim.a =20 +## Override wildcards that trigger common/modules.c to be (incorrectly) us= ed. +%D%/modules.o: %D%/modules.c + %D%/%.o: common/%.c ; $(SIM_COMPILE) -@am__include@ %D%/$(DEPDIR)/*.Po =20 diff --git a/sim/avr/local.mk b/sim/avr/local.mk index 07752e546a1..306cf88adc2 100644 --- a/sim/avr/local.mk +++ b/sim/avr/local.mk @@ -28,6 +28,9 @@ $(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-co= nfig.h =20 noinst_LIBRARIES +=3D %D%/libsim.a =20 +## Override wildcards that trigger common/modules.c to be (incorrectly) us= ed. +%D%/modules.o: %D%/modules.c + %D%/%.o: common/%.c ; $(SIM_COMPILE) -@am__include@ %D%/$(DEPDIR)/*.Po =20 diff --git a/sim/bfin/local.mk b/sim/bfin/local.mk index e6f6662020a..26ad90e8835 100644 --- a/sim/bfin/local.mk +++ b/sim/bfin/local.mk @@ -36,6 +36,9 @@ $(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-co= nfig.h =20 noinst_LIBRARIES +=3D %D%/libsim.a =20 +## Override wildcards that trigger common/modules.c to be (incorrectly) us= ed. +%D%/modules.o: %D%/modules.c + %D%/%.o: common/%.c ; $(SIM_COMPILE) -@am__include@ %D%/$(DEPDIR)/*.Po =20 diff --git a/sim/bpf/local.mk b/sim/bpf/local.mk index 04f06e3aed3..d4aa0a4dd79 100644 --- a/sim/bpf/local.mk +++ b/sim/bpf/local.mk @@ -53,6 +53,9 @@ $(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-co= nfig.h =20 noinst_LIBRARIES +=3D %D%/libsim.a =20 +## Override wildcards that trigger common/modules.c to be (incorrectly) us= ed. +%D%/modules.o: %D%/modules.c + %D%/%.o: common/%.c ; $(SIM_COMPILE) -@am__include@ %D%/$(DEPDIR)/*.Po =20 diff --git a/sim/cr16/local.mk b/sim/cr16/local.mk index 6d1dd02b68c..10533a46733 100644 --- a/sim/cr16/local.mk +++ b/sim/cr16/local.mk @@ -31,6 +31,9 @@ $(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-co= nfig.h =20 noinst_LIBRARIES +=3D %D%/libsim.a =20 +## Override wildcards that trigger common/modules.c to be (incorrectly) us= ed. +%D%/modules.o: %D%/modules.c + %D%/%.o: common/%.c ; $(SIM_COMPILE) -@am__include@ %D%/$(DEPDIR)/*.Po =20 diff --git a/sim/cris/local.mk b/sim/cris/local.mk index 884024a8e5f..df370e6cdf9 100644 --- a/sim/cris/local.mk +++ b/sim/cris/local.mk @@ -48,6 +48,9 @@ $(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-co= nfig.h =20 noinst_LIBRARIES +=3D %D%/libsim.a =20 +## Override wildcards that trigger common/modules.c to be (incorrectly) us= ed. +%D%/modules.o: %D%/modules.c + %D%/%.o: common/%.c ; $(SIM_COMPILE) -@am__include@ %D%/$(DEPDIR)/*.Po =20 diff --git a/sim/d10v/local.mk b/sim/d10v/local.mk index 25578dd537f..a65635e81ed 100644 --- a/sim/d10v/local.mk +++ b/sim/d10v/local.mk @@ -32,6 +32,9 @@ $(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-co= nfig.h =20 noinst_LIBRARIES +=3D %D%/libsim.a =20 +## Override wildcards that trigger common/modules.c to be (incorrectly) us= ed. +%D%/modules.o: %D%/modules.c + %D%/%.o: common/%.c ; $(SIM_COMPILE) -@am__include@ %D%/$(DEPDIR)/*.Po =20 diff --git a/sim/erc32/local.mk b/sim/erc32/local.mk index 2a3f541b145..177509750a3 100644 --- a/sim/erc32/local.mk +++ b/sim/erc32/local.mk @@ -40,6 +40,9 @@ $(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-co= nfig.h =20 noinst_LIBRARIES +=3D %D%/libsim.a =20 +## Override wildcards that trigger common/modules.c to be (incorrectly) us= ed. +%D%/modules.o: %D%/modules.c + %D%/%.o: common/%.c ; $(SIM_COMPILE) -@am__include@ %D%/$(DEPDIR)/*.Po =20 diff --git a/sim/example-synacor/local.mk b/sim/example-synacor/local.mk index a0de3372dac..959f9ca7c71 100644 --- a/sim/example-synacor/local.mk +++ b/sim/example-synacor/local.mk @@ -30,6 +30,9 @@ $(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-co= nfig.h =20 noinst_LIBRARIES +=3D %D%/libsim.a =20 +## Override wildcards that trigger common/modules.c to be (incorrectly) us= ed. +%D%/modules.o: %D%/modules.c + %D%/%.o: common/%.c ; $(SIM_COMPILE) -@am__include@ %D%/$(DEPDIR)/*.Po =20 diff --git a/sim/frv/local.mk b/sim/frv/local.mk index 14db9b64272..32d81f5f409 100644 --- a/sim/frv/local.mk +++ b/sim/frv/local.mk @@ -64,6 +64,9 @@ $(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-co= nfig.h =20 noinst_LIBRARIES +=3D %D%/libsim.a =20 +## Override wildcards that trigger common/modules.c to be (incorrectly) us= ed. +%D%/modules.o: %D%/modules.c + %D%/%.o: common/%.c ; $(SIM_COMPILE) -@am__include@ %D%/$(DEPDIR)/*.Po =20 diff --git a/sim/ft32/local.mk b/sim/ft32/local.mk index c582cebeec6..96b22f6613a 100644 --- a/sim/ft32/local.mk +++ b/sim/ft32/local.mk @@ -29,6 +29,9 @@ $(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-co= nfig.h =20 noinst_LIBRARIES +=3D %D%/libsim.a =20 +## Override wildcards that trigger common/modules.c to be (incorrectly) us= ed. +%D%/modules.o: %D%/modules.c + %D%/%.o: common/%.c ; $(SIM_COMPILE) -@am__include@ %D%/$(DEPDIR)/*.Po =20 diff --git a/sim/h8300/local.mk b/sim/h8300/local.mk index f1a17efeda1..9d16ba581e2 100644 --- a/sim/h8300/local.mk +++ b/sim/h8300/local.mk @@ -29,6 +29,9 @@ $(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-co= nfig.h =20 noinst_LIBRARIES +=3D %D%/libsim.a =20 +## Override wildcards that trigger common/modules.c to be (incorrectly) us= ed. +%D%/modules.o: %D%/modules.c + %D%/%.o: common/%.c ; $(SIM_COMPILE) -@am__include@ %D%/$(DEPDIR)/*.Po =20 diff --git a/sim/iq2000/local.mk b/sim/iq2000/local.mk index 0d00c672e67..c4518a61eb7 100644 --- a/sim/iq2000/local.mk +++ b/sim/iq2000/local.mk @@ -42,6 +42,9 @@ $(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-co= nfig.h =20 noinst_LIBRARIES +=3D %D%/libsim.a =20 +## Override wildcards that trigger common/modules.c to be (incorrectly) us= ed. +%D%/modules.o: %D%/modules.c + %D%/%.o: common/%.c ; $(SIM_COMPILE) -@am__include@ %D%/$(DEPDIR)/*.Po =20 diff --git a/sim/lm32/local.mk b/sim/lm32/local.mk index f4a4233e7be..404ba5d76d4 100644 --- a/sim/lm32/local.mk +++ b/sim/lm32/local.mk @@ -45,6 +45,9 @@ $(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-co= nfig.h =20 noinst_LIBRARIES +=3D %D%/libsim.a =20 +## Override wildcards that trigger common/modules.c to be (incorrectly) us= ed. +%D%/modules.o: %D%/modules.c + %D%/%.o: common/%.c ; $(SIM_COMPILE) -@am__include@ %D%/$(DEPDIR)/*.Po =20 diff --git a/sim/m32c/local.mk b/sim/m32c/local.mk index dc145302eb4..39620b5ce2f 100644 --- a/sim/m32c/local.mk +++ b/sim/m32c/local.mk @@ -38,6 +38,9 @@ $(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-co= nfig.h =20 noinst_LIBRARIES +=3D %D%/libsim.a =20 +## Override wildcards that trigger common/modules.c to be (incorrectly) us= ed. +%D%/modules.o: %D%/modules.c + %D%/%.o: common/%.c ; $(SIM_COMPILE) -@am__include@ %D%/$(DEPDIR)/*.Po =20 diff --git a/sim/m32r/local.mk b/sim/m32r/local.mk index 072618ff93f..321693bbf01 100644 --- a/sim/m32r/local.mk +++ b/sim/m32r/local.mk @@ -71,6 +71,9 @@ $(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-co= nfig.h =20 noinst_LIBRARIES +=3D %D%/libsim.a =20 +## Override wildcards that trigger common/modules.c to be (incorrectly) us= ed. +%D%/modules.o: %D%/modules.c + %D%/%.o: common/%.c ; $(SIM_COMPILE) -@am__include@ %D%/$(DEPDIR)/*.Po =20 diff --git a/sim/m68hc11/local.mk b/sim/m68hc11/local.mk index 5f585dfd05f..36c503e3bd8 100644 --- a/sim/m68hc11/local.mk +++ b/sim/m68hc11/local.mk @@ -46,6 +46,9 @@ $(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-co= nfig.h =20 noinst_LIBRARIES +=3D %D%/libsim.a =20 +## Override wildcards that trigger common/modules.c to be (incorrectly) us= ed. +%D%/modules.o: %D%/modules.c + %D%/%.o: common/%.c ; $(SIM_COMPILE) -@am__include@ %D%/$(DEPDIR)/*.Po =20 diff --git a/sim/mcore/local.mk b/sim/mcore/local.mk index bde13dbb6a4..6580122b8a5 100644 --- a/sim/mcore/local.mk +++ b/sim/mcore/local.mk @@ -29,6 +29,9 @@ $(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-co= nfig.h =20 noinst_LIBRARIES +=3D %D%/libsim.a =20 +## Override wildcards that trigger common/modules.c to be (incorrectly) us= ed. +%D%/modules.o: %D%/modules.c + %D%/%.o: common/%.c ; $(SIM_COMPILE) -@am__include@ %D%/$(DEPDIR)/*.Po =20 diff --git a/sim/microblaze/local.mk b/sim/microblaze/local.mk index bde13dbb6a4..6580122b8a5 100644 --- a/sim/microblaze/local.mk +++ b/sim/microblaze/local.mk @@ -29,6 +29,9 @@ $(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-co= nfig.h =20 noinst_LIBRARIES +=3D %D%/libsim.a =20 +## Override wildcards that trigger common/modules.c to be (incorrectly) us= ed. +%D%/modules.o: %D%/modules.c + %D%/%.o: common/%.c ; $(SIM_COMPILE) -@am__include@ %D%/$(DEPDIR)/*.Po =20 diff --git a/sim/mips/local.mk b/sim/mips/local.mk index 88d4c900d5f..558dae8f91d 100644 --- a/sim/mips/local.mk +++ b/sim/mips/local.mk @@ -75,6 +75,9 @@ $(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-co= nfig.h =20 noinst_LIBRARIES +=3D %D%/libsim.a =20 +## Override wildcards that trigger common/modules.c to be (incorrectly) us= ed. +%D%/modules.o: %D%/modules.c + %D%/%.o: common/%.c ; $(SIM_COMPILE) -@am__include@ %D%/$(DEPDIR)/*.Po =20 diff --git a/sim/mn10300/local.mk b/sim/mn10300/local.mk index f7c2d553735..448ee0f60dc 100644 --- a/sim/mn10300/local.mk +++ b/sim/mn10300/local.mk @@ -42,6 +42,9 @@ $(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-co= nfig.h =20 noinst_LIBRARIES +=3D %D%/libsim.a =20 +## Override wildcards that trigger common/modules.c to be (incorrectly) us= ed. +%D%/modules.o: %D%/modules.c + %D%/%.o: common/%.c ; $(SIM_COMPILE) -@am__include@ %D%/$(DEPDIR)/*.Po =20 diff --git a/sim/moxie/local.mk b/sim/moxie/local.mk index 4a8b9f740c8..970c0f0ba15 100644 --- a/sim/moxie/local.mk +++ b/sim/moxie/local.mk @@ -31,6 +31,9 @@ $(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-co= nfig.h =20 noinst_LIBRARIES +=3D %D%/libsim.a =20 +## Override wildcards that trigger common/modules.c to be (incorrectly) us= ed. +%D%/modules.o: %D%/modules.c + %D%/%.o: common/%.c ; $(SIM_COMPILE) -@am__include@ %D%/$(DEPDIR)/*.Po =20 diff --git a/sim/msp430/local.mk b/sim/msp430/local.mk index b6ae9c0848b..dc43abc689e 100644 --- a/sim/msp430/local.mk +++ b/sim/msp430/local.mk @@ -29,6 +29,9 @@ $(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-co= nfig.h =20 noinst_LIBRARIES +=3D %D%/libsim.a =20 +## Override wildcards that trigger common/modules.c to be (incorrectly) us= ed. +%D%/modules.o: %D%/modules.c + %D%/%.o: common/%.c ; $(SIM_COMPILE) -@am__include@ %D%/$(DEPDIR)/*.Po =20 diff --git a/sim/or1k/local.mk b/sim/or1k/local.mk index 23625580dbb..d0201ae9fd9 100644 --- a/sim/or1k/local.mk +++ b/sim/or1k/local.mk @@ -46,6 +46,9 @@ $(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-co= nfig.h =20 noinst_LIBRARIES +=3D %D%/libsim.a =20 +## Override wildcards that trigger common/modules.c to be (incorrectly) us= ed. +%D%/modules.o: %D%/modules.c + %D%/%.o: common/%.c ; $(SIM_COMPILE) -@am__include@ %D%/$(DEPDIR)/*.Po =20 diff --git a/sim/pru/local.mk b/sim/pru/local.mk index 0aead8e0ce6..8437ad930d6 100644 --- a/sim/pru/local.mk +++ b/sim/pru/local.mk @@ -29,6 +29,9 @@ $(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-co= nfig.h =20 noinst_LIBRARIES +=3D %D%/libsim.a =20 +## Override wildcards that trigger common/modules.c to be (incorrectly) us= ed. +%D%/modules.o: %D%/modules.c + %D%/%.o: common/%.c ; $(SIM_COMPILE) -@am__include@ %D%/$(DEPDIR)/*.Po =20 diff --git a/sim/riscv/local.mk b/sim/riscv/local.mk index d1e84123b9b..a1bb97c939e 100644 --- a/sim/riscv/local.mk +++ b/sim/riscv/local.mk @@ -33,6 +33,9 @@ $(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-co= nfig.h =20 noinst_LIBRARIES +=3D %D%/libsim.a =20 +## Override wildcards that trigger common/modules.c to be (incorrectly) us= ed. +%D%/modules.o: %D%/modules.c + %D%/%.o: common/%.c ; $(SIM_COMPILE) -@am__include@ %D%/$(DEPDIR)/*.Po =20 diff --git a/sim/rl78/local.mk b/sim/rl78/local.mk index bab9e4561ca..a84334ccdc5 100644 --- a/sim/rl78/local.mk +++ b/sim/rl78/local.mk @@ -31,6 +31,9 @@ $(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-co= nfig.h =20 noinst_LIBRARIES +=3D %D%/libsim.a =20 +## Override wildcards that trigger common/modules.c to be (incorrectly) us= ed. +%D%/modules.o: %D%/modules.c + %D%/%.o: common/%.c ; $(SIM_COMPILE) -@am__include@ %D%/$(DEPDIR)/*.Po =20 diff --git a/sim/rx/local.mk b/sim/rx/local.mk index 63993b9d278..94129652ced 100644 --- a/sim/rx/local.mk +++ b/sim/rx/local.mk @@ -37,6 +37,9 @@ $(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-co= nfig.h =20 noinst_LIBRARIES +=3D %D%/libsim.a =20 +## Override wildcards that trigger common/modules.c to be (incorrectly) us= ed. +%D%/modules.o: %D%/modules.c + %D%/%.o: common/%.c ; $(SIM_COMPILE) -@am__include@ %D%/$(DEPDIR)/*.Po =20 diff --git a/sim/sh/local.mk b/sim/sh/local.mk index 71fa8f2245e..6cbd3a7f158 100644 --- a/sim/sh/local.mk +++ b/sim/sh/local.mk @@ -29,6 +29,9 @@ $(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-co= nfig.h =20 noinst_LIBRARIES +=3D %D%/libsim.a =20 +## Override wildcards that trigger common/modules.c to be (incorrectly) us= ed. +%D%/modules.o: %D%/modules.c + %D%/%.o: common/%.c ; $(SIM_COMPILE) -@am__include@ %D%/$(DEPDIR)/*.Po =20 diff --git a/sim/v850/local.mk b/sim/v850/local.mk index df0045765c2..77b9022d66a 100644 --- a/sim/v850/local.mk +++ b/sim/v850/local.mk @@ -39,6 +39,9 @@ $(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-co= nfig.h =20 noinst_LIBRARIES +=3D %D%/libsim.a =20 +## Override wildcards that trigger common/modules.c to be (incorrectly) us= ed. +%D%/modules.o: %D%/modules.c + %D%/%.o: common/%.c ; $(SIM_COMPILE) -@am__include@ %D%/$(DEPDIR)/*.Po