From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1521) id 742C13858CD1; Fri, 8 Dec 2023 05:31:42 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 742C13858CD1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1702013502; bh=sEvuXpMdusqDaOASLS0pSQF2Q7rUYrL3qNYyrudNbRE=; h=From:To:Subject:Date:From; b=CZvcPpk/B0p+YQk/2USn0Ee76R/oU8Hi+eRNrgXOhD77yq7Hpi7dsOHpuY/ZCrJ7+ ds0+v1WXMAEWvE0DdxOVVPbRrSjALcKHaabWWaQKrLw+HiA8tZ89bRPe5Ma6aFHzsv oPp4gxytrPkxbwylG4Ucgi6wvWcwIxZmruQc8I3M= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Michael Frysinger To: gdb-cvs@sourceware.org Subject: [binutils-gdb] sim: v850: fix -Wunused-but-set-variable warnings X-Act-Checkin: binutils-gdb X-Git-Author: Mike Frysinger X-Git-Refname: refs/heads/master X-Git-Oldrev: 49b556efb55f50d6cd3db39e05edc84df1c3cb69 X-Git-Newrev: bbe7b93875b78ae0831b811a2a8ebb114c71dd27 Message-Id: <20231208053142.742C13858CD1@sourceware.org> Date: Fri, 8 Dec 2023 05:31:42 +0000 (GMT) List-Id: https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3Dbbe7b93875b7= 8ae0831b811a2a8ebb114c71dd27 commit bbe7b93875b78ae0831b811a2a8ebb114c71dd27 Author: Mike Frysinger Date: Wed Dec 6 20:08:19 2023 -0700 sim: v850: fix -Wunused-but-set-variable warnings Diff: --- sim/v850/simops.c | 13 ++++++------- sim/v850/v850.igen | 6 ++---- 2 files changed, 8 insertions(+), 11 deletions(-) diff --git a/sim/v850/simops.c b/sim/v850/simops.c index 326745efcb2..05770a946ea 100644 --- a/sim/v850/simops.c +++ b/sim/v850/simops.c @@ -2106,7 +2106,6 @@ divn unsigned int DBZ =3D als =3D=3D 0 ? 1 : 0; unsigned int Q =3D ~(SS ^ SD) & 1; unsigned int C; - unsigned int S; unsigned int i; unsigned long alt =3D Q ? ~als : als; =20 @@ -2118,7 +2117,7 @@ divn | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31))); Q =3D C ^ SS; R1 =3D (alo =3D=3D 0) ? 0 : (R1 & (Q ^ (SS ^ SD))); - S =3D alo >> 31; + /* S =3D alo >> 31; */ sfi =3D (sfi << (32-N+1)) | Q; ald =3D (alo << 1) | (sfi >> 31); if ((alo >> 31) ^ (ald >> 31)) @@ -2136,7 +2135,7 @@ divn | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31))); Q =3D C ^ SS; R1 =3D (alo =3D=3D 0) ? 0 : (R1 & (Q ^ (SS ^ SD))); - S =3D alo >> 31; + /* S =3D alo >> 31; */ sfi =3D (sfi << 1) | Q; ald =3D (alo << 1) | (sfi >> 31); if ((alo >> 31) ^ (ald >> 31)) @@ -3034,7 +3033,7 @@ v850_float_compare (SIM_DESC sd, int cmp, sim_fpu wop= 1, sim_fpu wop2, int double } else { - int gt =3D 0,lt =3D 0,eq =3D 0, status; + int lt =3D 0, eq =3D 0, status; =20 status =3D sim_fpu_cmp (&wop1, &wop2); =20 @@ -3049,19 +3048,19 @@ v850_float_compare (SIM_DESC sd, int cmp, sim_fpu w= op1, sim_fpu wop2, int double lt =3D 1; break; case SIM_FPU_IS_PINF: - gt =3D 1; + /* gt =3D 1; */ break; case SIM_FPU_IS_NNUMBER: lt =3D 1; break; case SIM_FPU_IS_PNUMBER: - gt =3D 1; + /* gt =3D 1; */ break; case SIM_FPU_IS_NDENORM: lt =3D 1; break; case SIM_FPU_IS_PDENORM: - gt =3D 1; + /* gt =3D 1; */ break; case SIM_FPU_IS_NZERO: case SIM_FPU_IS_PZERO: diff --git a/sim/v850/v850.igen b/sim/v850/v850.igen index bd8de8e2790..6b9a8bb4a5c 100644 --- a/sim/v850/v850.igen +++ b/sim/v850/v850.igen @@ -3537,12 +3537,11 @@ rrrrr,11111100001 + wwww,010001000100:F_I:::trncf_sl { int64_t ans; sim_fpu wop; - sim_fpu_status status; =20 sim_fpu_32to (&wop, GR[reg2]); TRACE_FP_INPUT_FPU1 (&wop); =20 - status =3D sim_fpu_to64i (&ans, &wop, sim_fpu_round_zero); + sim_fpu_to64i (&ans, &wop, sim_fpu_round_zero); =20 GR[reg3e] =3D ans; GR[reg3e+1] =3D ans >> 32L; @@ -3557,12 +3556,11 @@ rrrrr,11111110001 + wwww,010001000100:F_I:::trncf_s= ul { uint64_t ans; sim_fpu wop; - sim_fpu_status status; =20 sim_fpu_32to (&wop, GR[reg2]); TRACE_FP_INPUT_FPU1 (&wop); =20 - status =3D sim_fpu_to64u (&ans, &wop, sim_fpu_round_zero); + sim_fpu_to64u (&ans, &wop, sim_fpu_round_zero); =20 GR[reg3e] =3D ans; GR[reg3e+1] =3D ans >> 32L;