From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2119) id 871963858C5F; Tue, 19 Dec 2023 05:05:16 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 871963858C5F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1702962316; bh=Bbj3XeaGLOK5E7rM0IOSwc4jqJh7v+FnUPvjEfIDAH4=; h=From:To:Subject:Date:From; b=AdpUrIcqpa4rIpr0TxU+BmDV1UYVkIYog91/o1QIn4+DywTOdTZk6IjQMHY9Elgmr dyrvlX9C88cW0/8eoIAAMGR+upF6nQKYFs0qHGQ+qNfCgteyqIjbnAy7GE0tkMx2rx MX3Xt2CdJlEwLSPMLadT+JD4yZtgYoS7Wj2qOC70= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Jeff Law To: gdb-cvs@sourceware.org Subject: [binutils-gdb] Yet another fix for mcore-sim (rotli) X-Act-Checkin: binutils-gdb X-Git-Author: Jeff Law X-Git-Refname: refs/heads/master X-Git-Oldrev: f6149394f9a46d03ff853a0e83aae61441182811 X-Git-Newrev: b3fa92f12a83d284db3124e0992e15d1ff31a3d8 Message-Id: <20231219050516.871963858C5F@sourceware.org> Date: Tue, 19 Dec 2023 05:05:16 +0000 (GMT) List-Id: https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3Db3fa92f12a83= d284db3124e0992e15d1ff31a3d8 commit b3fa92f12a83d284db3124e0992e15d1ff31a3d8 Author: Jeff Law Date: Mon Dec 18 22:04:25 2023 -0700 Yet another fix for mcore-sim (rotli) =20 This came up testing the CRC optimization work from Mariam@RAU. Basically to optimize some CRC loops into table lookups or carryless multiplies, we may need to do a bit reflection, which on the mcore processor is done using a rotate instruction. =20 Unfortunately the simulator implementation of rotates has the exact same problem as we saw with right shifts. The input value may have been sign extended from 32 to 64 bits. When we rotate the extended value, we get those sign extension bits and thus the wrong result. =20 The fix is the same. Rather than using a "long", use a uint32_t for the type of the temporary. This fixes a handful of tests in the GCC testsu= ite: Diff: --- sim/mcore/interp.c | 2 +- sim/testsuite/mcore/rotli.s | 31 +++++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+), 1 deletion(-) diff --git a/sim/mcore/interp.c b/sim/mcore/interp.c index 8bfb745a11f..94e0a1675be 100644 --- a/sim/mcore/interp.c +++ b/sim/mcore/interp.c @@ -1015,7 +1015,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu) case 0x38: case 0x39: /* xsr, rotli */ { unsigned imm =3D IMM5; - unsigned long tmp =3D gr[RD]; + uint32_t tmp =3D gr[RD]; if (imm =3D=3D 0) { int32_t cbit; diff --git a/sim/testsuite/mcore/rotli.s b/sim/testsuite/mcore/rotli.s new file mode 100644 index 00000000000..fd9a8994bc5 --- /dev/null +++ b/sim/testsuite/mcore/rotli.s @@ -0,0 +1,31 @@ +# check that lsri works correctly +# mach: mcore + +.include "testutils.inc" + + start + # Construct -1 + bmaski r2, 32 + + # Clear a couple bits + bclri r2, 0 + bclri r2, 1 + + # rotate by 16 + rotli r2, 16 + + # Construct 0xfffcffff + bmaski r1, 32 + bclri r1, 16 + bclri r1, 17 + + # Compare them, they should be equal + cmpne r2,r1 + jbt .L1 + pass +.L1: + fail + + + +