From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1521) id 129613861837; Tue, 19 Dec 2023 10:53:22 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 129613861837 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1702983202; bh=aO2SiHYNBYWhoyhVIW/rGRzvQGJNUliv47aHmcBytgo=; h=From:To:Subject:Date:From; b=ukLQ25Qh6mPwcVG7QxyZbOQPzGfK9q4tQFew+XG8bKdlGT8DZLvB/o4IEgL+gM+2M Z2GM05XQewUcPiBrcQTeDt/b+p+/37Vq4BLsyaIOwKO7pAhpP5xZ5A9Nwp/dB++6fA f9TFxSTx/KAL2mBh+MDsDv91emhzjMIDjSmONyMc= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Michael Frysinger To: gdb-cvs@sourceware.org Subject: [binutils-gdb] sim: mcore: fix -Wunused-variable warnings X-Act-Checkin: binutils-gdb X-Git-Author: Mike Frysinger X-Git-Refname: refs/heads/master X-Git-Oldrev: 568b2f90c7d5c1ecb6bfea7963c4dd744cad80bb X-Git-Newrev: 2705c08342f6c8f30a4b7439e7352871ce0bc427 Message-Id: <20231219105322.129613861837@sourceware.org> Date: Tue, 19 Dec 2023 10:53:22 +0000 (GMT) List-Id: https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D2705c08342f6= c8f30a4b7439e7352871ce0bc427 commit 2705c08342f6c8f30a4b7439e7352871ce0bc427 Author: Mike Frysinger Date: Fri Dec 15 22:20:48 2023 -0500 sim: mcore: fix -Wunused-variable warnings Diff: --- sim/mcore/interp.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/sim/mcore/interp.c b/sim/mcore/interp.c index 94e0a1675be..b0c2cc2b317 100644 --- a/sim/mcore/interp.c +++ b/sim/mcore/interp.c @@ -303,9 +303,8 @@ step_once (SIM_DESC sd, SIM_CPU *cpu) int memops; int bonus_cycles; int insts; - int w; - int cycs; #ifdef WATCHFUNCTIONS + int w; int32_t WLhash; #endif =20 @@ -356,8 +355,8 @@ step_once (SIM_DESC sd, SIM_CPU *cpu) =20 if ((WLincyc =3D=3D 1) && (pc =3D=3D WLendpc)) { - cycs =3D (mcore_cpu->cycles + (insts + bonus_cycles + - (memops * memcycles)) - WLbcyc); + int cycs =3D (mcore_cpu->cycles + (insts + bonus_cycles + + (memops * memcycles)) - WLbcyc); =20 if (WLcnts[WLW] =3D=3D 1) {