[PATCH] Add MIPS UFR support

[PATCH] Add MIPS UFR support

[Andrew Bennett]

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Hi,

This patch adds support to the MIPS backend to deal with changing the FR mode in user mode
(which I will now refer to as UFR).  The technical details are explained in the following paragraph.

The read only field UFR (at bit 28) in the floating point implementation register (CP1 control register 0) 
represents if the CPU supports UFR.  The UFR field (bit 2) in configuration register 5 (CP0 register 16, 
select 5) allows user mode to enable or disable UFR support.  The current value of the FR mode can be 
obtained if a read is made from the UFR register (CP1 control register 1), and UFR support is enabled.  
If register zero is written to the UFR register, and UFR support is enabled, then the FR mode is set to 0.  
If register zero is written to the UNFR register (CP1 control register 4), and the UFR support is enabled, 
then the FR mode is set to 1.  

To implement this I have firstly added the config 5 register to the simulator model, and added support to 
read and write to it.  Secondly, I have added support for the CTC1 and CFC1 instructions to write/read 
to/from the UFR and UNFR registers.

I have also added a testcase to validate the implementation.  To run the testcase you will need to apply 
the following binutils patch:

https://sourceware.org/ml/binutils/2013-11/msg00065.html


The simulator patch is attached to this email and the ChangeLog is shown below.  

This is my first patch to gdb, so I am unsure the protocol on committing.  Would someone be able to clarify?


Many thanks,



Andrew


2013-11-08  Andrew Bennett  <andrew.bennett@imgtec.com>
	sim/mips/
	* interp.c (ColdReset): Reset the config 5 register and
	set FCR0 to allow user mode FR switching instructions.
	(decode_coproc): Add support for reading and setting the config 5
	register.
	* mips.igen (CTC1c): Add UFR support.
	(CFC1c): Likewise.
	* sim-main.h (_sim_cpu): Add config 5 register and support macros.

	sim/testsuite/sim/mips/
	* basic.exp: Added ufr testcase.
	* ufr.s: New.


Andrew Bennett
Software Design Engineer, MIPS Processor IP
Imagination Technologies Limited
t: +44 (0)113 2429814
www.imgtec.com



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From 8712d51f325ce0e97c75716dc69579288adedb36 Mon Sep 17 00:00:00 2001
From: Andrew Bennett <andrew.bennett@imgtec.com>
Date: Thu, 7 Nov 2013 15:01:35 +0000
Subject: [PATCH] Add support for MIPS UFR.

---
 sim/mips/interp.c                |   17 ++++++++++++++++
 sim/mips/mips.igen               |   27 +++++++++++++++++++++++--
 sim/mips/sim-main.h              |    5 +++++
 sim/testsuite/sim/mips/basic.exp |    2 ++
 sim/testsuite/sim/mips/ufr.s     |   40 ++++++++++++++++++++++++++++++++++++++
 5 files changed, 89 insertions(+), 2 deletions(-)
 create mode 100644 sim/testsuite/sim/mips/ufr.s

diff --git a/sim/mips/interp.c b/sim/mips/interp.c
index 032570a..b5958ac 100644
--- a/sim/mips/interp.c
+++ b/sim/mips/interp.c
@@ -1810,6 +1810,12 @@ ColdReset (SIM_DESC sd)
 	}
       if (BigEndianMem)
 	C0_CONFIG |= 0x00008000;	/* Big Endian */
+
+      /* Initialise the Config5 register. */
+      C5_CONFIG = 0;
+
+      /* User mode FR switching instructions supported */
+      FCR0 |= status_UFRP;
     }
 }
 
@@ -2349,6 +2355,17 @@ decode_coproc (SIM_DESC sd,
 #endif
 	      }
 	  }
+	/* This covers the case of reading and setting the Config5 register */
+	else if (((code == 0x00) || (code == 0x04))  /* MFC0 or MTC0 register 16 select 5 */
+	         && rd == 16  && ((tail & 0x07) == 5))
+	  {
+	    if (code == 0x00)
+	      GPR[rt] = C5_CONFIG;
+	    else if (FCR0 & status_UFRP)
+	      C5_CONFIG = GPR[rt];
+	    else
+	      C5_CONFIG = (GPR[rt] & ~config5_UFR);
+	  }
 	else if ((code == 0x00 || code == 0x01)
 		 && rd == 16)
 	  {
diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen
index 5a6326f..5f271b8 100644
--- a/sim/mips/mips.igen
+++ b/sim/mips/mips.igen
@@ -4520,7 +4520,15 @@
       TRACE_ALU_INPUT1 (fcr);
       GPR[RT] = fcr;
     }
-  /* else NOP */
+  else if ((FS == 1) && (FCR0 & status_UFRP))
+    {
+      if (C5_CONFIG & config5_UFR)
+        GPR[RT] = (unsigned32) ((SR & status_FR) >> 26);
+      else
+        SignalException (ReservedInstruction, instruction_0);
+    }
+  else
+    Unpredictable ();
   TRACE_ALU_RESULT (GPR[RT]);
 }
 
@@ -4562,7 +4570,22 @@
   TRACE_ALU_INPUT1 (GPR[RT]);
   if (FS == 25 || FS == 26 || FS == 28 || FS == 31)
       StoreFCR (FS, GPR[RT]);
-  /* else NOP */
+  else if ((FS == 1) && (RT == 0) && (FCR0 & status_UFRP))
+    {
+      if (C5_CONFIG & config5_UFR)
+        SR &= ~status_FR;
+      else
+        SignalException (ReservedInstruction, instruction_0);
+    }
+  else if ((FS == 4) && (RT == 0) && (FCR0 & status_UFRP))
+    {
+      if (C5_CONFIG & config5_UFR)
+        SR |= status_FR;
+      else
+        SignalException (ReservedInstruction, instruction_0);
+    }
+  else
+    Unpredictable();
 }
 
 
diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h
index b8c75c9..c520afe 100644
--- a/sim/mips/sim-main.h
+++ b/sim/mips/sim-main.h
@@ -407,6 +407,10 @@ struct _sim_cpu {
   unsigned_word c0_config_reg;
 #define C0_CONFIG ((CPU)->c0_config_reg)
 
+  unsigned_word c5_config_reg;
+#define C5_CONFIG ((CPU)->c5_config_reg)
+#define config5_UFR	(1 << 2) 	/* Allow user mode access to StatusFR */
+
 /* The following are pseudonyms for standard registers */
 #define ZERO    (REGISTERS[0])
 #define V0      (REGISTERS[2])
@@ -551,6 +555,7 @@ struct sim_state {
 #define status_CU1       (1 << 29)      /* Coprocessor 1 usable */
 #define status_CU2       (1 << 30)      /* Coprocessor 2 usable */
 #define status_CU3       (1 << 31)      /* Coprocessor 3 usable */
+#define status_UFRP      (1 << 28)      /* User mode FR switching instructions: 0 = not supported, 1 = supported */
 /* Bits reserved for implementations:  */
 #define status_SBX       (1 << 16)      /* Enable SiByte SB-1 extensions.  */
 
diff --git a/sim/testsuite/sim/mips/basic.exp b/sim/testsuite/sim/mips/basic.exp
index 1c78c87..be7284a 100644
--- a/sim/testsuite/sim/mips/basic.exp
+++ b/sim/testsuite/sim/mips/basic.exp
@@ -86,4 +86,6 @@ if {[istarget mips*-*-elf]} {
 
     run_sim_test mips32-dsp.s $dspmodels
     run_sim_test mips32-dsp2.s $dspmodels
+
+    run_sim_test ufr.s $submodels
 }
diff --git a/sim/testsuite/sim/mips/ufr.s b/sim/testsuite/sim/mips/ufr.s
new file mode 100644
index 0000000..1870827
--- /dev/null
+++ b/sim/testsuite/sim/mips/ufr.s
@@ -0,0 +1,40 @@
+# mips test ufr, expected to pass.
+# mach:	 mips32r2 mips64r2
+# as:		-mabi=eabi
+# ld:		-N -Ttext=0x80010000
+#output:	*\\npass\\n
+
+	.include "testutils.inc"
+
+	setup
+
+	.set noreorder
+
+	.ent DIAG
+DIAG:
+	writemsg "[1] Enable writing to FR"
+	li $2, 0x4
+	mfc0 $3, $16, 5
+	or $3, $3, $2
+	mtc0 $3, $16, 5
+	mfc0 $3, $16, 5
+	and $3, $3, $2
+	beq $3, $0, _fail
+	nop
+
+	writemsg "[2] Change to FR 0 mode"
+	ufr 0
+	cfc1 $2, $f1
+	bne $2, $0, _fail
+	nop
+
+	writemsg "[3] Change to FR 1 mode"
+	ufr 1
+	cfc1 $2, $f1
+	li $3, 1
+	bne $2, $3, _fail
+	nop
+
+	pass
+
+	.end DIAG
-- 
1.7.10.1

Re: [PATCH] Add MIPS UFR support

[Mike Frysinger]

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On Friday 08 November 2013 12:36:45 Andrew Bennett wrote:
> This patch adds support to the MIPS backend to deal with changing the FR
> mode in user mode (which I will now refer to as UFR).  The technical
> details are explained in the following paragraph.
> 
> The read only field UFR (at bit 28) in the floating point implementation
> register (CP1 control register 0) represents if the CPU supports UFR.  The
> UFR field (bit 2) in configuration register 5 (CP0 register 16, select 5)
> allows user mode to enable or disable UFR support.  The current value of
> the FR mode can be obtained if a read is made from the UFR register (CP1
> control register 1), and UFR support is enabled. If register zero is
> written to the UFR register, and UFR support is enabled, then the FR mode
> is set to 0. If register zero is written to the UNFR register (CP1 control
> register 4), and the UFR support is enabled, then the FR mode is set to 1.
> 
> To implement this I have firstly added the config 5 register to the
> simulator model, and added support to read and write to it.  Secondly, I
> have added support for the CTC1 and CFC1 instructions to write/read
> to/from the UFR and UNFR registers.

is this standard functionality available to all CPUs ?  your new status_UFRP 
bit overlaps with the existing status_CU0 bit, and you unconditionally enable 
this feature.

> I have also added a testcase to validate the implementation.  To run the
> testcase you will need to apply the following binutils patch:
> 
> https://sourceware.org/ml/binutils/2013-11/msg00065.html
> 
> 
> The simulator patch is attached to this email and the ChangeLog is shown
> below.

looks like your comments need tweaking to follow GNU style.  that means a 
period at the end followed by two spaces and then the closing */.  i also see 
"Unpredictable();" and that needs a space before the "(".

in your mips.igen change, the code changes the else case from a NOP to 
Unpredictable().  is that really what you want ?

> This is my first patch to gdb, so I am unsure the protocol on committing. 
> Would someone be able to clarify?

does your employer have copyright assignments in place ?

otherwise, we don't have a MIPS sim maintainer atm, so i'll do a crappy stand-
in job.
-mike

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Re: [PATCH] Add MIPS UFR support

[Maciej W. Rozycki]

On Sat, 30 Nov 2013, Mike Frysinger wrote:

> is this standard functionality available to all CPUs ?  your new status_UFRP 
> bit overlaps with the existing status_CU0 bit, and you unconditionally enable 
> this feature.

 I'd say this is a misnomer, the macro should be called fir_UFRP as it 
refers to a bit in the CP1.FIR register, not CP0.Status (and moved 
elsewhere in the header accordingly).

  Maciej

RE: [PATCH] Add MIPS UFR support

[Andrew Bennett]

> From: Mike Frysinger [mailto:vapier@gentoo.org] 
> Sent: 30 November 2013 08:57
> To: gdb-patches@sourceware.org
> Cc: Andrew Bennett
> Subject: Re: [PATCH] Add MIPS UFR support
> 
> On Friday 08 November 2013 12:36:45 Andrew Bennett wrote:
> > This patch adds support to the MIPS backend to deal with changing the FR
> > mode in user mode (which I will now refer to as UFR).  The technical
> > details are explained in the following paragraph.
> > 
> > The read only field UFR (at bit 28) in the floating point implementation
> > register (CP1 control register 0) represents if the CPU supports UFR.  The
> > UFR field (bit 2) in configuration register 5 (CP0 register 16, select 5)
> > allows user mode to enable or disable UFR support.  The current value of
> > the FR mode can be obtained if a read is made from the UFR register (CP1
> > control register 1), and UFR support is enabled. If register zero is
> > written to the UFR register, and UFR support is enabled, then the FR mode
> > is set to 0. If register zero is written to the UNFR register (CP1 control
> > register 4), and the UFR support is enabled, then the FR mode is set to 1.
> > 
> > To implement this I have firstly added the config 5 register to the
> > simulator model, and added support to read and write to it.  Secondly, I
> > have added support for the CTC1 and CFC1 instructions to write/read
> > to/from the UFR and UNFR registers.
> 
> is this standard functionality available to all CPUs ?  your new status_UFRP 
> bit overlaps with the existing status_CU0 bit, and you unconditionally enable 
> this feature.
> 
> > I have also added a testcase to validate the implementation.  To run the
> > testcase you will need to apply the following binutils patch:
> > 
> > https://sourceware.org/ml/binutils/2013-11/msg00065.html
> > 
> > 
> > The simulator patch is attached to this email and the ChangeLog is shown
> > below.
> 
> looks like your comments need tweaking to follow GNU style.  that means a 
> period at the end followed by two spaces and then the closing */.  i also see 
> "Unpredictable();" and that needs a space before the "(".

Many thanks for finding these I will amend my patch.

> in your mips.igen change, the code changes the else case from a NOP to 
> Unpredictable().  is that really what you want ?

Yes, I was following the spec from the MIPS 32 instruction set document at the
following URL: http://www.imgtec.com/powervr/insider/powervr-login.asp?doc=MD00082

> > This is my first patch to gdb, so I am unsure the protocol on committing. 
> > Would someone be able to clarify?
> 
> does your employer have copyright assignments in place ?
> 
> otherwise, we don't have a MIPS sim maintainer atm, so i'll do a crappy stand-
> in job.

No, but we are working on getting this sorted out.


Regards,


Andrew

RE: [PATCH] Add MIPS UFR support

[Andrew Bennett]

>> From: Mike Frysinger [mailto:vapier@gentoo.org] 
>> Sent: 30 November 2013 08:57
>> To: gdb-patches@sourceware.org
>> Cc: Andrew Bennett
>> Subject: Re: [PATCH] Add MIPS UFR support
>> 
>> On Friday 08 November 2013 12:36:45 Andrew Bennett wrote:
>> > This patch adds support to the MIPS backend to deal with changing the FR
>> > mode in user mode (which I will now refer to as UFR).  The technical
>> > details are explained in the following paragraph.
>> > 
>> > The read only field UFR (at bit 28) in the floating point implementation
>> > register (CP1 control register 0) represents if the CPU supports UFR.  The
>> > UFR field (bit 2) in configuration register 5 (CP0 register 16, select 5)
>> > allows user mode to enable or disable UFR support.  The current value of
>> > the FR mode can be obtained if a read is made from the UFR register (CP1
>> > control register 1), and UFR support is enabled. If register zero is
>> > written to the UFR register, and UFR support is enabled, then the FR mode
>> > is set to 0. If register zero is written to the UNFR register (CP1 control
>> > register 4), and the UFR support is enabled, then the FR mode is set to 1.
>> > 
>> > To implement this I have firstly added the config 5 register to the
>> > simulator model, and added support to read and write to it.  Secondly, I
>> > have added support for the CTC1 and CFC1 instructions to write/read
>> > to/from the UFR and UNFR registers.
>> 
>> is this standard functionality available to all CPUs ?  your new status_UFRP 
>> bit overlaps with the existing status_CU0 bit, and you unconditionally enable 
>> this feature.
>> 
>> > I have also added a testcase to validate the implementation.  To run the
>> > testcase you will need to apply the following binutils patch:
>> > 
>> > https://sourceware.org/ml/binutils/2013-11/msg00065.html
>> > 
>> > 
>> > The simulator patch is attached to this email and the ChangeLog is shown
>> > below.
>> 
>> looks like your comments need tweaking to follow GNU style.  that means a 
>> period at the end followed by two spaces and then the closing */.  i also see 
>> "Unpredictable();" and that needs a space before the "(".
>
> Many thanks for finding these I will amend my patch.
>
>> in your mips.igen change, the code changes the else case from a NOP to 
>> Unpredictable().  is that really what you want ?
>
> Yes, I was following the spec from the MIPS 32 instruction set document at the
> following URL: http://www.imgtec.com/powervr/insider/powervr-login.asp?doc=MD00082
>
>> > This is my first patch to gdb, so I am unsure the protocol on committing. 
>> > Would someone be able to clarify?
>> 
>> does your employer have copyright assignments in place ?
>> 
>> otherwise, we don't have a MIPS sim maintainer atm, so i'll do a crappy stand-
>> in job.
>
> No, but we are working on getting this sorted out.
>

The following patch and ChangeLog addresses the issues raised with coding style, and status_UFR.
I have also removed the ufr macro instruction from the testcase, and replaced it with the 
actual ctc1 instruction as my ufr patch to binutils does not support this anymore.  Finally, 
I have added extra assembler mnemonics to the CFC1 and CTC1 instructions to print out the 
symbolic names for the CP1 ufr and unfr registers in the same manner as binutils does.

Steve Ellcey (cc'd on this email) does have copyright assignment for gdb.  Would you be happy
if we used his copyright assignment?  Steve is also happy to submit the patch if you don't want to.

Regards,


Andrew


2013-12-18  Andrew Bennett  <andrew.bennett@imgtec.com>
		Steve Ellcey  <steve.ellcey@imgtec.com>
	sim/mips/
	* interp.c (ColdReset): Reset the config 5 register and
	set FCR0 to allow user mode FR switching instructions.
	(decode_coproc): Add support for reading and setting the config 5
	register.
	* mips.igen (CTC1c): Add UFR support.
	(CFC1c): Likewise.
	* sim-main.h (_sim_cpu): Add config 5 register and support macros.

	sim/testsuite/sim/mips/
	* basic.exp: Added ufr testcase.
	* ufr.s: New test.


 sim/mips/interp.c                |   17 ++++++++++++++++
 sim/mips/mips.igen               |   30 ++++++++++++++++++++++++++--
 sim/mips/sim-main.h              |    6 ++++++
 sim/testsuite/sim/mips/basic.exp |    2 ++
 sim/testsuite/sim/mips/ufr.s     |   40 ++++++++++++++++++++++++++++++++++++++
 7 files changed, 108 insertions(+), 2 deletions(-)
 create mode 100644 sim/testsuite/sim/mips/ufr.s

diff --git a/sim/mips/interp.c b/sim/mips/interp.c
index 032570a..44e9b93 100644
--- a/sim/mips/interp.c
+++ b/sim/mips/interp.c
@@ -1810,6 +1810,12 @@ ColdReset (SIM_DESC sd)
 	}
       if (BigEndianMem)
 	C0_CONFIG |= 0x00008000;	/* Big Endian */
+
+      /* Initialise the Config5 register.  */
+      C5_CONFIG = 0;
+
+      /* User mode FR switching instructions supported.  */
+      FCR0 |= fir_UFRP;
     }
 }
 
@@ -2349,6 +2355,17 @@ decode_coproc (SIM_DESC sd,
 #endif
 	      }
 	  }
+	/* This covers the case of reading and setting the Config5 register.  */
+	else if (((code == 0x00) || (code == 0x04))  /* MFC0 or MTC0 register 16 select 5 */
+	         && rd == 16 && ((tail & 0x07) == 5))
+	  {
+	    if (code == 0x00)
+	      GPR[rt] = C5_CONFIG;
+	    else if (FCR0 & fir_UFRP)
+	      C5_CONFIG = GPR[rt];
+	    else
+	      C5_CONFIG = (GPR[rt] & ~config5_UFR);
+	  }
 	else if ((code == 0x00 || code == 0x01)
 		 && rd == 16)
 	  {
diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen
index 5a6326f..f2b44fd 100644
--- a/sim/mips/mips.igen
+++ b/sim/mips/mips.igen
@@ -4506,6 +4506,7 @@
 }
 
 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1c
+"cfc1 r<RT>, c1_ufr": FS == 1
 "cfc1 r<RT>, f<FS>"
 *mipsV:
 *mips32:
@@ -4520,7 +4521,15 @@
       TRACE_ALU_INPUT1 (fcr);
       GPR[RT] = fcr;
     }
-  /* else NOP */
+  else if ((FS == 1) && (FCR0 & fir_UFRP))
+    {
+      if (C5_CONFIG & config5_UFR)
+        GPR[RT] = (unsigned32) ((SR & status_FR) >> 26);
+      else
+        SignalException (ReservedInstruction, instruction_0);
+    }
+  else
+    Unpredictable ();
   TRACE_ALU_RESULT (GPR[RT]);
 }
 
@@ -4551,6 +4560,8 @@
 }
 
 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1c
+"ctc1 r<RT>, c1_ufr": RT == 0 && FS == 1
+"ctc1 r<RT>, c1_unfr": RT == 0 && FS == 4
 "ctc1 r<RT>, f<FS>"
 *mipsV:
 *mips32:
@@ -4562,7 +4573,22 @@
   TRACE_ALU_INPUT1 (GPR[RT]);
   if (FS == 25 || FS == 26 || FS == 28 || FS == 31)
       StoreFCR (FS, GPR[RT]);
-  /* else NOP */
+  else if ((FS == 1) && (RT == 0) && (FCR0 & fir_UFRP))
+    {
+      if (C5_CONFIG & config5_UFR)
+        SR &= ~status_FR;
+      else
+        SignalException (ReservedInstruction, instruction_0);
+    }
+  else if ((FS == 4) && (RT == 0) && (FCR0 & fir_UFRP))
+    {
+      if (C5_CONFIG & config5_UFR)
+        SR |= status_FR;
+      else
+        SignalException (ReservedInstruction, instruction_0);
+    }
+  else
+    Unpredictable ();
 }
 
 
diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h
index b8c75c9..2742c8e 100644
--- a/sim/mips/sim-main.h
+++ b/sim/mips/sim-main.h
@@ -407,6 +407,10 @@ struct _sim_cpu {
   unsigned_word c0_config_reg;
 #define C0_CONFIG ((CPU)->c0_config_reg)
 
+  unsigned_word c5_config_reg;
+#define C5_CONFIG ((CPU)->c5_config_reg)
+#define config5_UFR	(1 << 2) 	/* Allow user mode access to StatusFR */
+
 /* The following are pseudonyms for standard registers */
 #define ZERO    (REGISTERS[0])
 #define V0      (REGISTERS[2])
@@ -576,6 +580,8 @@ struct sim_state {
 #define cause_set_EXC(x)  CAUSE = (CAUSE & ~cause_EXC_mask)  | ((x << cause_EXC_shift)  & cause_EXC_mask)
 #define cause_set_EXC2(x) CAUSE = (CAUSE & ~cause_EXC2_mask) | ((x << cause_EXC2_shift) & cause_EXC2_mask)
 
+/* FIR bits used by MIPS32/MIPS64.  */
+#define fir_UFRP         (1 << 28)      /* User mode FR switching instructions: 0 = not supported, 1 = supported */
 
 /* NOTE: We keep the following status flags as bit values (1 for true,
    0 for false). This allows them to be used in binary boolean
diff --git a/sim/testsuite/sim/mips/basic.exp b/sim/testsuite/sim/mips/basic.exp
index 1c78c87..be7284a 100644
--- a/sim/testsuite/sim/mips/basic.exp
+++ b/sim/testsuite/sim/mips/basic.exp
@@ -86,4 +86,6 @@ if {[istarget mips*-*-elf]} {
 
     run_sim_test mips32-dsp.s $dspmodels
     run_sim_test mips32-dsp2.s $dspmodels
+
+    run_sim_test ufr.s $submodels
 }
diff --git a/sim/testsuite/sim/mips/ufr.s b/sim/testsuite/sim/mips/ufr.s
new file mode 100644
index 0000000..785fefc
--- /dev/null
+++ b/sim/testsuite/sim/mips/ufr.s
@@ -0,0 +1,40 @@
+# mips test ufr, expected to pass.
+# mach:	 mips32r2 mips64r2
+# as:		-mabi=eabi
+# ld:		-N -Ttext=0x80010000
+#output:	*\\npass\\n
+
+	.include "testutils.inc"
+
+	setup
+
+	.set noreorder
+
+	.ent DIAG
+DIAG:
+	writemsg "[1] Enable writing to FR"
+	li $2, 0x4
+	mfc0 $3, $16, 5
+	or $3, $3, $2
+	mtc0 $3, $16, 5
+	mfc0 $3, $16, 5
+	and $3, $3, $2
+	beq $3, $0, _fail
+	nop
+
+	writemsg "[2] Change to FR 0 mode"
+	ctc1 $0, $1
+	cfc1 $2, $1
+	bne $2, $0, _fail
+	nop
+
+	writemsg "[3] Change to FR 1 mode"
+	ctc1 $0, $4
+	cfc1 $2, $1
+	li $3, 1
+	bne $2, $3, _fail
+	nop
+
+	pass
+
+	.end DIAG

Re: [PATCH] Add MIPS UFR support

[Mike Frysinger]

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On Wednesday 18 December 2013 10:36:05 Andrew Bennett wrote:
> Steve Ellcey (cc'd on this email) does have copyright assignment for gdb. 
> Would you be happy if we used his copyright assignment?  Steve is also
> happy to submit the patch if you don't want to.

anyone who has contributed substantially has to have papers to cover them 
specifically.  if you did it for a company, then that company has to have 
papers filed (which it seems you did via imgtec).  the fact that Steve has 
papers in place is irrelevant.

so if imgtec has papers covering all of its employees, then that should be 
sufficient here.

note: i'm not applying these rules because i want to (or even agree with 
them).  the fsf governs this code base, and their rules are to no longer 
accept unassigned work.
-mike

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Re: [PATCH] Add MIPS UFR support

[Joel Brobecker]

Hello!

One small request while copyright assignment issues get resolved:

> diff --git a/sim/testsuite/sim/mips/ufr.s b/sim/testsuite/sim/mips/ufr.s
> new file mode 100644
> index 0000000..785fefc
> --- /dev/null
> +++ b/sim/testsuite/sim/mips/ufr.s
> @@ -0,0 +1,40 @@
> +# mips test ufr, expected to pass.
> +# mach:	 mips32r2 mips64r2
> +# as:		-mabi=eabi

Every file should have a copyright header in it. The range of years
for the copyright notice should start with the year the file was
first committed to a medium, so the year the file was first created.

Thank you,
-- 
Joel

RE: [PATCH] Add MIPS UFR support

[Andrew Bennett]

> Hello!
>
> One small request while copyright assignment issues get resolved:
>
>> diff --git a/sim/testsuite/sim/mips/ufr.s b/sim/testsuite/sim/mips/ufr.s
>> new file mode 100644
>> index 0000000..785fefc
>> --- /dev/null
>> +++ b/sim/testsuite/sim/mips/ufr.s
>> @@ -0,0 +1,40 @@
>> +# mips test ufr, expected to pass.
>> +# mach:	 mips32r2 mips64r2
>> +# as:		-mabi=eabi
>
> Every file should have a copyright header in it. The range of years
> for the copyright notice should start with the year the file was
> first committed to a medium, so the year the file was first created.

I am happy to add a copyright header to this file.  However, I can only 
find three assembler files in the sim/testsuite/sim directory that contain 
a copyright header (two of these are mips tests).  I was therefore wondering
if it is better to follow the prior art and not contain a header?  I don't 
know the history here, so would someone be able to advise me?

Many thanks,



Andrew

Re: [PATCH] Add MIPS UFR support

[Joel Brobecker]

> I am happy to add a copyright header to this file.  However, I can only 
> find three assembler files in the sim/testsuite/sim directory that contain 
> a copyright header (two of these are mips tests).  I was therefore wondering
> if it is better to follow the prior art and not contain a header?  I don't 
> know the history here, so would someone be able to advise me?

In this case, we've had clear directions from the FSF that new files
should always have a copyright header. The lack of header in other
files is a potential issue which we'd like to solve, if we had the
time (to do the research)... But, in the meantime, making sure that
new files have the header allows us to at least not make things worse.

Thank you,
-- 
Joel

RE: [PATCH] Add MIPS UFR support

[Andrew Bennett]

>> I am happy to add a copyright header to this file.  However, I can only 
>> find three assembler files in the sim/testsuite/sim directory that contain 
>> a copyright header (two of these are mips tests).  I was therefore wondering
>> if it is better to follow the prior art and not contain a header?  I don't 
>> know the history here, so would someone be able to advise me?
>
> In this case, we've had clear directions from the FSF that new files
> should always have a copyright header. The lack of header in other
> files is a potential issue which we'd like to solve, if we had the
> time (to do the research)... But, in the meantime, making sure that
> new files have the header allows us to at least not make things worse.

Thats great.  Many thanks for clarifying this.

Regards,


Andrew

RE: [PATCH] Add MIPS UFR support

[Andrew Bennett]

>On Wednesday 18 December 2013 10:36:05 Andrew Bennett wrote:
>> Steve Ellcey (cc'd on this email) does have copyright assignment for gdb. 
>> Would you be happy if we used his copyright assignment?  Steve is also
>> happy to submit the patch if you don't want to.
> 
> anyone who has contributed substantially has to have papers to cover them 
> specifically.  if you did it for a company, then that company has to have 
> papers filed (which it seems you did via imgtec).  the fact that Steve has 
> papers in place is irrelevant.
> 
> so if imgtec has papers covering all of its employees, then that should be 
> sufficient here.

> note: i'm not applying these rules because i want to (or even agree with 
> them).  the fsf governs this code base, and their rules are to no longer 
> accept unassigned work.

Thats absolutely fine.  We are currently sorting this out, and we should have 
it done by early next year.

Regards,


Andrew