RE: [PATCH] Add micromips support to the MIPS simulator

[Andrew Bennett <Andrew.Bennett@imgtec.com>]

> As a microMIPS engine is not included in a mips-linux-gnu build the file
> supposed to provide `micromips_instruction_decode' is not generated or
> compiled, whereas `delayslot_micromips' (and a bunch of other functions)
> is built unconditionally.
> 
>  Restricting the affected functions to microMIPS processors only has fixed
> the build problem for me, see the patch below.  I have not verified it
> further though, will you be able to look into it soon?

Hi Maciej,

The patch looks good, I noticed that the FMT_MICROMIPS, FMT_MICROMIPS_CVT_D
and FMT_MICROMIPS_CVT_S functions also needed fixing.  I have built it for the 
mips-elf, mips-linux-gnu and mips-mti-elf targets and they all build successfully.
The updated patch and ChangeLog is below.

Ok to commit?

Many thanks,



Andrew  


	sim/mips/
 	* micromips.igen (delayslot_micromips): Enable for `micromips32',
 	`micromips64' and `micromipsdsp' only.
 	(process_isa_mode): Enable for `micromips32' and `micromips64'
 	only.
 	(do_micromips_jalr, do_micromips_jal): Likewise.
 	(compute_movep_src_reg): Likewise.
 	(compute_andi16_imm): Likewise.
 	(convert_fmt_micromips): Likewise.
 	(convert_fmt_micromips_cvt_d): Likewise.
 	(convert_fmt_micromips_cvt_s): Likewise.
	(FMT_MICROMIPS): Likewise
	(FMT_MICROMIPS_CVT_D): Likewise
	(FMT_MICROMIPS_CVT_S): Likewise


--- a/sim/mips/micromips.igen
+++ b/sim/mips/micromips.igen
@@ -39,6 +39,9 @@
 :compute:::int:IMM_SHIFT_2BIT:IMMEDIATE:(IMMEDIATE << 2)
 
 :function:::address_word:delayslot_micromips:address_word target, address_word nia, int delayslot_instruction_size
+*micromips32:
+*micromips64:
+*micromipsdsp:
 {
   instruction_word delay_insn;
   sim_events_slip (SD, 1);
@@ -52,12 +55,16 @@
 }
 
 :function:::address_word:process_isa_mode:address_word target
+*micromips32:
+*micromips64:
 {
   SD->isa_mode = target & 0x1;
   return (target & (-(1 << 1)));
 }
 
 :function:::address_word:do_micromips_jalr:int rt, int rs, address_word nia, int delayslot_instruction_size
+*micromips32:
+*micromips64:
 {
   GPR[rt] = (nia + delayslot_instruction_size) | ISA_MODE_MICROMIPS;
   return (process_isa_mode (SD_,
@@ -65,6 +72,8 @@
 }
 
 :function:::address_word:do_micromips_jal:address_word target, address_word nia, int delayslot_instruction_size
+*micromips32:
+*micromips64:
 {
   RA = (nia + delayslot_instruction_size) | ISA_MODE_MICROMIPS;
   return delayslot_micromips (SD_, target, nia, delayslot_instruction_size);
@@ -72,6 +81,8 @@
 
 
 :function:::unsigned32:compute_movep_src_reg:int reg
+*micromips32:
+*micromips64:
 {
   switch(reg)
     {
@@ -88,6 +99,8 @@
 }
 
 :function:::unsigned32:compute_andi16_imm:int encoded_imm
+*micromips32:
+*micromips64:
 {
   switch (encoded_imm)
     {
@@ -112,6 +125,8 @@
 }
 
 :function:::FP_formats:convert_fmt_micromips:int fmt
+*micromips32:
+*micromips64:
 {
   switch (fmt)
     {
@@ -123,6 +138,8 @@
 }
 
 :function:::FP_formats:convert_fmt_micromips_cvt_d:int fmt
+*micromips32:
+*micromips64:
 {
   switch (fmt)
     {
@@ -135,6 +152,8 @@
 
 
 :function:::FP_formats:convert_fmt_micromips_cvt_s:int fmt
+*micromips32:
+*micromips64:
 {
   switch (fmt)
     {
@@ -2252,6 +2271,8 @@
 
 
 :%s::::FMT_MICROMIPS:int fmt
+*micromips32:
+*micromips64:
 {
   switch (fmt)
     {
@@ -2264,6 +2285,8 @@
 
 
 :%s::::FMT_MICROMIPS_CVT_D:int fmt
+*micromips32:
+*micromips64:
 {
   switch (fmt)
     {
@@ -2276,6 +2299,8 @@
 
 
 :%s::::FMT_MICROMIPS_CVT_S:int fmt
+*micromips32:
+*micromips64:
 {
   switch (fmt)
     {