* [PATCH] ARM gdb record-replay bug fixes
@ 2015-02-03 12:47 Omair Javaid
2015-02-16 14:21 ` Yao Qi
2015-05-11 7:27 ` [PATCH v5 0/6] Omair Javaid
0 siblings, 2 replies; 11+ messages in thread
From: Omair Javaid @ 2015-02-03 12:47 UTC (permalink / raw)
To: gdb-patches
This patch provides fixes for some gdb record-replay related testsuite failures
on arm. The patch fixes instruction decoding errors in vector data transfer and
extension register load/store instructions.
This patch has been tested in remote/native mode on armv7 hardware and fixes
failures in gdb.record gdb.mi testsuites. Fixes around 40 tests overall.
gdb:
2015-02-03 Omair Javaid <omair.javaid@linaro.org>
* aarch64-tdep.c (arm_record_vdata_transfer_insn): Correct floating
point register numbers handling.
(arm_record_exreg_ld_st_insn): Fix offset calculation, memory recording
and floating point register numbers handling.
---
gdb/arm-tdep.c | 67 ++++++++++++++++++++++++++++------------------------------
1 file changed, 32 insertions(+), 35 deletions(-)
diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
index 8e9552a..5efc3ea 100644
--- a/gdb/arm-tdep.c
+++ b/gdb/arm-tdep.c
@@ -11943,7 +11943,6 @@ arm_record_vdata_transfer_insn (insn_decode_record *arm_insn_r)
uint32_t bits_a, bit_c, bit_l, reg_t, reg_v;
uint32_t record_buf[4];
- const int num_regs = gdbarch_num_regs (arm_insn_r->gdbarch);
reg_t = bits (arm_insn_r->arm_insn, 12, 15);
reg_v = bits (arm_insn_r->arm_insn, 21, 23);
bits_a = bits (arm_insn_r->arm_insn, 21, 23);
@@ -11961,12 +11960,7 @@ arm_record_vdata_transfer_insn (insn_decode_record *arm_insn_r)
/* Handle VMOV instruction. */
if (bits_a == 0x00)
{
- if (bit (arm_insn_r->arm_insn, 20))
- record_buf[0] = reg_t;
- else
- record_buf[0] = num_regs + (bit (arm_insn_r->arm_insn, 7) |
- (reg_v << 1));
-
+ record_buf[0] = reg_t;
arm_insn_r->reg_rec_count = 1;
}
/* Handle VMRS instruction. */
@@ -11984,12 +11978,9 @@ arm_record_vdata_transfer_insn (insn_decode_record *arm_insn_r)
/* Handle VMOV instruction. */
if (bits_a == 0x00)
{
- if (bit (arm_insn_r->arm_insn, 20))
- record_buf[0] = reg_t;
- else
- record_buf[0] = num_regs + (bit (arm_insn_r->arm_insn, 7) |
- (reg_v << 1));
-
+ uint32_t reg_single;
+ reg_single = bit (arm_insn_r->arm_insn, 7) | (reg_v << 1);
+ record_buf[0] = ARM_D0_REGNUM + reg_single / 2;
arm_insn_r->reg_rec_count = 1;
}
/* Handle VMSR instruction. */
@@ -12042,7 +12033,6 @@ arm_record_exreg_ld_st_insn (insn_decode_record *arm_insn_r)
ULONGEST u_regval = 0;
struct regcache *reg_cache = arm_insn_r->regcache;
- const int num_regs = gdbarch_num_regs (arm_insn_r->gdbarch);
opcode = bits (arm_insn_r->arm_insn, 20, 24);
single_reg = bit (arm_insn_r->arm_insn, 8);
@@ -12064,9 +12054,17 @@ arm_record_exreg_ld_st_insn (insn_decode_record *arm_insn_r)
if (!single_reg)
{
- record_buf[0] = num_regs + reg_m;
- record_buf[1] = num_regs + reg_m + 1;
- arm_insn_r->reg_rec_count = 2;
+ if (reg_m & 0x01)
+ {
+ record_buf[0] = ARM_D0_REGNUM + reg_m / 2;
+ record_buf[1] = ARM_D0_REGNUM + (reg_m + 1) / 2;
+ arm_insn_r->reg_rec_count = 2;
+ }
+ else
+ {
+ record_buf[0] = ARM_D0_REGNUM + reg_m / 2;
+ arm_insn_r->reg_rec_count = 1;
+ }
}
else
{
@@ -12085,7 +12083,7 @@ arm_record_exreg_ld_st_insn (insn_decode_record *arm_insn_r)
reg_rn = bits (arm_insn_r->arm_insn, 16, 19);
regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval);
imm_off8 = bits (arm_insn_r->arm_insn, 0, 7);
- imm_off32 = imm_off8 << 24;
+ imm_off32 = imm_off8 << 2;
memory_count = imm_off8;
if (bit (arm_insn_r->arm_insn, 23))
@@ -12103,19 +12101,17 @@ arm_record_exreg_ld_st_insn (insn_decode_record *arm_insn_r)
{
if (!single_reg)
{
- record_buf_mem[memory_index] = start_address;
- record_buf_mem[memory_index + 1] = 4;
+ record_buf_mem[memory_index++] = 4;
+ record_buf_mem[memory_index++] = start_address;
start_address = start_address + 4;
- memory_index = memory_index + 2;
}
else
{
- record_buf_mem[memory_index] = start_address;
- record_buf_mem[memory_index + 1] = 4;
- record_buf_mem[memory_index + 2] = start_address + 4;
- record_buf_mem[memory_index + 3] = 4;
+ record_buf_mem[memory_index++] = 4;
+ record_buf_mem[memory_index++] = start_address;
+ record_buf_mem[memory_index++] = 4;
+ record_buf_mem[memory_index++] = start_address + 4;
start_address = start_address + 8;
- memory_index = memory_index + 4;
}
memory_count--;
}
@@ -12142,7 +12138,8 @@ arm_record_exreg_ld_st_insn (insn_decode_record *arm_insn_r)
while (reg_count > 0)
{
if (single_reg)
- record_buf[reg_index++] = num_regs + reg_vd + reg_count - 1;
+ record_buf[reg_index++] = ARM_D0_REGNUM +
+ (reg_vd + reg_count - 1) / 2;
else
record_buf[reg_index++] = ARM_D0_REGNUM + reg_vd + reg_count - 1;
@@ -12159,7 +12156,7 @@ arm_record_exreg_ld_st_insn (insn_decode_record *arm_insn_r)
reg_rn = bits (arm_insn_r->arm_insn, 16, 19);
regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval);
imm_off8 = bits (arm_insn_r->arm_insn, 0, 7);
- imm_off32 = imm_off8 << 24;
+ imm_off32 = imm_off8 << 2;
memory_count = imm_off8;
if (bit (arm_insn_r->arm_insn, 23))
@@ -12169,16 +12166,16 @@ arm_record_exreg_ld_st_insn (insn_decode_record *arm_insn_r)
if (single_reg)
{
- record_buf_mem[memory_index] = start_address;
- record_buf_mem[memory_index + 1] = 4;
+ record_buf_mem[memory_index++] = 4;
+ record_buf_mem[memory_index++] = start_address;
arm_insn_r->mem_rec_count = 1;
}
else
{
- record_buf_mem[memory_index] = start_address;
- record_buf_mem[memory_index + 1] = 4;
- record_buf_mem[memory_index + 2] = start_address + 4;
- record_buf_mem[memory_index + 3] = 4;
+ record_buf_mem[memory_index++] = 4;
+ record_buf_mem[memory_index++] = start_address;
+ record_buf_mem[memory_index++] = 4;
+ record_buf_mem[memory_index++] = start_address + 4;
arm_insn_r->mem_rec_count = 2;
}
}
@@ -12195,7 +12192,7 @@ arm_record_exreg_ld_st_insn (insn_decode_record *arm_insn_r)
else
{
reg_vd = (reg_vd << 1) | bit (arm_insn_r->arm_insn, 22);
- record_buf[0] = num_regs + reg_vd;
+ record_buf[0] = ARM_D0_REGNUM + reg_vd / 2;
}
arm_insn_r->reg_rec_count = 1;
}
--
1.9.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] ARM gdb record-replay bug fixes
2015-02-03 12:47 [PATCH] ARM gdb record-replay bug fixes Omair Javaid
@ 2015-02-16 14:21 ` Yao Qi
2015-05-11 7:27 ` [PATCH v5 0/6] Omair Javaid
1 sibling, 0 replies; 11+ messages in thread
From: Yao Qi @ 2015-02-16 14:21 UTC (permalink / raw)
To: Omair Javaid, gdb-patches
Hi Omair,
Sorry for the delayed review...
On 03/02/15 12:47, Omair Javaid wrote:
> This patch provides fixes for some gdb record-replay related testsuite failures
> on arm. The patch fixes instruction decoding errors in vector data transfer and
> extension register load/store instructions.
The patch has been in a good shape, but some bits are still missing.
Could you please split your patch to small pieces (one patch for each
instruction encoding, maybe?). In each of them, give the details on
why current one is wrong, how is the encoding described in the ARM
ARM, and how does the patch fix it.
>
> This patch has been tested in remote/native mode on armv7 hardware and fixes
> failures in gdb.record gdb.mi testsuites. Fixes around 40 tests overall.
>
The result looks good. Could you please add test cases for the
instructions affected by this patch? These cases should fail before
your patch and pass with your patch applied. ARM process record bits
are not good, so we need more test cases to guarantee that it isn't
worse.
> gdb:
>
> 2015-02-03 Omair Javaid<omair.javaid@linaro.org>
>
> * aarch64-tdep.c (arm_record_vdata_transfer_insn): Correct floating
^^^^^^^^^^^^^^^^
typo: arm-tdep.c
> @@ -11961,12 +11960,7 @@ arm_record_vdata_transfer_insn (insn_decode_record *arm_insn_r)
> /* Handle VMOV instruction. */
> if (bits_a == 0x00)
> {
> - if (bit (arm_insn_r->arm_insn, 20))
> - record_buf[0] = reg_t;
> - else
> - record_buf[0] = num_regs + (bit (arm_insn_r->arm_insn, 7) |
> - (reg_v << 1));
> -
> + record_buf[0] = reg_t;
Let us replace 8 spaces with tab here and somewhere else. I know this
format issue was there when arm record/replay was added, but let us fix
it from now on.
> arm_insn_r->reg_rec_count = 1;
> }
> /* Handle VMRS instruction. */
> @@ -11984,12 +11978,9 @@ arm_record_vdata_transfer_insn (insn_decode_record *arm_insn_r)
> /* Handle VMOV instruction. */
> if (bits_a == 0x00)
> {
> - if (bit (arm_insn_r->arm_insn, 20))
> - record_buf[0] = reg_t;
> - else
> - record_buf[0] = num_regs + (bit (arm_insn_r->arm_insn, 7) |
> - (reg_v << 1));
> -
> + uint32_t reg_single;
> + reg_single = bit (arm_insn_r->arm_insn, 7) | (reg_v << 1);
> + record_buf[0] = ARM_D0_REGNUM + reg_single / 2;
I think "reg_single / 2" should be equal to "reg_v".
> @@ -12064,9 +12054,17 @@ arm_record_exreg_ld_st_insn (insn_decode_record *arm_insn_r)
>
> if (!single_reg)
> {
> - record_buf[0] = num_regs + reg_m;
> - record_buf[1] = num_regs + reg_m + 1;
> - arm_insn_r->reg_rec_count = 2;
> + if (reg_m & 0x01)
> + {
> + record_buf[0] = ARM_D0_REGNUM + reg_m / 2;
> + record_buf[1] = ARM_D0_REGNUM + (reg_m + 1) / 2;
> + arm_insn_r->reg_rec_count = 2;
> + }
> + else
> + {
> + record_buf[0] = ARM_D0_REGNUM + reg_m / 2;
> + arm_insn_r->reg_rec_count = 1;
> + }
> }
> else
> {
I am still confused that how gdb can go here, the code looks like:
arm_record_exreg_ld_st_insn
{
...
if ((opcode & 0x1e) == 0x04)
{
if (bit (arm_insn_r->arm_insn, 4)) <-- [1]
{}
else
{}
}
else
{
}
}
According to ARM ARM, A7.9 64-bit transfers between ARM core and
extension registers, the bit 4 is 1, so condition on [1] is always
true.
> @@ -12103,19 +12101,17 @@ arm_record_exreg_ld_st_insn (insn_decode_record *arm_insn_r)
> {
> if (!single_reg)
This block is about handling VSTM and VPUSH, so 'single_reg' (bit 8) is
always 1, isn't?
> {
> - record_buf_mem[memory_index] = start_address;
> - record_buf_mem[memory_index + 1] = 4;
> + record_buf_mem[memory_index++] = 4;
> + record_buf_mem[memory_index++] = start_address;
> start_address = start_address + 4;
> - memory_index = memory_index + 2;
> }
> else
> {
> - record_buf_mem[memory_index] = start_address;
> - record_buf_mem[memory_index + 1] = 4;
> - record_buf_mem[memory_index + 2] = start_address + 4;
> - record_buf_mem[memory_index + 3] = 4;
> + record_buf_mem[memory_index++] = 4;
> + record_buf_mem[memory_index++] = start_address;
> + record_buf_mem[memory_index++] = 4;
> + record_buf_mem[memory_index++] = start_address + 4;
> start_address = start_address + 8;
> - memory_index = memory_index + 4;
> }
> memory_count--;
> }
although your changes in this block looks reasonable to me.
--
Yao (é½å°§)
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v5 2/6] Implements aarch64 process record and reverse debugging support
2015-05-11 7:27 ` [PATCH v5 0/6] Omair Javaid
2015-05-11 7:27 ` [PATCH v5 1/6] NEWS entry about aarch64-linux record/replay support Omair Javaid
@ 2015-05-11 7:27 ` Omair Javaid
2015-05-11 7:27 ` [PATCH v5 6/6] Adds testcases to test arm64 instruction set recording Omair Javaid
` (4 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Omair Javaid @ 2015-05-11 7:27 UTC (permalink / raw)
To: gdb-patches
Updated after incorporating suggestion.
2015-05-11 Omair Javaid <omair.javaid@linaro.org>
* aarch64-linux-tdep.c (aarch64_linux_init_abi): Install AArch64
process record handler.
* aarch64-tdep.c (record.h): Include.
(record-full.h): Include.
(submask): New macro.
(bit): New macro.
(bits): New macro.
(REG_ALLOC): New macro.
(MEM_ALLOC): New macro.
(struct aarch64_mem_r): Define.
(aarch64_record_result): New enum.
(struct insn_decode_record): Define.
(insn_decode_record): New typedef.
(aarch64_record_data_proc_reg): New function.
(aarch64_record_data_proc_imm): New function.
(aarch64_record_branch_except_sys): New function.
(aarch64_record_load_store): New function.
(aarch64_record_decode_insn_handler): New function.
(deallocate_reg_mem): New function.
(aarch64_process_record): New function.
* aarch64-tdep.h (aarch64_process_record): New extern declaration.
---
gdb/aarch64-linux-tdep.c | 3 +
gdb/aarch64-tdep.c | 595 +++++++++++++++++++++++++++++++++++++++++++++++
gdb/aarch64-tdep.h | 3 +
3 files changed, 601 insertions(+)
diff --git a/gdb/aarch64-linux-tdep.c b/gdb/aarch64-linux-tdep.c
index 0ee5ecb..e579858 100644
--- a/gdb/aarch64-linux-tdep.c
+++ b/gdb/aarch64-linux-tdep.c
@@ -409,6 +409,9 @@ aarch64_linux_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
set_gdbarch_stap_parse_special_token (gdbarch,
aarch64_stap_parse_special_token);
+ /* Reversible debugging, process record. */
+ set_gdbarch_process_record (gdbarch, aarch64_process_record);
+
/* `catch syscall' */
set_xml_syscall_file_name (gdbarch, "syscalls/aarch64-linux.xml");
set_gdbarch_get_syscall_number (gdbarch, aarch64_linux_get_syscall_number);
diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index ddc9022..3c29f43 100644
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -50,6 +50,9 @@
#include "vec.h"
+#include "record.h"
+#include "record-full.h"
+
#include "features/aarch64.c"
/* Pseudo register base numbers. */
@@ -2803,3 +2806,595 @@ When on, AArch64 specific debugging is enabled."),
show_aarch64_debug,
&setdebuglist, &showdebuglist);
}
+
+/* AArch64 process record-replay related structures, defines etc. */
+
+#define submask(x) ((1L << ((x) + 1)) - 1)
+#define bit(obj,st) (((obj) >> (st)) & 1)
+#define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
+
+#define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
+ do \
+ { \
+ unsigned int reg_len = LENGTH; \
+ if (reg_len) \
+ { \
+ REGS = XNEWVEC (uint32_t, reg_len); \
+ memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
+ } \
+ } \
+ while (0)
+
+#define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
+ do \
+ { \
+ unsigned int mem_len = LENGTH; \
+ if (mem_len) \
+ { \
+ MEMS = XNEWVEC (struct aarch64_mem_r, mem_len); \
+ memcpy(&MEMS->len, &RECORD_BUF[0], \
+ sizeof(struct aarch64_mem_r) * LENGTH); \
+ } \
+ } \
+ while (0)
+
+/* AArch64 record/replay structures and enumerations. */
+
+struct aarch64_mem_r
+{
+ uint64_t len; /* Record length. */
+ uint64_t addr; /* Memory address. */
+};
+
+enum aarch64_record_result
+{
+ AARCH64_RECORD_SUCCESS,
+ AARCH64_RECORD_FAILURE,
+ AARCH64_RECORD_UNSUPPORTED,
+ AARCH64_RECORD_UNKNOWN
+};
+
+typedef struct insn_decode_record_t
+{
+ struct gdbarch *gdbarch;
+ struct regcache *regcache;
+ CORE_ADDR this_addr; /* Address of insn to be recorded. */
+ uint32_t aarch64_insn; /* Insn to be recorded. */
+ uint32_t mem_rec_count; /* Count of memory records. */
+ uint32_t reg_rec_count; /* Count of register records. */
+ uint32_t *aarch64_regs; /* Registers to be recorded. */
+ struct aarch64_mem_r *aarch64_mems; /* Memory locations to be recorded. */
+} insn_decode_record;
+
+/* Record handler for data processing - register instructions. */
+
+static unsigned int
+aarch64_record_data_proc_reg (insn_decode_record *aarch64_insn_r)
+{
+ uint8_t reg_rd, insn_bits24_27, insn_bits21_23;
+ uint32_t record_buf[4];
+
+ reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
+ insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
+ insn_bits21_23 = bits (aarch64_insn_r->aarch64_insn, 21, 23);
+
+ if (!bit (aarch64_insn_r->aarch64_insn, 28))
+ {
+ uint8_t setflags;
+
+ /* Logical (shifted register). */
+ if (insn_bits24_27 == 0x0a)
+ setflags = (bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03);
+ /* Add/subtract. */
+ else if (insn_bits24_27 == 0x0b)
+ setflags = bit (aarch64_insn_r->aarch64_insn, 29);
+ else
+ return AARCH64_RECORD_UNKNOWN;
+
+ record_buf[0] = reg_rd;
+ aarch64_insn_r->reg_rec_count = 1;
+ if (setflags)
+ record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
+ }
+ else
+ {
+ if (insn_bits24_27 == 0x0b)
+ {
+ /* Data-processing (3 source). */
+ record_buf[0] = reg_rd;
+ aarch64_insn_r->reg_rec_count = 1;
+ }
+ else if (insn_bits24_27 == 0x0a)
+ {
+ if (insn_bits21_23 == 0x00)
+ {
+ /* Add/subtract (with carry). */
+ record_buf[0] = reg_rd;
+ aarch64_insn_r->reg_rec_count = 1;
+ if (bit (aarch64_insn_r->aarch64_insn, 29))
+ {
+ record_buf[1] = AARCH64_CPSR_REGNUM;
+ aarch64_insn_r->reg_rec_count = 2;
+ }
+ }
+ else if (insn_bits21_23 == 0x02)
+ {
+ /* Conditional compare (register) and conditional compare
+ (immediate) instructions. */
+ record_buf[0] = AARCH64_CPSR_REGNUM;
+ aarch64_insn_r->reg_rec_count = 1;
+ }
+ else if (insn_bits21_23 == 0x04 || insn_bits21_23 == 0x06)
+ {
+ /* CConditional select. */
+ /* Data-processing (2 source). */
+ /* Data-processing (1 source). */
+ record_buf[0] = reg_rd;
+ aarch64_insn_r->reg_rec_count = 1;
+ }
+ else
+ return AARCH64_RECORD_UNKNOWN;
+ }
+ }
+
+ REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
+ record_buf);
+ return AARCH64_RECORD_SUCCESS;
+}
+
+/* Record handler for data processing - immediate instructions. */
+static unsigned int
+aarch64_record_data_proc_imm (insn_decode_record *aarch64_insn_r)
+{
+ uint8_t reg_rd, insn_bit28, insn_bit23, insn_bits24_27, setflags;
+ uint32_t record_buf[4];
+
+ reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
+ insn_bit28 = bit (aarch64_insn_r->aarch64_insn, 28);
+ insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23);
+ insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
+
+ if (insn_bits24_27 == 0x00 /* PC rel addressing. */
+ || insn_bits24_27 == 0x03 /* Bitfield and Extract. */
+ || (insn_bits24_27 == 0x02 && insn_bit23)) /* Move wide (immediate). */
+ {
+ record_buf[0] = reg_rd;
+ aarch64_insn_r->reg_rec_count = 1;
+ }
+ else if (insn_bits24_27 == 0x01)
+ {
+ /* Add/Subtract (immediate). */
+ setflags = bit (aarch64_insn_r->aarch64_insn, 29);
+ record_buf[0] = reg_rd;
+ aarch64_insn_r->reg_rec_count = 1;
+ if (setflags)
+ record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
+ }
+ else if (insn_bits24_27 == 0x02 && !insn_bit23)
+ {
+ /* Logical (immediate). */
+ setflags = bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03;
+ record_buf[0] = reg_rd;
+ aarch64_insn_r->reg_rec_count = 1;
+ if (setflags)
+ record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
+ }
+ else
+ return AARCH64_RECORD_UNKNOWN;
+
+ REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
+ record_buf);
+ return AARCH64_RECORD_SUCCESS;
+}
+
+/* Record handler for branch, exception generation and system instructions. */
+static unsigned int
+aarch64_record_branch_except_sys (insn_decode_record *aarch64_insn_r)
+{
+ uint8_t insn_bits24_27, insn_bits28_31, insn_bits22_23;
+ uint32_t record_buf[4];
+
+ insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
+ insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31);
+ insn_bits22_23 = bits (aarch64_insn_r->aarch64_insn, 22, 23);
+
+ if (insn_bits28_31 == 0x0d)
+ {
+ /* Exception generation instructions. */
+ if (insn_bits24_27 == 0x04)
+ return AARCH64_RECORD_UNSUPPORTED;
+ /* System instructions. */
+ else if (insn_bits24_27 == 0x05 && insn_bits22_23 == 0x00)
+ {
+ uint32_t reg_rt, reg_crn;
+ reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
+ reg_crn = bits (aarch64_insn_r->aarch64_insn, 12, 15);
+
+ /* Record rt in case of sysl and mrs instructions. */
+ if (bit (aarch64_insn_r->aarch64_insn, 21))
+ {
+ record_buf[0] = reg_rt;
+ aarch64_insn_r->reg_rec_count = 1;
+ }
+ /* Record cpsr for hint and msr(immediate) instructions. */
+ else if (reg_crn == 0x02 || reg_crn == 0x04)
+ {
+ record_buf[0] = AARCH64_CPSR_REGNUM;
+ aarch64_insn_r->reg_rec_count = 1;
+ }
+ }
+ /* Unconditional branch (register). */
+ else if((insn_bits24_27 & 0x0e) == 0x06)
+ {
+ record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
+ if (bits (aarch64_insn_r->aarch64_insn, 21, 22) == 0x01)
+ record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM;
+ }
+ else
+ return AARCH64_RECORD_UNKNOWN;
+ }
+ /* Unconditional branch (immediate). */
+ else if ((insn_bits28_31 & 0x07) == 0x01 && (insn_bits24_27 & 0x0c) == 0x04)
+ {
+ record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
+ if (bit (aarch64_insn_r->aarch64_insn, 31))
+ record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM;
+ }
+ else
+ /* Compare & branch (immediate), Test & branch (immediate) and
+ Conditional branch (immediate). */
+ record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
+
+ REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
+ record_buf);
+ return AARCH64_RECORD_SUCCESS;
+}
+
+/* Record handler for load and store instructions. */
+static unsigned int
+aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
+{
+ uint8_t insn_bits24_27, insn_bits28_29, insn_bits10_11;
+ uint8_t insn_bit23, insn_bit21;
+ uint8_t opc, size_bits, ld_flag, vector_flag;
+ uint32_t reg_rn, reg_rt, reg_rt2;
+ uint64_t datasize, offset;
+ uint32_t record_buf[8];
+ uint64_t record_buf_mem[8];
+ CORE_ADDR address;
+
+ insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11);
+ insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
+ insn_bits28_29 = bits (aarch64_insn_r->aarch64_insn, 28, 29);
+ insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21);
+ insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23);
+ ld_flag = bit (aarch64_insn_r->aarch64_insn, 22);
+ vector_flag = bit (aarch64_insn_r->aarch64_insn, 26);
+ reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
+ reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9);
+ reg_rt2 = bits (aarch64_insn_r->aarch64_insn, 10, 14);
+ size_bits = bits (aarch64_insn_r->aarch64_insn, 30, 31);
+
+ /* Load/store exclusive. */
+ if (insn_bits24_27 == 0x08 && insn_bits28_29 == 0x00)
+ {
+ if (ld_flag)
+ {
+ record_buf[0] = reg_rt;
+ aarch64_insn_r->reg_rec_count = 1;
+ if (insn_bit21)
+ {
+ record_buf[1] = reg_rt2;
+ aarch64_insn_r->reg_rec_count = 2;
+ }
+ }
+ else
+ {
+ if (insn_bit21)
+ datasize = (8 << size_bits) * 2;
+ else
+ datasize = (8 << size_bits);
+ regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
+ &address);
+ record_buf_mem[0] = datasize / 8;
+ record_buf_mem[1] = address;
+ aarch64_insn_r->mem_rec_count = 1;
+ if (!insn_bit23)
+ {
+ /* Save register rs. */
+ record_buf[0] = bits (aarch64_insn_r->aarch64_insn, 16, 20);
+ aarch64_insn_r->reg_rec_count = 1;
+ }
+ }
+ }
+ /* Load register (literal) instructions decoding. */
+ else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x01)
+ {
+ if (vector_flag)
+ record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
+ else
+ record_buf[0] = reg_rt;
+ aarch64_insn_r->reg_rec_count = 1;
+ }
+ /* All types of load/store pair instructions decoding. */
+ else if ((insn_bits24_27 & 0x0a) == 0x08 && insn_bits28_29 == 0x02)
+ {
+ if (ld_flag)
+ {
+ if (vector_flag)
+ {
+ record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
+ record_buf[1] = reg_rt2 + AARCH64_V0_REGNUM;
+ }
+ else
+ {
+ record_buf[0] = reg_rt;
+ record_buf[1] = reg_rt2;
+ }
+ aarch64_insn_r->reg_rec_count = 2;
+ }
+ else
+ {
+ uint16_t imm7_off;
+ imm7_off = bits (aarch64_insn_r->aarch64_insn, 15, 21);
+ if (!vector_flag)
+ size_bits = size_bits >> 1;
+ datasize = 8 << (2 + size_bits);
+ offset = (imm7_off & 0x40) ? (~imm7_off & 0x007f) + 1 : imm7_off;
+ offset = offset << (2 + size_bits);
+ regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
+ &address);
+ if (!((insn_bits24_27 & 0x0b) == 0x08 && insn_bit23))
+ {
+ if (imm7_off & 0x40)
+ address = address - offset;
+ else
+ address = address + offset;
+ }
+
+ record_buf_mem[0] = datasize / 8;
+ record_buf_mem[1] = address;
+ record_buf_mem[2] = datasize / 8;
+ record_buf_mem[3] = address + (datasize / 8);
+ aarch64_insn_r->mem_rec_count = 2;
+ }
+ if (bit (aarch64_insn_r->aarch64_insn, 23))
+ record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn;
+ }
+ /* Load/store register (unsigned immediate) instructions. */
+ else if ((insn_bits24_27 & 0x0b) == 0x09 && insn_bits28_29 == 0x03)
+ {
+ opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
+ if (!(opc >> 1))
+ if (opc & 0x01)
+ ld_flag = 0x01;
+ else
+ ld_flag = 0x0;
+ else
+ if (size_bits != 0x03)
+ ld_flag = 0x01;
+ else
+ return AARCH64_RECORD_UNKNOWN;
+
+ if (!ld_flag)
+ {
+ offset = bits (aarch64_insn_r->aarch64_insn, 10, 21);
+ datasize = 8 << size_bits;
+ regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
+ &address);
+ offset = offset << size_bits;
+ address = address + offset;
+
+ record_buf_mem[0] = datasize >> 3;
+ record_buf_mem[1] = address;
+ aarch64_insn_r->mem_rec_count = 1;
+ }
+ else
+ {
+ if (vector_flag)
+ record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
+ else
+ record_buf[0] = reg_rt;
+ aarch64_insn_r->reg_rec_count = 1;
+ }
+ }
+ /* Load/store register (register offset) instructions. */
+ else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03 &&
+ insn_bits10_11 == 0x02 && insn_bit21)
+ {
+ opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
+ if (!(opc >> 1))
+ if (opc & 0x01)
+ ld_flag = 0x01;
+ else
+ ld_flag = 0x0;
+ else
+ if (size_bits != 0x03)
+ ld_flag = 0x01;
+ else
+ return AARCH64_RECORD_UNKNOWN;
+
+ if (!ld_flag)
+ {
+ uint64_t reg_rm_val;
+ regcache_raw_read_unsigned (aarch64_insn_r->regcache,
+ bits (aarch64_insn_r->aarch64_insn, 16, 20), ®_rm_val);
+ if (bit (aarch64_insn_r->aarch64_insn, 12))
+ offset = reg_rm_val << size_bits;
+ else
+ offset = reg_rm_val;
+ datasize = 8 << size_bits;
+ regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
+ &address);
+ address = address + offset;
+ record_buf_mem[0] = datasize >> 3;
+ record_buf_mem[1] = address;
+ aarch64_insn_r->mem_rec_count = 1;
+ }
+ else
+ {
+ if (vector_flag)
+ record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
+ else
+ record_buf[0] = reg_rt;
+ aarch64_insn_r->reg_rec_count = 1;
+ }
+ }
+ /* Load/store register (immediate and unprivileged) instructions. */
+ else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03 &&
+ !insn_bit21)
+ {
+ opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
+ if (!(opc >> 1))
+ if (opc & 0x01)
+ ld_flag = 0x01;
+ else
+ ld_flag = 0x0;
+ else
+ if (size_bits != 0x03)
+ ld_flag = 0x01;
+ else
+ return AARCH64_RECORD_UNKNOWN;
+
+ if (!ld_flag)
+ {
+ uint16_t imm9_off;
+ imm9_off = bits (aarch64_insn_r->aarch64_insn, 12, 20);
+ offset = (imm9_off & 0x0100) ? (((~imm9_off) & 0x01ff) + 1) : imm9_off;
+ datasize = 8 << size_bits;
+ regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
+ &address);
+ if (insn_bits10_11 != 0x01)
+ {
+ if (imm9_off & 0x0100)
+ address = address - offset;
+ else
+ address = address + offset;
+ }
+ record_buf_mem[0] = datasize >> 3;
+ record_buf_mem[1] = address;
+ aarch64_insn_r->mem_rec_count = 1;
+ }
+ else
+ {
+ if (vector_flag)
+ record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
+ else
+ record_buf[0] = reg_rt;
+ aarch64_insn_r->reg_rec_count = 1;
+ }
+ if (insn_bits10_11 == 0x01 || insn_bits10_11 == 0x03)
+ record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn;
+ }
+ /* Advanced SIMD load/store instructions. */
+ else
+ return AARCH64_RECORD_UNSUPPORTED;
+
+ MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count,
+ record_buf_mem);
+ REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
+ record_buf);
+ return AARCH64_RECORD_SUCCESS;
+}
+/* Decodes insns type and invokes its record handler. */
+
+static unsigned int
+aarch64_record_decode_insn_handler (insn_decode_record *aarch64_insn_r)
+{
+ uint32_t ins_bit25, ins_bit26, ins_bit27, ins_bit28;
+
+ ins_bit25 = bit (aarch64_insn_r->aarch64_insn, 25);
+ ins_bit26 = bit (aarch64_insn_r->aarch64_insn, 26);
+ ins_bit27 = bit (aarch64_insn_r->aarch64_insn, 27);
+ ins_bit28 = bit (aarch64_insn_r->aarch64_insn, 28);
+
+ /* Data processing - immediate instructions. */
+ if (!ins_bit26 && !ins_bit27 && ins_bit28)
+ return aarch64_record_data_proc_imm (aarch64_insn_r);
+
+ /* Branch, exception generation and system instructions. */
+ if (ins_bit26 && !ins_bit27 && ins_bit28)
+ return aarch64_record_branch_except_sys (aarch64_insn_r);
+
+ /* Load and store instructions. */
+ if (!ins_bit25 && ins_bit27)
+ return aarch64_record_load_store (aarch64_insn_r);
+
+ /* Data processing - register instructions. */
+ if (ins_bit25 && !ins_bit26 && ins_bit27)
+ return aarch64_record_data_proc_reg (aarch64_insn_r);
+
+ /* Data processing - SIMD and floating point instructions. */
+ if (ins_bit25 && ins_bit26 && ins_bit27)
+ return AARCH64_RECORD_UNSUPPORTED;
+
+ return AARCH64_RECORD_UNSUPPORTED;
+}
+
+/* Cleans up local record registers and memory allocations. */
+
+static void
+deallocate_reg_mem (insn_decode_record *record)
+{
+ xfree (record->aarch64_regs);
+ xfree (record->aarch64_mems);
+}
+
+/* Parse the current instruction and record the values of the registers and
+ memory that will be changed in current instruction to record_arch_list
+ return -1 if something is wrong. */
+
+int
+aarch64_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
+ CORE_ADDR insn_addr)
+{
+ uint32_t rec_no = 0;
+ uint8_t insn_size = 4;
+ uint32_t ret = 0;
+ ULONGEST t_bit = 0, insn_id = 0;
+ gdb_byte buf[insn_size];
+ insn_decode_record aarch64_record;
+
+ memset (&buf[0], 0, insn_size);
+ memset (&aarch64_record, 0, sizeof (insn_decode_record));
+ target_read_memory (insn_addr, &buf[0], insn_size);
+ aarch64_record.aarch64_insn = (uint32_t) extract_unsigned_integer (&buf[0],
+ insn_size, gdbarch_byte_order (gdbarch));
+ aarch64_record.regcache = regcache;
+ aarch64_record.this_addr = insn_addr;
+ aarch64_record.gdbarch = gdbarch;
+
+ ret = aarch64_record_decode_insn_handler (&aarch64_record);
+ if (ret == AARCH64_RECORD_UNSUPPORTED)
+ {
+ printf_unfiltered (_("Process record does not support instruction "
+ "0x%0x at address %s.\n"),aarch64_record.aarch64_insn,
+ paddress (gdbarch, insn_addr));
+ ret = -1;
+ }
+
+ if (0 == ret)
+ {
+ /* Record registers. */
+ record_full_arch_list_add_reg (aarch64_record.regcache, AARCH64_PC_REGNUM);
+ if (aarch64_record.aarch64_regs)
+ for (rec_no = 0; rec_no < aarch64_record.reg_rec_count; rec_no++)
+ if (record_full_arch_list_add_reg (aarch64_record.regcache,
+ aarch64_record.aarch64_regs[rec_no]))
+ ret = -1;
+
+ /* Record memories. */
+ if (aarch64_record.aarch64_mems)
+ for (rec_no = 0; rec_no < aarch64_record.mem_rec_count; rec_no++)
+ if (record_full_arch_list_add_mem
+ ((CORE_ADDR)aarch64_record.aarch64_mems[rec_no].addr,
+ aarch64_record.aarch64_mems[rec_no].len))
+ ret = -1;
+
+ if (record_full_arch_list_add_end ())
+ ret = -1;
+ }
+
+ deallocate_reg_mem (&aarch64_record);
+ return ret;
+}
diff --git a/gdb/aarch64-tdep.h b/gdb/aarch64-tdep.h
index 976ad32..0a8bb26 100644
--- a/gdb/aarch64-tdep.h
+++ b/gdb/aarch64-tdep.h
@@ -92,4 +92,7 @@ struct gdbarch_tdep
extern struct target_desc *tdesc_aarch64;
+extern int aarch64_process_record (struct gdbarch *gdbarch,
+ struct regcache *regcache, CORE_ADDR addr);
+
#endif /* aarch64-tdep.h */
--
1.9.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v5 3/6] Support for recording syscall on aarch64-linux
2015-05-11 7:27 ` [PATCH v5 0/6] Omair Javaid
` (3 preceding siblings ...)
2015-05-11 7:27 ` [PATCH v5 5/6] Enables gdb.reverse testsuite for aarch64*-linux targets Omair Javaid
@ 2015-05-11 7:27 ` Omair Javaid
2015-05-11 7:27 ` [PATCH v5 4/6] Support for recording aarch64 advanced SIMD instructions Omair Javaid
2015-05-11 11:18 ` [PATCH v5 0/6] Yao Qi
6 siblings, 0 replies; 11+ messages in thread
From: Omair Javaid @ 2015-05-11 7:27 UTC (permalink / raw)
To: gdb-patches
Most of suggestion have been incorporated. However I wasnt able to find a better way to translate syscall
numbers from aarch64 to canonical.
Also arm v8 abi standard has x7 as an argument register. So i havnt changed that as well.
enum aarch64_syscall is still residing in aarch64-linux-tdep.h because if found that similar enums for other architectures are also defined in header files.
gdb:
2015-05-11 Omair Javaid <omair.javaid@linaro.org>
* aarch64-linux-tdep.c (linux-record.h): Include.
(record-full.h): Include.
(struct linux_record_tdep aarch64_linux_record_tdep): Declare.
(aarch64_canonicalize_syscall): New function.
(aarch64_all_but_pc_registers_record): New function.
(aarch64_linux_syscall_record): New function.
(aarch64_linux_init_abi): Update to handle syscall recording.
* aarch64-linux-tdep.h (aarch64_syscall): New enum.
* aarch64-tdep.c (aarch64_record_branch_except_sys): Add code to
handle recording of syscalls.
* aarch64-tdep.h
(struct gdbarch_tdep) <aarch64_syscall_record>: Defined.
* linux-record.h (struct linux_record_tdep): Add two more syscall
argument fields.
* configure.tgt: Add linux-record.o to gdb_target_obs.
---
gdb/aarch64-linux-tdep.c | 914 +++++++++++++++++++++++++++++++++++++++++++++++
gdb/aarch64-linux-tdep.h | 266 ++++++++++++++
gdb/aarch64-tdep.c | 16 +-
gdb/aarch64-tdep.h | 3 +
gdb/configure.tgt | 2 +-
gdb/linux-record.h | 2 +
6 files changed, 1201 insertions(+), 2 deletions(-)
diff --git a/gdb/aarch64-linux-tdep.c b/gdb/aarch64-linux-tdep.c
index e579858..ad2d0e2 100644
--- a/gdb/aarch64-linux-tdep.c
+++ b/gdb/aarch64-linux-tdep.c
@@ -42,6 +42,9 @@
#include "xml-syscall.h"
#include <ctype.h>
+#include "record-full.h"
+#include "linux-record.h"
+
/* Signal frame handling.
+------------+ ^
@@ -364,6 +367,753 @@ aarch64_linux_get_syscall_number (struct gdbarch *gdbarch,
return ret;
}
+/* AArch64 process record-replay constructs: syscall, signal etc. */
+
+struct linux_record_tdep aarch64_linux_record_tdep;
+
+/* aarch64_canonicalize_syscall maps syscall ids from the native AArch64
+ linux set of syscall ids into a canonical set of syscall ids used by
+ process record. */
+
+static enum gdb_syscall
+aarch64_canonicalize_syscall (enum aarch64_syscall syscall_number)
+{
+ switch (syscall_number) {
+ case aarch64_sys_read:
+ return gdb_sys_read;
+
+ case aarch64_sys_write:
+ return gdb_sys_write;
+
+ case aarch64_sys_open:
+ return gdb_sys_open;
+
+ case aarch64_sys_close:
+ return gdb_sys_close;
+
+ case aarch64_sys_lseek:
+ return gdb_sys_lseek;
+
+ case aarch64_sys_mprotect:
+ return gdb_sys_mprotect;
+
+ case aarch64_sys_munmap:
+ return gdb_sys_munmap;
+
+ case aarch64_sys_brk:
+ return gdb_sys_brk;
+
+ case aarch64_sys_rt_sigaction:
+ return gdb_sys_rt_sigaction;
+
+ case aarch64_sys_rt_sigprocmask:
+ return gdb_sys_rt_sigprocmask;
+
+ case aarch64_sys_rt_sigreturn:
+ return gdb_sys_rt_sigreturn;
+
+ case aarch64_sys_ioctl:
+ return gdb_sys_ioctl;
+
+ case aarch64_sys_pread64:
+ return gdb_sys_pread64;
+
+ case aarch64_sys_pwrite64:
+ return gdb_sys_pwrite64;
+
+ case aarch64_sys_readv:
+ return gdb_sys_readv;
+
+ case aarch64_sys_writev:
+ return gdb_sys_writev;
+
+ case aarch64_sys_sched_yield:
+ return gdb_sys_sched_yield;
+
+ case aarch64_sys_mremap:
+ return gdb_sys_mremap;
+
+ case aarch64_sys_msync:
+ return gdb_sys_msync;
+
+ case aarch64_sys_mincore:
+ return gdb_sys_mincore;
+
+ case aarch64_sys_madvise:
+ return gdb_sys_madvise;
+
+ case aarch64_sys_shmget:
+ return gdb_sys_shmget;
+
+ case aarch64_sys_shmat:
+ return gdb_sys_shmat;
+
+ case aarch64_sys_shmctl:
+ return gdb_sys_shmctl;
+
+ case aarch64_sys_dup:
+ return gdb_sys_dup;
+
+ case aarch64_sys_nanosleep:
+ return gdb_sys_nanosleep;
+
+ case aarch64_sys_getitimer:
+ return gdb_sys_getitimer;
+
+ case aarch64_sys_setitimer:
+ return gdb_sys_setitimer;
+
+ case aarch64_sys_getpid:
+ return gdb_sys_getpid;
+
+ case aarch64_sys_sendfile:
+ return gdb_sys_sendfile;
+
+ case aarch64_sys_socket:
+ return gdb_sys_socket;
+
+ case aarch64_sys_connect:
+ return gdb_sys_connect;
+
+ case aarch64_sys_accept:
+ return gdb_sys_accept;
+
+ case aarch64_sys_sendto:
+ return gdb_sys_sendto;
+
+ case aarch64_sys_recvfrom:
+ return gdb_sys_recvfrom;
+
+ case aarch64_sys_sendmsg:
+ return gdb_sys_sendmsg;
+
+ case aarch64_sys_recvmsg:
+ return gdb_sys_recvmsg;
+
+ case aarch64_sys_shutdown:
+ return gdb_sys_shutdown;
+
+ case aarch64_sys_bind:
+ return gdb_sys_bind;
+
+ case aarch64_sys_listen:
+ return gdb_sys_listen;
+
+ case aarch64_sys_getsockname:
+ return gdb_sys_getsockname;
+
+ case aarch64_sys_getpeername:
+ return gdb_sys_getpeername;
+
+ case aarch64_sys_socketpair:
+ return gdb_sys_socketpair;
+
+ case aarch64_sys_setsockopt:
+ return gdb_sys_setsockopt;
+
+ case aarch64_sys_getsockopt:
+ return gdb_sys_getsockopt;
+
+ case aarch64_sys_clone:
+ return gdb_sys_clone;
+
+ case aarch64_sys_execve:
+ return gdb_sys_execve;
+
+ case aarch64_sys_exit:
+ return gdb_sys_exit;
+
+ case aarch64_sys_wait4:
+ return gdb_sys_wait4;
+
+ case aarch64_sys_kill:
+ return gdb_sys_kill;
+
+ case aarch64_sys_uname:
+ return gdb_sys_uname;
+
+ case aarch64_sys_semget:
+ return gdb_sys_semget;
+
+ case aarch64_sys_semop:
+ return gdb_sys_semop;
+
+ case aarch64_sys_semctl:
+ return gdb_sys_semctl;
+
+ case aarch64_sys_shmdt:
+ return gdb_sys_shmdt;
+
+ case aarch64_sys_msgget:
+ return gdb_sys_msgget;
+
+ case aarch64_sys_msgsnd:
+ return gdb_sys_msgsnd;
+
+ case aarch64_sys_msgrcv:
+ return gdb_sys_msgrcv;
+
+ case aarch64_sys_msgctl:
+ return gdb_sys_msgctl;
+
+ case aarch64_sys_fcntl:
+ return gdb_sys_fcntl;
+
+ case aarch64_sys_flock:
+ return gdb_sys_flock;
+
+ case aarch64_sys_fsync:
+ return gdb_sys_fsync;
+
+ case aarch64_sys_fdatasync:
+ return gdb_sys_fdatasync;
+
+ case aarch64_sys_truncate:
+ return gdb_sys_truncate;
+
+ case aarch64_sys_ftruncate:
+ return gdb_sys_ftruncate;
+
+ case aarch64_sys_getcwd:
+ return gdb_sys_getcwd;
+
+ case aarch64_sys_chdir:
+ return gdb_sys_chdir;
+
+ case aarch64_sys_fchdir:
+ return gdb_sys_fchdir;
+
+ case aarch64_sys_rename:
+ return gdb_sys_rename;
+
+ case aarch64_sys_mkdir:
+ return gdb_sys_mkdir;
+
+ case aarch64_sys_link:
+ return gdb_sys_link;
+
+ case aarch64_sys_unlink:
+ return gdb_sys_unlink;
+
+ case aarch64_sys_symlink:
+ return gdb_sys_symlink;
+
+ case aarch64_sys_readlink:
+ return gdb_sys_readlink;
+
+ case aarch64_sys_fchmodat:
+ return gdb_sys_fchmodat;
+
+ case aarch64_sys_fchmod:
+ return gdb_sys_fchmod;
+
+ case aarch64_sys_fchownat:
+ return gdb_sys_fchownat;
+
+ case aarch64_sys_fchown:
+ return gdb_sys_fchown;
+
+ case aarch64_sys_umask:
+ return gdb_sys_umask;
+
+ case aarch64_sys_gettimeofday:
+ return gdb_sys_gettimeofday;
+
+ case aarch64_sys_getrlimit:
+ return gdb_sys_getrlimit;
+
+ case aarch64_sys_getrusage:
+ return gdb_sys_getrusage;
+
+ case aarch64_sys_sysinfo:
+ return gdb_sys_sysinfo;
+
+ case aarch64_sys_ptrace:
+ return gdb_sys_ptrace;
+
+ case aarch64_sys_getuid:
+ return gdb_sys_getuid;
+
+ case aarch64_sys_syslog:
+ return gdb_sys_syslog;
+
+ case aarch64_sys_getgid:
+ return gdb_sys_getgid;
+
+ case aarch64_sys_setuid:
+ return gdb_sys_setuid;
+
+ case aarch64_sys_setgid:
+ return gdb_sys_setgid;
+
+ case aarch64_sys_geteuid:
+ return gdb_sys_geteuid;
+
+ case aarch64_sys_getegid:
+ return gdb_sys_getegid;
+
+ case aarch64_sys_setpgid:
+ return gdb_sys_setpgid;
+
+ case aarch64_sys_getppid:
+ return gdb_sys_getppid;
+
+ case aarch64_sys_setsid:
+ return gdb_sys_setsid;
+
+ case aarch64_sys_setreuid:
+ return gdb_sys_setreuid;
+
+ case aarch64_sys_setregid:
+ return gdb_sys_setregid;
+
+ case aarch64_sys_getgroups:
+ return gdb_sys_getgroups;
+
+ case aarch64_sys_setgroups:
+ return gdb_sys_setgroups;
+
+ case aarch64_sys_setresuid:
+ return gdb_sys_setresuid;
+
+ case aarch64_sys_getresuid:
+ return gdb_sys_getresuid;
+
+ case aarch64_sys_setresgid:
+ return gdb_sys_setresgid;
+
+ case aarch64_sys_getresgid:
+ return gdb_sys_getresgid;
+
+ case aarch64_sys_getpgid:
+ return gdb_sys_getpgid;
+
+ case aarch64_sys_setfsuid:
+ return gdb_sys_setfsuid;
+
+ case aarch64_sys_setfsgid:
+ return gdb_sys_setfsgid;
+
+ case aarch64_sys_getsid:
+ return gdb_sys_getsid;
+
+ case aarch64_sys_capget:
+ return gdb_sys_capget;
+
+ case aarch64_sys_capset:
+ return gdb_sys_capset;
+
+ case aarch64_sys_rt_sigpending:
+ return gdb_sys_rt_sigpending;
+
+ case aarch64_sys_rt_sigtimedwait:
+ return gdb_sys_rt_sigtimedwait;
+
+ case aarch64_sys_rt_sigqueueinfo:
+ return gdb_sys_rt_sigqueueinfo;
+
+ case aarch64_sys_rt_sigsuspend:
+ return gdb_sys_rt_sigsuspend;
+
+ case aarch64_sys_sigaltstack:
+ return gdb_sys_sigaltstack;
+
+ case aarch64_sys_mknod:
+ return gdb_sys_mknod;
+
+ case aarch64_sys_personality:
+ return gdb_sys_personality;
+
+ case aarch64_sys_statfs:
+ return gdb_sys_statfs;
+
+ case aarch64_sys_fstat:
+ return gdb_sys_fstat;
+
+ case aarch64_sys_fstatfs:
+ return gdb_sys_fstatfs;
+
+ case aarch64_sys_getpriority:
+ return gdb_sys_getpriority;
+
+ case aarch64_sys_setpriority:
+ return gdb_sys_setpriority;
+
+ case aarch64_sys_sched_setparam:
+ return gdb_sys_sched_setparam;
+
+ case aarch64_sys_sched_getparam:
+ return gdb_sys_sched_getparam;
+
+ case aarch64_sys_sched_setscheduler:
+ return gdb_sys_sched_setscheduler;
+
+ case aarch64_sys_sched_getscheduler:
+ return gdb_sys_sched_getscheduler;
+
+ case aarch64_sys_sched_get_priority_max:
+ return gdb_sys_sched_get_priority_max;
+
+ case aarch64_sys_sched_get_priority_min:
+ return gdb_sys_sched_get_priority_min;
+
+ case aarch64_sys_sched_rr_get_interval:
+ return gdb_sys_sched_rr_get_interval;
+
+ case aarch64_sys_mlock:
+ return gdb_sys_mlock;
+
+ case aarch64_sys_munlock:
+ return gdb_sys_munlock;
+
+ case aarch64_sys_mlockall:
+ return gdb_sys_mlockall;
+
+ case aarch64_sys_munlockall:
+ return gdb_sys_munlockall;
+
+ case aarch64_sys_vhangup:
+ return gdb_sys_vhangup;
+
+ case aarch64_sys_prctl:
+ return gdb_sys_prctl;
+
+ case aarch64_sys_adjtimex:
+ return gdb_sys_adjtimex;
+
+ case aarch64_sys_setrlimit:
+ return gdb_sys_setrlimit;
+
+ case aarch64_sys_chroot:
+ return gdb_sys_chroot;
+
+ case aarch64_sys_sync:
+ return gdb_sys_sync;
+
+ case aarch64_sys_acct:
+ return gdb_sys_acct;
+
+ case aarch64_sys_settimeofday:
+ return gdb_sys_settimeofday;
+
+ case aarch64_sys_mount:
+ return gdb_sys_mount;
+
+ case aarch64_sys_swapon:
+ return gdb_sys_swapon;
+
+ case aarch64_sys_swapoff:
+ return gdb_sys_swapoff;
+
+ case aarch64_sys_reboot:
+ return gdb_sys_reboot;
+
+ case aarch64_sys_sethostname:
+ return gdb_sys_sethostname;
+
+ case aarch64_sys_setdomainname:
+ return gdb_sys_setdomainname;
+
+ case aarch64_sys_init_module:
+ return gdb_sys_init_module;
+
+ case aarch64_sys_delete_module:
+ return gdb_sys_delete_module;
+
+ case aarch64_sys_quotactl:
+ return gdb_sys_quotactl;
+
+ case aarch64_sys_nfsservctl:
+ return gdb_sys_nfsservctl;
+
+ case aarch64_sys_gettid:
+ return gdb_sys_gettid;
+
+ case aarch64_sys_readahead:
+ return gdb_sys_readahead;
+
+ case aarch64_sys_setxattr:
+ return gdb_sys_setxattr;
+
+ case aarch64_sys_lsetxattr:
+ return gdb_sys_lsetxattr;
+
+ case aarch64_sys_fsetxattr:
+ return gdb_sys_fsetxattr;
+
+ case aarch64_sys_getxattr:
+ return gdb_sys_getxattr;
+
+ case aarch64_sys_lgetxattr:
+ return gdb_sys_lgetxattr;
+
+ case aarch64_sys_fgetxattr:
+ return gdb_sys_fgetxattr;
+
+ case aarch64_sys_listxattr:
+ return gdb_sys_listxattr;
+
+ case aarch64_sys_llistxattr:
+ return gdb_sys_llistxattr;
+
+ case aarch64_sys_flistxattr:
+ return gdb_sys_flistxattr;
+
+ case aarch64_sys_removexattr:
+ return gdb_sys_removexattr;
+
+ case aarch64_sys_lremovexattr:
+ return gdb_sys_lremovexattr;
+
+ case aarch64_sys_fremovexattr:
+ return gdb_sys_fremovexattr;
+
+ case aarch64_sys_tkill:
+ return gdb_sys_tkill;
+
+ case aarch64_sys_times:
+ return gdb_sys_times;
+
+ case aarch64_sys_futex:
+ return gdb_sys_futex;
+
+ case aarch64_sys_sched_setaffinity:
+ return gdb_sys_sched_setaffinity;
+
+ case aarch64_sys_sched_getaffinity:
+ return gdb_sys_sched_getaffinity;
+
+ case aarch64_sys_io_setup:
+ return gdb_sys_io_setup;
+
+ case aarch64_sys_io_destroy:
+ return gdb_sys_io_destroy;
+
+ case aarch64_sys_io_getevents:
+ return gdb_sys_io_getevents;
+
+ case aarch64_sys_io_submit:
+ return gdb_sys_io_submit;
+
+ case aarch64_sys_io_cancel:
+ return gdb_sys_io_cancel;
+
+ case aarch64_sys_lookup_dcookie:
+ return gdb_sys_lookup_dcookie;
+
+ case aarch64_sys_epoll_create1:
+ return gdb_sys_epoll_create;
+
+ case aarch64_sys_remap_file_pages:
+ return gdb_sys_remap_file_pages;
+
+ case aarch64_sys_getdents64:
+ return gdb_sys_getdents64;
+
+ case aarch64_sys_set_tid_address:
+ return gdb_sys_set_tid_address;
+
+ case aarch64_sys_semtimedop:
+ return gdb_sys_semtimedop;
+
+ case aarch64_sys_fadvise64:
+ return gdb_sys_fadvise64;
+
+ case aarch64_sys_timer_create:
+ return gdb_sys_timer_create;
+
+ case aarch64_sys_timer_settime:
+ return gdb_sys_timer_settime;
+
+ case aarch64_sys_timer_gettime:
+ return gdb_sys_timer_gettime;
+
+ case aarch64_sys_timer_getoverrun:
+ return gdb_sys_timer_getoverrun;
+
+ case aarch64_sys_timer_delete:
+ return gdb_sys_timer_delete;
+
+ case aarch64_sys_clock_settime:
+ return gdb_sys_clock_settime;
+
+ case aarch64_sys_clock_gettime:
+ return gdb_sys_clock_gettime;
+
+ case aarch64_sys_clock_getres:
+ return gdb_sys_clock_getres;
+
+ case aarch64_sys_clock_nanosleep:
+ return gdb_sys_clock_nanosleep;
+
+ case aarch64_sys_exit_group:
+ return gdb_sys_exit_group;
+
+ case aarch64_sys_epoll_pwait:
+ return gdb_sys_epoll_pwait;
+
+ case aarch64_sys_epoll_ctl:
+ return gdb_sys_epoll_ctl;
+
+ case aarch64_sys_tgkill:
+ return gdb_sys_tgkill;
+
+ case aarch64_sys_mbind:
+ return gdb_sys_mbind;
+
+ case aarch64_sys_set_mempolicy:
+ return gdb_sys_set_mempolicy;
+
+ case aarch64_sys_get_mempolicy:
+ return gdb_sys_get_mempolicy;
+
+ case aarch64_sys_mq_open:
+ return gdb_sys_mq_open;
+
+ case aarch64_sys_mq_unlink:
+ return gdb_sys_mq_unlink;
+
+ case aarch64_sys_mq_timedsend:
+ return gdb_sys_mq_timedsend;
+
+ case aarch64_sys_mq_timedreceive:
+ return gdb_sys_mq_timedreceive;
+
+ case aarch64_sys_mq_notify:
+ return gdb_sys_mq_notify;
+
+ case aarch64_sys_mq_getsetattr:
+ return gdb_sys_mq_getsetattr;
+
+ case aarch64_sys_kexec_load:
+ return gdb_sys_kexec_load;
+
+ case aarch64_sys_waitid:
+ return gdb_sys_waitid;
+
+ case aarch64_sys_add_key:
+ return gdb_sys_add_key;
+
+ case aarch64_sys_request_key:
+ return gdb_sys_request_key;
+
+ case aarch64_sys_keyctl:
+ return gdb_sys_keyctl;
+
+ case aarch64_sys_ioprio_set:
+ return gdb_sys_ioprio_set;
+
+ case aarch64_sys_ioprio_get:
+ return gdb_sys_ioprio_get;
+
+ case aarch64_sys_inotify_add_watch:
+ return gdb_sys_inotify_add_watch;
+
+ case aarch64_sys_inotify_rm_watch:
+ return gdb_sys_inotify_rm_watch;
+
+ case aarch64_sys_migrate_pages:
+ return gdb_sys_migrate_pages;
+
+ case aarch64_sys_pselect6:
+ return gdb_sys_pselect6;
+
+ case aarch64_sys_ppoll:
+ return gdb_sys_ppoll;
+
+ case aarch64_sys_unshare:
+ return gdb_sys_unshare;
+
+ case aarch64_sys_set_robust_list:
+ return gdb_sys_set_robust_list;
+
+ case aarch64_sys_get_robust_list:
+ return gdb_sys_get_robust_list;
+
+ case aarch64_sys_splice:
+ return gdb_sys_splice;
+
+ case aarch64_sys_tee:
+ return gdb_sys_tee;
+
+ case aarch64_sys_sync_file_range:
+ return gdb_sys_sync_file_range;
+
+ case aarch64_sys_vmsplice:
+ return gdb_sys_vmsplice;
+
+ case aarch64_sys_move_pages:
+ return gdb_sys_move_pages;
+
+ case aarch64_sys_mmap:
+ return gdb_sys_mmap2;
+
+ default:
+ return -1;
+ }
+}
+
+/* Record all registers but PC register for process-record. */
+
+static int
+aarch64_all_but_pc_registers_record (struct regcache *regcache)
+{
+ int i;
+
+ for (i = AARCH64_X0_REGNUM; i < AARCH64_PC_REGNUM; i++)
+ if (record_full_arch_list_add_reg (regcache, i))
+ return -1;
+
+ if (record_full_arch_list_add_reg (regcache, AARCH64_CPSR_REGNUM))
+ return -1;
+
+ return 0;
+}
+
+/* Handler for arm system call instruction recording. */
+
+static int
+aarch64_linux_syscall_record (struct regcache *regcache, unsigned long svc_number)
+{
+ int ret = 0;
+ enum gdb_syscall syscall_gdb;
+
+ syscall_gdb = aarch64_canonicalize_syscall (svc_number);
+
+ if (syscall_gdb < 0)
+ {
+ printf_unfiltered (_("Process record and replay target doesn't "
+ "support syscall number %s\n"),
+ plongest (svc_number));
+ return -1;
+ }
+
+ if (syscall_gdb == gdb_sys_sigreturn
+ || syscall_gdb == gdb_sys_rt_sigreturn)
+ {
+ if (aarch64_all_but_pc_registers_record (regcache))
+ return -1;
+ return 0;
+ }
+
+ ret = record_linux_system_call (syscall_gdb, regcache,
+ &aarch64_linux_record_tdep);
+ if (ret != 0)
+ return ret;
+
+ /* Record the return value of the system call. */
+ if (record_full_arch_list_add_reg (regcache, AARCH64_X0_REGNUM))
+ return -1;
+ /* Record LR. */
+ if (record_full_arch_list_add_reg (regcache, AARCH64_LR_REGNUM))
+ return -1;
+ /* Record CPSR. */
+ if (record_full_arch_list_add_reg (regcache, AARCH64_CPSR_REGNUM))
+ return -1;
+
+ return 0;
+}
+
static void
aarch64_linux_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
{
@@ -411,6 +1161,170 @@ aarch64_linux_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
/* Reversible debugging, process record. */
set_gdbarch_process_record (gdbarch, aarch64_process_record);
+ /* Syscall record. */
+ tdep->aarch64_syscall_record = aarch64_linux_syscall_record;
+
+ /* Initialize the aarch64_linux_record_tdep. */
+ /* These values are the size of the type that will be used in a system
+ call. They are obtained from Linux Kernel source. */
+ aarch64_linux_record_tdep.size_pointer
+ = gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT;
+ aarch64_linux_record_tdep.size__old_kernel_stat = 32;
+ aarch64_linux_record_tdep.size_tms = 32;
+ aarch64_linux_record_tdep.size_loff_t = 8;
+ aarch64_linux_record_tdep.size_flock = 32;
+ aarch64_linux_record_tdep.size_oldold_utsname = 45;
+ aarch64_linux_record_tdep.size_ustat = 32;
+ aarch64_linux_record_tdep.size_old_sigaction = 152;
+ aarch64_linux_record_tdep.size_old_sigset_t = 128;
+ aarch64_linux_record_tdep.size_rlimit = 16;
+ aarch64_linux_record_tdep.size_rusage = 144;
+ aarch64_linux_record_tdep.size_timeval = 16;
+ aarch64_linux_record_tdep.size_timezone = 8;
+ aarch64_linux_record_tdep.size_old_gid_t = 2;
+ aarch64_linux_record_tdep.size_old_uid_t = 2;
+ aarch64_linux_record_tdep.size_fd_set = 128;
+ aarch64_linux_record_tdep.size_dirent = 280;
+ aarch64_linux_record_tdep.size_dirent64 = 280;
+ aarch64_linux_record_tdep.size_statfs = 120;
+ aarch64_linux_record_tdep.size_statfs64 = 120;
+ aarch64_linux_record_tdep.size_sockaddr = 16;
+ aarch64_linux_record_tdep.size_int
+ = gdbarch_int_bit (gdbarch) / TARGET_CHAR_BIT;
+ aarch64_linux_record_tdep.size_long
+ = gdbarch_long_bit (gdbarch) / TARGET_CHAR_BIT;
+ aarch64_linux_record_tdep.size_ulong
+ = gdbarch_long_bit (gdbarch) / TARGET_CHAR_BIT;
+ aarch64_linux_record_tdep.size_msghdr = 56;
+ aarch64_linux_record_tdep.size_itimerval = 32;
+ aarch64_linux_record_tdep.size_stat = 144;
+ aarch64_linux_record_tdep.size_old_utsname = 325;
+ aarch64_linux_record_tdep.size_sysinfo = 112;
+ aarch64_linux_record_tdep.size_msqid_ds = 120;
+ aarch64_linux_record_tdep.size_shmid_ds = 112;
+ aarch64_linux_record_tdep.size_new_utsname = 390;
+ aarch64_linux_record_tdep.size_timex = 208;
+ aarch64_linux_record_tdep.size_mem_dqinfo = 24;
+ aarch64_linux_record_tdep.size_if_dqblk = 72;
+ aarch64_linux_record_tdep.size_fs_quota_stat = 80;
+ aarch64_linux_record_tdep.size_timespec = 16;
+ aarch64_linux_record_tdep.size_pollfd = 8;
+ aarch64_linux_record_tdep.size_NFS_FHSIZE = 32;
+ aarch64_linux_record_tdep.size_knfsd_fh = 132;
+ aarch64_linux_record_tdep.size_TASK_COMM_LEN = 16;
+ aarch64_linux_record_tdep.size_sigaction = 152;
+ aarch64_linux_record_tdep.size_sigset_t = 128;
+ aarch64_linux_record_tdep.size_siginfo_t = 128;
+ aarch64_linux_record_tdep.size_cap_user_data_t = 8;
+ aarch64_linux_record_tdep.size_stack_t = 24;
+ aarch64_linux_record_tdep.size_off_t = 8;
+ aarch64_linux_record_tdep.size_stat64 = 144;
+ aarch64_linux_record_tdep.size_gid_t = 4;
+ aarch64_linux_record_tdep.size_uid_t = 4;
+ aarch64_linux_record_tdep.size_PAGE_SIZE = 4096;
+ aarch64_linux_record_tdep.size_flock64 = 32;
+ aarch64_linux_record_tdep.size_user_desc = 16;
+ aarch64_linux_record_tdep.size_io_event = 32;
+ aarch64_linux_record_tdep.size_iocb = 64;
+ aarch64_linux_record_tdep.size_epoll_event = 12;
+ aarch64_linux_record_tdep.size_itimerspec = 32;
+ aarch64_linux_record_tdep.size_mq_attr = 64;
+ aarch64_linux_record_tdep.size_siginfo = 128;
+ aarch64_linux_record_tdep.size_termios = 60;
+ aarch64_linux_record_tdep.size_termios2 = 44;
+ aarch64_linux_record_tdep.size_pid_t = 4;
+ aarch64_linux_record_tdep.size_winsize = 8;
+ aarch64_linux_record_tdep.size_serial_struct = 72;
+ aarch64_linux_record_tdep.size_serial_icounter_struct = 80;
+ aarch64_linux_record_tdep.size_hayes_esp_config = 12;
+ aarch64_linux_record_tdep.size_size_t = 8;
+ aarch64_linux_record_tdep.size_iovec = 16;
+
+ /* These values are the second argument of system call "sys_ioctl".
+ They are obtained from Linux Kernel source. */
+ aarch64_linux_record_tdep.ioctl_TCGETS = 0x5401;
+ aarch64_linux_record_tdep.ioctl_TCSETS = 0x5402;
+ aarch64_linux_record_tdep.ioctl_TCSETSW = 0x5403;
+ aarch64_linux_record_tdep.ioctl_TCSETSF = 0x5404;
+ aarch64_linux_record_tdep.ioctl_TCGETA = 0x5405;
+ aarch64_linux_record_tdep.ioctl_TCSETA = 0x5406;
+ aarch64_linux_record_tdep.ioctl_TCSETAW = 0x5407;
+ aarch64_linux_record_tdep.ioctl_TCSETAF = 0x5408;
+ aarch64_linux_record_tdep.ioctl_TCSBRK = 0x5409;
+ aarch64_linux_record_tdep.ioctl_TCXONC = 0x540a;
+ aarch64_linux_record_tdep.ioctl_TCFLSH = 0x540b;
+ aarch64_linux_record_tdep.ioctl_TIOCEXCL = 0x540c;
+ aarch64_linux_record_tdep.ioctl_TIOCNXCL = 0x540d;
+ aarch64_linux_record_tdep.ioctl_TIOCSCTTY = 0x540e;
+ aarch64_linux_record_tdep.ioctl_TIOCGPGRP = 0x540f;
+ aarch64_linux_record_tdep.ioctl_TIOCSPGRP = 0x5410;
+ aarch64_linux_record_tdep.ioctl_TIOCOUTQ = 0x5411;
+ aarch64_linux_record_tdep.ioctl_TIOCSTI = 0x5412;
+ aarch64_linux_record_tdep.ioctl_TIOCGWINSZ = 0x5413;
+ aarch64_linux_record_tdep.ioctl_TIOCSWINSZ = 0x5414;
+ aarch64_linux_record_tdep.ioctl_TIOCMGET = 0x5415;
+ aarch64_linux_record_tdep.ioctl_TIOCMBIS = 0x5416;
+ aarch64_linux_record_tdep.ioctl_TIOCMBIC = 0x5417;
+ aarch64_linux_record_tdep.ioctl_TIOCMSET = 0x5418;
+ aarch64_linux_record_tdep.ioctl_TIOCGSOFTCAR = 0x5419;
+ aarch64_linux_record_tdep.ioctl_TIOCSSOFTCAR = 0x541a;
+ aarch64_linux_record_tdep.ioctl_FIONREAD = 0x541b;
+ aarch64_linux_record_tdep.ioctl_TIOCINQ = 0x541b;
+ aarch64_linux_record_tdep.ioctl_TIOCLINUX = 0x541c;
+ aarch64_linux_record_tdep.ioctl_TIOCCONS = 0x541d;
+ aarch64_linux_record_tdep.ioctl_TIOCGSERIAL = 0x541e;
+ aarch64_linux_record_tdep.ioctl_TIOCSSERIAL = 0x541f;
+ aarch64_linux_record_tdep.ioctl_TIOCPKT = 0x5420;
+ aarch64_linux_record_tdep.ioctl_FIONBIO = 0x5421;
+ aarch64_linux_record_tdep.ioctl_TIOCNOTTY = 0x5422;
+ aarch64_linux_record_tdep.ioctl_TIOCSETD = 0x5423;
+ aarch64_linux_record_tdep.ioctl_TIOCGETD = 0x5424;
+ aarch64_linux_record_tdep.ioctl_TCSBRKP = 0x5425;
+ aarch64_linux_record_tdep.ioctl_TIOCTTYGSTRUCT = 0x5426;
+ aarch64_linux_record_tdep.ioctl_TIOCSBRK = 0x5427;
+ aarch64_linux_record_tdep.ioctl_TIOCCBRK = 0x5428;
+ aarch64_linux_record_tdep.ioctl_TIOCGSID = 0x5429;
+ aarch64_linux_record_tdep.ioctl_TCGETS2 = 0x802c542a;
+ aarch64_linux_record_tdep.ioctl_TCSETS2 = 0x402c542b;
+ aarch64_linux_record_tdep.ioctl_TCSETSW2 = 0x402c542c;
+ aarch64_linux_record_tdep.ioctl_TCSETSF2 = 0x402c542d;
+ aarch64_linux_record_tdep.ioctl_TIOCGPTN = 0x80045430;
+ aarch64_linux_record_tdep.ioctl_TIOCSPTLCK = 0x40045431;
+ aarch64_linux_record_tdep.ioctl_FIONCLEX = 0x5450;
+ aarch64_linux_record_tdep.ioctl_FIOCLEX = 0x5451;
+ aarch64_linux_record_tdep.ioctl_FIOASYNC = 0x5452;
+ aarch64_linux_record_tdep.ioctl_TIOCSERCONFIG = 0x5453;
+ aarch64_linux_record_tdep.ioctl_TIOCSERGWILD = 0x5454;
+ aarch64_linux_record_tdep.ioctl_TIOCSERSWILD = 0x5455;
+ aarch64_linux_record_tdep.ioctl_TIOCGLCKTRMIOS = 0x5456;
+ aarch64_linux_record_tdep.ioctl_TIOCSLCKTRMIOS = 0x5457;
+ aarch64_linux_record_tdep.ioctl_TIOCSERGSTRUCT = 0x5458;
+ aarch64_linux_record_tdep.ioctl_TIOCSERGETLSR = 0x5459;
+ aarch64_linux_record_tdep.ioctl_TIOCSERGETMULTI = 0x545a;
+ aarch64_linux_record_tdep.ioctl_TIOCSERSETMULTI = 0x545b;
+ aarch64_linux_record_tdep.ioctl_TIOCMIWAIT = 0x545c;
+ aarch64_linux_record_tdep.ioctl_TIOCGICOUNT = 0x545d;
+ aarch64_linux_record_tdep.ioctl_TIOCGHAYESESP = 0x545e;
+ aarch64_linux_record_tdep.ioctl_TIOCSHAYESESP = 0x545f;
+ aarch64_linux_record_tdep.ioctl_FIOQSIZE = 0x5460;
+
+ /* These values are the second argument of system call "sys_fcntl"
+ and "sys_fcntl64". They are obtained from Linux Kernel source. */
+ aarch64_linux_record_tdep.fcntl_F_GETLK = 5;
+ aarch64_linux_record_tdep.fcntl_F_GETLK64 = 12;
+ aarch64_linux_record_tdep.fcntl_F_SETLK64 = 13;
+ aarch64_linux_record_tdep.fcntl_F_SETLKW64 = 14;
+
+ /* The AArch64 syscall calling convention: reg x0-x7 for arguments,
+ reg x8 for syscall number and return value in reg x0. */
+ aarch64_linux_record_tdep.arg1 = AARCH64_X0_REGNUM + 0;
+ aarch64_linux_record_tdep.arg2 = AARCH64_X0_REGNUM + 1;
+ aarch64_linux_record_tdep.arg3 = AARCH64_X0_REGNUM + 2;
+ aarch64_linux_record_tdep.arg4 = AARCH64_X0_REGNUM + 3;
+ aarch64_linux_record_tdep.arg5 = AARCH64_X0_REGNUM + 4;
+ aarch64_linux_record_tdep.arg6 = AARCH64_X0_REGNUM + 5;
+ aarch64_linux_record_tdep.arg7 = AARCH64_X0_REGNUM + 6;
+ aarch64_linux_record_tdep.arg8 = AARCH64_X0_REGNUM + 7;
/* `catch syscall' */
set_xml_syscall_file_name (gdbarch, "syscalls/aarch64-linux.xml");
diff --git a/gdb/aarch64-linux-tdep.h b/gdb/aarch64-linux-tdep.h
index 9d09ae6..4475f2e 100644
--- a/gdb/aarch64-linux-tdep.h
+++ b/gdb/aarch64-linux-tdep.h
@@ -32,3 +32,269 @@
extern const struct regset aarch64_linux_gregset;
extern const struct regset aarch64_linux_fpregset;
+
+/* Enum that defines the AArch64 linux specific syscall identifiers used for
+ process record/replay. */
+
+enum aarch64_syscall {
+ aarch64_sys_io_setup = 0,
+ aarch64_sys_io_destroy = 1,
+ aarch64_sys_io_submit = 2,
+ aarch64_sys_io_cancel = 3,
+ aarch64_sys_io_getevents = 4,
+ aarch64_sys_setxattr = 5,
+ aarch64_sys_lsetxattr = 6,
+ aarch64_sys_fsetxattr = 7,
+ aarch64_sys_getxattr = 8,
+ aarch64_sys_lgetxattr = 9,
+ aarch64_sys_fgetxattr = 10,
+ aarch64_sys_listxattr = 11,
+ aarch64_sys_llistxattr = 12,
+ aarch64_sys_flistxattr = 13,
+ aarch64_sys_removexattr = 14,
+ aarch64_sys_lremovexattr = 15,
+ aarch64_sys_fremovexattr = 16,
+ aarch64_sys_getcwd = 17,
+ aarch64_sys_lookup_dcookie = 18,
+ aarch64_sys_eventfd2 = 19,
+ aarch64_sys_epoll_create1 = 20,
+ aarch64_sys_epoll_ctl = 21,
+ aarch64_sys_epoll_pwait = 22,
+ aarch64_sys_dup = 23,
+ aarch64_sys_dup3 = 24,
+ aarch64_sys_fcntl = 25,
+ aarch64_sys_inotify_init1 = 26,
+ aarch64_sys_inotify_add_watch = 27,
+ aarch64_sys_inotify_rm_watch = 28,
+ aarch64_sys_ioctl = 29,
+ aarch64_sys_ioprio_set = 30,
+ aarch64_sys_ioprio_get = 31,
+ aarch64_sys_flock = 32,
+ aarch64_sys_mknod = 33,
+ aarch64_sys_mkdir = 34,
+ aarch64_sys_unlink = 35,
+ aarch64_sys_symlink = 36,
+ aarch64_sys_link = 37,
+ aarch64_sys_rename = 38,
+ aarch64_sys_umount2 = 39,
+ aarch64_sys_mount = 40,
+ aarch64_sys_pivot_root = 41,
+ aarch64_sys_nfsservctl = 42,
+ aarch64_sys_statfs = 43,
+ aarch64_sys_fstatfs = 44,
+ aarch64_sys_truncate = 45,
+ aarch64_sys_ftruncate = 46,
+ aarch64_sys_fallocate = 47,
+ aarch64_sys_faccess = 48,
+ aarch64_sys_chdir = 49,
+ aarch64_sys_fchdir = 50,
+ aarch64_sys_chroot = 51,
+ aarch64_sys_fchmod = 52,
+ aarch64_sys_fchmodat = 53,
+ aarch64_sys_fchownat = 54,
+ aarch64_sys_fchown = 55,
+ aarch64_sys_open = 56,
+ aarch64_sys_close = 57,
+ aarch64_sys_vhangup = 58,
+ aarch64_sys_pipe2 = 59,
+ aarch64_sys_quotactl = 60,
+ aarch64_sys_getdents64 = 61,
+ aarch64_sys_lseek = 62,
+ aarch64_sys_read = 63,
+ aarch64_sys_write = 64,
+ aarch64_sys_readv = 65,
+ aarch64_sys_writev = 66,
+ aarch64_sys_pread64 = 67,
+ aarch64_sys_pwrite64 = 68,
+ aarch64_sys_preadv = 69,
+ aarch64_sys_pwritev = 70,
+ aarch64_sys_sendfile = 71,
+ aarch64_sys_pselect6 = 72,
+ aarch64_sys_ppoll = 73,
+ aarch64_sys_signalfd4 = 74,
+ aarch64_sys_vmsplice = 75,
+ aarch64_sys_splice = 76,
+ aarch64_sys_tee = 77,
+ aarch64_sys_readlink = 78,
+ aarch64_sys_fstatat = 79,
+ aarch64_sys_fstat = 80,
+ aarch64_sys_sync = 81,
+ aarch64_sys_fsync = 82,
+ aarch64_sys_fdatasync = 83,
+ aarch64_sys_sync_file_range2 = 84,
+ aarch64_sys_sync_file_range = 84,
+ aarch64_sys_timerfd_create = 85,
+ aarch64_sys_timerfd_settime = 86,
+ aarch64_sys_timerfd_gettime = 87,
+ aarch64_sys_utimensat = 88,
+ aarch64_sys_acct = 89,
+ aarch64_sys_capget = 90,
+ aarch64_sys_capset = 91,
+ aarch64_sys_personality = 92,
+ aarch64_sys_exit = 93,
+ aarch64_sys_exit_group = 94,
+ aarch64_sys_waitid = 95,
+ aarch64_sys_set_tid_address = 96,
+ aarch64_sys_unshare = 97,
+ aarch64_sys_futex = 98,
+ aarch64_sys_set_robust_list = 99,
+ aarch64_sys_get_robust_list = 100,
+ aarch64_sys_nanosleep = 101,
+ aarch64_sys_getitimer = 102,
+ aarch64_sys_setitimer = 103,
+ aarch64_sys_kexec_load = 104,
+ aarch64_sys_init_module = 105,
+ aarch64_sys_delete_module = 106,
+ aarch64_sys_timer_create = 107,
+ aarch64_sys_timer_gettime = 108,
+ aarch64_sys_timer_getoverrun = 109,
+ aarch64_sys_timer_settime = 110,
+ aarch64_sys_timer_delete = 111,
+ aarch64_sys_clock_settime = 112,
+ aarch64_sys_clock_gettime = 113,
+ aarch64_sys_clock_getres = 114,
+ aarch64_sys_clock_nanosleep = 115,
+ aarch64_sys_syslog = 116,
+ aarch64_sys_ptrace = 117,
+ aarch64_sys_sched_setparam = 118,
+ aarch64_sys_sched_setscheduler = 119,
+ aarch64_sys_sched_getscheduler = 120,
+ aarch64_sys_sched_getparam = 121,
+ aarch64_sys_sched_setaffinity = 122,
+ aarch64_sys_sched_getaffinity = 123,
+ aarch64_sys_sched_yield = 124,
+ aarch64_sys_sched_get_priority_max = 125,
+ aarch64_sys_sched_get_priority_min = 126,
+ aarch64_sys_sched_rr_get_interval = 127,
+ aarch64_sys_kill = 129,
+ aarch64_sys_tkill = 130,
+ aarch64_sys_tgkill = 131,
+ aarch64_sys_sigaltstack = 132,
+ aarch64_sys_rt_sigsuspend = 133,
+ aarch64_sys_rt_sigaction = 134,
+ aarch64_sys_rt_sigprocmask = 135,
+ aarch64_sys_rt_sigpending = 136,
+ aarch64_sys_rt_sigtimedwait = 137,
+ aarch64_sys_rt_sigqueueinfo = 138,
+ aarch64_sys_rt_sigreturn = 139,
+ aarch64_sys_setpriority = 140,
+ aarch64_sys_getpriority = 141,
+ aarch64_sys_reboot = 142,
+ aarch64_sys_setregid = 143,
+ aarch64_sys_setgid = 144,
+ aarch64_sys_setreuid = 145,
+ aarch64_sys_setuid = 146,
+ aarch64_sys_setresuid = 147,
+ aarch64_sys_getresuid = 148,
+ aarch64_sys_setresgid = 149,
+ aarch64_sys_getresgid = 150,
+ aarch64_sys_setfsuid = 151,
+ aarch64_sys_setfsgid = 152,
+ aarch64_sys_times = 153,
+ aarch64_sys_setpgid = 154,
+ aarch64_sys_getpgid = 155,
+ aarch64_sys_getsid = 156,
+ aarch64_sys_setsid = 157,
+ aarch64_sys_getgroups = 158,
+ aarch64_sys_setgroups = 159,
+ aarch64_sys_uname = 160,
+ aarch64_sys_sethostname = 161,
+ aarch64_sys_setdomainname = 162,
+ aarch64_sys_getrlimit = 163,
+ aarch64_sys_setrlimit = 164,
+ aarch64_sys_getrusage = 165,
+ aarch64_sys_umask = 166,
+ aarch64_sys_prctl = 167,
+ aarch64_sys_getcpu = 168,
+ aarch64_sys_gettimeofday = 169,
+ aarch64_sys_settimeofday = 170,
+ aarch64_sys_adjtimex = 171,
+ aarch64_sys_getpid = 172,
+ aarch64_sys_getppid = 173,
+ aarch64_sys_getuid = 174,
+ aarch64_sys_geteuid = 175,
+ aarch64_sys_getgid = 176,
+ aarch64_sys_getegid = 177,
+ aarch64_sys_gettid = 178,
+ aarch64_sys_sysinfo = 179,
+ aarch64_sys_mq_open = 180,
+ aarch64_sys_mq_unlink = 181,
+ aarch64_sys_mq_timedsend = 182,
+ aarch64_sys_mq_timedreceive = 183,
+ aarch64_sys_mq_notify = 184,
+ aarch64_sys_mq_getsetattr = 185,
+ aarch64_sys_msgget = 186,
+ aarch64_sys_msgctl = 187,
+ aarch64_sys_msgrcv = 188,
+ aarch64_sys_msgsnd = 189,
+ aarch64_sys_semget = 190,
+ aarch64_sys_semctl = 191,
+ aarch64_sys_semtimedop = 192,
+ aarch64_sys_semop = 193,
+ aarch64_sys_shmget = 194,
+ aarch64_sys_shmctl = 195,
+ aarch64_sys_shmat = 196,
+ aarch64_sys_shmdt = 197,
+ aarch64_sys_socket = 198,
+ aarch64_sys_socketpair = 199,
+ aarch64_sys_bind = 200,
+ aarch64_sys_listen = 201,
+ aarch64_sys_accept = 202,
+ aarch64_sys_connect = 203,
+ aarch64_sys_getsockname = 204,
+ aarch64_sys_getpeername = 205,
+ aarch64_sys_sendto = 206,
+ aarch64_sys_recvfrom = 207,
+ aarch64_sys_setsockopt = 208,
+ aarch64_sys_getsockopt = 209,
+ aarch64_sys_shutdown = 210,
+ aarch64_sys_sendmsg = 211,
+ aarch64_sys_recvmsg = 212,
+ aarch64_sys_readahead = 213,
+ aarch64_sys_brk = 214,
+ aarch64_sys_munmap = 215,
+ aarch64_sys_mremap = 216,
+ aarch64_sys_add_key = 217,
+ aarch64_sys_request_key = 218,
+ aarch64_sys_keyctl = 219,
+ aarch64_sys_clone = 220,
+ aarch64_sys_execve = 221,
+ aarch64_sys_mmap = 222,
+ aarch64_sys_fadvise64 = 223,
+ aarch64_sys_swapon = 224,
+ aarch64_sys_swapoff = 225,
+ aarch64_sys_mprotect = 226,
+ aarch64_sys_msync = 227,
+ aarch64_sys_mlock = 228,
+ aarch64_sys_munlock = 229,
+ aarch64_sys_mlockall = 230,
+ aarch64_sys_munlockall = 231,
+ aarch64_sys_mincore = 232,
+ aarch64_sys_madvise = 233,
+ aarch64_sys_remap_file_pages = 234,
+ aarch64_sys_mbind = 235,
+ aarch64_sys_get_mempolicy = 236,
+ aarch64_sys_set_mempolicy = 237,
+ aarch64_sys_migrate_pages = 238,
+ aarch64_sys_move_pages = 239,
+ aarch64_sys_rt_tgsigqueueinfo = 240,
+ aarch64_sys_perf_event_open = 241,
+ aarch64_sys_accept4 = 242,
+ aarch64_sys_recvmmsg = 243,
+ aarch64_sys_wait4 = 260,
+ aarch64_sys_prlimit64 = 261,
+ aarch64_sys_fanotify_init = 262,
+ aarch64_sys_fanotify_mark = 263,
+ aarch64_sys_name_to_handle_at = 264,
+ aarch64_sys_open_by_handle_at = 265,
+ aarch64_sys_clock_adjtime = 266,
+ aarch64_sys_syncfs = 267,
+ aarch64_sys_setns = 268,
+ aarch64_sys_sendmmsg = 269,
+ aarch64_sys_process_vm_readv = 270,
+ aarch64_sys_process_vm_writev = 271,
+ aarch64_sys_kcmp = 272,
+ aarch64_sys_finit_module = 273,
+ aarch64_sys_sched_setattr = 274,
+ aarch64_sys_sched_getattr = 275,
+};
diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index 3c29f43..9905552 100644
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -2991,6 +2991,7 @@ aarch64_record_data_proc_imm (insn_decode_record *aarch64_insn_r)
static unsigned int
aarch64_record_branch_except_sys (insn_decode_record *aarch64_insn_r)
{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (aarch64_insn_r->gdbarch);
uint8_t insn_bits24_27, insn_bits28_31, insn_bits22_23;
uint32_t record_buf[4];
@@ -3002,7 +3003,20 @@ aarch64_record_branch_except_sys (insn_decode_record *aarch64_insn_r)
{
/* Exception generation instructions. */
if (insn_bits24_27 == 0x04)
- return AARCH64_RECORD_UNSUPPORTED;
+ {
+ if (!bits (aarch64_insn_r->aarch64_insn, 2, 4) &&
+ !bits (aarch64_insn_r->aarch64_insn, 21, 23) &&
+ bits (aarch64_insn_r->aarch64_insn, 0, 1) == 0x01)
+ {
+ ULONGEST svc_number;
+ regcache_raw_read_unsigned (aarch64_insn_r->regcache, 8,
+ &svc_number);
+ return tdep->aarch64_syscall_record (aarch64_insn_r->regcache,
+ svc_number);
+ }
+ else
+ return AARCH64_RECORD_UNSUPPORTED;
+ }
/* System instructions. */
else if (insn_bits24_27 == 0x05 && insn_bits22_23 == 0x00)
{
diff --git a/gdb/aarch64-tdep.h b/gdb/aarch64-tdep.h
index 0a8bb26..af209a9 100644
--- a/gdb/aarch64-tdep.h
+++ b/gdb/aarch64-tdep.h
@@ -88,6 +88,9 @@ struct gdbarch_tdep
struct type *vns_type;
struct type *vnh_type;
struct type *vnb_type;
+
+ /* syscall record. */
+ int (*aarch64_syscall_record) (struct regcache *regcache, unsigned long svc_number);
};
extern struct target_desc *tdesc_aarch64;
diff --git a/gdb/configure.tgt b/gdb/configure.tgt
index 8feda7c..4e4d6a9 100644
--- a/gdb/configure.tgt
+++ b/gdb/configure.tgt
@@ -45,7 +45,7 @@ aarch64*-*-linux*)
# Target: AArch64 linux
gdb_target_obs="aarch64-tdep.o aarch64-linux-tdep.o \
glibc-tdep.o linux-tdep.o solib-svr4.o \
- symfile-mem.o"
+ symfile-mem.o linux-record.o"
build_gdbserver=yes
;;
diff --git a/gdb/linux-record.h b/gdb/linux-record.h
index ab39cb9..34dad52 100644
--- a/gdb/linux-record.h
+++ b/gdb/linux-record.h
@@ -174,6 +174,8 @@ struct linux_record_tdep
int arg4;
int arg5;
int arg6;
+ int arg7;
+ int arg8;
};
/* Enum that defines the gdb-canonical set of Linux syscall identifiers.
--
1.9.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v5 1/6] NEWS entry about aarch64-linux record/replay support
2015-05-11 7:27 ` [PATCH v5 0/6] Omair Javaid
@ 2015-05-11 7:27 ` Omair Javaid
2015-05-11 15:02 ` Eli Zaretskii
2015-05-11 7:27 ` [PATCH v5 2/6] Implements aarch64 process record and reverse debugging support Omair Javaid
` (5 subsequent siblings)
6 siblings, 1 reply; 11+ messages in thread
From: Omair Javaid @ 2015-05-11 7:27 UTC (permalink / raw)
To: gdb-patches
gdb:
2015-05-11 Omair Javaid <omair.javaid@linaro.org>
* NEWS: Add a note on process record-replay support on aarch64*-linux*
targets.
---
gdb/NEWS | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/gdb/NEWS b/gdb/NEWS
index 51e4f4e..1e517d2 100644
--- a/gdb/NEWS
+++ b/gdb/NEWS
@@ -3,6 +3,10 @@
*** Changes since GDB 7.9
+* Support for process record-replay and reverse debugging on aarch64*-linux*
+ targets has been added. GDB now supports recording of A64 instruction set
+ including advance SIMD instructions.
+
* GDB now honors the content of the file /proc/PID/coredump_filter
(PID is the process ID) on GNU/Linux systems. This file can be used
to specify the types of memory mappings that will be included in a
--
1.9.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v5 5/6] Enables gdb.reverse testsuite for aarch64*-linux targets
2015-05-11 7:27 ` [PATCH v5 0/6] Omair Javaid
` (2 preceding siblings ...)
2015-05-11 7:27 ` [PATCH v5 6/6] Adds testcases to test arm64 instruction set recording Omair Javaid
@ 2015-05-11 7:27 ` Omair Javaid
2015-05-11 7:27 ` [PATCH v5 3/6] Support for recording syscall on aarch64-linux Omair Javaid
` (2 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Omair Javaid @ 2015-05-11 7:27 UTC (permalink / raw)
To: gdb-patches
gdb/testsuite:
2015-05-11 Omair Javaid <omair.javaid@linaro.org>
* lib/gdb.exp (supports_process_record): Return true for aarch64*-linux*.
(supports_reverse): Likewise.
---
gdb/testsuite/lib/gdb.exp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/gdb/testsuite/lib/gdb.exp b/gdb/testsuite/lib/gdb.exp
index 73e55e3..2152a0e 100644
--- a/gdb/testsuite/lib/gdb.exp
+++ b/gdb/testsuite/lib/gdb.exp
@@ -2008,6 +2008,7 @@ proc supports_process_record {} {
if { [istarget "arm*-*-linux*"] || [istarget "x86_64-*-linux*"]
|| [istarget "i\[34567\]86-*-linux*"]
+ || [istarget "aarch64*-*-linux*"]
|| [istarget "powerpc*-*-linux*"] } {
return 1
}
@@ -2025,6 +2026,7 @@ proc supports_reverse {} {
if { [istarget "arm*-*-linux*"] || [istarget "x86_64-*-linux*"]
|| [istarget "i\[34567\]86-*-linux*"]
+ || [istarget "aarch64*-*-linux*"]
|| [istarget "powerpc*-*-linux*"] } {
return 1
}
--
1.9.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v5 0/6]
2015-02-03 12:47 [PATCH] ARM gdb record-replay bug fixes Omair Javaid
2015-02-16 14:21 ` Yao Qi
@ 2015-05-11 7:27 ` Omair Javaid
2015-05-11 7:27 ` [PATCH v5 1/6] NEWS entry about aarch64-linux record/replay support Omair Javaid
` (6 more replies)
1 sibling, 7 replies; 11+ messages in thread
From: Omair Javaid @ 2015-05-11 7:27 UTC (permalink / raw)
To: gdb-patches
Hi Yao,
I am reposting these patches. You can take them forward from here.
(No change: Patch approved in previous iterations)
Patch#1 NEWS entry about aarch64-linux record/replay support
has been previously posted and approved here:
https://sourceware.org/ml/gdb-patches/2014-06/msg00185.html
https://sourceware.org/ml/gdb-patches/2014-09/msg00611.html
(Updated: Added suggested changes)
Patch#2 Implements aarch64 process record and reverse debugging support
has been discussed and updated in several iteration. Previous versions and
discussions can be found here:
https://sourceware.org/ml/gdb-patches/2014-10/msg00540.html
https://sourceware.org/ml/gdb-patches/2014-08/msg00662.html
(Updated: Added suggested changes)
Patch#3 Support for recording syscall on aarch64-linux
has been previously discussed and improved in this version too.
Previous discussions can be found here:
https://sourceware.org/ml/gdb-patches/2014-10/msg00541.html
(Updated: Added suggested changes)
Patch#4 Support for recording aarch64 advanced SIMD instructions
has also been previously posted and discussed here:
https://sourceware.org/ml/gdb-patches/2014-10/msg00345.html
(No change: Patch approved in previous iterations)
Patch#5 Enables gdb.reverse testsuite for aarch64*-linux targets
is a pretty trivial patch to enable gdb testsuite. Its previously posted and discussed here:
https://sourceware.org/ml/gdb-patches/2014-06/msg00242.html
(New Patch)
Patch#6 Adds testcases to test arm64 instruction set recording
Omair Javaid (6):
NEWS entry about aarch64-linux record/replay support
Implements aarch64 process record and reverse debugging support
Support for recording syscall on aarch64-linux
Support for recording aarch64 advanced SIMD instructions
Enables gdb.reverse testsuite for aarch64*-linux targets
Adds testcases to test arm64 instruction set recording
gdb/NEWS | 4 +
gdb/aarch64-linux-tdep.c | 917 ++++++++++
gdb/aarch64-linux-tdep.h | 266 +++
gdb/aarch64-tdep.c | 862 ++++++++++
gdb/aarch64-tdep.h | 6 +
gdb/configure.tgt | 2 +-
gdb/linux-record.h | 2 +
gdb/testsuite/gdb.reverse/aarch64-test-rrp.exp | 234 +++
gdb/testsuite/gdb.reverse/aarch64-test-rrp.txt | 2115 ++++++++++++++++++++++++
gdb/testsuite/lib/gdb.exp | 2 +
10 files changed, 4409 insertions(+), 1 deletion(-)
create mode 100644 gdb/testsuite/gdb.reverse/aarch64-test-rrp.exp
create mode 100644 gdb/testsuite/gdb.reverse/aarch64-test-rrp.txt
--
1.9.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v5 6/6] Adds testcases to test arm64 instruction set recording
2015-05-11 7:27 ` [PATCH v5 0/6] Omair Javaid
2015-05-11 7:27 ` [PATCH v5 1/6] NEWS entry about aarch64-linux record/replay support Omair Javaid
2015-05-11 7:27 ` [PATCH v5 2/6] Implements aarch64 process record and reverse debugging support Omair Javaid
@ 2015-05-11 7:27 ` Omair Javaid
2015-05-11 7:27 ` [PATCH v5 5/6] Enables gdb.reverse testsuite for aarch64*-linux targets Omair Javaid
` (3 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Omair Javaid @ 2015-05-11 7:27 UTC (permalink / raw)
To: gdb-patches
This patch adds testcases to test recording of arm64 instructions set.
This testcase takes snapshot of registers and memory before recording them and then comapres the snapshot once stepped backwards to the starting point.
This patch also adds a instruction data set that covers almost all vector and asimd instruction except for store instuctions.
More data and similar tests for arm will be added later.
---
gdb/testsuite/gdb.reverse/aarch64-test-rrp.exp | 234 +++
gdb/testsuite/gdb.reverse/aarch64-test-rrp.txt | 2115 ++++++++++++++++++++++++
2 files changed, 2349 insertions(+)
create mode 100644 gdb/testsuite/gdb.reverse/aarch64-test-rrp.exp
create mode 100644 gdb/testsuite/gdb.reverse/aarch64-test-rrp.txt
diff --git a/gdb/testsuite/gdb.reverse/aarch64-test-rrp.exp b/gdb/testsuite/gdb.reverse/aarch64-test-rrp.exp
new file mode 100644
index 0000000..ddf36d5
--- /dev/null
+++ b/gdb/testsuite/gdb.reverse/aarch64-test-rrp.exp
@@ -0,0 +1,234 @@
+# Copyright (C) 2012-2015 Free Software Foundation, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+if ![supports_reverse] {
+ return
+}
+
+# Test aarch64 instruction recording.
+
+if {![istarget "aarch64*-*-*"]} then {
+ verbose "Skipping aarch64 instruction recording tests."
+ return
+}
+
+# Compile .S File.
+
+proc CompileFile {} {
+
+ global objdir
+ global subdir
+ global srcdir
+
+ set testfile "aarch64-test-rrp"
+ set srcfile ${testfile}.S
+ set binfile ${objdir}/${subdir}/${testfile}
+
+ set additional_flags "-Wa,-g"
+
+ if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable [list debug $additional_flags]] != "" } {
+ untested aarch64-test-rrp.exp
+ return -1
+ }
+
+ # Get things started.
+
+ clean_restart ${testfile}
+
+ # Setting breakpoint at main
+
+ if ![runto_main] then {
+ fail "Can't run to main"
+ return 0
+ }
+}
+
+# Return the List of register values required.
+
+proc Read_Registers {Reg_li} {
+ global gdb_prompt
+ upvar 1 $Reg_li Reg_list
+ set Reg_value_list {}
+
+ foreach index $Reg_list {
+ if { $index != {} } {
+ send_gdb "info registers $index \n"
+ gdb_expect {
+ -re "($index +.*\n)(.*)(\n$gdb_prompt)" {
+ lappend Reg_value_list $expect_out(2,string)
+ }
+ }
+ }
+ }
+ return $Reg_value_list
+}
+
+# Verifying Registers before and after reverse.
+
+proc verify_Registers {Reg_names Reg_values instruction} {
+ global gdb_prompt
+ upvar 1 $Reg_names reg_names
+ upvar 1 $Reg_values reg_values
+ set ind 0
+
+ foreach index $reg_names {
+ if { $index != {} } {
+ set temp_value [lindex $reg_values $ind]
+ incr ind
+ send_gdb "info registers $index \n"
+ gdb_expect {
+ -re "($index +.*\n)(.*)(\n$gdb_prompt)" {
+ if {[string equal "$temp_value" "$expect_out(2,string)"]} {
+ pass "Register $index preserved in $instruction"
+ } else {
+ fail "Register $index corrupted in $instruction"
+ }
+ }
+ }
+ }
+ }
+}
+
+# Read Byte_Length memory from mem_address.
+
+proc Read_Memory {mem_address Byte_Length} {
+ set output {}
+ set str [format x/%sxb%s$mem_address $Byte_Length " "]
+ send_gdb "$str \n"
+ gdb_expect {
+ -re {..*} {
+ append output $expect_out(0,string)
+ exp_continue
+ }
+ }
+ return $output
+}
+
+
+proc verify_Memory {mem_before mem_after instruction} {
+
+ if {[string equal "$mem_before" "$mem_after"]} {
+ pass "Memory preserved in $instruction"
+ } else {
+ fail "Memory corrupted in $instruction"
+ }
+}
+
+# Run the instruction and record the registers and memory.
+
+proc Run_Test {Label_start Label_end Reg_list Mem_address Wordcount instruction} {
+
+ upvar 1 $Reg_list reg_list
+
+ gdb_test "break $Label_start"
+ gdb_test "continue"
+
+ # Reading Registers and Memory before reversing.
+
+ set reg_before [Read_Registers reg_list]
+
+ if { [lindex $Mem_address 0] != {} } {
+ set mem_before [Read_Memory Mem_address Wordcount]
+ }
+
+ # Activate process record/replay.
+ gdb_test "record"
+
+ gdb_test "break $Label_end"
+ gdb_test "continue"
+
+ gdb_test "reverse-continue"
+
+ # Verify if Register values are preserved after Reverse.
+ if { [lindex $reg_list 0] != {} } {
+ verify_Registers reg_list reg_before "$instruction"
+ }
+ # Verify if Memory is restored after Reverse.
+ if { [lindex $Mem_address 0] != {} } {
+ set mem_after [Read_Memory Mem_address Wordcount]
+ }
+}
+
+# Generates .S file/ compile/ run.
+
+proc run_rrp_tests {} {
+
+ global subdir
+ global srcdir
+
+ set testfile "aarch64-test-rrp"
+ set srcfile ${testfile}.S
+
+ # Reading from instructions File.
+ set file_ins [open "$srcdir/$subdir/aarch64-test-rrp.txt" "r"]
+ set ins_data [read $file_ins]
+ set ins_data [split $ins_data "\n"]
+
+ for {set i 0} {$i < [llength $ins_data]-1} {incr i} {
+ if {[string index [lindex $ins_data $i] 0] != "@" \
+ && [string index [lindex $ins_data $i] 0] != ""} {
+
+ # Generating .S File.
+ set Sfile [open $srcdir/$subdir/$srcfile "w+"]
+
+ # appending Lines in Array.
+ puts -nonewline $Sfile "\
+ .cpu generic
+ .text
+ .align 2
+ .global main
+ .type main, %function
+main:
+ stp x29, x30, \[sp, -16\]!
+ add x29, sp, 0
+ bl Start
+ mov w0, 0
+ ldp x29, x30, \[sp\], 16
+ ret
+ .align 2
+ .global Start
+ .type Start, %function
+Start:
+ mov w0, w0
+ mov w0, w0
+ [lindex $ins_data $i]
+ mov w0, w0
+End:
+ mov w0, 0
+ ret
+"
+ close $Sfile
+ set line [lindex $ins_data $i]
+ incr i
+ set regs_mem [split [lindex $ins_data $i] ":"]
+ set registers [split [lindex $regs_mem 0], ","]
+ set mem [split [lindex $regs_mem 1], ","]
+ if { [lindex $mem 0] != {} } {
+ set memaddr [lindex $mem 0]
+ set bytesize [lindex $mem 1]
+ } else {
+ set bytesize {}
+ set memaddr {}
+ }
+ # Compile .S File.
+ CompileFile
+
+ # Run the instruction and verify the registers and memory after reverse.
+ Run_Test "Start" "End" registers "$memaddr" "$bytesize" "$line"
+ }
+ }
+}
+
+run_rrp_tests
diff --git a/gdb/testsuite/gdb.reverse/aarch64-test-rrp.txt b/gdb/testsuite/gdb.reverse/aarch64-test-rrp.txt
new file mode 100644
index 0000000..5b67661
--- /dev/null
+++ b/gdb/testsuite/gdb.reverse/aarch64-test-rrp.txt
@@ -0,0 +1,2115 @@
+@ load and STORE
+@-------------------------------------------------------
+ld1 { v1.8b }, [x0]
+v1:
+ld1 { v2.8b, v3.8b }, [x0]
+v2,v3:
+ld1 { v3.8b, v4.8b, v5.8b }, [x0]
+v3,v4,v5:
+ld1 { v4.8b, v5.8b, v6.8b, v7.8b }, [x0]
+v4,v5,v6,v7:
+ld1 { v1.16b }, [x0]
+v1:
+ld1 { v2.16b, v3.16b }, [x0]
+v2,v3:
+ld1 { v3.16b, v4.16b, v5.16b }, [x0]
+v3,v4,v5:
+ld1 { v4.16b, v5.16b, v6.16b, v7.16b }, [x0]
+v4,v5,v6,v7:
+ld1 { v1.4h }, [x0]
+v1:
+ld1 { v2.4h, v3.4h }, [x0]
+v2,v3:
+ld1 { v3.4h, v4.4h, v5.4h }, [x0]
+v3,v4,v5:
+ld1 { v7.4h, v8.4h, v9.4h, v10.4h }, [x0]
+v7,v8,v9,v10:
+ld1 { v1.8h }, [x0]
+v1:
+ld1 { v2.8h, v3.8h }, [x0]
+v2,v3:
+ld1 { v3.8h, v4.8h, v5.8h }, [x0]
+v3,v4,v5:
+ld1 { v7.8h, v8.8h, v9.8h, v10.8h }, [x0]
+v7,v8,v9,v10:
+ld1 { v1.2s }, [x0]
+v1:
+ld1 { v2.2s, v3.2s }, [x0]
+v2,v3:
+ld1 { v3.2s, v4.2s, v5.2s }, [x0]
+v3,v4,v5:
+ld1 { v7.2s, v8.2s, v9.2s, v10.2s }, [x0]
+v7,v8,v9,v10:
+ld1 { v1.4s }, [x0]
+v1:
+ld1 { v2.4s, v3.4s }, [x0]
+v2,v3:
+ld1 { v3.4s, v4.4s, v5.4s }, [x0]
+v3,v4,v5:
+ld1 { v7.4s, v8.4s, v9.4s, v10.4s }, [x0]
+v7,v8,v9,v10:
+ld1 { v1.1d }, [x0]
+v1:
+ld1 { v2.1d, v3.1d }, [x0]
+v2,v3:
+ld1 { v3.1d, v4.1d, v5.1d }, [x0]
+v3,v4,v5:
+ld1 { v7.1d, v8.1d, v9.1d, v10.1d }, [x0]
+v7,v8,v9,v10:
+ld1 { v1.2d }, [x0]
+v1:
+ld1 { v2.2d, v3.2d }, [x0]
+v2,v3:
+ld1 { v3.2d, v4.2d, v5.2d }, [x0]
+v3,v4,v5:
+ld1 { v7.2d, v8.2d, v9.2d, v10.2d }, [x0]
+v7,v8,v9,v10:
+
+ld2 { v3.8b, v4.8b }, [x19]
+v3,v4:
+ld2 { v3.16b, v4.16b }, [x19]
+v3,v4:
+ld2 { v3.4h, v4.4h }, [x19]
+v3,v4:
+ld2 { v3.8h, v4.8h }, [x19]
+v3,v4:
+ld2 { v3.2s, v4.2s }, [x19]
+v3,v4:
+ld2 { v3.4s, v4.4s }, [x19]
+v3,v4:
+ld2 { v3.2d, v4.2d }, [x19]
+v3,v4:
+
+ld3 { v2.8b, v3.8b, v4.8b }, [x19]
+v2,v3,v4:
+ld3 { v2.16b, v3.16b, v4.16b }, [x19]
+v2,v3,v4:
+ld3 { v2.4h, v3.4h, v4.4h }, [x19]
+v2,v3,v4:
+ld3 { v2.8h, v3.8h, v4.8h }, [x19]
+v2,v3,v4:
+ld3 { v2.2s, v3.2s, v4.2s }, [x19]
+v2,v3,v4:
+ld3 { v2.4s, v3.4s, v4.4s }, [x19]
+v2,v3,v4:
+ld3 { v2.2d, v3.2d, v4.2d }, [x19]
+v2,v3,v4:
+
+ld4 { v2.8b, v3.8b, v4.8b, v5.8b }, [x19]
+v2,v3,v4,v5:
+ld4 { v2.16b, v3.16b, v4.16b, v5.16b }, [x19]
+v2,v3,v4,v5:
+ld4 { v2.4h, v3.4h, v4.4h, v5.4h }, [x19]
+v2,v3,v4,v5:
+ld4 { v2.8h, v3.8h, v4.8h, v5.8h }, [x19]
+v2,v3,v4,v5:
+ld4 { v2.2s, v3.2s, v4.2s, v5.2s }, [x19]
+v2,v3,v4,v5:
+ld4 { v2.4s, v3.4s, v4.4s, v5.4s }, [x19]
+v2,v3,v4,v5:
+ld4 { v2.2d, v3.2d, v4.2d, v5.2d }, [x19]
+v2,v3,v4,v5:
+
+ld1 { v1.8b }, [x0], x15
+v1:
+ld1 { v2.8b, v3.8b }, [x0], x15
+v2,v3:
+ld1 { v3.8b, v4.8b, v5.8b }, [x0], x15
+v2,v3,v5:
+ld1 { v4.8b, v5.8b, v6.8b, v7.8b }, [x0], x15
+v4,v5,v6,v7:
+ld1 { v1.16b }, [x0], x15
+v1:
+ld1 { v2.16b, v3.16b }, [x0], x15
+v2,v3:
+ld1 { v3.16b, v4.16b, v5.16b }, [x0], x15
+v3,v4,v5:
+ld1 { v4.16b, v5.16b, v6.16b, v7.16b }, [x0], x15
+v4,v5,v6,v7:
+ld1 { v1.4h }, [x0], x15
+v1:
+ld1 { v2.4h, v3.4h }, [x0], x15
+v2,v3:
+ld1 { v3.4h, v4.4h, v5.4h }, [x0], x15
+v3,v4,v5:
+ld1 { v7.4h, v8.4h, v9.4h, v10.4h }, [x0], x15
+v7,v8,v9,v10:
+ld1 { v1.8h }, [x0], x15
+v1:
+ld1 { v2.8h, v3.8h }, [x0], x15
+v2,v3:
+ld1 { v3.8h, v4.8h, v5.8h }, [x0], x15
+v3,v4,v5:
+ld1 { v7.8h, v8.8h, v9.8h, v10.8h }, [x0], x15
+v7,v8,v9,v10:
+ld1 { v1.2s }, [x0], x15
+v1:
+ld1 { v2.2s, v3.2s }, [x0], x15
+v2,v3:
+ld1 { v3.2s, v4.2s, v5.2s }, [x0], x15
+v3,v4,v5:
+ld1 { v7.2s, v8.2s, v9.2s, v10.2s }, [x0], x15
+v7,v8,v9,v10:
+ld1 { v1.4s }, [x0], x15
+v1:
+ld1 { v2.4s, v3.4s }, [x0], x15
+v2,v3:
+ld1 { v3.4s, v4.4s, v5.4s }, [x0], x15
+v3,v4,v5:
+ld1 { v7.4s, v8.4s, v9.4s, v10.4s }, [x0], x15
+v7,v8,v9,v10:
+ld1 { v1.1d }, [x0], x15
+v1:
+ld1 { v2.1d, v3.1d }, [x0], x15
+v2,v3:
+ld1 { v3.1d, v4.1d, v5.1d }, [x0], x15
+v3,v4,v5:
+ld1 { v7.1d, v8.1d, v9.1d, v10.1d }, [x0], x15
+v7,v8,v9,v10:
+ld1 { v1.2d }, [x0], x15
+v1:
+ld1 { v2.2d, v3.2d }, [x0], x15
+v2,v3:
+ld1 { v3.2d, v4.2d, v5.2d }, [x0], x15
+v3,v4,v5:
+ld1 { v7.2d, v8.2d, v9.2d, v10.2d }, [x0], x15
+v7,v8,v9,v10:
+
+ld1 { v1.8b }, [x0], #8
+v1:
+ld1 { v2.8b, v3.8b }, [x0], #16
+v2,v3:
+ld1 { v3.8b, v4.8b, v5.8b }, [x0], #24
+v3,v4,v5:
+ld1 { v4.8b, v5.8b, v6.8b, v7.8b }, [x0], #32
+v4,v5,v6,v7:
+ld1 { v1.16b }, [x0], #16
+v1:
+ld1 { v2.16b, v3.16b }, [x0], #32
+v2,v3:
+ld1 { v3.16b, v4.16b, v5.16b }, [x0], #48
+v3,v4,v5:
+ld1 { v4.16b, v5.16b, v6.16b, v7.16b }, [x0], #64
+v4,v5,v6,v7:
+ld1 { v1.4h }, [x0], #8
+v1:
+ld1 { v2.4h, v3.4h }, [x0], #16
+v2,v3:
+ld1 { v3.4h, v4.4h, v5.4h }, [x0], #24
+v3,v4,v5:
+ld1 { v7.4h, v8.4h, v9.4h, v10.4h }, [x0], #32
+v7,v8,v9,v10:
+ld1 { v1.8h }, [x0], #16
+v1:
+ld1 { v2.8h, v3.8h }, [x0], #32
+v2,v3:
+ld1 { v3.8h, v4.8h, v5.8h }, [x0], #48
+v3,v4,v5:
+ld1 { v7.8h, v8.8h, v9.8h, v10.8h }, [x0], #64
+v7,v8,v9,v10:
+ld1 { v1.2s }, [x0], #8
+v1:
+ld1 { v2.2s, v3.2s }, [x0], #16
+v2,v3:
+ld1 { v3.2s, v4.2s, v5.2s }, [x0], #24
+v3,v4,v5:
+ld1 { v7.2s, v8.2s, v9.2s, v10.2s }, [x0], #32
+v7,v8,v9,v10:
+ld1 { v1.4s }, [x0], #16
+v1:
+ld1 { v2.4s, v3.4s }, [x0], #32
+v2,v3:
+ld1 { v3.4s, v4.4s, v5.4s }, [x0], #48
+v3,v4,v5:
+ld1 { v7.4s, v8.4s, v9.4s, v10.4s }, [x0], #64
+v7,v8,v9,v10:
+ld1 { v1.1d }, [x0], #8
+v1:
+ld1 { v2.1d, v3.1d }, [x0], #16
+v2,v3:
+ld1 { v3.1d, v4.1d, v5.1d }, [x0], #24
+v3,v4,v5:
+ld1 { v7.1d, v8.1d, v9.1d, v10.1d }, [x0], #32
+v7,v8,v9,v10:
+ld1 { v1.2d }, [x0], #16
+v1:
+ld1 { v2.2d, v3.2d }, [x0], #32
+v2,v3:
+ld1 { v3.2d, v4.2d, v5.2d }, [x0], #48
+v3,v4,v5:
+ld1 { v7.2d, v8.2d, v9.2d, v10.2d }, [x0], #64
+v7,v8,v9,v10:
+
+ld2 { v2.8b, v3.8b }, [x0], x15
+v2,v3:
+ld2 { v2.16b, v3.16b }, [x0], x15
+v2,v3:
+ld2 { v2.4h, v3.4h }, [x0], x15
+v2,v3:
+ld2 { v2.8h, v3.8h }, [x0], x15
+v2,v3:
+ld2 { v2.2s, v3.2s }, [x0], x15
+v2,v3:
+ld2 { v2.4s, v3.4s }, [x0], x15
+v2,v3:
+ld2 { v2.2d, v3.2d }, [x0], x15
+v2,v3:
+
+ld2 { v2.8b, v3.8b }, [x0], #16
+v2,v3:
+ld2 { v2.16b, v3.16b }, [x0], #32
+v2,v3:
+ld2 { v2.4h, v3.4h }, [x0], #16
+v2,v3:
+ld2 { v2.8h, v3.8h }, [x0], #32
+v2,v3:
+ld2 { v2.2s, v3.2s }, [x0], #16
+v2,v3:
+ld2 { v2.4s, v3.4s }, [x0], #32
+v2,v3:
+ld2 { v2.2d, v3.2d }, [x0], #32
+v2,v3:
+
+ld3 { v3.8b, v4.8b, v5.8b }, [x0], x15
+v3,v4,v5:
+ld3 { v3.16b, v4.16b, v5.16b }, [x0], x15
+v3,v4,v5:
+ld3 { v3.4h, v4.4h, v5.4h }, [x0], x15
+v3,v4,v5:
+ld3 { v3.8h, v4.8h, v5.8h }, [x0], x15
+v3,v4,v5:
+ld3 { v3.2s, v4.2s, v5.2s }, [x0], x15
+v3,v4,v5:
+ld3 { v3.4s, v4.4s, v5.4s }, [x0], x15
+v3,v4,v5:
+ld3 { v3.2d, v4.2d, v5.2d }, [x0], x15
+v3,v4,v5:
+
+ld3 { v3.8b, v4.8b, v5.8b }, [x0], #24
+v3,v4,v5:
+ld3 { v3.16b, v4.16b, v5.16b }, [x0], #48
+v3,v4,v5:
+ld3 { v3.4h, v4.4h, v5.4h }, [x0], #24
+v3,v4,v5:
+ld3 { v3.8h, v4.8h, v5.8h }, [x0], #48
+v3,v4,v5:
+ld3 { v3.2s, v4.2s, v5.2s }, [x0], #24
+v3,v4,v5:
+ld3 { v3.4s, v4.4s, v5.4s }, [x0], #48
+v3,v4,v5:
+ld3 { v3.2d, v4.2d, v5.2d }, [x0], #48
+v3,v4,v5:
+
+ld4 { v4.8b, v5.8b, v6.8b, v7.8b }, [x0], x15
+v4,v5,v6,v7:
+ld4 { v4.16b, v5.16b, v6.16b, v7.16b }, [x0], x15
+v4,v5,v6,v7:
+ld4 { v7.4h, v8.4h, v9.4h, v10.4h }, [x0], x15
+v7,v8,v9,v10:
+ld4 { v7.8h, v8.8h, v9.8h, v10.8h }, [x0], x15
+v7,v8,v9,v10:
+ld4 { v7.2s, v8.2s, v9.2s, v10.2s }, [x0], x15
+v7,v8,v9,v10:
+ld4 { v7.4s, v8.4s, v9.4s, v10.4s }, [x0], x15
+v7,v8,v9,v10:
+ld4 { v7.2d, v8.2d, v9.2d, v10.2d }, [x0], x15
+v7,v8,v9,v10:
+
+ld4 { v4.8b, v5.8b, v6.8b, v7.8b }, [x0], #32
+v4,v5,v6,v7:
+ld4 { v4.16b, v5.16b, v6.16b, v7.16b }, [x0], #64
+v4,v5,v6,v7:
+ld4 { v7.4h, v8.4h, v9.4h, v10.4h }, [x0], #32
+v7,v8,v9,v10:
+ld4 { v7.8h, v8.8h, v9.8h, v10.8h }, [x0], #64
+v7,v8,v9,v10:
+ld4 { v7.2s, v8.2s, v9.2s, v10.2s }, [x0], #32
+v7,v8,v9,v10:
+ld4 { v7.4s, v8.4s, v9.4s, v10.4s }, [x0], #64
+v7,v8,v9,v10:
+ld4 { v7.2d, v8.2d, v9.2d, v10.2d }, [x0], #64
+v7,v8,v9,v10:
+
+ld1r { v12.8b }, [x2]
+v12:
+ld1r { v12.8b }, [x2], x3
+v12:
+ld1r { v12.16b }, [x2]
+v12:
+ld1r { v12.16b }, [x2], x3
+v12:
+ld1r { v12.4h }, [x2]
+v12:
+ld1r { v12.4h }, [x2], x3
+v12:
+ld1r { v12.8h }, [x2]
+v12:
+ld1r { v12.8h }, [x2], x3
+v12:
+ld1r { v12.2s }, [x2]
+v12:
+ld1r { v12.2s }, [x2], x3
+v12:
+ld1r { v12.4s }, [x2]
+v12:
+ld1r { v12.4s }, [x2], x3
+v12:
+ld1r { v12.1d }, [x2]
+v12:
+ld1r { v12.1d }, [x2], x3
+v12:
+ld1r { v12.2d }, [x2]
+v12:
+ld1r { v12.2d }, [x2], x3
+v12:
+ld1r { v12.8b }, [x2], #1
+v12:
+ld1r { v12.16b }, [x2], #1
+v12:
+ld1r { v12.4h }, [x2], #2
+v12:
+ld1r { v12.8h }, [x2], #2
+v12:
+ld1r { v12.2s }, [x2], #4
+v12:
+ld1r { v12.4s }, [x2], #4
+v12:
+ld1r { v12.1d }, [x2], #8
+v12:
+ld1r { v12.2d }, [x2], #8
+v12:
+ld2r { v3.8b, v4.8b }, [x2]
+v3,v4:
+ld2r { v3.8b, v4.8b }, [x2], x3
+v3,v4:
+ld2r { v3.16b, v4.16b }, [x2]
+v3,v4:
+ld2r { v3.16b, v4.16b }, [x2], x3
+v3,v4:
+ld2r { v3.4h, v4.4h }, [x2]
+v3,v4:
+ld2r { v3.4h, v4.4h }, [x2], x3
+v3,v4:
+ld2r { v3.8h, v4.8h }, [x2]
+v3,v4:
+ld2r { v3.8h, v4.8h }, [x2], x3
+v3,v4:
+ld2r { v3.2s, v4.2s }, [x2]
+v3,v4:
+ld2r { v3.2s, v4.2s }, [x2], x3
+v3,v4:
+ld2r { v3.4s, v4.4s }, [x2]
+v3,v4:
+ld2r { v3.4s, v4.4s }, [x2], x3
+v3,v4:
+ld2r { v3.1d, v4.1d }, [x2]
+v3,v4:
+ld2r { v3.1d, v4.1d }, [x2], x3
+v3,v4:
+ld2r { v3.2d, v4.2d }, [x2]
+v3,v4:
+ld2r { v3.2d, v4.2d }, [x2], x3
+v3,v4:
+ld2r { v3.8b, v4.8b }, [x2], #2
+v3,v4:
+ld2r { v3.16b, v4.16b }, [x2], #2
+v3,v4:
+ld2r { v3.4h, v4.4h }, [x2], #4
+v3,v4:
+ld2r { v3.8h, v4.8h }, [x2], #4
+v3,v4:
+ld2r { v3.2s, v4.2s }, [x2], #8
+v3,v4:
+ld2r { v3.4s, v4.4s }, [x2], #8
+v3,v4:
+ld2r { v3.1d, v4.1d }, [x2], #16
+v3,v4:
+ld2r { v3.2d, v4.2d }, [x2], #16
+v3,v4:
+ld3r { v2.8b, v3.8b, v4.8b }, [x2]
+v2,v3,v4:
+ld3r { v2.8b, v3.8b, v4.8b }, [x2], x3
+v2,v3,v4:
+ld3r { v2.16b, v3.16b, v4.16b }, [x2]
+v2,v3,v4:
+ld3r { v2.16b, v3.16b, v4.16b }, [x2], x3
+v2,v3,v4:
+ld3r { v2.4h, v3.4h, v4.4h }, [x2]
+v2,v3,v4:
+ld3r { v2.4h, v3.4h, v4.4h }, [x2], x3
+v2,v3,v4:
+ld3r { v2.8h, v3.8h, v4.8h }, [x2]
+v2,v3,v4:
+ld3r { v2.8h, v3.8h, v4.8h }, [x2], x3
+v2,v3,v4:
+ld3r { v2.2s, v3.2s, v4.2s }, [x2]
+v2,v3,v4:
+ld3r { v2.2s, v3.2s, v4.2s }, [x2], x3
+v2,v3,v4:
+ld3r { v2.4s, v3.4s, v4.4s }, [x2]
+v2,v3,v4:
+ld3r { v2.4s, v3.4s, v4.4s }, [x2], x3
+v2,v3,v4:
+ld3r { v2.1d, v3.1d, v4.1d }, [x2]
+v2,v3,v4:
+ld3r { v2.1d, v3.1d, v4.1d }, [x2], x3
+v2,v3,v4:
+ld3r { v2.2d, v3.2d, v4.2d }, [x2]
+v2,v3,v4:
+ld3r { v2.2d, v3.2d, v4.2d }, [x2], x3
+v2,v3,v4:
+ld3r { v2.8b, v3.8b, v4.8b }, [x2], #3
+v2,v3,v4:
+ld3r { v2.16b, v3.16b, v4.16b }, [x2], #3
+v2,v3,v4:
+ld3r { v2.4h, v3.4h, v4.4h }, [x2], #6
+v2,v3,v4:
+ld3r { v2.8h, v3.8h, v4.8h }, [x2], #6
+v2,v3,v4:
+ld3r { v2.2s, v3.2s, v4.2s }, [x2], #12
+v2,v3,v4:
+ld3r { v2.4s, v3.4s, v4.4s }, [x2], #12
+v2,v3,v4:
+ld3r { v2.1d, v3.1d, v4.1d }, [x2], #24
+v2,v3,v4:
+ld3r { v2.2d, v3.2d, v4.2d }, [x2], #24
+v2,v3,v4:
+ld4r { v2.8b, v3.8b, v4.8b, v5.8b }, [x2]
+v2,v3,v4,v5:
+ld4r { v2.8b, v3.8b, v4.8b, v5.8b }, [x2], x3
+v2,v3,v4,v5:
+ld4r { v2.16b, v3.16b, v4.16b, v5.16b }, [x2]
+v2,v3,v4,v5:
+ld4r { v2.16b, v3.16b, v4.16b, v5.16b }, [x2], x3
+v2,v3,v4,v5:
+ld4r { v2.4h, v3.4h, v4.4h, v5.4h }, [x2]
+v2,v3,v4,v5:
+ld4r { v2.4h, v3.4h, v4.4h, v5.4h }, [x2], x3
+v2,v3,v4,v5:
+ld4r { v2.8h, v3.8h, v4.8h, v5.8h }, [x2]
+v2,v3,v4,v5:
+ld4r { v2.8h, v3.8h, v4.8h, v5.8h }, [x2], x3
+v2,v3,v4,v5:
+ld4r { v2.2s, v3.2s, v4.2s, v5.2s }, [x2]
+v2,v3,v4,v5:
+ld4r { v2.2s, v3.2s, v4.2s, v5.2s }, [x2], x3
+v2,v3,v4,v5:
+ld4r { v2.4s, v3.4s, v4.4s, v5.4s }, [x2]
+v2,v3,v4,v5:
+ld4r { v2.4s, v3.4s, v4.4s, v5.4s }, [x2], x3
+v2,v3,v4,v5:
+ld4r { v2.1d, v3.1d, v4.1d, v5.1d }, [x2]
+v2,v3,v4,v5:
+ld4r { v2.1d, v3.1d, v4.1d, v5.1d }, [x2], x3
+v2,v3,v4,v5:
+ld4r { v2.2d, v3.2d, v4.2d, v5.2d }, [x2]
+v2,v3,v4,v5:
+ld4r { v2.2d, v3.2d, v4.2d, v5.2d }, [x2], x3
+v2,v3,v4,v5:
+ld4r { v2.8b, v3.8b, v4.8b, v5.8b }, [x2], #4
+v2,v3,v4,v5:
+ld4r { v2.16b, v3.16b, v4.16b, v5.16b }, [x2], #4
+v2,v3,v4,v5:
+ld4r { v2.4h, v3.4h, v4.4h, v5.4h }, [x2], #8
+v2,v3,v4,v5:
+ld4r { v2.8h, v3.8h, v4.8h, v5.8h }, [x2], #8
+v2,v3,v4,v5:
+ld4r { v2.2s, v3.2s, v4.2s, v5.2s }, [x2], #16
+v2,v3,v4,v5:
+ld4r { v2.4s, v3.4s, v4.4s, v5.4s }, [x2], #16
+v2,v3,v4,v5:
+ld4r { v2.1d, v3.1d, v4.1d, v5.1d }, [x2], #32
+v2,v3,v4,v5:
+ld4r { v2.2d, v3.2d, v4.2d, v5.2d }, [x2], #32
+v2,v3,v4,v5:
+ld1 { v6.b }[13], [x3]
+v6:
+ld1 { v6.h }[2], [x3]
+v6:
+ld1 { v6.s }[2], [x3]
+v6:
+ld1 { v6.d }[1], [x3]
+v6:
+ld1 { v6.b }[13], [x3], x5
+v6:
+ld1 { v6.h }[2], [x3], x5
+v6:
+ld1 { v6.s }[2], [x3], x5
+v6:
+ld1 { v6.d }[1], [x3], x5
+v6:
+ld1 { v6.b }[13], [x3], #1
+v6:
+ld1 { v6.h }[2], [x3], #2
+v6:
+ld1 { v6.s }[2], [x3], #4
+v6:
+ld1 { v6.d }[1], [x3], #8
+v6:
+ld2 { v5.b, v6.b }[13], [x3]
+v5,v6:
+ld2 { v5.h, v6.h }[2], [x3]
+v5,v6:
+ld2 { v5.s, v6.s }[2], [x3]
+v5,v6:
+ld2 { v5.d, v6.d }[1], [x3]
+v5,v6:
+ld2 { v5.b, v6.b }[13], [x3], x5
+v5,v6:
+ld2 { v5.h, v6.h }[2], [x3], x5
+v5,v6:
+ld2 { v5.s, v6.s }[2], [x3], x5
+v5,v6:
+ld2 { v5.d, v6.d }[1], [x3], x5
+v5,v6:
+ld2 { v5.b, v6.b }[13], [x3], #2
+v5,v6:
+ld2 { v5.h, v6.h }[2], [x3], #4
+v5,v6:
+ld2 { v5.s, v6.s }[2], [x3], #8
+v5,v6:
+ld2 { v5.d, v6.d }[1], [x3], #16
+v5,v6:
+ld3 { v7.b, v8.b, v9.b }[13], [x3]
+v7,v8,v9:
+ld3 { v7.h, v8.h, v9.h }[2], [x3]
+v7,v8,v9:
+ld3 { v7.s, v8.s, v9.s }[2], [x3]
+v7,v8,v9:
+ld3 { v7.d, v8.d, v9.d }[1], [x3]
+v7,v8,v9:
+ld3 { v7.b, v8.b, v9.b }[13], [x3], x5
+v7,v8,v9:
+ld3 { v7.h, v8.h, v9.h }[2], [x3], x5
+v7,v8,v9:
+ld3 { v7.s, v8.s, v9.s }[2], [x3], x5
+v7,v8,v9:
+ld3 { v7.d, v8.d, v9.d }[1], [x3], x5
+v7,v8,v9:
+ld3 { v7.b, v8.b, v9.b }[13], [x3], #3
+v7,v8,v9:
+ld3 { v7.h, v8.h, v9.h }[2], [x3], #6
+v7,v8,v9:
+ld3 { v7.s, v8.s, v9.s }[2], [x3], #12
+v7,v8,v9:
+ld3 { v7.d, v8.d, v9.d }[1], [x3], #24
+v7,v8,v9:
+ld4 { v7.b, v8.b, v9.b, v10.b }[13], [x3]
+v7,v8,v9,v10:
+ld4 { v7.h, v8.h, v9.h, v10.h }[2], [x3]
+v7,v8,v9,v10:
+ld4 { v7.s, v8.s, v9.s, v10.s }[2], [x3]
+v7,v8,v9,v10:
+ld4 { v7.d, v8.d, v9.d, v10.d }[1], [x3]
+v7,v8,v9,v10:
+ld4 { v7.b, v8.b, v9.b, v10.b }[13], [x3], x5
+v7,v8,v9,v10:
+ld4 { v7.h, v8.h, v9.h, v10.h }[2], [x3], x5
+v7,v8,v9,v10:
+ld4 { v7.s, v8.s, v9.s, v10.s }[2], [x3], x5
+v7,v8,v9,v10:
+ld4 { v7.d, v8.d, v9.d, v10.d }[1], [x3], x5
+v7,v8,v9,v10:
+ld4 { v7.b, v8.b, v9.b, v10.b }[13], [x3], #4
+v7,v8,v9,v10:
+ld4 { v7.h, v8.h, v9.h, v10.h }[2], [x3], #8
+v7,v8,v9,v10:
+ld4 { v7.s, v8.s, v9.s, v10.s }[2], [x3], #16
+v7,v8,v9,v10:
+ld4 { v7.d, v8.d, v9.d, v10.d }[1], [x3], #32
+v7,v8,v9,v10:
+
+@........................................................
+abs v0.8b , v0.8b
+v0:
+abs v0.16b, v0.16b
+v0:
+abs v0.4h , v0.4h
+v0:
+abs v0.8h , v0.8h
+v0:
+abs v0.2s , v0.2s
+v0:
+abs v0.4s , v0.4s
+v0:
+add v0.8b , v0.8b , v0.8b
+v0:
+add v0.16b, v0.16b, v0.16b
+v0:
+add v0.4h , v0.4h , v0.4h
+v0:
+add v0.8h , v0.8h , v0.8h
+v0:
+add v0.2s , v0.2s , v0.2s
+v0:
+add v0.4s , v0.4s , v0.4s
+v0:
+add v0.2d , v0.2d , v0.2d
+v0:
+add d1, d2, d3
+d1:
+addhn v0.8b , v0.8h, v0.8h
+v0:
+addhn2 v0.16b, v0.8h, v0.8h
+v0:
+addhn v0.4h , v0.4s , v0.4s
+v0:
+addhn2 v0.8h , v0.4s , v0.4s
+v0:
+addhn v0.2s , v0.2d , v0.2d
+v0:
+addhn2 v0.4s , v0.2d , v0.2d
+v0:
+addp v0.8b , v0.8b , v0.8b
+v0:
+addp v0.16b, v0.16b, v0.16b
+v0:
+addp v0.4h , v0.4h , v0.4h
+v0:
+addp v0.8h , v0.8h , v0.8h
+v0:
+addp v0.2s , v0.2s , v0.2s
+v0:
+addp v0.4s , v0.4s , v0.4s
+v0:
+addp v0.2d , v0.2d , v0.2d
+v0:
+addp d0, v0.2d
+d0:
+addv b0, v0.8b
+b0:
+addv b0, v0.16b
+b0:
+addv h0, v0.4h
+h0:
+addv h0, v0.8h
+h0:
+addv s0, v0.4s
+s0:
+
+dup v0.2d , x3
+v0:
+dup v0.4s , w3
+v0:
+dup v0.2s , w3
+v0:
+dup v0.8h , w3
+v0:
+dup v0.4h , w3
+v0:
+dup v0.16b, w3
+v0:
+dup v0.8b , w3
+v0:
+dup v1.2d, x3
+v1:
+dup v2.4s, w4
+v2:
+dup v3.2s, w5
+v3:
+dup v4.8h, w6
+v4:
+dup v5.4h, w7
+v5:
+dup v6.16b, w8
+v6:
+dup v7.8b, w9
+v7:
+dup v0.2d , v3.2d[1]
+v0:
+dup v0.2s , v3.2s[1]
+v0:
+dup v0.4s , v3.4s[1]
+v0:
+dup v0.4h , v3.4h[1]
+v0:
+dup v0.8h , v3.8h[1]
+v0:
+dup v0.8b , v3.8b[1]
+v0:
+dup v0.16b, v3.16b[1]
+v0:
+dup v7.2d, v9.d[1]
+v7:
+dup v6.2s, v8.s[1]
+v6:
+dup v5.4s, v7.s[2]
+v5:
+dup v4.4h, v6.h[3]
+v4:
+dup v3.8h, v5.h[4]
+v3:
+dup v2.8b, v4.b[5]
+v2:
+dup v1.16b, v3.b[6]
+v1:
+dup b3, v4.b[1]
+b3:
+dup h3, v4.h[1]
+h3:
+dup s3, v4.s[1]
+s3:
+dup d3, v4.d[1]
+d3:
+
+mov b3, v4.b[1]
+b3:
+mov h3, v4.h[1]
+h3:
+mov s3, v4.s[1]
+s3:
+mov d3, v4.d[1]
+d3:
+smov x3, v2.s[2]
+x3:
+umov w3, v2.s[2]
+w3:
+umov x3, v2.d[1]
+x3:
+
+@ MOV aliases for UMOV instructions above
+
+mov w5, v7.s[2]
+x5:
+mov x17, v19.d[0]
+x17:
+
+ins v2.d[1], x5
+v2:
+ins v2.s[1], w5
+v2:
+ins v2.h[1], w5
+v2:
+ins v2.b[1], w5
+v2:
+
+ins v2.d[1], v15.d[1]
+v2:
+ins v2.s[1], v15.s[1]
+v2:
+ins v2.h[1], v15.h[1]
+v2:
+ins v2.b[1], v15.b[1]
+v2:
+
+@ MOV aliases for the above INS instructions.
+
+mov v9.d[1], x2
+v9:
+mov v8.s[1], w3
+v8:
+mov v7.h[1], w4
+v7:
+mov v6.b[1], w5
+v6:
+mov v2.d[1], v15.d[0]
+v2:
+mov v7.s[3], v16.s[2]
+v7:
+mov v8.h[7], v17.h[3]
+v8:
+mov v9.b[10], v18.b[5]
+v9:
+and v0.8b, v0.8b, v0.8b
+v0:
+and v0.16b, v0.16b, v0.16b
+v0:
+bic v0.8b, v0.8b, v0.8b
+v0:
+cmeq v0.8b, v0.8b, v0.8b
+v0:
+cmge v0.8b, v0.8b, v0.8b
+v0:
+cmgt v0.8b, v0.8b, v0.8b
+v0:
+cmhi v0.8b, v0.8b, v0.8b
+v0:
+cmhs v0.8b, v0.8b, v0.8b
+v0:
+cmtst v0.8b, v0.8b, v0.8b
+v0:
+fabd v0.2s, v0.2s, v0.2s
+v0:
+facge v0.2s, v0.2s, v0.2s
+v0:
+facgt v0.2s, v0.2s, v0.2s
+v0:
+faddp v0.2s, v0.2s, v0.2s
+v0:
+fadd v0.2s, v0.2s, v0.2s
+v0:
+fcmeq v0.2s, v0.2s, v0.2s
+v0:
+fcmge v0.2s, v0.2s, v0.2s
+v0:
+fcmgt v0.2s, v0.2s, v0.2s
+v0:
+fdiv v0.2s, v0.2s, v0.2s
+v0:
+fmaxnmp v0.2s, v0.2s, v0.2s
+v0:
+fmaxnm v0.2s, v0.2s, v0.2s
+v0:
+fmaxp v0.2s, v0.2s, v0.2s
+v0:
+fmax v0.2s, v0.2s, v0.2s
+v0:
+fminnmp v0.2s, v0.2s, v0.2s
+v0:
+fminnm v0.2s, v0.2s, v0.2s
+v0:
+fminp v0.2s, v0.2s, v0.2s
+v0:
+fmin v0.2s, v0.2s, v0.2s
+v0:
+fmla v0.2s, v0.2s, v0.2s
+v0:
+fmls v0.2s, v0.2s, v0.2s
+v0:
+fmulx v0.2s, v0.2s, v0.2s
+v0:
+fmul v0.2s, v0.2s, v0.2s
+v0:
+frecps v0.2s, v0.2s, v0.2s
+v0:
+frsqrts v0.2s, v0.2s, v0.2s
+v0:
+fsub v0.2s, v0.2s, v0.2s
+v0:
+mla v0.8b, v0.8b, v0.8b
+v0:
+mls v0.8b, v0.8b, v0.8b
+v0:
+mul v0.8b, v0.8b, v0.8b
+v0:
+pmul v0.8b, v0.8b, v0.8b
+v0:
+saba v0.8b, v0.8b, v0.8b
+v0:
+sabd v0.8b, v0.8b, v0.8b
+v0:
+shadd v0.8b, v0.8b, v0.8b
+v0:
+shsub v0.8b, v0.8b, v0.8b
+v0:
+smaxp v0.8b, v0.8b, v0.8b
+v0:
+smax v0.8b, v0.8b, v0.8b
+v0:
+sminp v0.8b, v0.8b, v0.8b
+v0:
+smin v0.8b, v0.8b, v0.8b
+v0:
+sqadd v0.8b, v0.8b, v0.8b
+v0:
+sqdmulh v0.4h, v0.4h, v0.4h
+v0:
+sqrdmulh v0.4h, v0.4h, v0.4h
+v0:
+sqrshl v0.8b, v0.8b, v0.8b
+v0:
+sqshl v0.8b, v0.8b, v0.8b
+v0:
+sqsub v0.8b, v0.8b, v0.8b
+v0:
+srhadd v0.8b, v0.8b, v0.8b
+v0:
+srshl v0.8b, v0.8b, v0.8b
+v0:
+
+sshl v0.8b, v0.8b, v0.8b
+v0:
+sub v0.8b, v0.8b, v0.8b
+v0:
+uaba v0.8b, v0.8b, v0.8b
+v0:
+uabd v0.8b, v0.8b, v0.8b
+v0:
+uhadd v0.8b, v0.8b, v0.8b
+v0:
+uhsub v0.8b, v0.8b, v0.8b
+v0:
+umaxp v0.8b, v0.8b, v0.8b
+v0:
+umax v0.8b, v0.8b, v0.8b
+v0:
+uminp v0.8b, v0.8b, v0.8b
+v0:
+umin v0.8b, v0.8b, v0.8b
+v0:
+uqadd v0.8b, v0.8b, v0.8b
+v0:
+uqrshl v0.8b, v0.8b, v0.8b
+v0:
+uqshl v0.8b, v0.8b, v0.8b
+v0:
+uqsub v0.8b, v0.8b, v0.8b
+v0:
+urhadd v0.8b, v0.8b, v0.8b
+v0:
+urshl v0.8b, v0.8b, v0.8b
+v0:
+ushl v0.8b, v0.8b, v0.8b
+v0:
+bif v0.8b, v0.8b, v0.8b
+v0:
+bit v0.8b, v0.8b, v0.8b
+v0:
+bsl v0.8b, v0.8b, v0.8b
+v0:
+eor v0.8b, v0.8b, v0.8b
+v0:
+orn v0.8b, v0.8b, v0.8b
+v0:
+orr v0.8b, v0.8b, v1.8b
+v0:
+
+sadalp v0.4h, v0.8b
+v0:
+sadalp v0.8h, v0.16b
+v0:
+sadalp v0.2s, v0.4h
+v0:
+sadalp v0.4s, v0.8h
+v0:
+sadalp v0.1d, v0.2s
+v0:
+sadalp v0.2d, v0.4s
+v0:
+
+
+cls v0.8b, v0.8b
+v0:
+clz v0.8b, v0.8b
+v0:
+cnt v0.8b, v0.8b
+v0:
+fabs v0.2s, v0.2s
+v0:
+fneg v0.2s, v0.2s
+v0:
+frecpe v0.2s, v0.2s
+v0:
+frinta v0.2s, v0.2s
+v0:
+frintx v0.2s, v0.2s
+v0:
+frinti v0.2s, v0.2s
+v0:
+frintm v0.2s, v0.2s
+v0:
+frintn v0.2s, v0.2s
+v0:
+frintp v0.2s, v0.2s
+v0:
+frintz v0.2s, v0.2s
+v0:
+frsqrte v0.2s, v0.2s
+v0:
+fsqrt v0.2s, v0.2s
+v0:
+
+neg v0.8b, v0.8b
+v0:
+not v0.8b, v0.8b
+v0:
+rbit v0.8b, v0.8b
+v0:
+rev16 v0.8b, v0.8b
+v0:
+rev32 v0.8b, v0.8b
+v0:
+rev64 v0.8b, v0.8b
+v0:
+scvtf v0.2s, v0.2s
+v0:
+sqabs v0.8b, v0.8b
+v0:
+sqneg v0.8b, v0.8b
+v0:
+sqxtn v0.8b, v0.8h
+v0:
+sqxtun v0.8b, v0.8h
+v0:
+suqadd v0.8b, v0.8b
+v0:
+uadalp v0.4h, v0.8b
+v0:
+uaddlp v0.4h, v0.8b
+v0:
+ucvtf v0.2s, v0.2s
+v0:
+uqxtn v0.8b, v0.8h
+v0:
+urecpe v0.2s, v0.2s
+v0:
+ursqrte v0.2s, v0.2s
+v0:
+usqadd v0.8b, v0.8b
+v0:
+
+shll v1.8h, v2.8b, #8
+v1:
+shll v1.4s, v2.4h, #16
+v1:
+shll v1.2d, v2.2s, #32
+v1:
+shll2 v1.8h, v2.16b, #8
+v1:
+shll2 v1.4s, v2.8h, #16
+v1:
+shll2 v1.2d, v2.4s, #32
+v1:
+
+cmeq v0.8b , v0.8b , #0
+v0:
+cmeq v0.16b, v0.16b, #0
+v0:
+cmeq v0.4h , v0.4h , #0
+v0:
+cmeq v0.8h , v0.8h , #0
+v0:
+cmeq v0.2s , v0.2s , #0
+v0:
+cmeq v0.4s , v0.4s , #0
+v0:
+cmeq v0.2d , v0.2d , #0
+v0:
+cmge v0.8b , v0.8b , #0
+v0:
+cmgt v0.8b , v0.8b , #0
+v0:
+cmle v0.8b , v0.8b , #0
+v0:
+
+
+fcmeq v0.2s, v0.2s, #0
+v0:
+fcmge v0.2s, v0.2s, #0
+v0:
+fcmgt v0.2s, v0.2s, #0
+v0:
+fcmle v0.2s, v0.2s, #0
+v0:
+fcmlt v0.2s, v0.2s, #0
+v0:
+
+cmlt v8.8b, v14.8b, #0
+v8:
+cmlt v8.16b, v14.16b, #0
+v8:
+cmlt v8.4h, v14.4h, #0
+v8:
+cmlt v8.8h, v14.8h, #0
+v8:
+cmlt v8.2s, v14.2s, #0
+v8:
+cmlt v8.4s, v14.4s, #0
+v8:
+cmlt v8.2d, v14.2d, #0
+v8:
+@===-------------------------------------------------------------------------===
+@ AdvSIMD Floating-point <-> Integer Conversions
+@===-------------------------------------------------------------------------===
+fcvtas v0.2s, v0.2s
+v0:
+fcvtas v0.4s, v0.4s
+v0:
+fcvtas v0.2d, v0.2d
+v0:
+fcvtas s0, s0
+s0:
+fcvtas d0, d0
+d0:
+fcvtau v0.2s, v0.2s
+v0:
+fcvtau v0.4s, v0.4s
+v0:
+fcvtau v0.2d, v0.2d
+v0:
+fcvtau s0, s0
+s0:
+fcvtau d0, d0
+d0:
+fcvtl v1.4s, v5.4h
+v1:
+fcvtl v2.2d, v6.2s
+v2:
+fcvtl2 v3.4s, v7.8h
+v3:
+fcvtl2 v4.2d, v8.4s
+v4:
+fcvtms v0.2s, v0.2s
+v0:
+fcvtms v0.4s, v0.4s
+v0:
+fcvtms v0.2d, v0.2d
+v0:
+fcvtms s0, s0
+s0:
+fcvtms d0, d0
+d0:
+fcvtmu v0.2s, v0.2s
+v0:
+fcvtmu v0.4s, v0.4s
+v0:
+fcvtmu v0.2d, v0.2d
+v0:
+fcvtmu s0, s0
+s0:
+fcvtmu d0, d0
+d0:
+fcvtns v0.2s, v0.2s
+v0:
+fcvtns v0.4s, v0.4s
+v0:
+fcvtns v0.2d, v0.2d
+v0:
+fcvtns s0, s0
+s0:
+fcvtns d0, d0
+d0:
+fcvtnu v0.2s, v0.2s
+v0:
+fcvtnu v0.4s, v0.4s
+v0:
+fcvtnu v0.2d, v0.2d
+v0:
+fcvtnu s0, s0
+s0:
+fcvtnu d0, d0
+d0:
+fcvtn v2.4h, v4.4s
+v2:
+fcvtn v3.2s, v5.2d
+v3:
+fcvtn2 v4.8h, v6.4s
+v4:
+fcvtn2 v5.4s, v7.2d
+v5:
+fcvtxn v6.2s, v9.2d
+v6:
+fcvtxn2 v7.4s, v8.2d
+v7:
+fcvtps v0.2s, v0.2s
+v0:
+fcvtps v0.4s, v0.4s
+v0:
+fcvtps v0.2d, v0.2d
+v0:
+fcvtps s0, s0
+s0:
+fcvtps d0, d0
+d0:
+fcvtpu v0.2s, v0.2s
+v0:
+fcvtpu v0.4s, v0.4s
+v0:
+fcvtpu v0.2d, v0.2d
+v0:
+fcvtpu s0, s0
+s0:
+fcvtpu d0, d0
+d0:
+fcvtzs v0.2s, v0.2s
+v0:
+fcvtzs v0.4s, v0.4s
+v0:
+fcvtzs v0.2d, v0.2d
+v0:
+fcvtzs s0, s0
+s0:
+fcvtzs d0, d0
+d0:
+fcvtzu v0.2s, v0.2s
+v0:
+fcvtzu v0.4s, v0.4s
+v0:
+fcvtzu v0.2d, v0.2d
+v0:
+fcvtzu s0, s0
+s0:
+fcvtzu d0, d0
+d0:
+@===-------------------------------------------------------------------------===
+@ AdvSIMD modified immediate instructions
+@===-------------------------------------------------------------------------===
+bic v0.2s, #1
+v0:
+bic v0.2s, #1, lsl #0
+v0:
+bic v0.2s, #1, lsl #8
+v0:
+bic v0.2s, #1, lsl #16
+v0:
+bic v0.2s, #1, lsl #24
+v0:
+bic v0.4h, #1
+v0:
+bic v0.4h, #1, lsl #0
+v0:
+bic v0.4h, #1, lsl #8
+v0:
+bic v0.4s, #1
+v0:
+bic v0.4s, #1, lsl #0
+v0:
+bic v0.4s, #1, lsl #8
+v0:
+bic v0.4s, #1, lsl #16
+v0:
+bic v0.4s, #1, lsl #24
+v0:
+bic v0.8h, #1
+v0:
+bic v0.8h, #1, lsl #0
+v0:
+bic v0.8h, #1, lsl #8
+v0:
+fmov v0.2d, #1.250000e-01
+v0:
+fmov v0.2s, #1.250000e-01
+v0:
+fmov v0.4s, #1.250000e-01
+v0:
+orr v0.2s, #1
+v0:
+orr v0.2s, #1, lsl #0
+v0:
+orr v0.2s, #1, lsl #8
+v0:
+orr v0.2s, #1, lsl #16
+v0:
+orr v0.2s, #1, lsl #24
+v0:
+orr v0.4h, #1
+v0:
+orr v0.4h, #1, lsl #0
+v0:
+orr v0.4h, #1, lsl #8
+v0:
+orr v0.4s, #1
+v0:
+orr v0.4s, #1, lsl #0
+v0:
+orr v0.4s, #1, lsl #8
+v0:
+orr v0.4s, #1, lsl #16
+v0:
+orr v0.4s, #1, lsl #24
+v0:
+orr v0.8h, #1
+v0:
+orr v0.8h, #1, lsl #0
+v0:
+orr v0.8h, #1, lsl #8
+v0:
+
+
+
+movi d0, #0x000000000000ff
+d0:
+movi v0.2d, #0x000000000000ff
+v0:
+
+movi v0.2s, #1
+v0:
+movi v0.2s, #1, lsl #0
+v0:
+movi v0.2s, #1, lsl #8
+v0:
+movi v0.2s, #1, lsl #16
+v0:
+movi v0.2s, #1, lsl #24
+v0:
+movi v0.4s, #1
+v0:
+movi v0.4s, #1, lsl #0
+v0:
+movi v0.4s, #1, lsl #8
+v0:
+movi v0.4s, #1, lsl #16
+v0:
+movi v0.4s, #1, lsl #24
+v0:
+movi v0.4h, #1
+v0:
+movi v0.4h, #1, lsl #0
+v0:
+movi v0.4h, #1, lsl #8
+v0:
+movi v0.8h, #1
+v0:
+movi v0.8h, #1, lsl #0
+v0:
+movi v0.8h, #1, lsl #8
+v0:
+movi v0.2s, #1, msl #8
+v0:
+movi v0.2s, #1, msl #16
+v0:
+movi v0.4s, #1, msl #8
+v0:
+movi v0.4s, #1, msl #16
+v0:
+movi v0.8b, #1
+v0:
+movi v0.16b, #1
+v0:
+mvni v0.2s, #1
+v0:
+mvni v0.2s, #1, lsl #0
+v0:
+mvni v0.2s, #1, lsl #8
+v0:
+mvni v0.2s, #1, lsl #16
+v0:
+mvni v0.2s, #1, lsl #24
+v0:
+mvni v0.4s, #1
+v0:
+mvni v0.4s, #1, lsl #0
+v0:
+mvni v0.4s, #1, lsl #8
+v0:
+mvni v0.4s, #1, lsl #16
+v0:
+mvni v0.4s, #1, lsl #24
+v0:
+mvni v0.4h, #1
+v0:
+mvni v0.4h, #1, lsl #0
+v0:
+mvni v0.4h, #1, lsl #8
+v0:
+mvni v0.8h, #1
+v0:
+mvni v0.8h, #1, lsl #0
+v0:
+mvni v0.8h, #1, lsl #8
+v0:
+mvni v0.2s, #1, msl #8
+v0:
+mvni v0.2s, #1, msl #16
+v0:
+mvni v0.4s, #1, msl #8
+v0:
+mvni v0.4s, #1, msl #16
+v0:
+
+@===-------------------------------------------------------------------------===
+@ AdvSIMD scalar x index
+@===-------------------------------------------------------------------------===
+
+fmla s0, s0, v0.s[3]
+s0:
+fmla d0, d0, v0.d[1]
+d0:
+
+fmls s0, s0, v0.s[3]
+s0:
+fmls d0, d0, v0.d[1]
+d0:
+fmulx s0, s0, v0.s[3]
+s0:
+fmulx d0, d0, v0.d[1]
+d0:
+fmul s0, s0, v0.s[3]
+s0:
+fmul d0, d0, v0.d[1]
+d0:
+sqdmlal s0, h0, v0.h[7]
+s0:
+sqdmlal d0, s0, v0.s[3]
+d0:
+sqdmlsl s0, h0, v0.h[7]
+s0:
+sqdmulh h0, h0, v0.h[7]
+h0:
+sqdmulh s0, s0, v0.s[3]
+s0:
+sqdmull s0, h0, v0.h[7]
+s0:
+sqdmull d0, s0, v0.s[3]
+d0:
+sqrdmulh h0, h0, v0.h[7]
+h0:
+sqrdmulh s0, s0, v0.s[3]
+s0:
+
+@===-------------------------------------------------------------------------===
+@ AdvSIMD SMLAL
+@===-------------------------------------------------------------------------===
+
+smlal v13.8h, v8.8b, v0.8b
+v13:
+smlal v13.4s, v8.4h, v0.4h
+v13:
+smlal v13.2d, v8.2s, v0.2s
+v13:
+smlal2 v13.8h, v8.16b, v0.16b
+v13:
+smlal2 v13.4s, v8.8h, v0.8h
+v13:
+smlal2 v13.2d, v8.4s, v0.4s
+v13:
+@===-------------------------------------------------------------------------===
+@ AdvSIMD scalar x index
+@===-------------------------------------------------------------------------===
+fmla v0.2s, v0.2s, v0.2s[0]
+v0:
+fmla v0.4s, v0.4s, v0.4s[1]
+v0:
+fmla v0.2d, v0.2d, v0.2d[1]
+v0:
+fmls v0.2s, v0.2s, v0.2s[0]
+v0:
+fmls v0.4s, v0.4s, v0.4s[1]
+v0:
+fmls v0.2d, v0.2d, v0.2d[1]
+v0:
+fmulx v0.2s, v0.2s, v0.2s[0]
+v0:
+fmulx v0.4s, v0.4s, v0.4s[1]
+v0:
+fmulx v0.2d, v0.2d, v0.2d[1]
+v0:
+fmul v0.2s, v0.2s, v0.2s[0]
+v0:
+fmul v0.4s, v0.4s, v0.4s[1]
+v0:
+fmul v0.2d, v0.2d, v0.2d[1]
+v0:
+mla v0.4h, v0.4h, v0.4h[0]
+v0:
+mla v0.8h, v0.8h, v0.8h[1]
+v0:
+mla v0.2s, v0.2s, v0.2s[2]
+v0:
+mla v0.4s, v0.4s, v0.4s[3]
+v0:
+mls v0.4h, v0.4h, v0.4h[0]
+v0:
+mls v0.8h, v0.8h, v0.8h[1]
+v0:
+mls v0.2s, v0.2s, v0.2s[2]
+v0:
+mls v0.4s, v0.4s, v0.4s[3]
+v0:
+mul v0.4h, v0.4h, v0.4h[0]
+v0:
+mul v0.8h, v0.8h, v0.8h[1]
+v0:
+mul v0.2s, v0.2s, v0.2s[2]
+v0:
+mul v0.4s, v0.4s, v0.4s[3]
+v0:
+smlal v0.4s, v0.4h, v0.h[0]
+v0:
+smlal2 v0.4s, v0.8h, v0.h[1]
+v0:
+smlal v0.2d, v0.2s, v0.s[2]
+v0:
+smlal2 v0.2d, v0.4s, v0.s[3]
+v0:
+smlsl v0.4s, v0.4h, v0.h[0]
+v0:
+smlsl2 v0.4s, v0.8h, v0.h[1]
+v0:
+smlsl v0.2d, v0.2s, v0.s[2]
+v0:
+smlsl2 v0.2d, v0.4s, v0.s[3]
+v0:
+smull v0.4s, v0.4h, v0.h[0]
+v0:
+smull2 v0.4s, v0.8h, v0.h[1]
+v0:
+smull v0.2d, v0.2s, v0.s[2]
+v0:
+smull2 v0.2d, v0.4s, v0.s[3]
+v0:
+sqdmlal v0.4s, v0.4h, v0.h[0]
+v0:
+sqdmlal2 v0.4s, v0.8h, v0.h[1]
+v0:
+sqdmlal v0.2d, v0.2s, v0.s[2]
+v0:
+sqdmlal2 v0.2d, v0.4s, v0.s[3]
+v0:
+sqdmlsl v0.4s, v0.4h, v0.h[0]
+v0:
+sqdmlsl2 v0.4s, v0.8h, v0.h[1]
+v0:
+sqdmlsl v0.2d, v0.2s, v0.s[2]
+v0:
+sqdmlsl2 v0.2d, v0.4s, v0.s[3]
+v0:
+sqdmull v0.2d, v0.2s, v0.s[2]
+v0:
+sqdmull2 v0.2d, v0.4s, v0.s[3]
+v0:
+sqrdmulh v0.4h, v0.4h, v0.h[0]
+v0:
+sqrdmulh v0.8h, v0.8h, v0.h[1]
+v0:
+sqrdmulh v0.2s, v0.2s, v0.s[2]
+v0:
+sqrdmulh v0.4s, v0.4s, v0.s[3]
+v0:
+umlal v0.4s, v0.4h, v0.h[0]
+v0:
+umlal2 v0.4s, v0.8h, v0.h[1]
+v0:
+umlal v0.2d, v0.2s, v0.s[2]
+v0:
+umlal2 v0.2d, v0.4s, v0.s[3]
+v0:
+umlsl v0.4s, v0.4h, v0.h[0]
+v0:
+umlsl2 v0.4s, v0.8h, v0.h[1]
+v0:
+umlsl v0.2d, v0.2s, v0.s[2]
+v0:
+umlsl2 v0.2d, v0.4s, v0.s[3]
+v0:
+umull v0.4s, v0.4h, v0.h[0]
+v0:
+umull2 v0.4s, v0.8h, v0.h[1]
+v0:
+umull v0.2d, v0.2s, v0.s[2]
+v0:
+umull2 v0.2d, v0.4s, v0.s[3]
+v0:
+@===-------------------------------------------------------------------------===
+@ AdvSIMD scalar with shift
+@===-------------------------------------------------------------------------===
+fcvtzs s0, s0, #1
+s0:
+fcvtzs d0, d0, #2
+d0:
+fcvtzu s0, s0, #1
+s0:
+fcvtzu d0, d0, #2
+d0:
+shl d0, d0, #1
+d0:
+sli d0, d0, #1
+d0:
+sqrshrn b0, h0, #1
+b0:
+sqrshrn h0, s0, #2
+h0:
+sqrshrn s0, d0, #3
+s0:
+sqrshrun b0, h0, #1
+b0:
+sqrshrun h0, s0, #2
+h0:
+sqrshrun s0, d0, #3
+s0:
+sqshlu b0, b0, #1
+b0:
+sqshlu h0, h0, #2
+h0:
+sqshlu s0, s0, #3
+s0:
+sqshlu d0, d0, #4
+d0:
+sqshl b0, b0, #1
+b0:
+sqshl h0, h0, #2
+h0:
+sqshl s0, s0, #3
+s0:
+sqshl d0, d0, #4
+d0:
+sqshrn b0, h0, #1
+b0:
+sqshrn h0, s0, #2
+h0:
+sqshrn s0, d0, #3
+s0:
+sqshrun b0, h0, #1
+b0:
+sqshrun h0, s0, #2
+h0:
+sqshrun s0, d0, #3
+s0:
+sri d0, d0, #1
+d0:
+srshr d0, d0, #1
+d0:
+srsra d0, d0, #1
+d0:
+sshr d0, d0, #1
+d0:
+ucvtf s0, s0, #1
+s0:
+ucvtf d0, d0, #2
+d0:
+scvtf s0, s0, #1
+s0:
+scvtf d0, d0, #2
+d0:
+uqrshrn b0, h0, #1
+b0:
+uqrshrn h0, s0, #2
+h0:
+uqrshrn s0, d0, #3
+s0:
+uqshl b0, b0, #1
+b0:
+uqshl h0, h0, #2
+h0:
+uqshl s0, s0, #3
+s0:
+uqshl d0, d0, #4
+d0:
+uqshrn b0, h0, #1
+b0:
+uqshrn h0, s0, #2
+h0:
+uqshrn s0, d0, #3
+s0:
+urshr d0, d0, #1
+d0:
+ursra d0, d0, #1
+d0:
+ushr d0, d0, #1
+d0:
+usra d0, d0, #1
+d0:
+
+@===-------------------------------------------------------------------------===
+@ AdvSIMD vector with shift
+@===-------------------------------------------------------------------------===
+fcvtzs v0.2s , v0.2s , #1
+v0:
+fcvtzs v0.4s , v0.4s , #2
+v0:
+fcvtzs v0.2d , v0.2d , #3
+v0:
+fcvtzu v0.2s , v0.2s , #1
+v0:
+fcvtzu v0.4s , v0.4s , #2
+v0:
+fcvtzu v0.2d , v0.2d , #3
+v0:
+rshrn v0.8b , v0.8h , #1
+v0:
+rshrn2 v0.16b, v0.8h, #2
+v0:
+rshrn v0.4h , v0.4s , #3
+v0:
+rshrn2 v0.8h , v0.4s , #4
+v0:
+rshrn v0.2s , v0.2d , #5
+v0:
+rshrn2 v0.4s , v0.2d , #6
+v0:
+scvtf v0.2s , v0.2s , #1
+v0:
+scvtf v0.4s , v0.4s , #2
+v0:
+scvtf v0.2d , v0.2d , #3
+v0:
+shl v0.8b , v0.8b , #1
+v0:
+shl v0.16b, v0.16b, #2
+v0:
+shl v0.4h , v0.4h , #3
+v0:
+shl v0.8h , v0.8h , #4
+v0:
+shl v0.2s , v0.2s , #5
+v0:
+shl v0.4s , v0.4s , #6
+v0:
+shl v0.2d , v0.2d , #7
+v0:
+shrn v0.8b , v0.8h , #1
+v0:
+shrn2 v0.16b, v0.8h, #2
+v0:
+shrn v0.4h , v0.4s , #3
+v0:
+shrn2 v0.8h , v0.4s , #4
+v0:
+shrn v0.2s , v0.2d , #5
+v0:
+shrn2 v0.4s , v0.2d , #6
+v0:
+sli v0.8b , v0.8b , #1
+v0:
+sli v0.16b, v0.16b, #2
+v0:
+sli v0.4h , v0.4h , #3
+v0:
+sli v0.8h , v0.8h , #4
+v0:
+sli v0.2s , v0.2s , #5
+v0:
+sli v0.4s , v0.4s , #6
+v0:
+sli v0.2d , v0.2d , #7
+v0:
+sqrshrn v0.8b , v0.8h , #1
+v0:
+sqrshrn2 v0.16b, v0.8h, #2
+v0:
+sqrshrn v0.4h , v0.4s , #3
+v0:
+sqrshrn2 v0.8h , v0.4s , #4
+v0:
+sqrshrn v0.2s , v0.2d , #5
+v0:
+sqrshrn2 v0.4s , v0.2d , #6
+v0:
+sqrshrun v0.8b , v0.8h , #1
+v0:
+sqrshrun2 v0.16b, v0.8h, #2
+v0:
+sqrshrun v0.4h , v0.4s , #3
+v0:
+sqrshrun2 v0.8h , v0.4s , #4
+v0:
+sqrshrun v0.2s , v0.2d , #5
+v0:
+sqrshrun2 v0.4s , v0.2d , #6
+v0:
+sqshlu v0.8b , v0.8b , #1
+v0:
+sqshlu v0.16b, v0.16b, #2
+v0:
+sqshlu v0.4h , v0.4h , #3
+v0:
+sqshlu v0.8h , v0.8h , #4
+v0:
+sqshlu v0.2s , v0.2s , #5
+v0:
+sqshlu v0.4s , v0.4s , #6
+v0:
+sqshlu v0.2d , v0.2d , #7
+v0:
+sqshl v0.8b , v0.8b , #1
+v0:
+sqshl v0.16b, v0.16b, #2
+v0:
+sqshl v0.4h , v0.4h , #3
+v0:
+sqshl v0.8h , v0.8h , #4
+v0:
+sqshl v0.2s , v0.2s , #5
+v0:
+sqshl v0.4s , v0.4s , #6
+v0:
+sqshl v0.2d , v0.2d , #7
+v0:
+sqshrn v0.8b , v0.8h , #1
+v0:
+sqshrn2 v0.16b, v0.8h, #2
+v0:
+sqshrn v0.4h , v0.4s , #3
+v0:
+sqshrn2 v0.8h , v0.4s , #4
+v0:
+sqshrn v0.2s , v0.2d , #5
+v0:
+sqshrn2 v0.4s , v0.2d , #6
+v0:
+sqshrun v0.8b , v0.8h , #1
+v0:
+sqshrun2 v0.16b, v0.8h, #2
+v0:
+sqshrun v0.4h , v0.4s , #3
+v0:
+sqshrun2 v0.8h , v0.4s , #4
+v0:
+sqshrun v0.2s , v0.2d , #5
+v0:
+sqshrun2 v0.4s , v0.2d , #6
+v0:
+sri v0.8b , v0.8b , #1
+v0:
+sri v0.16b, v0.16b, #2
+v0:
+sri v0.4h , v0.4h , #3
+v0:
+sri v0.8h , v0.8h , #4
+v0:
+sri v0.2s , v0.2s , #5
+v0:
+sri v0.4s , v0.4s , #6
+v0:
+sri v0.2d , v0.2d , #7
+v0:
+srshr v0.8b , v0.8b , #1
+v0:
+srshr v0.16b, v0.16b, #2
+v0:
+srshr v0.4h , v0.4h , #3
+v0:
+srshr v0.8h , v0.8h , #4
+v0:
+srshr v0.2s , v0.2s , #5
+v0:
+srshr v0.4s , v0.4s , #6
+v0:
+srshr v0.2d , v0.2d , #7
+v0:
+srsra v0.8b , v0.8b , #1
+v0:
+srsra v0.16b, v0.16b, #2
+v0:
+srsra v0.4h , v0.4h , #3
+v0:
+srsra v0.8h , v0.8h , #4
+v0:
+srsra v0.2s , v0.2s , #5
+v0:
+srsra v0.4s , v0.4s , #6
+v0:
+srsra v0.2d , v0.2d , #7
+v0:
+sshll v0.8h , v0.8b , #1
+v0:
+sshll2 v0.8h , v0.16b, #2
+v0:
+sshll v0.4s , v0.4h , #3
+v0:
+sshll2 v0.4s , v0.8h , #4
+v0:
+sshll v0.2d , v0.2s , #5
+v0:
+sshll2 v0.2d , v0.4s , #6
+v0:
+sshr v0.8b , v0.8b , #1
+v0:
+sshr v0.16b, v0.16b, #2
+v0:
+sshr v0.4h , v0.4h , #3
+v0:
+sshr v0.8h , v0.8h , #4
+v0:
+sshr v0.2s , v0.2s , #5
+v0:
+sshr v0.4s , v0.4s , #6
+v0:
+sshr v0.2d , v0.2d , #7
+v0:
+sshr v0.8b , v0.8b , #1
+v0:
+ssra v0.16b, v0.16b, #2
+v0:
+ssra v0.4h , v0.4h , #3
+v0:
+ssra v0.8h , v0.8h , #4
+v0:
+ssra v0.2s , v0.2s , #5
+v0:
+ssra v0.4s , v0.4s , #6
+v0:
+ssra v0.2d , v0.2d , #7
+v0:
+ssra d0, d0, #64
+v0:
+ucvtf v0.2s , v0.2s , #1
+v0:
+ucvtf v0.4s , v0.4s , #2
+v0:
+ucvtf v0.2d , v0.2d , #3
+v0:
+uqrshrn v0.8b , v0.8h , #1
+v0:
+uqrshrn2 v0.16b, v0.8h, #2
+v0:
+uqrshrn v0.4h , v0.4s , #3
+v0:
+uqrshrn2 v0.8h , v0.4s , #4
+v0:
+uqrshrn v0.2s , v0.2d , #5
+v0:
+uqrshrn2 v0.4s , v0.2d , #6
+v0:
+uqshl v0.8b , v0.8b , #1
+v0:
+uqshl v0.16b, v0.16b, #2
+v0:
+uqshl v0.4h , v0.4h , #3
+v0:
+uqshl v0.8h , v0.8h , #4
+v0:
+uqshl v0.2s , v0.2s , #5
+v0:
+uqshl v0.4s , v0.4s , #6
+v0:
+uqshl v0.2d , v0.2d , #7
+v0:
+uqshrn v0.8b , v0.8h , #1
+v0:
+uqshrn2 v0.16b, v0.8h, #2
+v0:
+uqshrn v0.4h , v0.4s , #3
+v0:
+uqshrn2 v0.8h , v0.4s , #4
+v0:
+uqshrn v0.2s , v0.2d , #5
+v0:
+uqshrn2 v0.4s , v0.2d , #6
+v0:
+urshr v0.8b , v0.8b , #1
+v0:
+urshr v0.16b, v0.16b, #2
+v0:
+urshr v0.4h , v0.4h , #3
+v0:
+urshr v0.8h , v0.8h , #4
+v0:
+urshr v0.2s , v0.2s , #5
+v0:
+urshr v0.4s , v0.4s , #6
+v0:
+urshr v0.2d , v0.2d , #7
+v0:
+ursra v0.8b , v0.8b , #1
+v0:
+ursra v0.16b, v0.16b, #2
+v0:
+ursra v0.4h , v0.4h , #3
+v0:
+ursra v0.8h , v0.8h , #4
+v0:
+ursra v0.2s , v0.2s , #5
+v0:
+ursra v0.4s , v0.4s , #6
+v0:
+ursra v0.2d , v0.2d , #7
+v0:
+ushll v0.8h , v0.8b , #1
+v0:
+ushll2 v0.8h , v0.16b , #2
+v0:
+ushll v0.4s , v0.4h , #3
+v0:
+ushll2 v0.4s , v0.8h , #4
+v0:
+ushll v0.2d , v0.2s , #5
+v0:
+ushll2 v0.2d , v0.4s , #6
+v0:
+ushr v0.8b , v0.8b , #1
+v0:
+ushr v0.16b, v0.16b, #2
+v0:
+ushr v0.4h , v0.4h , #3
+v0:
+ushr v0.8h , v0.8h , #4
+v0:
+ushr v0.2s , v0.2s , #5
+v0:
+ushr v0.4s , v0.4s , #6
+v0:
+ushr v0.2d , v0.2d , #7
+v0:
+usra v0.8b , v0.8b , #1
+v0:
+usra v0.16b, v0.16b, #2
+v0:
+usra v0.4h , v0.4h , #3
+v0:
+usra v0.8h , v0.8h , #4
+v0:
+usra v0.2s , v0.2s , #5
+v0:
+usra v0.4s , v0.4s , #6
+v0:
+usra v0.2d , v0.2d , #7
+v0:
+sqdmull v10.4s, v12.4h, v12.4h
+v10:
+sqdmull2 v10.4s, v13.8h, v13.8h
+v10:
+sqdmull v10.2d, v13.2s, v13.2s
+v10:
+sqdmull2 v10.2d, v13.4s, v13.4s
+v10:
+xtn v14.8b, v14.8h
+v14:
+xtn2 v14.16b, v14.8h
+v14:
+xtn v14.4h, v14.4s
+v14:
+xtn2 v14.8h, v14.4s
+v14:
+xtn v14.2s, v14.2d
+v14:
+xtn2 v14.4s, v14.2d
+v14:
+uaddl v9.8h, v13.8b, v14.8b
+v9:
+uaddl2 v9.8h, v13.16b, v14.16b
+v9:
+uaddl v9.4s, v13.4h, v14.4h
+v9:
+uaddl2 v9.4s, v13.8h, v14.8h
+v9:
+uaddl v9.2d, v13.2s, v14.2s
+v9:
+uaddl2 v9.2d, v13.4s, v14.4s
+v9:
+bit v9.16b, v10.16b, v10.16b
+v9:
+bit v9.8b, v10.8b, v10.8b
+v9:
+pmull v8.8h, v8.8b, v8.8b
+v8:
+pmull2 v8.8h, v8.16b, v8.16b
+v8:
+usubl v9.8h, v13.8b, v14.8b
+v9:
+usubl2 v9.8h, v13.16b, v14.16b
+v9:
+usubl v9.4s, v13.4h, v14.4h
+v9:
+usubl2 v9.4s, v13.8h, v14.8h
+v9:
+usubl v9.2d, v13.2s, v14.2s
+v9:
+usubl2 v9.2d, v13.4s, v14.4s
+v9:
+uabdl v9.8h, v13.8b, v14.8b
+v9:
+uabdl2 v9.8h, v13.16b, v14.16b
+v9:
+uabdl v9.4s, v13.4h, v14.4h
+v9:
+uabdl2 v9.4s, v13.8h, v14.8h
+v9:
+uabdl v9.2d, v13.2s, v14.2s
+v9:
+uabdl2 v9.2d, v13.4s, v14.4s
+v9:
+umull v9.8h, v13.8b, v14.8b
+v9:
+umull2 v9.8h, v13.16b, v14.16b
+v9:
+umull v9.4s, v13.4h, v14.4h
+v9:
+umull2 v9.4s, v13.8h, v14.8h
+v9:
+umull v9.2d, v13.2s, v14.2s
+v9:
+umull2 v9.2d, v13.4s, v14.4s
+v9:
+smull v9.8h, v13.8b, v14.8b
+v9:
+smull2 v9.8h, v13.16b, v14.16b
+v9:
+smull v9.4s, v13.4h, v14.4h
+v9:
+smull2 v9.4s, v13.8h, v14.8h
+v9:
+smull v9.2d, v13.2s, v14.2s
+v9:
+smull2 v9.2d, v13.4s, v14.4s
+v9:
--
1.9.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v5 4/6] Support for recording aarch64 advanced SIMD instructions
2015-05-11 7:27 ` [PATCH v5 0/6] Omair Javaid
` (4 preceding siblings ...)
2015-05-11 7:27 ` [PATCH v5 3/6] Support for recording syscall on aarch64-linux Omair Javaid
@ 2015-05-11 7:27 ` Omair Javaid
2015-05-11 11:18 ` [PATCH v5 0/6] Yao Qi
6 siblings, 0 replies; 11+ messages in thread
From: Omair Javaid @ 2015-05-11 7:27 UTC (permalink / raw)
To: gdb-patches
I have updated this patch after suggested changes. I have made some updated though most of code seemed to follow the manual.
I will reply to questions on last review message separately.
gdb:
2015-05-11 Omair Javaid <omair.javaid@linaro.org>
* aarch64-tdep.c (aarch64_record_data_proc_simd_fp): New function.
(aarch64_record_asimd_load_store): New function.
(aarch64_record_load_store): Install record handler
aarch64_record_asimd_load_store.
(aarch64_record_decode_insn_handler): Install record handler
aarch64_record_data_proc_simd_fp.
---
gdb/aarch64-tdep.c | 257 ++++++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 255 insertions(+), 2 deletions(-)
diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index 9905552..365c2d0 100644
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -2943,6 +2943,7 @@ aarch64_record_data_proc_reg (insn_decode_record *aarch64_insn_r)
}
/* Record handler for data processing - immediate instructions. */
+
static unsigned int
aarch64_record_data_proc_imm (insn_decode_record *aarch64_insn_r)
{
@@ -2988,6 +2989,7 @@ aarch64_record_data_proc_imm (insn_decode_record *aarch64_insn_r)
}
/* Record handler for branch, exception generation and system instructions. */
+
static unsigned int
aarch64_record_branch_except_sys (insn_decode_record *aarch64_insn_r)
{
@@ -3064,7 +3066,168 @@ aarch64_record_branch_except_sys (insn_decode_record *aarch64_insn_r)
return AARCH64_RECORD_SUCCESS;
}
+/* Record handler for advanced SIMD load and store instructions. */
+
+static unsigned int
+aarch64_record_asimd_load_store (insn_decode_record *aarch64_insn_r)
+{
+ CORE_ADDR address;
+ uint64_t addr_offset = 0;
+ uint32_t record_buf[24];
+ uint64_t record_buf_mem[24];
+ uint32_t reg_rn, reg_rt;
+ uint32_t reg_index = 0, mem_index = 0;
+ uint8_t opcode_bits, size_bits;
+
+ reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
+ reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9);
+ size_bits = bits (aarch64_insn_r->aarch64_insn, 10, 11);
+ opcode_bits = bits (aarch64_insn_r->aarch64_insn, 12, 15);
+ regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, &address);
+
+ /* Load/store single structure. */
+ if (bit (aarch64_insn_r->aarch64_insn, 24))
+ {
+ uint8_t sindex, scale, selem, esize, replicate = 0;
+ scale = opcode_bits >> 2;
+ selem = ((opcode_bits & 0x02) |
+ bit (aarch64_insn_r->aarch64_insn, 21)) + 1;
+ switch (scale)
+ {
+ case 1:
+ if (size_bits & 0x01)
+ return AARCH64_RECORD_UNKNOWN;
+ break;
+ case 2:
+ if ((size_bits >> 1) & 0x01)
+ return AARCH64_RECORD_UNKNOWN;
+ if (size_bits & 0x01)
+ {
+ if (!((opcode_bits >> 1) & 0x01))
+ scale = 3;
+ else
+ return AARCH64_RECORD_UNKNOWN;
+ }
+ break;
+ case 3:
+ if (bit (aarch64_insn_r->aarch64_insn, 22) && !(opcode_bits & 0x01))
+ {
+ scale = size_bits;
+ replicate = 1;
+ break;
+ }
+ else
+ return AARCH64_RECORD_UNKNOWN;
+ default:
+ break;
+ }
+ esize = 8 << scale;
+ if (replicate)
+ for (sindex = 0; sindex < selem; sindex++)
+ {
+ record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM;
+ reg_rt = (reg_rt + 1) % 32;
+ }
+ else
+ {
+ for (sindex = 0; sindex < selem; sindex++)
+ if (bit (aarch64_insn_r->aarch64_insn, 22))
+ record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM;
+ else
+ {
+ record_buf_mem[mem_index++] = esize / 8;
+ record_buf_mem[mem_index++] = address + addr_offset;
+ }
+ addr_offset = addr_offset + (esize / 8);
+ reg_rt = (reg_rt + 1) % 32;
+ }
+ }
+ /* Load/store multiple structure. */
+ else
+ {
+ uint8_t selem, esize, rpt, elements;
+ uint8_t eindex, rindex;
+ esize = 8 << size_bits;
+ if (bit (aarch64_insn_r->aarch64_insn, 30))
+ elements = 128 / esize;
+ else
+ elements = 64 / esize;
+
+ switch (opcode_bits)
+ {
+ /*LD/ST4 (4 Registers). */
+ case 0:
+ rpt = 1;
+ selem = 4;
+ break;
+ /*LD/ST1 (4 Registers). */
+ case 2:
+ rpt = 4;
+ selem = 1;
+ break;
+ /*LD/ST3 (3 Registers). */
+ case 4:
+ rpt = 1;
+ selem = 3;
+ break;
+ /*LD/ST1 (3 Registers). */
+ case 6:
+ rpt = 3;
+ selem = 1;
+ break;
+ /*LD/ST1 (1 Register). */
+ case 7:
+ rpt = 1;
+ selem = 1;
+ break;
+ /*LD/ST2 (2 Registers). */
+ case 8:
+ rpt = 1;
+ selem = 2;
+ break;
+ /*LD/ST1 (2 Registers). */
+ case 10:
+ rpt = 2;
+ selem = 1;
+ break;
+ default:
+ return AARCH64_RECORD_UNSUPPORTED;
+ break;
+ }
+ for (rindex = 0; rindex < rpt; rindex++)
+ for (eindex = 0; eindex < elements; eindex++)
+ {
+ uint8_t reg_tt, sindex;
+ reg_tt = (reg_rt + rindex) % 32;
+ for (sindex = 0; sindex < selem; sindex++)
+ {
+ if (bit (aarch64_insn_r->aarch64_insn, 22))
+ record_buf[reg_index++] = reg_tt + AARCH64_V0_REGNUM;
+ else
+ {
+ record_buf_mem[mem_index++] = esize / 8;
+ record_buf_mem[mem_index++] = address + addr_offset;
+ }
+ addr_offset = addr_offset + (esize / 8);
+ reg_tt = (reg_tt + 1) % 32;
+ }
+ }
+ }
+
+ if (bit (aarch64_insn_r->aarch64_insn, 23))
+ record_buf[reg_index++] = reg_rn;
+
+ aarch64_insn_r->reg_rec_count = reg_index;
+ aarch64_insn_r->mem_rec_count = mem_index / 2;
+ MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count,
+ record_buf_mem);
+ REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
+ record_buf);
+ return AARCH64_RECORD_SUCCESS;
+}
+
/* Record handler for load and store instructions. */
+
static unsigned int
aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
{
@@ -3302,7 +3465,7 @@ aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
}
/* Advanced SIMD load/store instructions. */
else
- return AARCH64_RECORD_UNSUPPORTED;
+ return aarch64_record_asimd_load_store (aarch64_insn_r);
MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count,
record_buf_mem);
@@ -3310,6 +3473,96 @@ aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
record_buf);
return AARCH64_RECORD_SUCCESS;
}
+
+/* Record handler for data processing SIMD and floating point instructions. */
+
+static unsigned int
+aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
+{
+ uint8_t insn_bit21, opcode, rmode, reg_rd;
+ uint8_t insn_bits24_27, insn_bits28_31, insn_bits10_11, insn_bits12_15;
+ uint8_t insn_bits11_14;
+ uint32_t record_buf[2];
+
+ insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
+ insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31);
+ insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11);
+ insn_bits12_15 = bits (aarch64_insn_r->aarch64_insn, 12, 15);
+ insn_bits11_14 = bits (aarch64_insn_r->aarch64_insn, 11, 14);
+ opcode = bits (aarch64_insn_r->aarch64_insn, 16, 18);
+ rmode = bits (aarch64_insn_r->aarch64_insn, 19, 20);
+ reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
+ insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21);
+
+ if ((insn_bits28_31 & 0x05) == 0x01 && insn_bits24_27 == 0x0e)
+ {
+ /* Floating point - fixed point conversion instructions. */
+ if (!insn_bit21)
+ {
+ if ((opcode >> 1) == 0x0 && rmode == 0x03)
+ record_buf[0] = reg_rd;
+ else
+ record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
+ }
+ /* Floating point - conditional compare instructions. */
+ else if (insn_bits10_11 == 0x01)
+ record_buf[0] = AARCH64_CPSR_REGNUM;
+ /* Floating point - data processing (2-source) and
+ conditional select instructions. */
+ else if (insn_bits10_11 == 0x02 || insn_bits10_11 == 0x03)
+ record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
+ else if (insn_bits10_11 == 0x00)
+ {
+ /* Floating point - immediate instructions. */
+ if ((insn_bits12_15 & 0x01) == 0x01 || (insn_bits12_15 & 0x07) == 0x04)
+ record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
+ /* Floating point - compare instructions. */
+ else if ((insn_bits12_15 & 0x03) == 0x02)
+ record_buf[0] = AARCH64_CPSR_REGNUM;
+ /* Floating point - integer conversions instructions. */
+ if (insn_bits12_15 == 0x00)
+ {
+ /* Convert float to integer instruction. */
+ if (!(opcode >> 1) || ((opcode >> 1) == 0x02 && !rmode))
+ record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
+ /* Convert integer to float instruction. */
+ else if ((opcode >> 1) == 0x01 && !rmode)
+ record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
+ /* Move float to integer instruction. */
+ else if ((opcode >> 1) == 0x03)
+ {
+ if (!(opcode & 0x01))
+ record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
+ else
+ record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
+ }
+ }
+ }
+ }
+ else if ((insn_bits28_31 & 0x09) == 0x00 && insn_bits24_27 == 0x0e)
+ {
+ /* Advanced SIMD copy instructions. */
+ if (!bits (aarch64_insn_r->aarch64_insn, 21, 23)
+ && !bit (aarch64_insn_r->aarch64_insn, 15)
+ && bit (aarch64_insn_r->aarch64_insn, 10))
+ {
+ if (insn_bits11_14 == 0x05 || insn_bits11_14 == 0x07)
+ record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
+ else
+ record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
+ }
+ else
+ record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
+ }
+ /* All remaining floating point or advanced SIMD instructions. */
+ else
+ record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
+
+ REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
+ record_buf);
+ return AARCH64_RECORD_SUCCESS;
+}
+
/* Decodes insns type and invokes its record handler. */
static unsigned int
@@ -3340,7 +3593,7 @@ aarch64_record_decode_insn_handler (insn_decode_record *aarch64_insn_r)
/* Data processing - SIMD and floating point instructions. */
if (ins_bit25 && ins_bit26 && ins_bit27)
- return AARCH64_RECORD_UNSUPPORTED;
+ return aarch64_record_data_proc_simd_fp (aarch64_insn_r);
return AARCH64_RECORD_UNSUPPORTED;
}
--
1.9.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v5 0/6]
2015-05-11 7:27 ` [PATCH v5 0/6] Omair Javaid
` (5 preceding siblings ...)
2015-05-11 7:27 ` [PATCH v5 4/6] Support for recording aarch64 advanced SIMD instructions Omair Javaid
@ 2015-05-11 11:18 ` Yao Qi
6 siblings, 0 replies; 11+ messages in thread
From: Yao Qi @ 2015-05-11 11:18 UTC (permalink / raw)
To: Omair Javaid; +Cc: gdb-patches
Omair Javaid <omair.javaid@linaro.org> writes:
> I am reposting these patches. You can take them forward from here.
Thanks Omair.
To be clear, this patch series V5 is still WIP, and I'll take them over
from Omair. Here are still something I'll do:
- complete the test case,
- add changelog entry if missing, and complete commit log as well,
- adjust code to address some previous review comments,
--
Yao (齐尧)
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v5 1/6] NEWS entry about aarch64-linux record/replay support
2015-05-11 7:27 ` [PATCH v5 1/6] NEWS entry about aarch64-linux record/replay support Omair Javaid
@ 2015-05-11 15:02 ` Eli Zaretskii
0 siblings, 0 replies; 11+ messages in thread
From: Eli Zaretskii @ 2015-05-11 15:02 UTC (permalink / raw)
To: Omair Javaid; +Cc: gdb-patches
> From: Omair Javaid <omair.javaid@linaro.org>
> Date: Mon, 11 May 2015 12:26:55 +0500
>
> gdb:
>
> 2015-05-11 Omair Javaid <omair.javaid@linaro.org>
>
> * NEWS: Add a note on process record-replay support on aarch64*-linux*
> targets.
>
> ---
> gdb/NEWS | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/gdb/NEWS b/gdb/NEWS
> index 51e4f4e..1e517d2 100644
> --- a/gdb/NEWS
> +++ b/gdb/NEWS
> @@ -3,6 +3,10 @@
>
> *** Changes since GDB 7.9
>
> +* Support for process record-replay and reverse debugging on aarch64*-linux*
> + targets has been added. GDB now supports recording of A64 instruction set
> + including advance SIMD instructions.
> +
> * GDB now honors the content of the file /proc/PID/coredump_filter
> (PID is the process ID) on GNU/Linux systems. This file can be used
> to specify the types of memory mappings that will be included in a
OK, thanks.
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2015-05-11 15:02 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-02-03 12:47 [PATCH] ARM gdb record-replay bug fixes Omair Javaid
2015-02-16 14:21 ` Yao Qi
2015-05-11 7:27 ` [PATCH v5 0/6] Omair Javaid
2015-05-11 7:27 ` [PATCH v5 1/6] NEWS entry about aarch64-linux record/replay support Omair Javaid
2015-05-11 15:02 ` Eli Zaretskii
2015-05-11 7:27 ` [PATCH v5 2/6] Implements aarch64 process record and reverse debugging support Omair Javaid
2015-05-11 7:27 ` [PATCH v5 6/6] Adds testcases to test arm64 instruction set recording Omair Javaid
2015-05-11 7:27 ` [PATCH v5 5/6] Enables gdb.reverse testsuite for aarch64*-linux targets Omair Javaid
2015-05-11 7:27 ` [PATCH v5 3/6] Support for recording syscall on aarch64-linux Omair Javaid
2015-05-11 7:27 ` [PATCH v5 4/6] Support for recording aarch64 advanced SIMD instructions Omair Javaid
2015-05-11 11:18 ` [PATCH v5 0/6] Yao Qi
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