* [PATCH 1/8] [AArch64] Use debug_printf instead of fprintf_unfiltered
2015-09-14 11:31 [PATCH 0/8] [AArch64] Support fast tracepoints Pierre Langlois
@ 2015-09-14 11:31 ` Pierre Langlois
2015-09-15 10:06 ` Yao Qi
2015-09-14 11:31 ` [PATCH 3/8] [AArch64] Make aarch64_decode_adrp handle both ADR and ADRP instructions Pierre Langlois
` (8 subsequent siblings)
9 siblings, 1 reply; 37+ messages in thread
From: Pierre Langlois @ 2015-09-14 11:31 UTC (permalink / raw)
To: gdb-patches; +Cc: Pierre Langlois
GDBserver uses debug_printf to print debugging output. This patch makes
GDB use this too so we can share some of this code with GDBserver later.
gdb/ChangeLog:
* aarch64-tdep.c (decode_add_sub_imm): Use debug_printf.
(decode_adrp): Likewise.
(decode_b): Likewise.
(decode_bcond): Likewise.
(decode_br): Likewise.
(decode_cb): Likewise.
(decode_eret): Likewise.
(decode_movz): Likewise.
(decode_orr_shifted_register_x): Likewise.
(decode_ret): Likewise.
(decode_stp_offset): Likewise.
(decode_stp_offset_wb): Likewise.
(decode_stur): Likewise.
(decode_tb): Likewise.
(aarch64_analyze_prologue): Likewise.
(pass_in_x): Likewise.
(pass_in_v): Likewise.
(pass_on_stack): Likewise.
(aarch64_push_dummy_call): Likewise.
(aarch64_extract_return_value): Likewise.
(aarch64_store_return_value): Likewise.
(aarch64_return_value): Likewise.
(aarch64_record_asimd_load_store): Likewise.
(aarch64_record_load_store): Likewise.
(aarch64_record_data_proc_simd_fp): Likewise.
---
gdb/aarch64-tdep.c | 201 ++++++++++++++++++++++-------------------------------
1 file changed, 84 insertions(+), 117 deletions(-)
diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index 2ac1a49..ed6e83f 100644
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -261,10 +261,8 @@ decode_add_sub_imm (CORE_ADDR addr, uint32_t insn, unsigned *rd, unsigned *rn,
*imm = -*imm;
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "decode: 0x%s 0x%x add x%u, x%u, #%d\n",
- core_addr_to_string_nz (addr), insn, *rd, *rn,
- *imm);
+ debug_printf ("decode: 0x%s 0x%x add x%u, x%u, #%d\n",
+ core_addr_to_string_nz (addr), insn, *rd, *rn, *imm);
return 1;
}
return 0;
@@ -286,9 +284,8 @@ decode_adrp (CORE_ADDR addr, uint32_t insn, unsigned *rd)
*rd = (insn >> 0) & 0x1f;
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "decode: 0x%s 0x%x adrp x%u, #?\n",
- core_addr_to_string_nz (addr), insn, *rd);
+ debug_printf ("decode: 0x%s 0x%x adrp x%u, #?\n",
+ core_addr_to_string_nz (addr), insn, *rd);
return 1;
}
return 0;
@@ -315,11 +312,10 @@ decode_b (CORE_ADDR addr, uint32_t insn, int *is_bl, int32_t *offset)
*offset = extract_signed_bitfield (insn, 26, 0) << 2;
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "decode: 0x%s 0x%x %s 0x%s\n",
- core_addr_to_string_nz (addr), insn,
- *is_bl ? "bl" : "b",
- core_addr_to_string_nz (addr + *offset));
+ debug_printf ("decode: 0x%s 0x%x %s 0x%s\n",
+ core_addr_to_string_nz (addr), insn,
+ *is_bl ? "bl" : "b",
+ core_addr_to_string_nz (addr + *offset));
return 1;
}
@@ -346,10 +342,9 @@ decode_bcond (CORE_ADDR addr, uint32_t insn, unsigned *cond, int32_t *offset)
*offset = extract_signed_bitfield (insn, 19, 5) << 2;
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "decode: 0x%s 0x%x b<%u> 0x%s\n",
- core_addr_to_string_nz (addr), insn, *cond,
- core_addr_to_string_nz (addr + *offset));
+ debug_printf ("decode: 0x%s 0x%x b<%u> 0x%s\n",
+ core_addr_to_string_nz (addr), insn, *cond,
+ core_addr_to_string_nz (addr + *offset));
return 1;
}
return 0;
@@ -376,10 +371,9 @@ decode_br (CORE_ADDR addr, uint32_t insn, int *is_blr, unsigned *rn)
*rn = (insn >> 5) & 0x1f;
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "decode: 0x%s 0x%x %s 0x%x\n",
- core_addr_to_string_nz (addr), insn,
- *is_blr ? "blr" : "br", *rn);
+ debug_printf ("decode: 0x%s 0x%x %s 0x%x\n",
+ core_addr_to_string_nz (addr), insn,
+ *is_blr ? "blr" : "br", *rn);
return 1;
}
@@ -411,11 +405,10 @@ decode_cb (CORE_ADDR addr, uint32_t insn, int *is64, int *is_cbnz,
*offset = extract_signed_bitfield (insn, 19, 5) << 2;
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "decode: 0x%s 0x%x %s 0x%s\n",
- core_addr_to_string_nz (addr), insn,
- *is_cbnz ? "cbnz" : "cbz",
- core_addr_to_string_nz (addr + *offset));
+ debug_printf ("decode: 0x%s 0x%x %s 0x%s\n",
+ core_addr_to_string_nz (addr), insn,
+ *is_cbnz ? "cbnz" : "cbz",
+ core_addr_to_string_nz (addr + *offset));
return 1;
}
return 0;
@@ -435,8 +428,8 @@ decode_eret (CORE_ADDR addr, uint32_t insn)
if (insn == 0xd69f03e0)
{
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog, "decode: 0x%s 0x%x eret\n",
- core_addr_to_string_nz (addr), insn);
+ debug_printf ("decode: 0x%s 0x%x eret\n",
+ core_addr_to_string_nz (addr), insn);
return 1;
}
return 0;
@@ -458,9 +451,8 @@ decode_movz (CORE_ADDR addr, uint32_t insn, unsigned *rd)
*rd = (insn >> 0) & 0x1f;
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "decode: 0x%s 0x%x movz x%u, #?\n",
- core_addr_to_string_nz (addr), insn, *rd);
+ debug_printf ("decode: 0x%s 0x%x movz x%u, #?\n",
+ core_addr_to_string_nz (addr), insn, *rd);
return 1;
}
return 0;
@@ -491,10 +483,9 @@ decode_orr_shifted_register_x (CORE_ADDR addr,
*imm = (insn >> 10) & 0x3f;
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "decode: 0x%s 0x%x orr x%u, x%u, x%u, #%u\n",
- core_addr_to_string_nz (addr), insn, *rd,
- *rn, *rm, *imm);
+ debug_printf ("decode: 0x%s 0x%x orr x%u, x%u, x%u, #%u\n",
+ core_addr_to_string_nz (addr), insn, *rd,
+ *rn, *rm, *imm);
return 1;
}
return 0;
@@ -515,9 +506,8 @@ decode_ret (CORE_ADDR addr, uint32_t insn, unsigned *rn)
{
*rn = (insn >> 5) & 0x1f;
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "decode: 0x%s 0x%x ret x%u\n",
- core_addr_to_string_nz (addr), insn, *rn);
+ debug_printf ("decode: 0x%s 0x%x ret x%u\n",
+ core_addr_to_string_nz (addr), insn, *rn);
return 1;
}
return 0;
@@ -549,10 +539,9 @@ decode_stp_offset (CORE_ADDR addr,
*imm <<= 3;
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "decode: 0x%s 0x%x stp x%u, x%u, [x%u + #%d]\n",
- core_addr_to_string_nz (addr), insn,
- *rt1, *rt2, *rn, *imm);
+ debug_printf ("decode: 0x%s 0x%x stp x%u, x%u, [x%u + #%d]\n",
+ core_addr_to_string_nz (addr), insn, *rt1, *rt2, *rn,
+ *imm);
return 1;
}
return 0;
@@ -585,10 +574,9 @@ decode_stp_offset_wb (CORE_ADDR addr,
*imm <<= 3;
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "decode: 0x%s 0x%x stp x%u, x%u, [x%u + #%d]!\n",
- core_addr_to_string_nz (addr), insn,
- *rt1, *rt2, *rn, *imm);
+ debug_printf ("decode: 0x%s 0x%x stp x%u, x%u, [x%u + #%d]!\n",
+ core_addr_to_string_nz (addr), insn, *rt1, *rt2, *rn,
+ *imm);
return 1;
}
return 0;
@@ -618,10 +606,9 @@ decode_stur (CORE_ADDR addr, uint32_t insn, int *is64, unsigned *rt,
*imm = extract_signed_bitfield (insn, 9, 12);
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "decode: 0x%s 0x%x stur %c%u, [x%u + #%d]\n",
- core_addr_to_string_nz (addr), insn,
- *is64 ? 'x' : 'w', *rt, *rn, *imm);
+ debug_printf ("decode: 0x%s 0x%x stur %c%u, [x%u + #%d]\n",
+ core_addr_to_string_nz (addr), insn,
+ *is64 ? 'x' : 'w', *rt, *rn, *imm);
return 1;
}
return 0;
@@ -652,11 +639,10 @@ decode_tb (CORE_ADDR addr, uint32_t insn, int *is_tbnz, unsigned *bit,
*imm = extract_signed_bitfield (insn, 14, 5) << 2;
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "decode: 0x%s 0x%x %s x%u, #%u, 0x%s\n",
- core_addr_to_string_nz (addr), insn,
- *is_tbnz ? "tbnz" : "tbz", *rt, *bit,
- core_addr_to_string_nz (addr + *imm));
+ debug_printf ("decode: 0x%s 0x%x %s x%u, #%u, 0x%s\n",
+ core_addr_to_string_nz (addr), insn,
+ *is_tbnz ? "tbnz" : "tbz", *rt, *bit,
+ core_addr_to_string_nz (addr + *imm));
return 1;
}
return 0;
@@ -742,12 +728,9 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
else
{
if (aarch64_debug)
- fprintf_unfiltered
- (gdb_stdlog,
- "aarch64: prologue analysis gave up addr=0x%s "
- "opcode=0x%x (orr x register)\n",
- core_addr_to_string_nz (start),
- insn);
+ debug_printf ("aarch64: prologue analysis gave up addr=0x%s "
+ "opcode=0x%x (orr x register)\n",
+ core_addr_to_string_nz (start), insn);
break;
}
}
@@ -806,10 +789,9 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
else
{
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "aarch64: prologue analysis gave up addr=0x%s"
- " opcode=0x%x\n",
- core_addr_to_string_nz (start), insn);
+ debug_printf ("aarch64: prologue analysis gave up addr=0x%s"
+ " opcode=0x%x\n", core_addr_to_string_nz (start),
+ insn);
break;
}
}
@@ -1453,10 +1435,9 @@ pass_in_x (struct gdbarch *gdbarch, struct regcache *regcache,
regval <<= ((X_REGISTER_SIZE - partial_len) * TARGET_CHAR_BIT);
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n",
- info->argnum,
- gdbarch_register_name (gdbarch, regnum),
- phex (regval, X_REGISTER_SIZE));
+ debug_printf ("arg %d in %s = 0x%s\n", info->argnum,
+ gdbarch_register_name (gdbarch, regnum),
+ phex (regval, X_REGISTER_SIZE));
regcache_cooked_write_unsigned (regcache, regnum, regval);
len -= partial_len;
buf += partial_len;
@@ -1485,9 +1466,8 @@ pass_in_v (struct gdbarch *gdbarch,
regcache_cooked_write (regcache, regnum, buf);
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog, "arg %d in %s\n",
- info->argnum,
- gdbarch_register_name (gdbarch, regnum));
+ debug_printf ("arg %d in %s\n", info->argnum,
+ gdbarch_register_name (gdbarch, regnum));
return 1;
}
info->nsrn = 8;
@@ -1517,8 +1497,8 @@ pass_on_stack (struct aarch64_call_info *info, struct type *type,
align = 16;
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog, "arg %d len=%d @ sp + %d\n",
- info->argnum, len, info->nsaa);
+ debug_printf ("arg %d len=%d @ sp + %d\n", info->argnum, len,
+ info->nsaa);
item.len = len;
item.data = buf;
@@ -1653,11 +1633,10 @@ aarch64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
if (struct_return || lang_struct_return)
{
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog, "struct return in %s = 0x%s\n",
- gdbarch_register_name
- (gdbarch,
- AARCH64_STRUCT_RETURN_REGNUM),
- paddress (gdbarch, struct_addr));
+ debug_printf ("struct return in %s = 0x%s\n",
+ gdbarch_register_name (gdbarch,
+ AARCH64_STRUCT_RETURN_REGNUM),
+ paddress (gdbarch, struct_addr));
regcache_cooked_write_unsigned (regcache, AARCH64_STRUCT_RETURN_REGNUM,
struct_addr);
}
@@ -2062,10 +2041,8 @@ aarch64_extract_return_value (struct type *type, struct regcache *regs,
bfd_byte buf[X_REGISTER_SIZE];
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "read HFA return value element %d from %s\n",
- i + 1,
- gdbarch_register_name (gdbarch, regno));
+ debug_printf ("read HFA return value element %d from %s\n",
+ i + 1, gdbarch_register_name (gdbarch, regno));
regcache_cooked_read (regs, regno, buf);
memcpy (valbuf, buf, len);
@@ -2190,10 +2167,8 @@ aarch64_store_return_value (struct type *type, struct regcache *regs,
bfd_byte tmpbuf[MAX_REGISTER_SIZE];
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "write HFA return value element %d to %s\n",
- i + 1,
- gdbarch_register_name (gdbarch, regno));
+ debug_printf ("write HFA return value element %d to %s\n",
+ i + 1, gdbarch_register_name (gdbarch, regno));
memcpy (tmpbuf, valbuf, len);
regcache_cooked_write (regs, regno, tmpbuf);
@@ -2236,7 +2211,7 @@ aarch64_return_value (struct gdbarch *gdbarch, struct value *func_value,
if (aarch64_return_in_memory (gdbarch, valtype))
{
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog, "return value in memory\n");
+ debug_printf ("return value in memory\n");
return RETURN_VALUE_STRUCT_CONVENTION;
}
}
@@ -2248,7 +2223,7 @@ aarch64_return_value (struct gdbarch *gdbarch, struct value *func_value,
aarch64_extract_return_value (valtype, regcache, readbuf);
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog, "return value in registers\n");
+ debug_printf ("return value in registers\n");
return RETURN_VALUE_REGISTER_CONVENTION;
}
@@ -3186,8 +3161,7 @@ aarch64_record_asimd_load_store (insn_decode_record *aarch64_insn_r)
if (record_debug)
{
- fprintf_unfiltered (gdb_stdlog,
- "Process record: Advanced SIMD load/store\n");
+ debug_printf ("Process record: Advanced SIMD load/store\n");
}
/* Load/store single structure. */
@@ -3363,8 +3337,7 @@ aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
{
if (record_debug)
{
- fprintf_unfiltered (gdb_stdlog,
- "Process record: load/store exclusive\n");
+ debug_printf ("Process record: load/store exclusive\n");
}
if (ld_flag)
@@ -3401,8 +3374,7 @@ aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
{
if (record_debug)
{
- fprintf_unfiltered (gdb_stdlog,
- "Process record: load register (literal)\n");
+ debug_printf ("Process record: load register (literal)\n");
}
if (vector_flag)
record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
@@ -3415,8 +3387,7 @@ aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
{
if (record_debug)
{
- fprintf_unfiltered (gdb_stdlog,
- "Process record: load/store pair\n");
+ debug_printf ("Process record: load/store pair\n");
}
if (ld_flag)
@@ -3478,10 +3449,9 @@ aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
if (record_debug)
{
- fprintf_unfiltered (gdb_stdlog,
- "Process record: load/store (unsigned immediate):"
- " size %x V %d opc %x\n", size_bits, vector_flag,
- opc);
+ debug_printf ("Process record: load/store (unsigned immediate):"
+ " size %x V %d opc %x\n", size_bits, vector_flag,
+ opc);
}
if (!ld_flag)
@@ -3512,8 +3482,7 @@ aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
{
if (record_debug)
{
- fprintf_unfiltered (gdb_stdlog,
- "Process record: load/store (register offset)\n");
+ debug_printf ("Process record: load/store (register offset)\n");
}
opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
if (!(opc >> 1))
@@ -3559,8 +3528,7 @@ aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
{
if (record_debug)
{
- fprintf_unfiltered (gdb_stdlog,
- "Process record: load/store (immediate and unprivileged)\n");
+ debug_printf ("Process record: load/store (immediate and unprivileged)\n");
}
opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
if (!(opc >> 1))
@@ -3637,8 +3605,7 @@ aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
if (record_debug)
{
- fprintf_unfiltered (gdb_stdlog,
- "Process record: data processing SIMD/FP: ");
+ debug_printf ("Process record: data processing SIMD/FP: ");
}
if ((insn_bits28_31 & 0x05) == 0x01 && insn_bits24_27 == 0x0e)
@@ -3647,7 +3614,7 @@ aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
if (!insn_bit21)
{
if (record_debug)
- fprintf_unfiltered (gdb_stdlog, "FP - fixed point conversion");
+ debug_printf ("FP - fixed point conversion");
if ((opcode >> 1) == 0x0 && rmode == 0x03)
record_buf[0] = reg_rd;
@@ -3658,7 +3625,7 @@ aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
else if (insn_bits10_11 == 0x01)
{
if (record_debug)
- fprintf_unfiltered (gdb_stdlog, "FP - conditional compare");
+ debug_printf ("FP - conditional compare");
record_buf[0] = AARCH64_CPSR_REGNUM;
}
@@ -3667,7 +3634,7 @@ aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
else if (insn_bits10_11 == 0x02 || insn_bits10_11 == 0x03)
{
if (record_debug)
- fprintf_unfiltered (gdb_stdlog, "FP - DP (2-source)");
+ debug_printf ("FP - DP (2-source)");
record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
}
@@ -3678,14 +3645,14 @@ aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
|| (insn_bits12_15 & 0x07) == 0x04)
{
if (record_debug)
- fprintf_unfiltered (gdb_stdlog, "FP - immediate");
+ debug_printf ("FP - immediate");
record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
}
/* Floating point - compare instructions. */
else if ((insn_bits12_15 & 0x03) == 0x02)
{
if (record_debug)
- fprintf_unfiltered (gdb_stdlog, "FP - immediate");
+ debug_printf ("FP - immediate");
record_buf[0] = AARCH64_CPSR_REGNUM;
}
/* Floating point - integer conversions instructions. */
@@ -3695,7 +3662,7 @@ aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
if (!(opcode >> 1) || ((opcode >> 1) == 0x02 && !rmode))
{
if (record_debug)
- fprintf_unfiltered (gdb_stdlog, "float to int conversion");
+ debug_printf ("float to int conversion");
record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
}
@@ -3703,7 +3670,7 @@ aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
else if ((opcode >> 1) == 0x01 && !rmode)
{
if (record_debug)
- fprintf_unfiltered (gdb_stdlog, "int to float conversion");
+ debug_printf ("int to float conversion");
record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
}
@@ -3711,7 +3678,7 @@ aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
else if ((opcode >> 1) == 0x03)
{
if (record_debug)
- fprintf_unfiltered (gdb_stdlog, "move float to int");
+ debug_printf ("move float to int");
if (!(opcode & 0x01))
record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
@@ -3730,7 +3697,7 @@ aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
else if ((insn_bits28_31 & 0x09) == 0x00 && insn_bits24_27 == 0x0e)
{
if (record_debug)
- fprintf_unfiltered (gdb_stdlog, "SIMD copy");
+ debug_printf ("SIMD copy");
/* Advanced SIMD copy instructions. */
if (!bits (aarch64_insn_r->aarch64_insn, 21, 23)
@@ -3749,13 +3716,13 @@ aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
else
{
if (record_debug)
- fprintf_unfiltered (gdb_stdlog, "all remain");
+ debug_printf ("all remain");
record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
}
if (record_debug)
- fprintf_unfiltered (gdb_stdlog, "\n");
+ debug_printf ("\n");
aarch64_insn_r->reg_rec_count++;
gdb_assert (aarch64_insn_r->reg_rec_count == 1);
--
2.4.6
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [PATCH 1/8] [AArch64] Use debug_printf instead of fprintf_unfiltered
2015-09-14 11:31 ` [PATCH 1/8] [AArch64] Use debug_printf instead of fprintf_unfiltered Pierre Langlois
@ 2015-09-15 10:06 ` Yao Qi
2015-09-15 11:07 ` Pierre Langlois
0 siblings, 1 reply; 37+ messages in thread
From: Yao Qi @ 2015-09-15 10:06 UTC (permalink / raw)
To: Pierre Langlois; +Cc: gdb-patches
Pierre Langlois <pierre.langlois@arm.com> writes:
> @@ -3363,8 +3337,7 @@ aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
> {
> if (record_debug)
> {
> - fprintf_unfiltered (gdb_stdlog,
> - "Process record: load/store exclusive\n");
> + debug_printf ("Process record: load/store exclusive\n");
> }
After your change, it becomes an one-line statement, so "{" and "}" are no
longer needed. We can remove them too. Here, and somewhere else.
OK with the changes.
--
Yao (齐尧)
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [PATCH 1/8] [AArch64] Use debug_printf instead of fprintf_unfiltered
2015-09-15 10:06 ` Yao Qi
@ 2015-09-15 11:07 ` Pierre Langlois
2015-09-15 11:19 ` Yao Qi
0 siblings, 1 reply; 37+ messages in thread
From: Pierre Langlois @ 2015-09-15 11:07 UTC (permalink / raw)
To: Yao Qi; +Cc: pierre.langlois, gdb-patches
On 15/09/15 11:06, Yao Qi wrote:
> Pierre Langlois <pierre.langlois@arm.com> writes:
>
>> @@ -3363,8 +3337,7 @@ aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
>> {
>> if (record_debug)
>> {
>> - fprintf_unfiltered (gdb_stdlog,
>> - "Process record: load/store exclusive\n");
>> + debug_printf ("Process record: load/store exclusive\n");
>> }
>
> After your change, it becomes an one-line statement, so "{" and "}" are no
> longer needed. We can remove them too. Here, and somewhere else.
OK, I'll fix this.
Should the other if statements like this one have braces? I can fix those
too in this patch.
@@ -261,10 +261,8 @@ decode_add_sub_imm (CORE_ADDR addr, uint32_t insn, unsigned *rd, unsigned *rn,
*imm = -*imm;
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "decode: 0x%s 0x%x add x%u, x%u, #%d\n",
- core_addr_to_string_nz (addr), insn, *rd, *rn,
- *imm);
+ debug_printf ("decode: 0x%s 0x%x add x%u, x%u, #%d\n",
+ core_addr_to_string_nz (addr), insn, *rd, *rn, *imm);
return 1;
}
return 0;
Thanks,
Pierre
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [PATCH 1/8] [AArch64] Use debug_printf instead of fprintf_unfiltered
2015-09-15 11:07 ` Pierre Langlois
@ 2015-09-15 11:19 ` Yao Qi
2015-09-15 11:43 ` [PATCH 2/8 v2] " Pierre Langlois
0 siblings, 1 reply; 37+ messages in thread
From: Yao Qi @ 2015-09-15 11:19 UTC (permalink / raw)
To: Pierre Langlois; +Cc: Yao Qi, gdb-patches
Pierre Langlois <pierre.langlois@arm.com> writes:
> Should the other if statements like this one have braces? I can fix those
> too in this patch.
>
> @@ -261,10 +261,8 @@ decode_add_sub_imm (CORE_ADDR addr, uint32_t insn, unsigned *rd, unsigned *rn,
> *imm = -*imm;
>
> if (aarch64_debug)
> - fprintf_unfiltered (gdb_stdlog,
> - "decode: 0x%s 0x%x add x%u, x%u, #%d\n",
> - core_addr_to_string_nz (addr), insn, *rd, *rn,
> - *imm);
> + debug_printf ("decode: 0x%s 0x%x add x%u, x%u, #%d\n",
> + core_addr_to_string_nz (addr), insn, *rd, *rn, *imm);
> return 1;
> }
> return 0;
If you want to fix them, yes, please.
--
Yao (齐尧)
^ permalink raw reply [flat|nested] 37+ messages in thread* [PATCH 2/8 v2] [AArch64] Use debug_printf instead of fprintf_unfiltered
2015-09-15 11:19 ` Yao Qi
@ 2015-09-15 11:43 ` Pierre Langlois
2015-09-15 17:40 ` Pierre Langlois
0 siblings, 1 reply; 37+ messages in thread
From: Pierre Langlois @ 2015-09-15 11:43 UTC (permalink / raw)
To: gdb-patches; +Cc: Pierre Langlois
Here is an updated patch that fixes the formatting issues. I've had to
rebase the following patches on top of this one, to propagate to changes
over to functions that were moved. I'll post them shortly.
Thanks,
Pierre
---
GDBserver uses debug_printf to print debugging output. This patch makes
GDB use this too so we can share some of this code with GDBserver later.
gdb/ChangeLog:
* aarch64-tdep.c (decode_add_sub_imm): Use debug_printf.
(decode_adrp): Likewise.
(decode_b): Likewise.
(decode_bcond): Likewise.
(decode_br): Likewise.
(decode_cb): Likewise.
(decode_eret): Likewise.
(decode_movz): Likewise.
(decode_orr_shifted_register_x): Likewise.
(decode_ret): Likewise.
(decode_stp_offset): Likewise.
(decode_stp_offset_wb): Likewise.
(decode_stur): Likewise.
(decode_tb): Likewise.
(aarch64_analyze_prologue): Likewise.
(pass_in_x): Likewise.
(pass_in_v): Likewise.
(pass_on_stack): Likewise.
(aarch64_push_dummy_call): Likewise.
(aarch64_extract_return_value): Likewise.
(aarch64_store_return_value): Likewise.
(aarch64_return_value): Likewise.
(aarch64_record_asimd_load_store): Likewise.
(aarch64_record_load_store): Likewise.
(aarch64_record_data_proc_simd_fp): Likewise.
---
gdb/aarch64-tdep.c | 261 +++++++++++++++++++++++++++--------------------------
1 file changed, 132 insertions(+), 129 deletions(-)
diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index 2ac1a49..9a4eda2 100644
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -261,10 +261,11 @@ decode_add_sub_imm (CORE_ADDR addr, uint32_t insn, unsigned *rd, unsigned *rn,
*imm = -*imm;
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "decode: 0x%s 0x%x add x%u, x%u, #%d\n",
- core_addr_to_string_nz (addr), insn, *rd, *rn,
- *imm);
+ {
+ debug_printf ("decode: 0x%s 0x%x add x%u, x%u, #%d\n",
+ core_addr_to_string_nz (addr), insn, *rd, *rn,
+ *imm);
+ }
return 1;
}
return 0;
@@ -286,9 +287,10 @@ decode_adrp (CORE_ADDR addr, uint32_t insn, unsigned *rd)
*rd = (insn >> 0) & 0x1f;
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "decode: 0x%s 0x%x adrp x%u, #?\n",
- core_addr_to_string_nz (addr), insn, *rd);
+ {
+ debug_printf ("decode: 0x%s 0x%x adrp x%u, #?\n",
+ core_addr_to_string_nz (addr), insn, *rd);
+ }
return 1;
}
return 0;
@@ -315,11 +317,12 @@ decode_b (CORE_ADDR addr, uint32_t insn, int *is_bl, int32_t *offset)
*offset = extract_signed_bitfield (insn, 26, 0) << 2;
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "decode: 0x%s 0x%x %s 0x%s\n",
- core_addr_to_string_nz (addr), insn,
- *is_bl ? "bl" : "b",
- core_addr_to_string_nz (addr + *offset));
+ {
+ debug_printf ("decode: 0x%s 0x%x %s 0x%s\n",
+ core_addr_to_string_nz (addr), insn,
+ *is_bl ? "bl" : "b",
+ core_addr_to_string_nz (addr + *offset));
+ }
return 1;
}
@@ -346,10 +349,11 @@ decode_bcond (CORE_ADDR addr, uint32_t insn, unsigned *cond, int32_t *offset)
*offset = extract_signed_bitfield (insn, 19, 5) << 2;
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "decode: 0x%s 0x%x b<%u> 0x%s\n",
- core_addr_to_string_nz (addr), insn, *cond,
- core_addr_to_string_nz (addr + *offset));
+ {
+ debug_printf ("decode: 0x%s 0x%x b<%u> 0x%s\n",
+ core_addr_to_string_nz (addr), insn, *cond,
+ core_addr_to_string_nz (addr + *offset));
+ }
return 1;
}
return 0;
@@ -376,10 +380,11 @@ decode_br (CORE_ADDR addr, uint32_t insn, int *is_blr, unsigned *rn)
*rn = (insn >> 5) & 0x1f;
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "decode: 0x%s 0x%x %s 0x%x\n",
- core_addr_to_string_nz (addr), insn,
- *is_blr ? "blr" : "br", *rn);
+ {
+ debug_printf ("decode: 0x%s 0x%x %s 0x%x\n",
+ core_addr_to_string_nz (addr), insn,
+ *is_blr ? "blr" : "br", *rn);
+ }
return 1;
}
@@ -411,11 +416,12 @@ decode_cb (CORE_ADDR addr, uint32_t insn, int *is64, int *is_cbnz,
*offset = extract_signed_bitfield (insn, 19, 5) << 2;
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "decode: 0x%s 0x%x %s 0x%s\n",
- core_addr_to_string_nz (addr), insn,
- *is_cbnz ? "cbnz" : "cbz",
- core_addr_to_string_nz (addr + *offset));
+ {
+ debug_printf ("decode: 0x%s 0x%x %s 0x%s\n",
+ core_addr_to_string_nz (addr), insn,
+ *is_cbnz ? "cbnz" : "cbz",
+ core_addr_to_string_nz (addr + *offset));
+ }
return 1;
}
return 0;
@@ -435,8 +441,10 @@ decode_eret (CORE_ADDR addr, uint32_t insn)
if (insn == 0xd69f03e0)
{
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog, "decode: 0x%s 0x%x eret\n",
- core_addr_to_string_nz (addr), insn);
+ {
+ debug_printf ("decode: 0x%s 0x%x eret\n",
+ core_addr_to_string_nz (addr), insn);
+ }
return 1;
}
return 0;
@@ -458,9 +466,10 @@ decode_movz (CORE_ADDR addr, uint32_t insn, unsigned *rd)
*rd = (insn >> 0) & 0x1f;
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "decode: 0x%s 0x%x movz x%u, #?\n",
- core_addr_to_string_nz (addr), insn, *rd);
+ {
+ debug_printf ("decode: 0x%s 0x%x movz x%u, #?\n",
+ core_addr_to_string_nz (addr), insn, *rd);
+ }
return 1;
}
return 0;
@@ -491,10 +500,11 @@ decode_orr_shifted_register_x (CORE_ADDR addr,
*imm = (insn >> 10) & 0x3f;
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "decode: 0x%s 0x%x orr x%u, x%u, x%u, #%u\n",
- core_addr_to_string_nz (addr), insn, *rd,
- *rn, *rm, *imm);
+ {
+ debug_printf ("decode: 0x%s 0x%x orr x%u, x%u, x%u, #%u\n",
+ core_addr_to_string_nz (addr), insn, *rd, *rn,
+ *rm, *imm);
+ }
return 1;
}
return 0;
@@ -515,9 +525,10 @@ decode_ret (CORE_ADDR addr, uint32_t insn, unsigned *rn)
{
*rn = (insn >> 5) & 0x1f;
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "decode: 0x%s 0x%x ret x%u\n",
- core_addr_to_string_nz (addr), insn, *rn);
+ {
+ debug_printf ("decode: 0x%s 0x%x ret x%u\n",
+ core_addr_to_string_nz (addr), insn, *rn);
+ }
return 1;
}
return 0;
@@ -549,10 +560,11 @@ decode_stp_offset (CORE_ADDR addr,
*imm <<= 3;
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "decode: 0x%s 0x%x stp x%u, x%u, [x%u + #%d]\n",
- core_addr_to_string_nz (addr), insn,
- *rt1, *rt2, *rn, *imm);
+ {
+ debug_printf ("decode: 0x%s 0x%x stp x%u, x%u, [x%u + #%d]\n",
+ core_addr_to_string_nz (addr), insn, *rt1, *rt2,
+ *rn, *imm);
+ }
return 1;
}
return 0;
@@ -585,10 +597,11 @@ decode_stp_offset_wb (CORE_ADDR addr,
*imm <<= 3;
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "decode: 0x%s 0x%x stp x%u, x%u, [x%u + #%d]!\n",
- core_addr_to_string_nz (addr), insn,
- *rt1, *rt2, *rn, *imm);
+ {
+ debug_printf ("decode: 0x%s 0x%x stp x%u, x%u, [x%u + #%d]!\n",
+ core_addr_to_string_nz (addr), insn, *rt1, *rt2,
+ *rn, *imm);
+ }
return 1;
}
return 0;
@@ -618,10 +631,11 @@ decode_stur (CORE_ADDR addr, uint32_t insn, int *is64, unsigned *rt,
*imm = extract_signed_bitfield (insn, 9, 12);
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "decode: 0x%s 0x%x stur %c%u, [x%u + #%d]\n",
- core_addr_to_string_nz (addr), insn,
- *is64 ? 'x' : 'w', *rt, *rn, *imm);
+ {
+ debug_printf ("decode: 0x%s 0x%x stur %c%u, [x%u + #%d]\n",
+ core_addr_to_string_nz (addr), insn,
+ *is64 ? 'x' : 'w', *rt, *rn, *imm);
+ }
return 1;
}
return 0;
@@ -652,11 +666,12 @@ decode_tb (CORE_ADDR addr, uint32_t insn, int *is_tbnz, unsigned *bit,
*imm = extract_signed_bitfield (insn, 14, 5) << 2;
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "decode: 0x%s 0x%x %s x%u, #%u, 0x%s\n",
- core_addr_to_string_nz (addr), insn,
- *is_tbnz ? "tbnz" : "tbz", *rt, *bit,
- core_addr_to_string_nz (addr + *imm));
+ {
+ debug_printf ("decode: 0x%s 0x%x %s x%u, #%u, 0x%s\n",
+ core_addr_to_string_nz (addr), insn,
+ *is_tbnz ? "tbnz" : "tbz", *rt, *bit,
+ core_addr_to_string_nz (addr + *imm));
+ }
return 1;
}
return 0;
@@ -742,12 +757,11 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
else
{
if (aarch64_debug)
- fprintf_unfiltered
- (gdb_stdlog,
- "aarch64: prologue analysis gave up addr=0x%s "
- "opcode=0x%x (orr x register)\n",
- core_addr_to_string_nz (start),
- insn);
+ {
+ debug_printf ("aarch64: prologue analysis gave up "
+ "addr=0x%s opcode=0x%x (orr x register)\n",
+ core_addr_to_string_nz (start), insn);
+ }
break;
}
}
@@ -806,10 +820,11 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
else
{
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "aarch64: prologue analysis gave up addr=0x%s"
- " opcode=0x%x\n",
- core_addr_to_string_nz (start), insn);
+ {
+ debug_printf ("aarch64: prologue analysis gave up addr=0x%s"
+ " opcode=0x%x\n",
+ core_addr_to_string_nz (start), insn);
+ }
break;
}
}
@@ -1453,10 +1468,11 @@ pass_in_x (struct gdbarch *gdbarch, struct regcache *regcache,
regval <<= ((X_REGISTER_SIZE - partial_len) * TARGET_CHAR_BIT);
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n",
- info->argnum,
- gdbarch_register_name (gdbarch, regnum),
- phex (regval, X_REGISTER_SIZE));
+ {
+ debug_printf ("arg %d in %s = 0x%s\n", info->argnum,
+ gdbarch_register_name (gdbarch, regnum),
+ phex (regval, X_REGISTER_SIZE));
+ }
regcache_cooked_write_unsigned (regcache, regnum, regval);
len -= partial_len;
buf += partial_len;
@@ -1485,9 +1501,10 @@ pass_in_v (struct gdbarch *gdbarch,
regcache_cooked_write (regcache, regnum, buf);
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog, "arg %d in %s\n",
- info->argnum,
- gdbarch_register_name (gdbarch, regnum));
+ {
+ debug_printf ("arg %d in %s\n", info->argnum,
+ gdbarch_register_name (gdbarch, regnum));
+ }
return 1;
}
info->nsrn = 8;
@@ -1517,8 +1534,10 @@ pass_on_stack (struct aarch64_call_info *info, struct type *type,
align = 16;
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog, "arg %d len=%d @ sp + %d\n",
- info->argnum, len, info->nsaa);
+ {
+ debug_printf ("arg %d len=%d @ sp + %d\n", info->argnum, len,
+ info->nsaa);
+ }
item.len = len;
item.data = buf;
@@ -1653,11 +1672,12 @@ aarch64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
if (struct_return || lang_struct_return)
{
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog, "struct return in %s = 0x%s\n",
- gdbarch_register_name
- (gdbarch,
- AARCH64_STRUCT_RETURN_REGNUM),
- paddress (gdbarch, struct_addr));
+ {
+ debug_printf ("struct return in %s = 0x%s\n",
+ gdbarch_register_name (gdbarch,
+ AARCH64_STRUCT_RETURN_REGNUM),
+ paddress (gdbarch, struct_addr));
+ }
regcache_cooked_write_unsigned (regcache, AARCH64_STRUCT_RETURN_REGNUM,
struct_addr);
}
@@ -2062,10 +2082,11 @@ aarch64_extract_return_value (struct type *type, struct regcache *regs,
bfd_byte buf[X_REGISTER_SIZE];
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "read HFA return value element %d from %s\n",
- i + 1,
- gdbarch_register_name (gdbarch, regno));
+ {
+ debug_printf ("read HFA return value element %d from %s\n",
+ i + 1,
+ gdbarch_register_name (gdbarch, regno));
+ }
regcache_cooked_read (regs, regno, buf);
memcpy (valbuf, buf, len);
@@ -2190,10 +2211,11 @@ aarch64_store_return_value (struct type *type, struct regcache *regs,
bfd_byte tmpbuf[MAX_REGISTER_SIZE];
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog,
- "write HFA return value element %d to %s\n",
- i + 1,
- gdbarch_register_name (gdbarch, regno));
+ {
+ debug_printf ("write HFA return value element %d to %s\n",
+ i + 1,
+ gdbarch_register_name (gdbarch, regno));
+ }
memcpy (tmpbuf, valbuf, len);
regcache_cooked_write (regs, regno, tmpbuf);
@@ -2236,7 +2258,7 @@ aarch64_return_value (struct gdbarch *gdbarch, struct value *func_value,
if (aarch64_return_in_memory (gdbarch, valtype))
{
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog, "return value in memory\n");
+ debug_printf ("return value in memory\n");
return RETURN_VALUE_STRUCT_CONVENTION;
}
}
@@ -2248,7 +2270,7 @@ aarch64_return_value (struct gdbarch *gdbarch, struct value *func_value,
aarch64_extract_return_value (valtype, regcache, readbuf);
if (aarch64_debug)
- fprintf_unfiltered (gdb_stdlog, "return value in registers\n");
+ debug_printf ("return value in registers\n");
return RETURN_VALUE_REGISTER_CONVENTION;
}
@@ -3185,10 +3207,7 @@ aarch64_record_asimd_load_store (insn_decode_record *aarch64_insn_r)
regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, &address);
if (record_debug)
- {
- fprintf_unfiltered (gdb_stdlog,
- "Process record: Advanced SIMD load/store\n");
- }
+ debug_printf ("Process record: Advanced SIMD load/store\n");
/* Load/store single structure. */
if (bit (aarch64_insn_r->aarch64_insn, 24))
@@ -3362,10 +3381,7 @@ aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
if (insn_bits24_27 == 0x08 && insn_bits28_29 == 0x00)
{
if (record_debug)
- {
- fprintf_unfiltered (gdb_stdlog,
- "Process record: load/store exclusive\n");
- }
+ debug_printf ("Process record: load/store exclusive\n");
if (ld_flag)
{
@@ -3400,10 +3416,7 @@ aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x01)
{
if (record_debug)
- {
- fprintf_unfiltered (gdb_stdlog,
- "Process record: load register (literal)\n");
- }
+ debug_printf ("Process record: load register (literal)\n");
if (vector_flag)
record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
else
@@ -3414,10 +3427,7 @@ aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
else if ((insn_bits24_27 & 0x0a) == 0x08 && insn_bits28_29 == 0x02)
{
if (record_debug)
- {
- fprintf_unfiltered (gdb_stdlog,
- "Process record: load/store pair\n");
- }
+ debug_printf ("Process record: load/store pair\n");
if (ld_flag)
{
@@ -3478,10 +3488,9 @@ aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
if (record_debug)
{
- fprintf_unfiltered (gdb_stdlog,
- "Process record: load/store (unsigned immediate):"
- " size %x V %d opc %x\n", size_bits, vector_flag,
- opc);
+ debug_printf ("Process record: load/store (unsigned immediate):"
+ " size %x V %d opc %x\n", size_bits, vector_flag,
+ opc);
}
if (!ld_flag)
@@ -3511,10 +3520,7 @@ aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
&& insn_bits10_11 == 0x02 && insn_bit21)
{
if (record_debug)
- {
- fprintf_unfiltered (gdb_stdlog,
- "Process record: load/store (register offset)\n");
- }
+ debug_printf ("Process record: load/store (register offset)\n");
opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
if (!(opc >> 1))
if (opc & 0x01)
@@ -3559,8 +3565,8 @@ aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
{
if (record_debug)
{
- fprintf_unfiltered (gdb_stdlog,
- "Process record: load/store (immediate and unprivileged)\n");
+ debug_printf ("Process record: load/store "
+ "(immediate and unprivileged)\n");
}
opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
if (!(opc >> 1))
@@ -3636,10 +3642,7 @@ aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21);
if (record_debug)
- {
- fprintf_unfiltered (gdb_stdlog,
- "Process record: data processing SIMD/FP: ");
- }
+ debug_printf ("Process record: data processing SIMD/FP: ");
if ((insn_bits28_31 & 0x05) == 0x01 && insn_bits24_27 == 0x0e)
{
@@ -3647,7 +3650,7 @@ aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
if (!insn_bit21)
{
if (record_debug)
- fprintf_unfiltered (gdb_stdlog, "FP - fixed point conversion");
+ debug_printf ("FP - fixed point conversion");
if ((opcode >> 1) == 0x0 && rmode == 0x03)
record_buf[0] = reg_rd;
@@ -3658,7 +3661,7 @@ aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
else if (insn_bits10_11 == 0x01)
{
if (record_debug)
- fprintf_unfiltered (gdb_stdlog, "FP - conditional compare");
+ debug_printf ("FP - conditional compare");
record_buf[0] = AARCH64_CPSR_REGNUM;
}
@@ -3667,7 +3670,7 @@ aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
else if (insn_bits10_11 == 0x02 || insn_bits10_11 == 0x03)
{
if (record_debug)
- fprintf_unfiltered (gdb_stdlog, "FP - DP (2-source)");
+ debug_printf ("FP - DP (2-source)");
record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
}
@@ -3678,14 +3681,14 @@ aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
|| (insn_bits12_15 & 0x07) == 0x04)
{
if (record_debug)
- fprintf_unfiltered (gdb_stdlog, "FP - immediate");
+ debug_printf ("FP - immediate");
record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
}
/* Floating point - compare instructions. */
else if ((insn_bits12_15 & 0x03) == 0x02)
{
if (record_debug)
- fprintf_unfiltered (gdb_stdlog, "FP - immediate");
+ debug_printf ("FP - immediate");
record_buf[0] = AARCH64_CPSR_REGNUM;
}
/* Floating point - integer conversions instructions. */
@@ -3695,7 +3698,7 @@ aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
if (!(opcode >> 1) || ((opcode >> 1) == 0x02 && !rmode))
{
if (record_debug)
- fprintf_unfiltered (gdb_stdlog, "float to int conversion");
+ debug_printf ("float to int conversion");
record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
}
@@ -3703,7 +3706,7 @@ aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
else if ((opcode >> 1) == 0x01 && !rmode)
{
if (record_debug)
- fprintf_unfiltered (gdb_stdlog, "int to float conversion");
+ debug_printf ("int to float conversion");
record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
}
@@ -3711,7 +3714,7 @@ aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
else if ((opcode >> 1) == 0x03)
{
if (record_debug)
- fprintf_unfiltered (gdb_stdlog, "move float to int");
+ debug_printf ("move float to int");
if (!(opcode & 0x01))
record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
@@ -3730,7 +3733,7 @@ aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
else if ((insn_bits28_31 & 0x09) == 0x00 && insn_bits24_27 == 0x0e)
{
if (record_debug)
- fprintf_unfiltered (gdb_stdlog, "SIMD copy");
+ debug_printf ("SIMD copy");
/* Advanced SIMD copy instructions. */
if (!bits (aarch64_insn_r->aarch64_insn, 21, 23)
@@ -3749,13 +3752,13 @@ aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
else
{
if (record_debug)
- fprintf_unfiltered (gdb_stdlog, "all remain");
+ debug_printf ("all remain");
record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
}
if (record_debug)
- fprintf_unfiltered (gdb_stdlog, "\n");
+ debug_printf ("\n");
aarch64_insn_r->reg_rec_count++;
gdb_assert (aarch64_insn_r->reg_rec_count == 1);
--
2.4.6
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [PATCH 2/8 v2] [AArch64] Use debug_printf instead of fprintf_unfiltered
2015-09-15 11:43 ` [PATCH 2/8 v2] " Pierre Langlois
@ 2015-09-15 17:40 ` Pierre Langlois
0 siblings, 0 replies; 37+ messages in thread
From: Pierre Langlois @ 2015-09-15 17:40 UTC (permalink / raw)
To: gdb-patches; +Cc: pierre.langlois
On 15/09/15 12:43, Pierre Langlois wrote:
> Here is an updated patch that fixes the formatting issues. I've had to
> rebase the following patches on top of this one, to propagate to changes
> over to functions that were moved. I'll post them shortly.
>
> Thanks,
> Pierre
>
> ---
>
> GDBserver uses debug_printf to print debugging output. This patch makes
> GDB use this too so we can share some of this code with GDBserver later.
>
> gdb/ChangeLog:
>
> * aarch64-tdep.c (decode_add_sub_imm): Use debug_printf.
> (decode_adrp): Likewise.
> (decode_b): Likewise.
> (decode_bcond): Likewise.
> (decode_br): Likewise.
> (decode_cb): Likewise.
> (decode_eret): Likewise.
> (decode_movz): Likewise.
> (decode_orr_shifted_register_x): Likewise.
> (decode_ret): Likewise.
> (decode_stp_offset): Likewise.
> (decode_stp_offset_wb): Likewise.
> (decode_stur): Likewise.
> (decode_tb): Likewise.
> (aarch64_analyze_prologue): Likewise.
> (pass_in_x): Likewise.
> (pass_in_v): Likewise.
> (pass_on_stack): Likewise.
> (aarch64_push_dummy_call): Likewise.
> (aarch64_extract_return_value): Likewise.
> (aarch64_store_return_value): Likewise.
> (aarch64_return_value): Likewise.
> (aarch64_record_asimd_load_store): Likewise.
> (aarch64_record_load_store): Likewise.
> (aarch64_record_data_proc_simd_fp): Likewise.
I've pushed this in.
Thanks,
Pierre
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 3/8] [AArch64] Make aarch64_decode_adrp handle both ADR and ADRP instructions
2015-09-14 11:31 [PATCH 0/8] [AArch64] Support fast tracepoints Pierre Langlois
2015-09-14 11:31 ` [PATCH 1/8] [AArch64] Use debug_printf instead of fprintf_unfiltered Pierre Langlois
@ 2015-09-14 11:31 ` Pierre Langlois
2015-09-15 10:12 ` Yao Qi
2015-09-14 11:32 ` [PATCH 7/8] [testsuite] Add a gdb.trace test for instruction relocation Pierre Langlois
` (7 subsequent siblings)
9 siblings, 1 reply; 37+ messages in thread
From: Pierre Langlois @ 2015-09-14 11:31 UTC (permalink / raw)
To: gdb-patches; +Cc: Pierre Langlois
We will need to decode both ADR and ADRP instructions in GDBserver.
This patch makes common code handle both cases, even if GDB only needs
to decode the ADRP instruction.
gdb/ChangeLog:
* aarch64-tdep.c (aarch64_analyze_prologue): New is_adrp
variable. Call aarch64_decode_adr instead of
aarch64_decode_adrp.
* arch/aarch64-insn.h (aarch64_decode_adrp): Delete.
(aarch64_decode_adr): New function declaration.
* arch/aarch64-insn.c (aarch64_decode_adrp): Delete.
(aarch64_decode_adr): New function, factored out from
aarch64_decode_adrp to decode both adr and adrp instructions.
---
gdb/aarch64-tdep.c | 4 +++-
gdb/arch/aarch64-insn.c | 29 ++++++++++++++++++++++++-----
gdb/arch/aarch64-insn.h | 3 ++-
3 files changed, 29 insertions(+), 7 deletions(-)
diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index e3340bd..86bc375 100644
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -532,13 +532,15 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
int is_cbnz;
int is_tbnz;
unsigned bit;
+ int is_adrp;
int32_t offset;
insn = read_memory_unsigned_integer (start, 4, byte_order_for_code);
if (aarch64_decode_add_sub_imm (start, insn, &rd, &rn, &imm))
regs[rd] = pv_add_constant (regs[rn], imm);
- else if (aarch64_decode_adrp (start, insn, &rd))
+ else if (aarch64_decode_adr (start, insn, &is_adrp, &rd, &offset)
+ && is_adrp)
regs[rd] = pv_unknown ();
else if (aarch64_decode_b (start, insn, &is_link, &offset))
{
diff --git a/gdb/arch/aarch64-insn.c b/gdb/arch/aarch64-insn.c
index 9834b9d..10cfa8b 100644
--- a/gdb/arch/aarch64-insn.c
+++ b/gdb/arch/aarch64-insn.c
@@ -55,24 +55,43 @@ decode_masked_match (uint32_t insn, uint32_t mask, uint32_t pattern)
return (insn & mask) == pattern;
}
-/* Decode an opcode if it represents an ADRP instruction.
+/* Decode an opcode if it represents an ADR or ADRP instruction.
ADDR specifies the address of the opcode.
INSN specifies the opcode to test.
+ IS_ADRP receives the 'op' field from the decoded instruction.
RD receives the 'rd' field from the decoded instruction.
+ OFFSET receives the 'immhi:immlo' field from the decoded instruction.
Return 1 if the opcodes matches and is decoded, otherwise 0. */
int
-aarch64_decode_adrp (CORE_ADDR addr, uint32_t insn, unsigned *rd)
+aarch64_decode_adr (CORE_ADDR addr, uint32_t insn, int *is_adrp,
+ unsigned *rd, int32_t *offset)
{
- if (decode_masked_match (insn, 0x9f000000, 0x90000000))
+ /* adr 0ii1 0000 iiii iiii iiii iiii iiir rrrr */
+ /* adrp 1ii1 0000 iiii iiii iiii iiii iiir rrrr */
+ if (decode_masked_match (insn, 0x1f000000, 0x10000000))
{
+ uint32_t immlo = (insn >> 29) & 0x3;
+ int32_t immhi = extract_signed_bitfield (insn, 19, 5) << 2;
+
+ *is_adrp = (insn >> 31) & 0x1;
*rd = (insn >> 0) & 0x1f;
+ if (*is_adrp)
+ {
+ /* The ADRP instruction has an offset with a -/+ 4GB range,
+ encoded as (immhi:immlo * 4096). */
+ *offset = (immhi | immlo) * 4096;
+ }
+ else
+ *offset = (immhi | immlo);
+
if (aarch64_debug)
- debug_printf ("decode: 0x%s 0x%x adrp x%u, #?\n",
- core_addr_to_string_nz (addr), insn, *rd);
+ debug_printf ("decode: 0x%s 0x%x %s x%u, #?\n",
+ core_addr_to_string_nz (addr), insn,
+ *is_adrp ? "adrp" : "adr", *rd);
return 1;
}
return 0;
diff --git a/gdb/arch/aarch64-insn.h b/gdb/arch/aarch64-insn.h
index 7775a34..2facb44 100644
--- a/gdb/arch/aarch64-insn.h
+++ b/gdb/arch/aarch64-insn.h
@@ -21,7 +21,8 @@
extern int aarch64_debug;
-int aarch64_decode_adrp (CORE_ADDR addr, uint32_t insn, unsigned *rd);
+int aarch64_decode_adr (CORE_ADDR addr, uint32_t insn, int *is_adrp,
+ unsigned *rd, int32_t *offset);
int aarch64_decode_b (CORE_ADDR addr, uint32_t insn, int *is_bl,
int32_t *offset);
--
2.4.6
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [PATCH 3/8] [AArch64] Make aarch64_decode_adrp handle both ADR and ADRP instructions
2015-09-14 11:31 ` [PATCH 3/8] [AArch64] Make aarch64_decode_adrp handle both ADR and ADRP instructions Pierre Langlois
@ 2015-09-15 10:12 ` Yao Qi
2015-09-15 12:05 ` [PATCH 3/8 v2] " Pierre Langlois
0 siblings, 1 reply; 37+ messages in thread
From: Yao Qi @ 2015-09-15 10:12 UTC (permalink / raw)
To: Pierre Langlois; +Cc: gdb-patches
Pierre Langlois <pierre.langlois@arm.com> writes:
> gdb/ChangeLog:
>
> * aarch64-tdep.c (aarch64_analyze_prologue): New is_adrp
> variable. Call aarch64_decode_adr instead of
> aarch64_decode_adrp.
> * arch/aarch64-insn.h (aarch64_decode_adrp): Delete.
> (aarch64_decode_adr): New function declaration.
> * arch/aarch64-insn.c (aarch64_decode_adrp): Delete.
> (aarch64_decode_adr): New function, factored out from
> aarch64_decode_adrp to decode both adr and adrp instructions.
Looks good to me.
--
Yao (齐尧)
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 3/8 v2] [AArch64] Make aarch64_decode_adrp handle both ADR and ADRP instructions
2015-09-15 10:12 ` Yao Qi
@ 2015-09-15 12:05 ` Pierre Langlois
0 siblings, 0 replies; 37+ messages in thread
From: Pierre Langlois @ 2015-09-15 12:05 UTC (permalink / raw)
To: gdb-patches; +Cc: Pierre Langlois
Here is the rebased patch.
Thanks,
Pierre
---
We will need to decode both ADR and ADRP instructions in GDBserver.
This patch makes common code handle both cases, even if GDB only needs
to decode the ADRP instruction.
gdb/ChangeLog:
* aarch64-tdep.c (aarch64_analyze_prologue): New is_adrp
variable. Call aarch64_decode_adr instead of
aarch64_decode_adrp.
* arch/aarch64-insn.h (aarch64_decode_adrp): Delete.
(aarch64_decode_adr): New function declaration.
* arch/aarch64-insn.c (aarch64_decode_adrp): Delete.
(aarch64_decode_adr): New function, factored out from
aarch64_decode_adrp to decode both adr and adrp instructions.
---
gdb/aarch64-tdep.c | 4 +++-
gdb/arch/aarch64-insn.c | 29 ++++++++++++++++++++++++-----
gdb/arch/aarch64-insn.h | 3 ++-
3 files changed, 29 insertions(+), 7 deletions(-)
diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index 92e2404..da61e54 100644
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -551,13 +551,15 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
int is_cbnz;
int is_tbnz;
unsigned bit;
+ int is_adrp;
int32_t offset;
insn = read_memory_unsigned_integer (start, 4, byte_order_for_code);
if (aarch64_decode_add_sub_imm (start, insn, &rd, &rn, &imm))
regs[rd] = pv_add_constant (regs[rn], imm);
- else if (aarch64_decode_adrp (start, insn, &rd))
+ else if (aarch64_decode_adr (start, insn, &is_adrp, &rd, &offset)
+ && is_adrp)
regs[rd] = pv_unknown ();
else if (aarch64_decode_b (start, insn, &is_link, &offset))
{
diff --git a/gdb/arch/aarch64-insn.c b/gdb/arch/aarch64-insn.c
index 3a289a2..13d0013 100644
--- a/gdb/arch/aarch64-insn.c
+++ b/gdb/arch/aarch64-insn.c
@@ -55,25 +55,44 @@ decode_masked_match (uint32_t insn, uint32_t mask, uint32_t pattern)
return (insn & mask) == pattern;
}
-/* Decode an opcode if it represents an ADRP instruction.
+/* Decode an opcode if it represents an ADR or ADRP instruction.
ADDR specifies the address of the opcode.
INSN specifies the opcode to test.
+ IS_ADRP receives the 'op' field from the decoded instruction.
RD receives the 'rd' field from the decoded instruction.
+ OFFSET receives the 'immhi:immlo' field from the decoded instruction.
Return 1 if the opcodes matches and is decoded, otherwise 0. */
int
-aarch64_decode_adrp (CORE_ADDR addr, uint32_t insn, unsigned *rd)
+aarch64_decode_adr (CORE_ADDR addr, uint32_t insn, int *is_adrp,
+ unsigned *rd, int32_t *offset)
{
- if (decode_masked_match (insn, 0x9f000000, 0x90000000))
+ /* adr 0ii1 0000 iiii iiii iiii iiii iiir rrrr */
+ /* adrp 1ii1 0000 iiii iiii iiii iiii iiir rrrr */
+ if (decode_masked_match (insn, 0x1f000000, 0x10000000))
{
+ uint32_t immlo = (insn >> 29) & 0x3;
+ int32_t immhi = extract_signed_bitfield (insn, 19, 5) << 2;
+
+ *is_adrp = (insn >> 31) & 0x1;
*rd = (insn >> 0) & 0x1f;
+ if (*is_adrp)
+ {
+ /* The ADRP instruction has an offset with a -/+ 4GB range,
+ encoded as (immhi:immlo * 4096). */
+ *offset = (immhi | immlo) * 4096;
+ }
+ else
+ *offset = (immhi | immlo);
+
if (aarch64_debug)
{
- debug_printf ("decode: 0x%s 0x%x adrp x%u, #?\n",
- core_addr_to_string_nz (addr), insn, *rd);
+ debug_printf ("decode: 0x%s 0x%x %s x%u, #?\n",
+ core_addr_to_string_nz (addr), insn,
+ *is_adrp ? "adrp" : "adr", *rd);
}
return 1;
}
diff --git a/gdb/arch/aarch64-insn.h b/gdb/arch/aarch64-insn.h
index 7775a34..2facb44 100644
--- a/gdb/arch/aarch64-insn.h
+++ b/gdb/arch/aarch64-insn.h
@@ -21,7 +21,8 @@
extern int aarch64_debug;
-int aarch64_decode_adrp (CORE_ADDR addr, uint32_t insn, unsigned *rd);
+int aarch64_decode_adr (CORE_ADDR addr, uint32_t insn, int *is_adrp,
+ unsigned *rd, int32_t *offset);
int aarch64_decode_b (CORE_ADDR addr, uint32_t insn, int *is_bl,
int32_t *offset);
--
2.4.6
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 7/8] [testsuite] Add a gdb.trace test for instruction relocation
2015-09-14 11:31 [PATCH 0/8] [AArch64] Support fast tracepoints Pierre Langlois
2015-09-14 11:31 ` [PATCH 1/8] [AArch64] Use debug_printf instead of fprintf_unfiltered Pierre Langlois
2015-09-14 11:31 ` [PATCH 3/8] [AArch64] Make aarch64_decode_adrp handle both ADR and ADRP instructions Pierre Langlois
@ 2015-09-14 11:32 ` Pierre Langlois
2015-09-15 11:27 ` Yao Qi
2015-09-14 11:32 ` [PATCH 6/8] [testsuite][AArch64] Enable fast tracepoint tests Pierre Langlois
` (6 subsequent siblings)
9 siblings, 1 reply; 37+ messages in thread
From: Pierre Langlois @ 2015-09-14 11:32 UTC (permalink / raw)
To: gdb-patches; +Cc: Pierre Langlois
This test case makes sure that relocating PC relative instructions does
not change their behaviors. All PC relative AArch64 instructions are
covered. While call and jump (32 bit relative) instructions are covered
on x86.
The test case creates a static array of function pointers for each
supported architecture. Each function in this array tests a specific
instruction using inline assembly. They all need to contain a symbol in
the form of 'set_point\[0-9\]+' and finish by either calling pass or
fail. The number of 'set_pointN' needs to go from 0 to
(ARRAY_SIZE - 1).
The test will:
- look up the number of function pointers in the static array.
- set fast tracepoints on each 'set_point\[0-9\]+' symbol, one in each
functions from 0 to (ARRAY_SIZE - 1).
- run the trace experiment and make sure the pass function is called for
every function.
gdb/testsuite/ChangeLog:
* gdb.trace/ftrace-insn-reloc.c: New file.
* gdb.trace/ftrace-insn-reloc.exp: New file.
---
gdb/testsuite/gdb.trace/ftrace-insn-reloc.c | 508 ++++++++++++++++++++++++++
gdb/testsuite/gdb.trace/ftrace-insn-reloc.exp | 114 ++++++
2 files changed, 622 insertions(+)
create mode 100644 gdb/testsuite/gdb.trace/ftrace-insn-reloc.c
create mode 100644 gdb/testsuite/gdb.trace/ftrace-insn-reloc.exp
diff --git a/gdb/testsuite/gdb.trace/ftrace-insn-reloc.c b/gdb/testsuite/gdb.trace/ftrace-insn-reloc.c
new file mode 100644
index 0000000..c7148a2
--- /dev/null
+++ b/gdb/testsuite/gdb.trace/ftrace-insn-reloc.c
@@ -0,0 +1,508 @@
+/* This testcase is part of GDB, the GNU debugger.
+
+ Copyright 2015 Free Software Foundation, Inc.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#include <stddef.h>
+#include <stdint.h>
+
+typedef void (*testcase_ftype)(void);
+
+/* Each function checks the correctness of the instruction being
+ relocated due to a fast tracepoint. Call function pass if it is
+ correct, otherwise call function fail. GDB sets a breakpoints on
+ pass and fail in order to check the correctness. */
+
+static void
+pass (void)
+{
+}
+
+static void
+fail (void)
+{
+}
+
+#if (defined __x86_64__ || defined __i386__)
+
+#ifdef SYMBOL_PREFIX
+#define SYMBOL(str) SYMBOL_PREFIX #str
+#else
+#define SYMBOL(str) #str
+#endif
+
+/* Make sure we can relocate a CALL instruction. CALL instructions are
+ 5 bytes long so we can always set a fast tracepoints on them.
+
+ JMP set_point0
+ f:
+ MOV $1, %[ok]
+ JMP end
+ set_point0:
+ CALL f ; tracepoint here.
+ end:
+
+ */
+
+static void
+can_relocate_call (void)
+{
+ int ok = 0;
+
+ asm (" .global " SYMBOL (set_point0) "\n"
+ " jmp " SYMBOL (set_point0) "\n"
+ "0:\n"
+ " mov $1, %[ok]\n"
+ " jmp 1f\n"
+ SYMBOL (set_point0) ":\n"
+ " call 0b\n"
+ "1:\n"
+ : [ok] "=r" (ok));
+
+ if (ok == 1)
+ pass ();
+ else
+ fail ();
+}
+
+/* Make sure we can relocate a JMP instruction. We need the JMP
+ instruction to be 5 bytes long in order to set a fast tracepoint on
+ it. To do this, we emit the opcode directly.
+
+ JMP next ; tracepoint here.
+ next:
+ MOV $1, %[ok]
+
+ */
+
+static void
+can_relocate_jump (void)
+{
+ int ok = 0;
+
+ asm (" .global " SYMBOL (set_point1) "\n"
+ SYMBOL (set_point1) ":\n"
+ ".byte 0xe9\n" /* jmp */
+ ".byte 0x00\n"
+ ".byte 0x00\n"
+ ".byte 0x00\n"
+ ".byte 0x00\n"
+ " mov $1, %[ok]\n"
+ : [ok] "=r" (ok));
+
+ if (ok == 1)
+ pass ();
+ else
+ fail ();
+}
+#elif (defined __aarch64__)
+
+/* Make sure we can relocate a B instruction.
+
+ B set_point0
+ set_ok:
+ MOV %[ok], #1
+ B end
+ set_point0:
+ B set_ok ; tracepoint here.
+ MOV %[ok], #0
+ end
+
+ */
+
+static void
+can_relocate_b (void)
+{
+ int ok = 0;
+
+ asm (" b set_point0\n"
+ "0:\n"
+ " mov %[ok], #1\n"
+ " b 1f\n"
+ "set_point0:\n"
+ " b 0b\n"
+ " mov %[ok], #0\n"
+ "1:\n"
+ : [ok] "=r" (ok));
+
+ if (ok == 1)
+ pass ();
+ else
+ fail ();
+}
+
+/* Make sure we can relocate a B.cond instruction.
+
+ MOV x0, #8
+ TST x0, #8 ; Clear the Z flag.
+ B set_point1
+ set_ok:
+ MOV %[ok], #1
+ B end
+ set_point1:
+ B.NE set_ok ; tracepoint here.
+ MOV %[ok], #0
+ end
+
+ */
+
+static void
+can_relocate_bcond (void)
+{
+ int ok = 0;
+
+ asm (" mov x0, #8\n"
+ " tst x0, #8\n"
+ " b set_point1\n"
+ "0:\n"
+ " mov %[ok], #1\n"
+ " b 1f\n"
+ "set_point1:\n"
+ " b.ne 0b\n"
+ " mov %[ok], #0\n"
+ "1:\n"
+ : [ok] "=r" (ok)
+ :
+ : "0", "cc");
+
+ if (ok == 1)
+ pass ();
+ else
+ fail ();
+}
+
+/* Make sure we can relocate a CBZ instruction.
+
+ MOV x0, #0
+ B set_point2
+ set_ok:
+ MOV %[ok], #1
+ B end
+ set_point2:
+ CBZ x0, set_ok ; tracepoint here.
+ MOV %[ok], #0
+ end
+
+ */
+
+static void
+can_relocate_cbz (void)
+{
+ int ok = 0;
+
+ asm (" mov x0, #0\n"
+ " b set_point2\n"
+ "0:\n"
+ " mov %[ok], #1\n"
+ " b 1f\n"
+ "set_point2:\n"
+ " cbz x0, 0b\n"
+ " mov %[ok], #0\n"
+ "1:\n"
+ : [ok] "=r" (ok)
+ :
+ : "0");
+
+ if (ok == 1)
+ pass ();
+ else
+ fail ();
+}
+
+/* Make sure we can relocate a CBNZ instruction.
+
+ MOV x0, #8
+ B set_point3
+ set_ok:
+ MOV %[ok], #1
+ B end
+ set_point3:
+ CBNZ x0, set_ok ; tracepoint here.
+ MOV %[ok], #0
+ end
+
+ */
+
+static void
+can_relocate_cbnz (void)
+{
+ int ok = 0;
+
+ asm (" mov x0, #8\n"
+ " b set_point3\n"
+ "0:\n"
+ " mov %[ok], #1\n"
+ " b 1f\n"
+ "set_point3:\n"
+ " cbnz x0, 0b\n"
+ " mov %[ok], #0\n"
+ "1:\n"
+ : [ok] "=r" (ok)
+ :
+ : "0");
+
+ if (ok == 1)
+ pass ();
+ else
+ fail ();
+}
+
+/* Make sure we can relocate a TBZ instruction.
+
+ MOV x0, #8
+ MVN x0, x0 ; Clear bit 3.
+ B set_point4
+ set_ok:
+ MOV %[ok], #1
+ B end
+ set_point4:
+ TBZ x0, #3, set_ok ; tracepoint here.
+ MOV %[ok], #0
+ end
+
+ */
+
+static void
+can_relocate_tbz (void)
+{
+ int ok = 0;
+
+ asm (" mov x0, #8\n"
+ " mvn x0, x0\n"
+ " b set_point4\n"
+ "0:\n"
+ " mov %[ok], #1\n"
+ " b 1f\n"
+ "set_point4:\n"
+ " tbz x0, #3, 0b\n"
+ " mov %[ok], #0\n"
+ "1:\n"
+ : [ok] "=r" (ok)
+ :
+ : "0");
+
+ if (ok == 1)
+ pass ();
+ else
+ fail ();
+}
+
+/* Make sure we can relocate a TBNZ instruction.
+
+ MOV x0, #8 ; Set bit 3.
+ B set_point5
+ set_ok:
+ MOV %[ok], #1
+ B end
+ set_point5:
+ TBNZ x0, #3, set_ok ; tracepoint here.
+ MOV %[ok], #0
+ end
+
+ */
+
+static void
+can_relocate_tbnz (void)
+{
+ int ok = 0;
+
+ asm (" mov x0, #8\n"
+ " b set_point5\n"
+ "0:\n"
+ " mov %[ok], #1\n"
+ " b 1f\n"
+ "set_point5:\n"
+ " tbnz x0, #3, 0b\n"
+ " mov %[ok], #0\n"
+ "1:\n"
+ : [ok] "=r" (ok)
+ :
+ : "0");
+
+ if (ok == 1)
+ pass ();
+ else
+ fail ();
+}
+
+/* Make sure we can relocate an ADR instruction with a positive offset.
+
+ set_point6:
+ ADR x0, target ; tracepoint here.
+ BR x0 ; jump to target
+ MOV %[ok], #0
+ B end
+ target:
+ MOV %[ok], #1
+ end
+
+ */
+
+static void
+can_relocate_adr_forward (void)
+{
+ int ok = 0;
+
+ asm ("set_point6:\n"
+ " adr x0, 0f\n"
+ " br x0\n"
+ " mov %[ok], #0\n"
+ " b 1f\n"
+ "0:\n"
+ " mov %[ok], #1\n"
+ "1:\n"
+ : [ok] "=r" (ok)
+ :
+ : "0");
+
+ if (ok == 1)
+ pass ();
+ else
+ fail ();
+}
+
+/* Make sure we can relocate an ADR instruction with a negative offset.
+
+ B set_point7
+ target:
+ MOV %[ok], #1
+ B end
+ set_point7:
+ ADR x0, target ; tracepoint here.
+ BR x0 ; jump to target
+ MOV %[ok], #0
+ end
+
+ */
+
+static void
+can_relocate_adr_backward (void)
+{
+ int ok = 0;
+
+ asm ("b set_point7\n"
+ "0:\n"
+ " mov %[ok], #1\n"
+ " b 1f\n"
+ "set_point7:\n"
+ " adr x0, 0b\n"
+ " br x0\n"
+ " mov %[ok], #0\n"
+ "1:\n"
+ : [ok] "=r" (ok)
+ :
+ : "0");
+
+ if (ok == 1)
+ pass ();
+ else
+ fail ();
+}
+
+/* Make sure we can relocate an ADRP instruction.
+
+ set_point8:
+ ADRP %[addr], set_point8 ; tracepoint here.
+ ADR %[pc], set_point8
+
+ ADR computes the address of the given label. While ADRP gives us its
+ page, on a 4K boundary. We can check ADRP executed normally by
+ making sure the result of ADR and ADRP are equivalent, except for the
+ 12 lowest bits which should be cleared.
+
+ */
+
+static void
+can_relocate_adrp (void)
+{
+ uintptr_t page;
+ uintptr_t pc;
+
+ asm ("set_point8:\n"
+ " adrp %[page], set_point8\n"
+ " adr %[pc], set_point8\n"
+ : [page] "=r" (page), [pc] "=r" (pc));
+
+ if (page == (pc & ~0xfff))
+ pass ();
+ else
+ fail ();
+}
+
+/* Make sure we can relocate an LDR instruction, where the memory to
+ read is an offset from the current PC.
+
+ B set_point9
+ data:
+ .word 0x0cabba9e
+ set_point9:
+ LDR %[result], data ; tracepoint here.
+
+ */
+
+static void
+can_relocate_ldr (void)
+{
+ uint32_t result = 0;
+
+ asm ("b set_point9\n"
+ "0:\n"
+ " .word 0x0cabba9e\n"
+ "set_point9:\n"
+ " ldr %w[result], 0b\n"
+ : [result] "=r" (result));
+
+ if (result == 0x0cabba9e)
+ pass ();
+ else
+ fail ();
+}
+#endif
+
+/* Functions testing relocations need to be placed here. GDB will read
+ n_testcases to know how many fast tracepoints to place. It will look
+ for symbols in the form of 'set_point\[0-9\]+' so each functions
+ needs one, starting at 0. */
+
+static testcase_ftype testcases[] = {
+#if (defined __x86_64__ || defined __i386__)
+ can_relocate_call,
+ can_relocate_jump
+#elif (defined __aarch64__)
+ can_relocate_b,
+ can_relocate_bcond,
+ can_relocate_cbz,
+ can_relocate_cbnz,
+ can_relocate_tbz,
+ can_relocate_tbnz,
+ can_relocate_adr_forward,
+ can_relocate_adr_backward,
+ can_relocate_adrp,
+ can_relocate_ldr
+#endif
+};
+
+static size_t n_testcases = (sizeof (testcases) / sizeof (testcase_ftype));
+
+int
+main ()
+{
+ int i = 0;
+
+ for (i = 0; i < n_testcases; i++)
+ testcases[i] ();
+
+ return 0;
+}
diff --git a/gdb/testsuite/gdb.trace/ftrace-insn-reloc.exp b/gdb/testsuite/gdb.trace/ftrace-insn-reloc.exp
new file mode 100644
index 0000000..dd33190
--- /dev/null
+++ b/gdb/testsuite/gdb.trace/ftrace-insn-reloc.exp
@@ -0,0 +1,114 @@
+# Copyright 2015 Free Software Foundation, Inc.
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+load_lib "trace-support.exp"
+
+standard_testfile
+set executable $testfile
+set expfile $testfile.exp
+
+# Some targets have leading underscores on assembly symbols.
+set additional_flags [gdb_target_symbol_prefix_flags]
+
+if [prepare_for_testing $expfile $executable $srcfile \
+ [list debug $additional_flags]] {
+ untested "failed to prepare for trace tests"
+ return -1
+}
+
+if ![runto_main] {
+ fail "Can't run to main to check for trace support"
+ return -1
+}
+
+if ![gdb_target_supports_trace] {
+ unsupported "target does not support trace"
+ return -1
+}
+
+set libipa [get_in_proc_agent]
+gdb_load_shlibs $libipa
+
+# Can't use prepare_for_testing, because that splits compiling into
+# building objects and then linking, and we'd fail with "linker input
+# file unused because linking not done" when building the object.
+
+if { [gdb_compile "$srcdir/$subdir/$srcfile" $binfile \
+ executable [list debug $additional_flags shlib=$libipa] ] != "" } {
+ untested "failed to compile ftrace tests"
+ return -1
+}
+clean_restart ${executable}
+
+if ![runto_main] {
+ fail "Can't run to main for ftrace tests"
+ return 0
+}
+
+gdb_reinitialize_dir $srcdir/$subdir
+
+if { [gdb_test "info sharedlibrary" ".*${libipa}.*" "IPA loaded"] != 0 } {
+ untested "Could not find IPA lib loaded"
+ return 1
+}
+
+# Read function name from testcases[N].
+
+proc read_testcase { n } {
+ global gdb_prompt
+
+ set result -1
+ gdb_test_multiple "print testcases\[${n}\]" "read name of test case ${n}" {
+ -re "\[$\].*= .*<(.*)>.*$gdb_prompt $" {
+ set result $expect_out(1,string)
+ }
+ -re "$gdb_prompt $" { }
+ }
+
+ return $result
+}
+
+set n_testcases [gdb_readexpr "n_testcases"]
+
+if { ${n_testcases} == 0 } {
+ untested "No instruction relocation to test"
+ return 1
+}
+
+# Set a fast tracepoint on each set_point${i} symbol. There is one for
+# each testcase.
+for { set i 0 } { ${i} < ${n_testcases} } { incr i } {
+ set testcase [read_testcase $i]
+
+ gdb_test "ftrace *set_point$i" "Fast tracepoint .*" \
+ "fast tracepoint on ${testcase}"
+}
+
+gdb_test "break pass" ".*" ""
+gdb_test "break fail" ".*" ""
+
+gdb_test_no_output "tstart" "start trace experiment"
+
+# Make sure we have hit the pass breakpoint for each testcase.
+for { set i 0 } { ${i} < ${n_testcases} } { incr i } {
+ set testcase [read_testcase $i]
+
+ gdb_test "continue" \
+ ".*Breakpoint \[0-9\]+, pass \(\).*" \
+ "relocated instruction at ${testcase}"
+}
+
+gdb_test "tstatus" ".*Collected ${n_testcases} trace frames.*" "check on trace status"
+
+gdb_test "tstop" "" ""
--
2.4.6
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [PATCH 7/8] [testsuite] Add a gdb.trace test for instruction relocation
2015-09-14 11:32 ` [PATCH 7/8] [testsuite] Add a gdb.trace test for instruction relocation Pierre Langlois
@ 2015-09-15 11:27 ` Yao Qi
0 siblings, 0 replies; 37+ messages in thread
From: Yao Qi @ 2015-09-15 11:27 UTC (permalink / raw)
To: Pierre Langlois; +Cc: gdb-patches
Pierre Langlois <pierre.langlois@arm.com> writes:
> This test case makes sure that relocating PC relative instructions does
> not change their behaviors. All PC relative AArch64 instructions are
> covered. While call and jump (32 bit relative) instructions are covered
> on x86.
>
> The test case creates a static array of function pointers for each
> supported architecture. Each function in this array tests a specific
> instruction using inline assembly. They all need to contain a symbol in
> the form of 'set_point\[0-9\]+' and finish by either calling pass or
> fail. The number of 'set_pointN' needs to go from 0 to
> (ARRAY_SIZE - 1).
>
> The test will:
> - look up the number of function pointers in the static array.
> - set fast tracepoints on each 'set_point\[0-9\]+' symbol, one in each
> functions from 0 to (ARRAY_SIZE - 1).
> - run the trace experiment and make sure the pass function is called for
> every function.
>
> gdb/testsuite/ChangeLog:
>
> * gdb.trace/ftrace-insn-reloc.c: New file.
> * gdb.trace/ftrace-insn-reloc.exp: New file.
The patch looks good to me.
I am wondering we could move gdb.trace/ftrace-insn-reloc.c to
gdb.arch/insn-reloc.c, because it is can be used for testing displaced
stepping as well. We can move gdb.trace/ftrace-insn-reloc.exp
to gdb.arch too. Any objections?
You can push it in in a few days if there are no objections on moving
them to gdb.arch directory.
--
Yao (齐尧)
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 6/8] [testsuite][AArch64] Enable fast tracepoint tests
2015-09-14 11:31 [PATCH 0/8] [AArch64] Support fast tracepoints Pierre Langlois
` (2 preceding siblings ...)
2015-09-14 11:32 ` [PATCH 7/8] [testsuite] Add a gdb.trace test for instruction relocation Pierre Langlois
@ 2015-09-14 11:32 ` Pierre Langlois
2015-09-15 10:18 ` Yao Qi
2015-09-14 11:32 ` [PATCH 5/8] [GDBserver][AArch64] Implement target_emit_ops Pierre Langlois
` (5 subsequent siblings)
9 siblings, 1 reply; 37+ messages in thread
From: Pierre Langlois @ 2015-09-14 11:32 UTC (permalink / raw)
To: gdb-patches; +Cc: Pierre Langlois
gdb/testsuite/ChangeLog:
* gdb.trace/change-loc.h (func4): Add a nop instruction for
__aarch64__.
* gdb.trace/pendshr1.c (pendfunc): Likewise.
* gdb.trace/pendshr2.c (pendfunc2): Likewise.
* gdb.trace/range-stepping.c: Likewise.
* gdb.trace/trace-break.c: Likewise.
* gdb.trace/trace-mt.c (thread_function): Likewise.
* gdb.trace/ftrace.c (marker): Likewise.
* gdb.trace/ftrace-condition.c (marker): Likewise.
* gdb.trace/ftrace.exp: Enable ftrace test if is_aarch64_target.
* gdb.trace/ftrace-condition.exp: Set pcreg to "\$pc" if
is_aarch64_target.
---
gdb/testsuite/gdb.trace/change-loc.h | 2 ++
gdb/testsuite/gdb.trace/ftrace.c | 2 ++
gdb/testsuite/gdb.trace/ftrace.exp | 2 +-
gdb/testsuite/gdb.trace/pendshr1.c | 2 ++
gdb/testsuite/gdb.trace/pendshr2.c | 2 ++
gdb/testsuite/gdb.trace/range-stepping.c | 2 ++
gdb/testsuite/gdb.trace/trace-break.c | 4 ++++
gdb/testsuite/gdb.trace/trace-condition.c | 2 ++
gdb/testsuite/gdb.trace/trace-condition.exp | 2 ++
gdb/testsuite/gdb.trace/trace-mt.c | 2 ++
10 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/gdb/testsuite/gdb.trace/change-loc.h b/gdb/testsuite/gdb.trace/change-loc.h
index e8e2e86..8201455 100644
--- a/gdb/testsuite/gdb.trace/change-loc.h
+++ b/gdb/testsuite/gdb.trace/change-loc.h
@@ -36,6 +36,8 @@ func4 (void)
SYMBOL(set_tracepoint) ":\n"
#if (defined __x86_64__ || defined __i386__)
" call " SYMBOL(func5) "\n"
+#elif (defined __aarch64__)
+ " nop\n"
#endif
);
diff --git a/gdb/testsuite/gdb.trace/ftrace.c b/gdb/testsuite/gdb.trace/ftrace.c
index f522e6f..7373d66 100644
--- a/gdb/testsuite/gdb.trace/ftrace.c
+++ b/gdb/testsuite/gdb.trace/ftrace.c
@@ -42,6 +42,8 @@ marker (int anarg)
SYMBOL(set_point) ":\n"
#if (defined __x86_64__ || defined __i386__)
" call " SYMBOL(func) "\n"
+#elif (defined __aarch64__)
+ " nop\n"
#endif
);
diff --git a/gdb/testsuite/gdb.trace/ftrace.exp b/gdb/testsuite/gdb.trace/ftrace.exp
index f2d8002..7515108 100644
--- a/gdb/testsuite/gdb.trace/ftrace.exp
+++ b/gdb/testsuite/gdb.trace/ftrace.exp
@@ -84,7 +84,7 @@ proc test_fast_tracepoints {} {
gdb_test "print gdb_agent_gdb_trampoline_buffer_error" ".*" ""
- if { [istarget "x86_64-*-*"] || [istarget "i\[34567\]86-*-*"] } {
+ if { [istarget "x86_64-*-*"] || [istarget "i\[34567\]86-*-*"] || [is_aarch64_target] } {
gdb_test "ftrace set_point" "Fast tracepoint .*" \
"fast tracepoint at a long insn"
diff --git a/gdb/testsuite/gdb.trace/pendshr1.c b/gdb/testsuite/gdb.trace/pendshr1.c
index d3b5463..f08fb91 100644
--- a/gdb/testsuite/gdb.trace/pendshr1.c
+++ b/gdb/testsuite/gdb.trace/pendshr1.c
@@ -38,6 +38,8 @@ pendfunc (int x)
SYMBOL(set_point1) ":\n"
#if (defined __x86_64__ || defined __i386__)
" call " SYMBOL(pendfunc1) "\n"
+#elif (defined __aarch64__)
+ " nop\n"
#endif
);
}
diff --git a/gdb/testsuite/gdb.trace/pendshr2.c b/gdb/testsuite/gdb.trace/pendshr2.c
index b8a51a5..f7ec733 100644
--- a/gdb/testsuite/gdb.trace/pendshr2.c
+++ b/gdb/testsuite/gdb.trace/pendshr2.c
@@ -35,6 +35,8 @@ pendfunc2 (int x)
SYMBOL(set_point2) ":\n"
#if (defined __x86_64__ || defined __i386__)
" call " SYMBOL(foo) "\n"
+#elif (defined __aarch64__)
+ " nop\n"
#endif
);
}
diff --git a/gdb/testsuite/gdb.trace/range-stepping.c b/gdb/testsuite/gdb.trace/range-stepping.c
index 113f0e2..41cd745 100644
--- a/gdb/testsuite/gdb.trace/range-stepping.c
+++ b/gdb/testsuite/gdb.trace/range-stepping.c
@@ -26,6 +26,8 @@
tracepoint jump. */
#if (defined __x86_64__ || defined __i386__)
# define NOP " .byte 0xe9,0x00,0x00,0x00,0x00\n" /* jmp $+5 (5-byte nop) */
+#elif (defined __aarch64__)
+# define NOP " nop\n"
#else
# define NOP "" /* port me */
#endif
diff --git a/gdb/testsuite/gdb.trace/trace-break.c b/gdb/testsuite/gdb.trace/trace-break.c
index f381ec6..66bbe53 100644
--- a/gdb/testsuite/gdb.trace/trace-break.c
+++ b/gdb/testsuite/gdb.trace/trace-break.c
@@ -41,6 +41,8 @@ marker (void)
SYMBOL(set_point) ":\n"
#if (defined __x86_64__ || defined __i386__)
" call " SYMBOL(func) "\n"
+#elif (defined __aarch64__)
+ " nop\n"
#endif
);
@@ -48,6 +50,8 @@ marker (void)
SYMBOL(after_set_point) ":\n"
#if (defined __x86_64__ || defined __i386__)
" call " SYMBOL(func) "\n"
+#elif (defined __aarch64__)
+ " nop\n"
#endif
);
}
diff --git a/gdb/testsuite/gdb.trace/trace-condition.c b/gdb/testsuite/gdb.trace/trace-condition.c
index 2e965c9..d988d76 100644
--- a/gdb/testsuite/gdb.trace/trace-condition.c
+++ b/gdb/testsuite/gdb.trace/trace-condition.c
@@ -44,6 +44,8 @@ marker (int anarg)
SYMBOL (set_point) ":\n"
#if (defined __x86_64__ || defined __i386__)
" call " SYMBOL (func) "\n"
+#elif (defined __aarch64__)
+ " nop\n"
#endif
);
}
diff --git a/gdb/testsuite/gdb.trace/trace-condition.exp b/gdb/testsuite/gdb.trace/trace-condition.exp
index 8bfd34a..e5cc69e 100644
--- a/gdb/testsuite/gdb.trace/trace-condition.exp
+++ b/gdb/testsuite/gdb.trace/trace-condition.exp
@@ -25,6 +25,8 @@ if [is_amd64_regs_target] {
set pcreg "\$rip"
} elseif [is_x86_like_target] {
set pcreg "\$eip"
+} elseif [is_aarch64_target] {
+ set pcreg "\$pc"
} else {
set pcreg "\$pc"
}
diff --git a/gdb/testsuite/gdb.trace/trace-mt.c b/gdb/testsuite/gdb.trace/trace-mt.c
index 38aeff5..7ae0305 100644
--- a/gdb/testsuite/gdb.trace/trace-mt.c
+++ b/gdb/testsuite/gdb.trace/trace-mt.c
@@ -37,6 +37,8 @@ thread_function(void *arg)
SYMBOL(set_point1) ":\n"
#if (defined __x86_64__ || defined __i386__)
" call " SYMBOL(func) "\n"
+#elif (defined __aarch64__)
+ " nop\n"
#endif
);
}
--
2.4.6
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [PATCH 6/8] [testsuite][AArch64] Enable fast tracepoint tests
2015-09-14 11:32 ` [PATCH 6/8] [testsuite][AArch64] Enable fast tracepoint tests Pierre Langlois
@ 2015-09-15 10:18 ` Yao Qi
0 siblings, 0 replies; 37+ messages in thread
From: Yao Qi @ 2015-09-15 10:18 UTC (permalink / raw)
To: Pierre Langlois; +Cc: gdb-patches
Pierre Langlois <pierre.langlois@arm.com> writes:
> gdb/testsuite/ChangeLog:
>
> * gdb.trace/change-loc.h (func4): Add a nop instruction for
> __aarch64__.
We write ChangeLog for that in this way,
* gdb.trace/change-loc.h (func4) [__aarch64__]: Add a nop
instruction.
> * gdb.trace/pendshr1.c (pendfunc): Likewise.
> * gdb.trace/pendshr2.c (pendfunc2): Likewise.
> * gdb.trace/range-stepping.c: Likewise.
> * gdb.trace/trace-break.c: Likewise.
> * gdb.trace/trace-mt.c (thread_function): Likewise.
> * gdb.trace/ftrace.c (marker): Likewise.
> * gdb.trace/ftrace-condition.c (marker): Likewise.
The file name should be trace-condition.c.
> * gdb.trace/ftrace.exp: Enable ftrace test if is_aarch64_target.
> * gdb.trace/ftrace-condition.exp: Set pcreg to "\$pc" if
> is_aarch64_target.
Likewise.
Otherwise, patch is OK.
--
Yao (齐尧)
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 5/8] [GDBserver][AArch64] Implement target_emit_ops
2015-09-14 11:31 [PATCH 0/8] [AArch64] Support fast tracepoints Pierre Langlois
` (3 preceding siblings ...)
2015-09-14 11:32 ` [PATCH 6/8] [testsuite][AArch64] Enable fast tracepoint tests Pierre Langlois
@ 2015-09-14 11:32 ` Pierre Langlois
2015-09-14 11:33 ` [PATCH 4/8] [GDBserver][AArch64] Add support for fast tracepoints Pierre Langlois
` (4 subsequent siblings)
9 siblings, 0 replies; 37+ messages in thread
From: Pierre Langlois @ 2015-09-14 11:32 UTC (permalink / raw)
To: gdb-patches; +Cc: Pierre Langlois
This patch implements compiling agent expressions to native code for
AArch64. This allows us to compile conditions set on fast tracepoints.
The compiled function has the following prologue:
High *------------------------------------------------------*
| LR |
| FP | <- FP
| x1 (ULONGEST *value) |
| x0 (struct fast_tracepoint_ctx *ctx) |
Low *------------------------------------------------------*
We save the function's argument on the stack as well as the return
address and the frame pointer. We then set the current frame pointer to
point to the previous one.
The generated code for the expression will freely update the stack
pointer so we use the frame pointer to refer to `*value' and `*ctx'.
`*value' needs to be accessed in the epilogue of the function, in order
to set it to whatever is on top of the stack. `*ctx' needs to be passed
down to the `gdb_agent_get_reg' function with the `reg' operation.
gdb/gdbserver/ChangeLog:
* linux-aarch64-low-.c: Include ax.h and tracepoint.h.
(enum aarch64_opcodes) <RET>, <SUBS>, <AND>, <ORR>, <ORN>,
<EOR>, <LSLV>, <LSRV>, <ASRV>, <SBFM>, <UBFM>, <CSINC>, <MUL>,
<NOP>: New.
(enum aarch64_condition_codes): New enum.
(w0): New static global.
(fp): Likewise.
(lr): Likewise.
(struct aarch64_memory_operand) <type>: New
MEMORY_OPERAND_POSTINDEX type.
(postindex_memory_operand): New helper function.
(emit_ret): New function.
(emit_load_store_pair): New function, factored out of emit_stp
with support for MEMORY_OPERAND_POSTINDEX.
(emit_stp): Rewrite using emit_load_store_pair.
(emit_ldp): New function.
(emit_load_store): Likewise.
(emit_ldr): Mention post-index instruction in comment.
(emit_ldrh): New function.
(emit_ldrb): New function.
(emit_ldrsw): Mention post-index instruction in comment.
(emit_str): Likewise.
(emit_subs): New function.
(emit_cmp): Likewise.
(emit_and): Likewise.
(emit_orr): Likewise.
(emit_orn): Likewise.
(emit_eor): Likewise.
(emit_mvn): Likewise.
(emit_lslv): Likewise.
(emit_lsrv): Likewise.
(emit_asrv): Likewise.
(emit_mul): Likewise.
(emit_sbfm): Likewise.
(emit_sbfx): Likewise.
(emit_ubfm): Likewise.
(emit_ubfx): Likewise.
(emit_csinc): Likewise.
(emit_cset): Likewise.
(emit_nop): Likewise.
(emit_ops_insns): New helper function.
(emit_pop): Likewise.
(emit_push): Likewise.
(aarch64_emit_prologue): New function.
(aarch64_emit_epilogue): Likewise.
(aarch64_emit_add): Likewise.
(aarch64_emit_sub): Likewise.
(aarch64_emit_mul): Likewise.
(aarch64_emit_lsh): Likewise.
(aarch64_emit_rsh_signed): Likewise.
(aarch64_emit_rsh_unsigned): Likewise.
(aarch64_emit_ext): Likewise.
(aarch64_emit_log_not): Likewise.
(aarch64_emit_bit_and): Likewise.
(aarch64_emit_bit_or): Likewise.
(aarch64_emit_bit_xor): Likewise.
(aarch64_emit_bit_not): Likewise.
(aarch64_emit_equal): Likewise.
(aarch64_emit_less_signed): Likewise.
(aarch64_emit_less_unsigned): Likewise.
(aarch64_emit_ref): Likewise.
(aarch64_emit_if_goto): Likewise.
(aarch64_emit_goto): Likewise.
(aarch64_write_goto_address): Likewise.
(aarch64_emit_const): Likewise.
(aarch64_emit_call): Likewise.
(aarch64_emit_reg): Likewise.
(aarch64_emit_pop): Likewise.
(aarch64_emit_stack_flush): Likewise.
(aarch64_emit_zero_ext): Likewise.
(aarch64_emit_swap): Likewise.
(aarch64_emit_stack_adjust): Likewise.
(aarch64_emit_int_call_1): Likewise.
(aarch64_emit_void_call_2): Likewise.
(aarch64_emit_eq_goto): Likewise.
(aarch64_emit_ne_goto): Likewise.
(aarch64_emit_lt_goto): Likewise.
(aarch64_emit_le_goto): Likewise.
(aarch64_emit_gt_goto): Likewise.
(aarch64_emit_ge_got): Likewise.
(aarch64_emit_ops_impl): New static global variable.
(aarch64_emit_ops): New target function, return
&aarch64_emit_ops_impl.
(struct linux_target_ops): Install it.
---
gdb/gdbserver/linux-aarch64-low.c | 1227 ++++++++++++++++++++++++++++++++++++-
1 file changed, 1213 insertions(+), 14 deletions(-)
diff --git a/gdb/gdbserver/linux-aarch64-low.c b/gdb/gdbserver/linux-aarch64-low.c
index bb06558..8eeddc8 100644
--- a/gdb/gdbserver/linux-aarch64-low.c
+++ b/gdb/gdbserver/linux-aarch64-low.c
@@ -26,6 +26,8 @@
#include "arch/aarch64-insn.h"
#include "linux-aarch32-low.h"
#include "elf/common.h"
+#include "ax.h"
+#include "tracepoint.h"
#include <signal.h>
#include <sys/user.h>
@@ -659,6 +661,8 @@ enum aarch64_opcodes
TBNZ = 0x37000000 | B,
/* BLR 1101 0110 0011 1111 0000 00rr rrr0 0000 */
BLR = 0xd63f0000,
+ /* RET 1101 0110 0101 1111 0000 00rr rrr0 0000 */
+ RET = 0xd65f0000,
/* STP s010 100o o0ii iiii irrr rrrr rrrr rrrr */
/* LDP s010 100o o1ii iiii irrr rrrr rrrr rrrr */
/* STP (SIMD&VFP) ss10 110o o0ii iiii irrr rrrr rrrr rrrr */
@@ -688,6 +692,29 @@ enum aarch64_opcodes
/* SUBS s11o ooo1 xxxx xxxx xxxx xxxx xxxx xxxx */
ADD = 0x01000000,
SUB = 0x40000000 | ADD,
+ SUBS = 0x20000000 | SUB,
+ /* AND s000 1010 xx0x xxxx xxxx xxxx xxxx xxxx */
+ /* ORR s010 1010 xx0x xxxx xxxx xxxx xxxx xxxx */
+ /* ORN s010 1010 xx1x xxxx xxxx xxxx xxxx xxxx */
+ /* EOR s100 1010 xx0x xxxx xxxx xxxx xxxx xxxx */
+ AND = 0x0a000000,
+ ORR = 0x20000000 | AND,
+ ORN = 0x00200000 | ORR,
+ EOR = 0x40000000 | AND,
+ /* LSLV s001 1010 110r rrrr 0010 00rr rrrr rrrr */
+ /* LSRV s001 1010 110r rrrr 0010 01rr rrrr rrrr */
+ /* ASRV s001 1010 110r rrrr 0010 10rr rrrr rrrr */
+ LSLV = 0x1ac02000,
+ LSRV = 0x00000400 | LSLV,
+ ASRV = 0x00000800 | LSLV,
+ /* SBFM s001 0011 0nii iiii iiii iirr rrrr rrrr */
+ SBFM = 0x13000000,
+ /* UBFM s101 0011 0nii iiii iiii iirr rrrr rrrr */
+ UBFM = 0x40000000 | SBFM,
+ /* CSINC s001 1010 100r rrrr cccc 01rr rrrr rrrr */
+ CSINC = 0x9a800400,
+ /* MUL s001 1011 000r rrrr 0111 11rr rrrr rrrr */
+ MUL = 0x1b007c00,
/* MSR (register) 1101 0101 0001 oooo oooo oooo ooor rrrr */
/* MRS 1101 0101 0011 oooo oooo oooo ooor rrrr */
MSR = 0xd5100000,
@@ -696,6 +723,20 @@ enum aarch64_opcodes
HINT = 0xd503201f,
SEVL = (5 << 5) | HINT,
WFE = (2 << 5) | HINT,
+ NOP = (0 << 5) | HINT,
+};
+
+/* List of condition codes that we need. */
+
+enum aarch64_condition_codes
+{
+ EQ = 0x0,
+ NE = 0x1,
+ LO = 0x3,
+ GE = 0xa,
+ LT = 0xb,
+ GT = 0xc,
+ LE = 0xd,
};
/* Representation of a general purpose register of the form xN or wN.
@@ -738,12 +779,15 @@ static struct aarch64_register x3 = { 3, 1 };
static struct aarch64_register x4 = { 4, 1 };
/* General purpose scratch registers (32 bit). */
+static struct aarch64_register w0 = { 0, 0 };
static struct aarch64_register w2 = { 2, 0 };
/* Intra-procedure scratch registers. */
static struct aarch64_register ip0 = { 16, 1 };
/* Special purpose registers. */
+static struct aarch64_register fp = { 29, 1 };
+static struct aarch64_register lr = { 30, 1 };
static struct aarch64_register sp = { 31, 1 };
static struct aarch64_register xzr = { 31, 1 };
@@ -796,8 +840,9 @@ immediate_operand (uint32_t imm)
The types correspond to the following variants:
- MEMORY_OPERAND_OFFSET: LDR rt, [rn, #offset]
- MEMORY_OPERAND_PREINDEX: LDR rt, [rn, #index]! */
+ MEMORY_OPERAND_OFFSET: LDR rt, [rn, #offset]
+ MEMORY_OPERAND_PREINDEX: LDR rt, [rn, #index]!
+ MEMORY_OPERAND_POSTINDEX: LDR rt, [rn], #index */
struct aarch64_memory_operand
{
@@ -806,6 +851,7 @@ struct aarch64_memory_operand
{
MEMORY_OPERAND_OFFSET,
MEMORY_OPERAND_PREINDEX,
+ MEMORY_OPERAND_POSTINDEX,
} type;
/* Index from the base register. */
int32_t index;
@@ -833,6 +879,17 @@ preindex_memory_operand (int32_t index)
return (struct aarch64_memory_operand) { MEMORY_OPERAND_PREINDEX, index };
}
+/* Helper function to create a post-index memory operand.
+
+ For example:
+ p += emit_ldr (p, x0, sp, postindex_memory_operand (16)); */
+
+static struct aarch64_memory_operand
+postindex_memory_operand (int32_t index)
+{
+ return (struct aarch64_memory_operand) { MEMORY_OPERAND_POSTINDEX, index };
+}
+
/* System control registers. These special registers can be written and
read with the MRS and MSR instructions.
@@ -965,20 +1022,24 @@ emit_blr (uint32_t *buf, struct aarch64_register rn)
return emit_insn (buf, BLR | ENCODE (rn.num, 5, 5));
}
-/* Write a STP instruction into *BUF.
+/* Write a RET instruction into *BUF.
- STP rt, rt2, [rn, #offset]
- STP rt, rt2, [rn, #index]!
+ RET xn
- RT and RT2 are the registers to store.
- RN is the base address register.
- OFFSET is the immediate to add to the base address. It is limited to a
- -512 .. 504 range (7 bits << 3). */
+ RN is the register to branch to. */
static int
-emit_stp (uint32_t *buf, struct aarch64_register rt,
- struct aarch64_register rt2, struct aarch64_register rn,
- struct aarch64_memory_operand operand)
+emit_ret (uint32_t *buf, struct aarch64_register rn)
+{
+ return emit_insn (buf, RET | ENCODE (rn.num, 5, 5));
+}
+
+static int
+emit_load_store_pair (uint32_t *buf, enum aarch64_opcodes opcode,
+ struct aarch64_register rt,
+ struct aarch64_register rt2,
+ struct aarch64_register rn,
+ struct aarch64_memory_operand operand)
{
uint32_t opc;
uint32_t pre_index;
@@ -997,6 +1058,12 @@ emit_stp (uint32_t *buf, struct aarch64_register rt,
write_back = ENCODE (0, 1, 23);
break;
}
+ case MEMORY_OPERAND_POSTINDEX:
+ {
+ pre_index = ENCODE (0, 1, 24);
+ write_back = ENCODE (1, 1, 23);
+ break;
+ }
case MEMORY_OPERAND_PREINDEX:
{
pre_index = ENCODE (1, 1, 24);
@@ -1007,11 +1074,49 @@ emit_stp (uint32_t *buf, struct aarch64_register rt,
return 0;
}
- return emit_insn (buf, STP | opc | pre_index | write_back
+ return emit_insn (buf, opcode | opc | pre_index | write_back
| ENCODE (operand.index >> 3, 7, 15) | ENCODE (rt2.num, 5, 10)
| ENCODE (rn.num, 5, 5) | ENCODE (rt.num, 5, 0));
}
+/* Write a STP instruction into *BUF.
+
+ STP rt, rt2, [rn, #offset]
+ STP rt, rt2, [rn, #index]!
+ STP rt, rt2, [rn], #index
+
+ RT and RT2 are the registers to store.
+ RN is the base address register.
+ OFFSET is the immediate to add to the base address. It is limited to a
+ -512 .. 504 range (7 bits << 3). */
+
+static int
+emit_stp (uint32_t *buf, struct aarch64_register rt,
+ struct aarch64_register rt2, struct aarch64_register rn,
+ struct aarch64_memory_operand operand)
+{
+ return emit_load_store_pair (buf, STP, rt, rt2, rn, operand);
+}
+
+/* Write a LDP instruction into *BUF.
+
+ LDP rt, rt2, [rn, #offset]
+ LDP rt, rt2, [rn, #index]!
+ LDP rt, rt2, [rn], #index
+
+ RT and RT2 are the registers to store.
+ RN is the base address register.
+ OFFSET is the immediate to add to the base address. It is limited to a
+ -512 .. 504 range (7 bits << 3). */
+
+static int
+emit_ldp (uint32_t *buf, struct aarch64_register rt,
+ struct aarch64_register rt2, struct aarch64_register rn,
+ struct aarch64_memory_operand operand)
+{
+ return emit_load_store_pair (buf, LDP, rt, rt2, rn, operand);
+}
+
/* Write a LDP (SIMD&VFP) instruction using Q registers into *BUF.
LDP qt, qt2, [rn, #offset]
@@ -1073,6 +1178,16 @@ emit_load_store (uint32_t *buf, uint32_t size, enum aarch64_opcodes opcode,
| ENCODE (operand.index >> 3, 12, 10)
| ENCODE (rn.num, 5, 5) | ENCODE (rt.num, 5, 0));
}
+ case MEMORY_OPERAND_POSTINDEX:
+ {
+ uint32_t post_index = ENCODE (1, 2, 10);
+
+ op = ENCODE (0, 1, 24);
+
+ return emit_insn (buf, opcode | ENCODE (size, 2, 30) | op
+ | post_index | ENCODE (operand.index, 9, 12)
+ | ENCODE (rn.num, 5, 5) | ENCODE (rt.num, 5, 0));
+ }
case MEMORY_OPERAND_PREINDEX:
{
uint32_t pre_index = ENCODE (3, 2, 10);
@@ -1092,6 +1207,7 @@ emit_load_store (uint32_t *buf, uint32_t size, enum aarch64_opcodes opcode,
LDR rt, [rn, #offset]
LDR rt, [rn, #index]!
+ LDR rt, [rn], #index
RT is the register to store.
RN is the base address register.
@@ -1105,10 +1221,49 @@ emit_ldr (uint32_t *buf, struct aarch64_register rt,
return emit_load_store (buf, rt.is64 ? 3 : 2, LDR, rt, rn, operand);
}
+/* Write a LDRH instruction into *BUF.
+
+ LDRH wt, [xn, #offset]
+ LDRH wt, [xn, #index]!
+ LDRH wt, [xn], #index
+
+ RT is the register to store.
+ RN is the base address register.
+ OFFSET is the immediate to add to the base address. It is limited to
+ 0 .. 32760 range (12 bits << 3). */
+
+static int
+emit_ldrh (uint32_t *buf, struct aarch64_register rt,
+ struct aarch64_register rn,
+ struct aarch64_memory_operand operand)
+{
+ return emit_load_store (buf, 1, LDR, rt, rn, operand);
+}
+
+/* Write a LDRB instruction into *BUF.
+
+ LDRB wt, [xn, #offset]
+ LDRB wt, [xn, #index]!
+ LDRB wt, [xn], #index
+
+ RT is the register to store.
+ RN is the base address register.
+ OFFSET is the immediate to add to the base address. It is limited to
+ 0 .. 32760 range (12 bits << 3). */
+
+static int
+emit_ldrb (uint32_t *buf, struct aarch64_register rt,
+ struct aarch64_register rn,
+ struct aarch64_memory_operand operand)
+{
+ return emit_load_store (buf, 0, LDR, rt, rn, operand);
+}
+
/* Write a LDRSW instruction into *BUF. The register size is 64-bit.
LDRSW xt, [rn, #offset]
LDRSW xt, [rn, #index]!
+ LDRSW xt, [rn], #index
RT is the register to store.
RN is the base address register.
@@ -1127,6 +1282,7 @@ emit_ldrsw (uint32_t *buf, struct aarch64_register rt,
STR rt, [rn, #offset]
STR rt, [rn, #index]!
+ STR rt, [rn], #index
RT is the register to store.
RN is the base address register.
@@ -1369,6 +1525,165 @@ emit_mov_addr (uint32_t *buf, struct aarch64_register rd, CORE_ADDR addr)
return p - buf;
}
+/* Write a SUBS instruction into *BUF.
+
+ SUBS rd, rn, rm
+
+ This instruction update the condition flags.
+
+ RD is the destination register.
+ RN and RM are the source registers. */
+
+static int
+emit_subs (uint32_t *buf, struct aarch64_register rd,
+ struct aarch64_register rn, struct aarch64_operand operand)
+{
+ return emit_data_processing (buf, SUBS, rd, rn, operand);
+}
+
+/* Write a CMP instruction into *BUF.
+
+ CMP rn, rm
+
+ This instruction is an alias of SUBS xzr, rn, rm.
+
+ RN and RM are the registers to compare. */
+
+static int
+emit_cmp (uint32_t *buf, struct aarch64_register rn,
+ struct aarch64_operand operand)
+{
+ return emit_subs (buf, xzr, rn, operand);
+}
+
+/* Write a AND instruction into *BUF.
+
+ AND rd, rn, rm
+
+ RD is the destination register.
+ RN and RM are the source registers. */
+
+static int
+emit_and (uint32_t *buf, struct aarch64_register rd,
+ struct aarch64_register rn, struct aarch64_register rm)
+{
+ return emit_data_processing_reg (buf, AND, rd, rn, rm);
+}
+
+/* Write a ORR instruction into *BUF.
+
+ ORR rd, rn, rm
+
+ RD is the destination register.
+ RN and RM are the source registers. */
+
+static int
+emit_orr (uint32_t *buf, struct aarch64_register rd,
+ struct aarch64_register rn, struct aarch64_register rm)
+{
+ return emit_data_processing_reg (buf, ORR, rd, rn, rm);
+}
+
+/* Write a ORN instruction into *BUF.
+
+ ORN rd, rn, rm
+
+ RD is the destination register.
+ RN and RM are the source registers. */
+
+static int
+emit_orn (uint32_t *buf, struct aarch64_register rd,
+ struct aarch64_register rn, struct aarch64_register rm)
+{
+ return emit_data_processing_reg (buf, ORN, rd, rn, rm);
+}
+
+/* Write a EOR instruction into *BUF.
+
+ EOR rd, rn, rm
+
+ RD is the destination register.
+ RN and RM are the source registers. */
+
+static int
+emit_eor (uint32_t *buf, struct aarch64_register rd,
+ struct aarch64_register rn, struct aarch64_register rm)
+{
+ return emit_data_processing_reg (buf, EOR, rd, rn, rm);
+}
+
+/* Write a MVN instruction into *BUF.
+
+ MVN rd, rm
+
+ This is an alias for ORN rd, xzr, rm.
+
+ RD is the destination register.
+ RM is the source register. */
+
+static int
+emit_mvn (uint32_t *buf, struct aarch64_register rd,
+ struct aarch64_register rm)
+{
+ return emit_orn (buf, rd, xzr, rm);
+}
+
+/* Write a LSLV instruction into *BUF.
+
+ LSLV rd, rn, rm
+
+ RD is the destination register.
+ RN and RM are the source registers. */
+
+static int
+emit_lslv (uint32_t *buf, struct aarch64_register rd,
+ struct aarch64_register rn, struct aarch64_register rm)
+{
+ return emit_data_processing_reg (buf, LSLV, rd, rn, rm);
+}
+
+/* Write a LSRV instruction into *BUF.
+
+ LSRV rd, rn, rm
+
+ RD is the destination register.
+ RN and RM are the source registers. */
+
+static int
+emit_lsrv (uint32_t *buf, struct aarch64_register rd,
+ struct aarch64_register rn, struct aarch64_register rm)
+{
+ return emit_data_processing_reg (buf, LSRV, rd, rn, rm);
+}
+
+/* Write a ASRV instruction into *BUF.
+
+ ASRV rd, rn, rm
+
+ RD is the destination register.
+ RN and RM are the source registers. */
+
+static int
+emit_asrv (uint32_t *buf, struct aarch64_register rd,
+ struct aarch64_register rn, struct aarch64_register rm)
+{
+ return emit_data_processing_reg (buf, ASRV, rd, rn, rm);
+}
+
+/* Write a MUL instruction into *BUF.
+
+ MUL rd, rn, rm
+
+ RD is the destination register.
+ RN and RM are the source registers. */
+
+static int
+emit_mul (uint32_t *buf, struct aarch64_register rd,
+ struct aarch64_register rn, struct aarch64_register rm)
+{
+ return emit_data_processing_reg (buf, MUL, rd, rn, rm);
+}
+
/* Write a MRS instruction into *BUF. The register size is 64-bit.
MRS xt, system_reg
@@ -1419,6 +1734,150 @@ emit_wfe (uint32_t *buf)
return emit_insn (buf, WFE);
}
+/* Write a SBFM instruction into *BUF.
+
+ SBFM rd, rn, #immr, #imms
+
+ This instruction moves the bits from #immr to #imms into the
+ destination, sign extending the result.
+
+ RD is the destination register.
+ RN is the source register.
+ IMMR is the bit number to start at (least significant bit).
+ IMMS is the bit number to stop at (most significant bit). */
+
+static int
+emit_sbfm (uint32_t *buf, struct aarch64_register rd,
+ struct aarch64_register rn, uint32_t immr, uint32_t imms)
+{
+ uint32_t size = ENCODE (rd.is64, 1, 31);
+ uint32_t n = ENCODE (rd.is64, 1, 22);
+
+ return emit_insn (buf, SBFM | size | n | ENCODE (immr, 6, 16)
+ | ENCODE (imms, 6, 10) | ENCODE (rn.num, 5, 5)
+ | ENCODE (rd.num, 5, 0));
+}
+
+/* Write a SBFX instruction into *BUF.
+
+ SBFX rd, rn, #lsb, #width
+
+ This instruction moves #width bits from #lsb into the destination, sign
+ extending the result. This is an alias for:
+
+ SBFM rd, rn, #lsb, #(lsb + width - 1)
+
+ RD is the destination register.
+ RN is the source register.
+ LSB is the bit number to start at (least significant bit).
+ WIDTH is the number of bits to move. */
+
+static int
+emit_sbfx (uint32_t *buf, struct aarch64_register rd,
+ struct aarch64_register rn, uint32_t lsb, uint32_t width)
+{
+ return emit_sbfm (buf, rd, rn, lsb, lsb + width - 1);
+}
+
+/* Write a UBFM instruction into *BUF.
+
+ UBFM rd, rn, #immr, #imms
+
+ This instruction moves the bits from #immr to #imms into the
+ destination, extending the result with zeros.
+
+ RD is the destination register.
+ RN is the source register.
+ IMMR is the bit number to start at (least significant bit).
+ IMMS is the bit number to stop at (most significant bit). */
+
+static int
+emit_ubfm (uint32_t *buf, struct aarch64_register rd,
+ struct aarch64_register rn, uint32_t immr, uint32_t imms)
+{
+ uint32_t size = ENCODE (rd.is64, 1, 31);
+ uint32_t n = ENCODE (rd.is64, 1, 22);
+
+ return emit_insn (buf, UBFM | size | n | ENCODE (immr, 6, 16)
+ | ENCODE (imms, 6, 10) | ENCODE (rn.num, 5, 5)
+ | ENCODE (rd.num, 5, 0));
+}
+
+/* Write a UBFX instruction into *BUF.
+
+ UBFX rd, rn, #lsb, #width
+
+ This instruction moves #width bits from #lsb into the destination,
+ extending the result with zeros. This is an alias for:
+
+ UBFM rd, rn, #lsb, #(lsb + width - 1)
+
+ RD is the destination register.
+ RN is the source register.
+ LSB is the bit number to start at (least significant bit).
+ WIDTH is the number of bits to move. */
+
+static int
+emit_ubfx (uint32_t *buf, struct aarch64_register rd,
+ struct aarch64_register rn, uint32_t lsb, uint32_t width)
+{
+ return emit_ubfm (buf, rd, rn, lsb, lsb + width - 1);
+}
+
+/* Write a CSINC instruction into *BUF.
+
+ CSINC rd, rn, rm, cond
+
+ This instruction conditionally increments rn or rm and places the result
+ in rd. rn is chosen is the condition is true.
+
+ RD is the destination register.
+ RN and RM are the source registers.
+ COND is the encoded condition. */
+
+static int
+emit_csinc (uint32_t *buf, struct aarch64_register rd,
+ struct aarch64_register rn, struct aarch64_register rm,
+ unsigned cond)
+{
+ uint32_t size = ENCODE (rd.is64, 1, 31);
+
+ return emit_insn (buf, CSINC | size | ENCODE (rm.num, 5, 16)
+ | ENCODE (cond, 4, 12) | ENCODE (rn.num, 5, 5)
+ | ENCODE (rd.num, 5, 0));
+}
+
+/* Write a CSET instruction into *BUF.
+
+ CSET rd, cond
+
+ This instruction conditionally write 1 or 0 in the destination register.
+ 1 is written if the condition is true. This is an alias for:
+
+ CSINC rd, xzr, xzr, !cond
+
+ Note that the condition needs to be inverted.
+
+ RD is the destination register.
+ RN and RM are the source registers.
+ COND is the encoded condition. */
+
+static int
+emit_cset (uint32_t *buf, struct aarch64_register rd, unsigned cond)
+{
+ /* The least significant bit of the condition needs toggling in order to
+ invert it. */
+ return emit_csinc (buf, rd, xzr, xzr, cond ^ 0x1);
+}
+
+/* Write a NOP instruction into *BUF. */
+
+static int
+emit_nop (uint32_t *buf)
+{
+ return emit_insn (buf, NOP);
+}
+
/* Write LEN instructions from BUF into the inferior memory at *TO.
Note instructions are always little endian on AArch64, unlike data. */
@@ -2003,6 +2462,746 @@ aarch64_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint,
return 0;
}
+/* Helper function writing LEN instructions from START into
+ current_insn_ptr. */
+
+static void
+emit_ops_insns (const uint32_t *start, int len)
+{
+ CORE_ADDR buildaddr = current_insn_ptr;
+
+ if (debug_threads)
+ debug_printf ("Adding %d instrucions at %s\n",
+ len, paddress (buildaddr));
+
+ append_insns (&buildaddr, len, start);
+ current_insn_ptr = buildaddr;
+}
+
+/* Pop a register from the stack. */
+
+static int
+emit_pop (uint32_t *buf, struct aarch64_register rt)
+{
+ return emit_ldr (buf, rt, sp, postindex_memory_operand (1 * 16));
+}
+
+/* Push a register on the stack. */
+
+static int
+emit_push (uint32_t *buf, struct aarch64_register rt)
+{
+ return emit_str (buf, rt, sp, preindex_memory_operand (-1 * 16));
+}
+
+/* Implementation of emit_ops method "emit_prologue". */
+
+static void
+aarch64_emit_prologue (void)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ /* This function emit a prologue for the following function prototype:
+
+ enum eval_result_type f (struct tracepoint_hit_ctx *ctx,
+ ULONGEST *value);
+
+ struct tracepoint_hit_ctx is a base struct, it will be of type
+ struct fast_tracepoint_ctx here. The second argument is the result of
+ evaluating the expression, which will be set to whatever is on top of
+ the stack at the end.
+
+ The stack set up by the prologue is as such:
+
+ High *------------------------------------------------------*
+ | LR |
+ | FP | <- FP
+ | x1 (ULONGEST *value) |
+ | x0 (struct fast_tracepoint_ctx *ctx) |
+ Low *------------------------------------------------------*
+
+ As we are implementing a stack machine, each opcode can expand the
+ stack so we never know how far we are from the data saved by this
+ prologue. In order to be able refer to value and ctx later, we save
+ the current stack pointer in the frame pointer. This way, it is not
+ clobbered when calling C functions.
+
+ Finally, throughtout every operation, we are using register x0 as the
+ top of the stack, and x1 as a scratch register. */
+
+ p += emit_stp (p, x0, x1, sp, preindex_memory_operand (-2 * 16));
+ p += emit_str (p, lr, sp, offset_memory_operand (3 * 8));
+ p += emit_str (p, fp, sp, offset_memory_operand (2 * 8));
+
+ p += emit_add (p, fp, sp, immediate_operand (2 * 8));
+
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_epilogue". */
+
+static void
+aarch64_emit_epilogue (void)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ /* Store the result of the expression (x0) in *value. */
+ p += emit_sub (p, x1, fp, immediate_operand (1 * 8));
+ p += emit_ldr (p, x1, x1, offset_memory_operand (0));
+ p += emit_str (p, x0, x1, offset_memory_operand (0));
+
+ /* Restore the previous state. */
+ p += emit_add (p, sp, fp, immediate_operand (2 * 8));
+ p += emit_ldp (p, fp, lr, fp, offset_memory_operand (0));
+
+ /* Return expr_eval_no_error. */
+ p += emit_mov (p, x0, immediate_operand (expr_eval_no_error));
+ p += emit_ret (p, lr);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_add". */
+
+static void
+aarch64_emit_add (void)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_pop (p, x1);
+ p += emit_add (p, x0, x0, register_operand (x1));
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_sub". */
+
+static void
+aarch64_emit_sub (void)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_pop (p, x1);
+ p += emit_sub (p, x0, x0, register_operand (x1));
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_mul". */
+
+static void
+aarch64_emit_mul (void)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_pop (p, x1);
+ p += emit_mul (p, x0, x1, x0);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_lsh". */
+
+static void
+aarch64_emit_lsh (void)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_pop (p, x1);
+ p += emit_lslv (p, x0, x1, x0);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_rsh_signed". */
+
+static void
+aarch64_emit_rsh_signed (void)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_pop (p, x1);
+ p += emit_asrv (p, x0, x1, x0);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_rsh_unsigned". */
+
+static void
+aarch64_emit_rsh_unsigned (void)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_pop (p, x1);
+ p += emit_lsrv (p, x0, x1, x0);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_ext". */
+
+static void
+aarch64_emit_ext (int arg)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_sbfx (p, x0, x0, 0, arg);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_log_not". */
+
+static void
+aarch64_emit_log_not (void)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ /* If the top of the stack is 0, replace it with 1. Else replace it with
+ 0. */
+
+ p += emit_cmp (p, x0, immediate_operand (0));
+ p += emit_cset (p, x0, EQ);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_bit_and". */
+
+static void
+aarch64_emit_bit_and (void)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_pop (p, x1);
+ p += emit_and (p, x0, x0, x1);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_bit_or". */
+
+static void
+aarch64_emit_bit_or (void)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_pop (p, x1);
+ p += emit_orr (p, x0, x0, x1);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_bit_xor". */
+
+static void
+aarch64_emit_bit_xor (void)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_pop (p, x1);
+ p += emit_eor (p, x0, x0, x1);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_bit_not". */
+
+static void
+aarch64_emit_bit_not (void)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_mvn (p, x0, x0);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_equal". */
+
+static void
+aarch64_emit_equal (void)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_pop (p, x1);
+ p += emit_cmp (p, x0, register_operand (x1));
+ p += emit_cset (p, x0, EQ);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_less_signed". */
+
+static void
+aarch64_emit_less_signed (void)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_pop (p, x1);
+ p += emit_cmp (p, x1, register_operand (x0));
+ p += emit_cset (p, x0, LT);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_less_unsigned". */
+
+static void
+aarch64_emit_less_unsigned (void)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_pop (p, x1);
+ p += emit_cmp (p, x1, register_operand (x0));
+ p += emit_cset (p, x0, LO);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_ref". */
+
+static void
+aarch64_emit_ref (int size)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ switch (size)
+ {
+ case 1:
+ p += emit_ldrb (p, w0, x0, offset_memory_operand (0));
+ break;
+ case 2:
+ p += emit_ldrh (p, w0, x0, offset_memory_operand (0));
+ break;
+ case 4:
+ p += emit_ldr (p, w0, x0, offset_memory_operand (0));
+ break;
+ case 8:
+ p += emit_ldr (p, x0, x0, offset_memory_operand (0));
+ break;
+ default:
+ /* Unknown size, bail on compilation. */
+ emit_error = 1;
+ break;
+ }
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_if_goto". */
+
+static void
+aarch64_emit_if_goto (int *offset_p, int *size_p)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ /* The Z flag is set or cleared here. */
+ p += emit_cmp (p, x0, immediate_operand (0));
+ /* This instruction must not change the Z flag. */
+ p += emit_pop (p, x0);
+ /* Branch over the next instruction if x0 == 0. */
+ p += emit_bcond (p, EQ, 8);
+
+ /* The NOP instruction will be patched with an unconditional branch. */
+ if (offset_p)
+ *offset_p = (p - buf) * 4;
+ if (size_p)
+ *size_p = 4;
+ p += emit_nop (p);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_goto". */
+
+static void
+aarch64_emit_goto (int *offset_p, int *size_p)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ /* The NOP instruction will be patched with an unconditional branch. */
+ if (offset_p)
+ *offset_p = 0;
+ if (size_p)
+ *size_p = 4;
+ p += emit_nop (p);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "write_goto_address". */
+
+void
+aarch64_write_goto_address (CORE_ADDR from, CORE_ADDR to, int size)
+{
+ uint32_t insn;
+
+ emit_b (&insn, 0, to - from);
+ append_insns (&from, 1, &insn);
+}
+
+/* Implementation of emit_ops method "emit_const". */
+
+static void
+aarch64_emit_const (LONGEST num)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_mov_addr (p, x0, num);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_call". */
+
+static void
+aarch64_emit_call (CORE_ADDR fn)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_mov_addr (p, ip0, fn);
+ p += emit_blr (p, ip0);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_reg". */
+
+static void
+aarch64_emit_reg (int reg)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ /* Set x0 to struct fast_tracepoint_ctx *ctx. */
+ p += emit_sub (p, x0, fp, immediate_operand (2 * 8));
+ p += emit_ldr (p, x0, x0, offset_memory_operand (0));
+ p += emit_mov (p, x1, immediate_operand (reg));
+
+ emit_ops_insns (buf, p - buf);
+
+ aarch64_emit_call (get_reg_func_addr ());
+}
+
+/* Implementation of emit_ops method "emit_pop". */
+
+static void
+aarch64_emit_pop (void)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_pop (p, x0);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_stack_flush". */
+
+static void
+aarch64_emit_stack_flush (void)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_push (p, x0);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_zero_ext". */
+
+static void
+aarch64_emit_zero_ext (int arg)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_ubfx (p, x0, x0, 0, arg);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_swap". */
+
+static void
+aarch64_emit_swap (void)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_ldr (p, x1, sp, offset_memory_operand (0 * 16));
+ p += emit_str (p, x0, sp, offset_memory_operand (0 * 16));
+ p += emit_mov (p, x0, register_operand (x1));
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_stack_adjust". */
+
+static void
+aarch64_emit_stack_adjust (int n)
+{
+ /* This is not needed with our design. */
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_add (p, sp, sp, immediate_operand (n * 16));
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_int_call_1". */
+
+static void
+aarch64_emit_int_call_1 (CORE_ADDR fn, int arg1)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_mov (p, x0, immediate_operand (arg1));
+
+ emit_ops_insns (buf, p - buf);
+
+ aarch64_emit_call (fn);
+}
+
+/* Implementation of emit_ops method "emit_void_call_2". */
+
+static void
+aarch64_emit_void_call_2 (CORE_ADDR fn, int arg1)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ /* Push x0 on the stack. */
+ aarch64_emit_stack_flush ();
+
+ /* Setup arguments for the function call:
+
+ x0: arg1
+ x1: top of the stack
+
+ MOV x1, x0
+ MOV x0, #arg1 */
+
+ p += emit_mov (p, x1, register_operand (x0));
+ p += emit_mov (p, x0, immediate_operand (arg1));
+
+ emit_ops_insns (buf, p - buf);
+
+ aarch64_emit_call (fn);
+
+ /* Restore x0. */
+ aarch64_emit_pop ();
+}
+
+/* Implementation of emit_ops method "emit_eq_goto". */
+
+static void
+aarch64_emit_eq_goto (int *offset_p, int *size_p)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_pop (p, x1);
+ p += emit_cmp (p, x1, register_operand (x0));
+ /* Branch over the next instruction if x0 != x1. */
+ p += emit_bcond (p, NE, 8);
+ /* The NOP instruction will be patched with an unconditional branch. */
+ if (offset_p)
+ *offset_p = (p - buf) * 4;
+ if (size_p)
+ *size_p = 4;
+ p += emit_nop (p);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_ne_goto". */
+
+static void
+aarch64_emit_ne_goto (int *offset_p, int *size_p)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_pop (p, x1);
+ p += emit_cmp (p, x1, register_operand (x0));
+ /* Branch over the next instruction if x0 == x1. */
+ p += emit_bcond (p, EQ, 8);
+ /* The NOP instruction will be patched with an unconditional branch. */
+ if (offset_p)
+ *offset_p = (p - buf) * 4;
+ if (size_p)
+ *size_p = 4;
+ p += emit_nop (p);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_lt_goto". */
+
+static void
+aarch64_emit_lt_goto (int *offset_p, int *size_p)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_pop (p, x1);
+ p += emit_cmp (p, x1, register_operand (x0));
+ /* Branch over the next instruction if x0 >= x1. */
+ p += emit_bcond (p, GE, 8);
+ /* The NOP instruction will be patched with an unconditional branch. */
+ if (offset_p)
+ *offset_p = (p - buf) * 4;
+ if (size_p)
+ *size_p = 4;
+ p += emit_nop (p);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_le_goto". */
+
+static void
+aarch64_emit_le_goto (int *offset_p, int *size_p)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_pop (p, x1);
+ p += emit_cmp (p, x1, register_operand (x0));
+ /* Branch over the next instruction if x0 > x1. */
+ p += emit_bcond (p, GT, 8);
+ /* The NOP instruction will be patched with an unconditional branch. */
+ if (offset_p)
+ *offset_p = (p - buf) * 4;
+ if (size_p)
+ *size_p = 4;
+ p += emit_nop (p);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_gt_goto". */
+
+static void
+aarch64_emit_gt_goto (int *offset_p, int *size_p)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_pop (p, x1);
+ p += emit_cmp (p, x1, register_operand (x0));
+ /* Branch over the next instruction if x0 <= x1. */
+ p += emit_bcond (p, LE, 8);
+ /* The NOP instruction will be patched with an unconditional branch. */
+ if (offset_p)
+ *offset_p = (p - buf) * 4;
+ if (size_p)
+ *size_p = 4;
+ p += emit_nop (p);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_ge_got". */
+
+static void
+aarch64_emit_ge_got (int *offset_p, int *size_p)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_pop (p, x1);
+ p += emit_cmp (p, x1, register_operand (x0));
+ /* Branch over the next instruction if x0 <= x1. */
+ p += emit_bcond (p, LT, 8);
+ /* The NOP instruction will be patched with an unconditional branch. */
+ if (offset_p)
+ *offset_p = (p - buf) * 4;
+ if (size_p)
+ *size_p = 4;
+ p += emit_nop (p);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+static struct emit_ops aarch64_emit_ops_impl =
+{
+ aarch64_emit_prologue,
+ aarch64_emit_epilogue,
+ aarch64_emit_add,
+ aarch64_emit_sub,
+ aarch64_emit_mul,
+ aarch64_emit_lsh,
+ aarch64_emit_rsh_signed,
+ aarch64_emit_rsh_unsigned,
+ aarch64_emit_ext,
+ aarch64_emit_log_not,
+ aarch64_emit_bit_and,
+ aarch64_emit_bit_or,
+ aarch64_emit_bit_xor,
+ aarch64_emit_bit_not,
+ aarch64_emit_equal,
+ aarch64_emit_less_signed,
+ aarch64_emit_less_unsigned,
+ aarch64_emit_ref,
+ aarch64_emit_if_goto,
+ aarch64_emit_goto,
+ aarch64_write_goto_address,
+ aarch64_emit_const,
+ aarch64_emit_call,
+ aarch64_emit_reg,
+ aarch64_emit_pop,
+ aarch64_emit_stack_flush,
+ aarch64_emit_zero_ext,
+ aarch64_emit_swap,
+ aarch64_emit_stack_adjust,
+ aarch64_emit_int_call_1,
+ aarch64_emit_void_call_2,
+ aarch64_emit_eq_goto,
+ aarch64_emit_ne_goto,
+ aarch64_emit_lt_goto,
+ aarch64_emit_le_goto,
+ aarch64_emit_gt_goto,
+ aarch64_emit_ge_got,
+};
+
+/* Implementation of linux_target_ops method "emit_ops". */
+
+static struct emit_ops *
+aarch64_emit_ops (void)
+{
+ return &aarch64_emit_ops_impl;
+}
+
/* Implementation of linux_target_ops method
"get_min_fast_tracepoint_insn_len". */
@@ -2050,7 +3249,7 @@ struct linux_target_ops the_low_target =
aarch64_supports_tracepoints,
aarch64_get_thread_area,
aarch64_install_fast_tracepoint_jump_pad,
- NULL, /* emit_ops */
+ aarch64_emit_ops,
aarch64_get_min_fast_tracepoint_insn_len,
aarch64_supports_range_stepping,
};
--
2.4.6
^ permalink raw reply [flat|nested] 37+ messages in thread* [PATCH 4/8] [GDBserver][AArch64] Add support for fast tracepoints
2015-09-14 11:31 [PATCH 0/8] [AArch64] Support fast tracepoints Pierre Langlois
` (4 preceding siblings ...)
2015-09-14 11:32 ` [PATCH 5/8] [GDBserver][AArch64] Implement target_emit_ops Pierre Langlois
@ 2015-09-14 11:33 ` Pierre Langlois
2015-09-15 13:01 ` Yao Qi
2015-09-14 11:38 ` [PATCH 2/8] [AArch64] Move instruction decoding into new arch/ directory Pierre Langlois
` (3 subsequent siblings)
9 siblings, 1 reply; 37+ messages in thread
From: Pierre Langlois @ 2015-09-14 11:33 UTC (permalink / raw)
To: gdb-patches; +Cc: Pierre Langlois
This patch adds support for fast tracepoints for aarch64-linux. With this
implementation, a tracepoint can only be placed in a +/- 128MB range of
the jump pad. This is due to the unconditional branch instruction
being limited to a (26 bit << 2) offset from the current PC.
Three target operations are implemented:
- target_install_fast_tracepoint_jump_pad
Building the jump pad the biggest change of this patch. We need to add
functions to emit all instructions needed to save and restore the
current state when the tracepoint is hit. As well as implementing a
lock and creating a collecting_t object identifying the current thread.
Steps performed by the jump pad:
* Save the current state on the stack.
* Push a collecting_t object on the stack. We read the special
tpidr_el0 system register to get the thread ID.
* Spin-lock on the shared memory location of all tracing threads. We
write the address of our collecting_t object there once we have the
lock.
* Call gdb_collect.
* Release the lock.
* Restore the state.
* Execute the replaced instruction which will have been relocated.
* Jump back to the program.
- target_get_thread_area
As implemented in ps_get_thread_area, target_get_thread_area uses ptrace
to fetch the NT_ARM_TLS register. At the architecture level, NT_ARM_TLS
represents the tpidr_el0 system register.
So this ptrace call (if lwpid is the current thread):
~~~
ptrace (PTRACE_GETREGSET, lwpid, NT_ARM_TLS, &iovec);
~~~
Is equivalent to the following instruction:
~~~
msr x0, tpidr_el0
~~~
This instruction is used when creating the collecting_t object that
GDBserver can read to know if a given thread is currently tracing.
So target_get_thread_area must get the same thread IDs as what the jump
pad writes into its collecting_t object.
- target_get_min_fast_tracepoint_insn_len
This just returns 4.
gdb/gdbserver/ChangeLog:
* Makefile.in (linux-aarch64-ipa.o, aarch64-ipa.o): New rules.
* configure.srv (aarch64*-*-linux*): Add linux-aarch64-ipa.o and
aarch64-ipa.o.
* linux-aarch64-ipa.c: New file.
* linux-aarch64-low.c: Include arch/aarch64-insn.h, inttypes.h
and endian.h.
(aarch64_get_thread_area): New target method.
(extract_signed_bitfield): New helper function.
(aarch64_decode_ldr_literal): New function.
(enum aarch64_opcodes): New enum.
(struct aarch64_register): New struct.
(struct aarch64_operand): New struct.
(x0): New static global.
(x1): Likewise.
(x2): Likewise.
(x3): Likewise.
(x4): Likewise.
(w2): Likewise.
(ip0): Likewise.
(sp): Likewise.
(xzr): Likewise.
(aarch64_register): New helper function.
(register_operand): Likewise.
(immediate_operand): Likewise.
(struct aarch64_memory_operand): New struct.
(offset_memory_operand): New helper function.
(preindex_memory_operand): Likewise.
(enum aarch64_system_control_registers): New enum.
(ENCODE): New macro.
(emit_insn): New helper function.
(emit_b): New function.
(emit_bcond): Likewise.
(emit_cb): Likewise.
(emit_tb): Likewise.
(emit_blr): Likewise.
(emit_stp): Likewise.
(emit_ldp_q_offset): Likewise.
(emit_stp_q_offset): Likewise.
(emit_load_store): Likewise.
(emit_ldr): Likewise.
(emit_ldrsw): Likewise.
(emit_str): Likewise.
(emit_ldaxr): Likewise.
(emit_stxr): Likewise.
(emit_stlr): Likewise.
(emit_data_processing_reg): Likewise.
(emit_data_processing): Likewise.
(emit_add): Likewise.
(emit_sub): Likewise.
(emit_mov): Likewise.
(emit_movk): Likewise.
(emit_mov_addr): Likewise.
(emit_mrs): Likewise.
(emit_msr): Likewise.
(emit_sevl): Likewise.
(emit_wfe): Likewise.
(append_insns): Likewise.
(can_encode_int32_in): New helper function.
(aarch64_relocate_instruction): New function.
(aarch64_install_fast_tracepoint_jump_pad): Likewise.
(aarch64_get_min_fast_tracepoint_insn_len): Likewise.
(struct linux_target_ops): Install aarch64_get_thread_area,
aarch64_install_fast_tracepoint_jump_pad and
aarch64_get_min_fast_tracepoint_insn_len.
---
gdb/gdbserver/Makefile.in | 6 +
gdb/gdbserver/configure.srv | 1 +
gdb/gdbserver/linux-aarch64-ipa.c | 141 ++++
gdb/gdbserver/linux-aarch64-low.c | 1466 ++++++++++++++++++++++++++++++++++++-
4 files changed, 1611 insertions(+), 3 deletions(-)
create mode 100644 gdb/gdbserver/linux-aarch64-ipa.c
diff --git a/gdb/gdbserver/Makefile.in b/gdb/gdbserver/Makefile.in
index d096663..cd146f4 100644
--- a/gdb/gdbserver/Makefile.in
+++ b/gdb/gdbserver/Makefile.in
@@ -499,6 +499,12 @@ linux-amd64-ipa.o: linux-amd64-ipa.c
amd64-linux-ipa.o: amd64-linux.c
$(IPAGENT_COMPILE) $<
$(POSTCOMPILE)
+linux-aarch64-ipa.o: linux-aarch64-ipa.c
+ $(IPAGENT_COMPILE) $<
+ $(POSTCOMPILE)
+aarch64-ipa.o: aarch64.c
+ $(IPAGENT_COMPILE) $<
+ $(POSTCOMPILE)
tdesc-ipa.o: tdesc.c
$(IPAGENT_COMPILE) $<
$(POSTCOMPILE)
diff --git a/gdb/gdbserver/configure.srv b/gdb/gdbserver/configure.srv
index d263381..ce6f3ca 100644
--- a/gdb/gdbserver/configure.srv
+++ b/gdb/gdbserver/configure.srv
@@ -61,6 +61,7 @@ case "${target}" in
srv_xmlfiles="${srv_xmlfiles} arm-with-neon.xml"
srv_linux_regsets=yes
srv_linux_thread_db=yes
+ ipa_obj="linux-aarch64-ipa.o aarch64-ipa.o"
;;
arm*-*-linux*) srv_regobj="reg-arm.o arm-with-iwmmxt.o"
srv_regobj="${srv_regobj} arm-with-vfpv2.o"
diff --git a/gdb/gdbserver/linux-aarch64-ipa.c b/gdb/gdbserver/linux-aarch64-ipa.c
new file mode 100644
index 0000000..b4cb1f7
--- /dev/null
+++ b/gdb/gdbserver/linux-aarch64-ipa.c
@@ -0,0 +1,141 @@
+/* GNU/Linux/AArch64 specific low level interface, for the in-process
+ agent library for GDB.
+
+ Copyright (C) 2015 Free Software Foundation, Inc.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#include "server.h"
+#include "tracepoint.h"
+
+/* Defined in auto-generated file aarch64.c. */
+void init_registers_aarch64 (void);
+extern const struct target_desc *tdesc_aarch64;
+
+/* Each register saved by the jump pad is in a 16 byte cell. */
+#define FT_CR_SIZE 16
+
+#define FT_CR_FPCR 0
+#define FT_CR_FPSR 1
+#define FT_CR_CPSR 2
+#define FT_CR_PC 3
+#define FT_CR_SP 4
+#define FT_CR_X0 5
+#define FT_CR_GPR(n) (FT_CR_X0 + (n))
+#define FT_CR_FPR(n) (FT_CR_GPR (31) + (n))
+
+/* Mapping between registers collected by the jump pad and GDB's register
+ array layout used by regcache.
+
+ See linux-aarch64-low.c (aarch64_install_fast_tracepoint_jump_pad) for
+ more details. */
+
+static const int aarch64_ft_collect_regmap[] = {
+ FT_CR_GPR (0),
+ FT_CR_GPR (1),
+ FT_CR_GPR (2),
+ FT_CR_GPR (3),
+ FT_CR_GPR (4),
+ FT_CR_GPR (5),
+ FT_CR_GPR (6),
+ FT_CR_GPR (7),
+ FT_CR_GPR (8),
+ FT_CR_GPR (9),
+ FT_CR_GPR (10),
+ FT_CR_GPR (11),
+ FT_CR_GPR (12),
+ FT_CR_GPR (13),
+ FT_CR_GPR (14),
+ FT_CR_GPR (15),
+ FT_CR_GPR (16),
+ FT_CR_GPR (17),
+ FT_CR_GPR (18),
+ FT_CR_GPR (19),
+ FT_CR_GPR (20),
+ FT_CR_GPR (21),
+ FT_CR_GPR (22),
+ FT_CR_GPR (23),
+ FT_CR_GPR (24),
+ FT_CR_GPR (25),
+ FT_CR_GPR (26),
+ FT_CR_GPR (27),
+ FT_CR_GPR (28),
+ /* FP */
+ FT_CR_GPR (29),
+ /* LR */
+ FT_CR_GPR (30),
+ FT_CR_SP,
+ FT_CR_PC,
+ FT_CR_CPSR,
+ FT_CR_FPR (0),
+ FT_CR_FPR (1),
+ FT_CR_FPR (2),
+ FT_CR_FPR (3),
+ FT_CR_FPR (4),
+ FT_CR_FPR (5),
+ FT_CR_FPR (6),
+ FT_CR_FPR (7),
+ FT_CR_FPR (8),
+ FT_CR_FPR (9),
+ FT_CR_FPR (10),
+ FT_CR_FPR (11),
+ FT_CR_FPR (12),
+ FT_CR_FPR (13),
+ FT_CR_FPR (14),
+ FT_CR_FPR (15),
+ FT_CR_FPR (16),
+ FT_CR_FPR (17),
+ FT_CR_FPR (18),
+ FT_CR_FPR (19),
+ FT_CR_FPR (20),
+ FT_CR_FPR (21),
+ FT_CR_FPR (22),
+ FT_CR_FPR (23),
+ FT_CR_FPR (24),
+ FT_CR_FPR (25),
+ FT_CR_FPR (26),
+ FT_CR_FPR (27),
+ FT_CR_FPR (28),
+ FT_CR_FPR (29),
+ FT_CR_FPR (30),
+ FT_CR_FPR (31),
+ FT_CR_FPSR,
+ FT_CR_FPCR
+};
+
+#define AARCH64_NUM_FT_COLLECT_GREGS \
+ (sizeof (aarch64_ft_collect_regmap) / sizeof(aarch64_ft_collect_regmap[0]))
+
+/* Fill in REGCACHE with registers saved by the jump pad in BUF. */
+
+void
+supply_fast_tracepoint_registers (struct regcache *regcache,
+ const unsigned char *buf)
+{
+ int i;
+
+ for (i = 0; i < AARCH64_NUM_FT_COLLECT_GREGS; i++)
+ supply_register (regcache, i,
+ ((char *) buf)
+ + (aarch64_ft_collect_regmap[i] * FT_CR_SIZE));
+}
+
+void
+initialize_low_tracepoint (void)
+{
+ init_registers_aarch64 ();
+ ipa_tdesc = tdesc_aarch64;
+}
diff --git a/gdb/gdbserver/linux-aarch64-low.c b/gdb/gdbserver/linux-aarch64-low.c
index aebf1e3..bb06558 100644
--- a/gdb/gdbserver/linux-aarch64-low.c
+++ b/gdb/gdbserver/linux-aarch64-low.c
@@ -23,6 +23,7 @@
#include "linux-low.h"
#include "nat/aarch64-linux.h"
#include "nat/aarch64-linux-hw-point.h"
+#include "arch/aarch64-insn.h"
#include "linux-aarch32-low.h"
#include "elf/common.h"
@@ -31,6 +32,8 @@
#include "nat/gdb_ptrace.h"
#include <asm/ptrace.h>
#include <sys/uio.h>
+#include <inttypes.h>
+#include <endian.h>
#include "gdb_proc_service.h"
@@ -552,6 +555,1463 @@ aarch64_supports_tracepoints (void)
}
}
+/* Implementation of linux_target_ops method "get_thread_area". */
+
+static int
+aarch64_get_thread_area (int lwpid, CORE_ADDR *addrp)
+{
+ struct iovec iovec;
+ uint64_t reg;
+
+ iovec.iov_base = ®
+ iovec.iov_len = sizeof (reg);
+
+ if (ptrace (PTRACE_GETREGSET, lwpid, NT_ARM_TLS, &iovec) != 0)
+ return -1;
+
+ *addrp = reg;
+
+ return 0;
+}
+
+/* Extract a signed value from a bit field within an instruction
+ encoding.
+
+ INSN is the instruction opcode.
+
+ WIDTH specifies the width of the bit field to extract (in bits).
+
+ OFFSET specifies the least significant bit of the field where bits
+ are numbered zero counting from least to most significant. */
+
+static int32_t
+extract_signed_bitfield (uint32_t insn, unsigned width, unsigned offset)
+{
+ unsigned shift_l = sizeof (int32_t) * 8 - (offset + width);
+ unsigned shift_r = sizeof (int32_t) * 8 - width;
+
+ return ((int32_t) insn << shift_l) >> shift_r;
+}
+
+/* Decode an opcode if it represents an LDR or LDRSW instruction taking a
+ literal offset from the current PC.
+
+ ADDR specifies the address of the opcode.
+ INSN specifies the opcode to test.
+ IS_W is set if the instruction is LDRSW.
+ IS64 receives size field from the decoded instruction.
+ RT receives the 'rt' field from the decoded instruction.
+ OFFSET receives the 'imm' field from the decoded instruction.
+
+ Return 1 if the opcodes matches and is decoded, otherwise 0. */
+
+int
+aarch64_decode_ldr_literal (CORE_ADDR addr, uint32_t insn, int *is_w,
+ int *is64, unsigned *rt, int32_t *offset)
+{
+ /* LDR 0T01 1000 iiii iiii iiii iiii iiir rrrr */
+ /* LDRSW 1001 1000 iiii iiii iiii iiii iiir rrrr */
+ if ((insn & 0x3f000000) == 0x18000000)
+ {
+ *is_w = (insn >> 31) & 0x1;
+
+ if (*is_w)
+ {
+ /* LDRSW always takes a 64-bit destination registers. */
+ *is64 = 1;
+ }
+ else
+ *is64 = (insn >> 30) & 0x1;
+
+ *rt = (insn >> 0) & 0x1f;
+ *offset = extract_signed_bitfield (insn, 19, 5) << 2;
+
+ if (aarch64_debug)
+ debug_printf ("decode: %s 0x%x %s %s%u, #?\n",
+ core_addr_to_string_nz (addr), insn,
+ *is_w ? "ldrsw" : "ldr",
+ *is64 ? "x" : "w", *rt);
+
+ return 1;
+ }
+
+ return 0;
+}
+
+/* List of opcodes that we need for building the jump pad and relocating
+ an instruction. */
+
+enum aarch64_opcodes
+{
+ /* B 0001 01ii iiii iiii iiii iiii iiii iiii */
+ /* BL 1001 01ii iiii iiii iiii iiii iiii iiii */
+ /* B.COND 0101 0100 iiii iiii iiii iiii iii0 cccc */
+ /* CBZ s011 0100 iiii iiii iiii iiii iiir rrrr */
+ /* CBNZ s011 0101 iiii iiii iiii iiii iiir rrrr */
+ /* TBZ b011 0110 bbbb biii iiii iiii iiir rrrr */
+ /* TBNZ b011 0111 bbbb biii iiii iiii iiir rrrr */
+ B = 0x14000000,
+ BL = 0x80000000 | B,
+ BCOND = 0x40000000 | B,
+ CBZ = 0x20000000 | B,
+ CBNZ = 0x21000000 | B,
+ TBZ = 0x36000000 | B,
+ TBNZ = 0x37000000 | B,
+ /* BLR 1101 0110 0011 1111 0000 00rr rrr0 0000 */
+ BLR = 0xd63f0000,
+ /* STP s010 100o o0ii iiii irrr rrrr rrrr rrrr */
+ /* LDP s010 100o o1ii iiii irrr rrrr rrrr rrrr */
+ /* STP (SIMD&VFP) ss10 110o o0ii iiii irrr rrrr rrrr rrrr */
+ /* LDP (SIMD&VFP) ss10 110o o1ii iiii irrr rrrr rrrr rrrr */
+ STP = 0x28000000,
+ LDP = 0x28400000,
+ STP_SIMD_VFP = 0x04000000 | STP,
+ LDP_SIMD_VFP = 0x04000000 | LDP,
+ /* STR ss11 100o 00xi iiii iiii xxrr rrrr rrrr */
+ /* LDR ss11 100o 01xi iiii iiii xxrr rrrr rrrr */
+ /* LDRSW 1011 100o 10xi iiii iiii xxrr rrrr rrrr */
+ STR = 0x38000000,
+ LDR = 0x00400000 | STR,
+ LDRSW = 0x80800000 | STR,
+ /* LDAXR ss00 1000 0101 1111 1111 11rr rrrr rrrr */
+ LDAXR = 0x085ffc00,
+ /* STXR ss00 1000 000r rrrr 0111 11rr rrrr rrrr */
+ STXR = 0x08007c00,
+ /* STLR ss00 1000 1001 1111 1111 11rr rrrr rrrr */
+ STLR = 0x089ffc00,
+ /* MOV s101 0010 1xxi iiii iiii iiii iiir rrrr */
+ /* MOVK s111 0010 1xxi iiii iiii iiii iiir rrrr */
+ MOV = 0x52800000,
+ MOVK = 0x20000000 | MOV,
+ /* ADD s00o ooo1 xxxx xxxx xxxx xxxx xxxx xxxx */
+ /* SUB s10o ooo1 xxxx xxxx xxxx xxxx xxxx xxxx */
+ /* SUBS s11o ooo1 xxxx xxxx xxxx xxxx xxxx xxxx */
+ ADD = 0x01000000,
+ SUB = 0x40000000 | ADD,
+ /* MSR (register) 1101 0101 0001 oooo oooo oooo ooor rrrr */
+ /* MRS 1101 0101 0011 oooo oooo oooo ooor rrrr */
+ MSR = 0xd5100000,
+ MRS = 0x00200000 | MSR,
+ /* HINT 1101 0101 0000 0011 0010 oooo ooo1 1111 */
+ HINT = 0xd503201f,
+ SEVL = (5 << 5) | HINT,
+ WFE = (2 << 5) | HINT,
+};
+
+/* Representation of a general purpose register of the form xN or wN.
+
+ This type is used by emitting functions that take registers as operands. */
+
+struct aarch64_register
+{
+ unsigned num;
+ int is64;
+};
+
+/* Representation of an operand. At this time, it only supports register
+ and immediate types. */
+
+struct aarch64_operand
+{
+ /* Type of the operand. */
+ enum
+ {
+ OPERAND_IMMEDIATE,
+ OPERAND_REGISTER,
+ } type;
+ /* Value of the operand according to the type. */
+ union
+ {
+ uint32_t imm;
+ struct aarch64_register reg;
+ };
+};
+
+/* List of registers that we are currently using, we can add more here as
+ we need to use them. */
+
+/* General purpose scratch registers (64 bit). */
+static struct aarch64_register x0 = { 0, 1 };
+static struct aarch64_register x1 = { 1, 1 };
+static struct aarch64_register x2 = { 2, 1 };
+static struct aarch64_register x3 = { 3, 1 };
+static struct aarch64_register x4 = { 4, 1 };
+
+/* General purpose scratch registers (32 bit). */
+static struct aarch64_register w2 = { 2, 0 };
+
+/* Intra-procedure scratch registers. */
+static struct aarch64_register ip0 = { 16, 1 };
+
+/* Special purpose registers. */
+static struct aarch64_register sp = { 31, 1 };
+static struct aarch64_register xzr = { 31, 1 };
+
+/* Dynamically allocate a new register. If we know the register
+ statically, we should make it a global as above instead of using this
+ helper function. */
+
+static struct aarch64_register
+aarch64_register (unsigned num, int is64)
+{
+ return (struct aarch64_register) { num, is64 };
+}
+
+/* Helper function to create a register operand, for instructions with
+ different types of operands.
+
+ For example:
+ p += emit_mov (p, x0, register_operand (x1)); */
+
+static struct aarch64_operand
+register_operand (struct aarch64_register reg)
+{
+ struct aarch64_operand operand;
+
+ operand.type = OPERAND_REGISTER;
+ operand.reg = reg;
+
+ return operand;
+}
+
+/* Helper function to create an immediate operand, for instructions with
+ different types of operands.
+
+ For example:
+ p += emit_mov (p, x0, immediate_operand (12)); */
+
+static struct aarch64_operand
+immediate_operand (uint32_t imm)
+{
+ struct aarch64_operand operand;
+
+ operand.type = OPERAND_IMMEDIATE;
+ operand.imm = imm;
+
+ return operand;
+}
+
+/* Representation of a memory operand, used for load and store
+ instructions.
+
+ The types correspond to the following variants:
+
+ MEMORY_OPERAND_OFFSET: LDR rt, [rn, #offset]
+ MEMORY_OPERAND_PREINDEX: LDR rt, [rn, #index]! */
+
+struct aarch64_memory_operand
+{
+ /* Type of the operand. */
+ enum
+ {
+ MEMORY_OPERAND_OFFSET,
+ MEMORY_OPERAND_PREINDEX,
+ } type;
+ /* Index from the base register. */
+ int32_t index;
+};
+
+/* Helper function to create an offset memory operand.
+
+ For example:
+ p += emit_ldr (p, x0, sp, offset_memory_operand (16)); */
+
+static struct aarch64_memory_operand
+offset_memory_operand (int32_t offset)
+{
+ return (struct aarch64_memory_operand) { MEMORY_OPERAND_OFFSET, offset };
+}
+
+/* Helper function to create a pre-index memory operand.
+
+ For example:
+ p += emit_ldr (p, x0, sp, preindex_memory_operand (16)); */
+
+static struct aarch64_memory_operand
+preindex_memory_operand (int32_t index)
+{
+ return (struct aarch64_memory_operand) { MEMORY_OPERAND_PREINDEX, index };
+}
+
+/* System control registers. These special registers can be written and
+ read with the MRS and MSR instructions.
+
+ - NZCV: Condition flags. GDB refers to this register under the CPSR
+ name.
+ - FPSR: Floating-point status register.
+ - FPCR: Floating-point control registers.
+ - TPIDR_EL0: Software thread ID register. */
+
+enum aarch64_system_control_registers
+{
+ /* op0 op1 crn crm op2 */
+ NZCV = (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x2 << 3) | 0x0,
+ FPSR = (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x4 << 3) | 0x1,
+ FPCR = (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x4 << 3) | 0x0,
+ TPIDR_EL0 = (0x1 << 14) | (0x3 << 11) | (0xd << 7) | (0x0 << 3) | 0x2
+};
+
+/* Helper macro to mask and shift a value into a bitfield. */
+
+#define ENCODE(val, size, offset) \
+ ((uint32_t) ((val & ((1ULL << size) - 1)) << offset))
+
+/* Write a 32-bit unsigned integer INSN info *BUF. Return the number of
+ instructions written (aka. 1). */
+
+static int
+emit_insn (uint32_t *buf, uint32_t insn)
+{
+ *buf = insn;
+ return 1;
+}
+
+/* Write a B or BL instruction into *BUF.
+
+ B #offset
+ BL #offset
+
+ IS_BL specifies if the link register should be updated.
+ OFFSET is the immediate offset from the current PC. It is
+ byte-addressed but should be 4 bytes aligned. It has a limited range of
+ +/- 128MB (26 bits << 2). */
+
+static int
+emit_b (uint32_t *buf, int is_bl, int32_t offset)
+{
+ uint32_t imm26 = ENCODE (offset >> 2, 26, 0);
+
+ if (is_bl)
+ return emit_insn (buf, BL | imm26);
+ else
+ return emit_insn (buf, B | imm26);
+}
+
+/* Write a BCOND instruction into *BUF.
+
+ B.COND #offset
+
+ COND specifies the condition field.
+ OFFSET is the immediate offset from the current PC. It is
+ byte-addressed but should be 4 bytes aligned. It has a limited range of
+ +/- 1MB (19 bits << 2). */
+
+static int
+emit_bcond (uint32_t *buf, unsigned cond, int32_t offset)
+{
+ return emit_insn (buf, BCOND | ENCODE (offset >> 2, 19, 5)
+ | ENCODE (cond, 4, 0));
+}
+
+/* Write a CBZ or CBNZ instruction into *BUF.
+
+ CBZ rt, #offset
+ CBNZ rt, #offset
+
+ IS_CBNZ distinguishes between CBZ and CBNZ instructions.
+ RN is the register to test.
+ OFFSET is the immediate offset from the current PC. It is
+ byte-addressed but should be 4 bytes aligned. It has a limited range of
+ +/- 1MB (19 bits << 2). */
+
+static int
+emit_cb (uint32_t *buf, int is_cbnz, struct aarch64_register rt,
+ int32_t offset)
+{
+ uint32_t imm19 = ENCODE (offset >> 2, 19, 5);
+ uint32_t sf = ENCODE (rt.is64, 1, 31);
+
+ if (is_cbnz)
+ return emit_insn (buf, CBNZ | sf | imm19 | ENCODE (rt.num, 5, 0));
+ else
+ return emit_insn (buf, CBZ | sf | imm19 | ENCODE (rt.num, 5, 0));
+}
+
+/* Write a TBZ or TBNZ instruction into *BUF.
+
+ TBZ rt, #bit, #offset
+ TBNZ rt, #bit, #offset
+
+ IS_TBNZ distinguishes between TBZ and TBNZ instructions.
+ RT is the register to test.
+ BIT is the index of the bit to test in register RT.
+ OFFSET is the immediate offset from the current PC. It is
+ byte-addressed but should be 4 bytes aligned. It has a limited range of
+ +/- 32KB (14 bits << 2). */
+
+static int
+emit_tb (uint32_t *buf, int is_tbnz, unsigned bit,
+ struct aarch64_register rt, int32_t offset)
+{
+ uint32_t imm14 = ENCODE (offset >> 2, 14, 5);
+ uint32_t b40 = ENCODE (bit, 5, 19);
+ uint32_t b5 = ENCODE (bit >> 5, 1, 31);
+
+ if (is_tbnz)
+ return emit_insn (buf, TBNZ | b5 | b40 | imm14 | ENCODE (rt.num, 5, 0));
+ else
+ return emit_insn (buf, TBZ | b5 | b40 | imm14 | ENCODE (rt.num, 5, 0));
+}
+
+/* Write a BLR instruction into *BUF.
+
+ BLR rn
+
+ RN is the register to branch to. */
+
+static int
+emit_blr (uint32_t *buf, struct aarch64_register rn)
+{
+ return emit_insn (buf, BLR | ENCODE (rn.num, 5, 5));
+}
+
+/* Write a STP instruction into *BUF.
+
+ STP rt, rt2, [rn, #offset]
+ STP rt, rt2, [rn, #index]!
+
+ RT and RT2 are the registers to store.
+ RN is the base address register.
+ OFFSET is the immediate to add to the base address. It is limited to a
+ -512 .. 504 range (7 bits << 3). */
+
+static int
+emit_stp (uint32_t *buf, struct aarch64_register rt,
+ struct aarch64_register rt2, struct aarch64_register rn,
+ struct aarch64_memory_operand operand)
+{
+ uint32_t opc;
+ uint32_t pre_index;
+ uint32_t write_back;
+
+ if (rt.is64)
+ opc = ENCODE (2, 2, 30);
+ else
+ opc = ENCODE (0, 2, 30);
+
+ switch (operand.type)
+ {
+ case MEMORY_OPERAND_OFFSET:
+ {
+ pre_index = ENCODE (1, 1, 24);
+ write_back = ENCODE (0, 1, 23);
+ break;
+ }
+ case MEMORY_OPERAND_PREINDEX:
+ {
+ pre_index = ENCODE (1, 1, 24);
+ write_back = ENCODE (1, 1, 23);
+ break;
+ }
+ default:
+ return 0;
+ }
+
+ return emit_insn (buf, STP | opc | pre_index | write_back
+ | ENCODE (operand.index >> 3, 7, 15) | ENCODE (rt2.num, 5, 10)
+ | ENCODE (rn.num, 5, 5) | ENCODE (rt.num, 5, 0));
+}
+
+/* Write a LDP (SIMD&VFP) instruction using Q registers into *BUF.
+
+ LDP qt, qt2, [rn, #offset]
+
+ RT and RT2 are the Q registers to store.
+ RN is the base address register.
+ OFFSET is the immediate to add to the base address. It is limited to
+ -1024 .. 1008 range (7 bits << 4). */
+
+static int
+emit_ldp_q_offset (uint32_t *buf, unsigned rt, unsigned rt2,
+ struct aarch64_register rn, int32_t offset)
+{
+ uint32_t opc = ENCODE (2, 2, 30);
+ uint32_t pre_index = ENCODE (1, 1, 24);
+
+ return emit_insn (buf, LDP_SIMD_VFP | opc | pre_index
+ | ENCODE (offset >> 4, 7, 15) | ENCODE (rt2, 5, 10)
+ | ENCODE (rn.num, 5, 5) | ENCODE (rt, 5, 0));
+}
+
+/* Write a STP (SIMD&VFP) instruction using Q registers into *BUF.
+
+ STP qt, qt2, [rn, #offset]
+
+ RT and RT2 are the Q registers to store.
+ RN is the base address register.
+ OFFSET is the immediate to add to the base address. It is limited to
+ -1024 .. 1008 range (7 bits << 4). */
+
+static int
+emit_stp_q_offset (uint32_t *buf, unsigned rt, unsigned rt2,
+ struct aarch64_register rn, int32_t offset)
+{
+ uint32_t opc = ENCODE (2, 2, 30);
+ uint32_t pre_index = ENCODE (1, 1, 24);
+
+ return emit_insn (buf, STP_SIMD_VFP | opc | pre_index
+ | ENCODE (offset >> 4, 7, 15) | ENCODE (rt2, 5, 10)
+ | ENCODE (rn.num, 5, 5) | ENCODE (rt, 5, 0));
+}
+
+/* Helper function emitting a load or store instruction. */
+
+static int
+emit_load_store (uint32_t *buf, uint32_t size, enum aarch64_opcodes opcode,
+ struct aarch64_register rt, struct aarch64_register rn,
+ struct aarch64_memory_operand operand)
+{
+ uint32_t op;
+
+ switch (operand.type)
+ {
+ case MEMORY_OPERAND_OFFSET:
+ {
+ op = ENCODE (1, 1, 24);
+
+ return emit_insn (buf, opcode | ENCODE (size, 2, 30) | op
+ | ENCODE (operand.index >> 3, 12, 10)
+ | ENCODE (rn.num, 5, 5) | ENCODE (rt.num, 5, 0));
+ }
+ case MEMORY_OPERAND_PREINDEX:
+ {
+ uint32_t pre_index = ENCODE (3, 2, 10);
+
+ op = ENCODE (0, 1, 24);
+
+ return emit_insn (buf, opcode | ENCODE (size, 2, 30) | op
+ | pre_index | ENCODE (operand.index, 9, 12)
+ | ENCODE (rn.num, 5, 5) | ENCODE (rt.num, 5, 0));
+ }
+ default:
+ return 0;
+ }
+}
+
+/* Write a LDR instruction into *BUF.
+
+ LDR rt, [rn, #offset]
+ LDR rt, [rn, #index]!
+
+ RT is the register to store.
+ RN is the base address register.
+ OFFSET is the immediate to add to the base address. It is limited to
+ 0 .. 32760 range (12 bits << 3). */
+
+static int
+emit_ldr (uint32_t *buf, struct aarch64_register rt,
+ struct aarch64_register rn, struct aarch64_memory_operand operand)
+{
+ return emit_load_store (buf, rt.is64 ? 3 : 2, LDR, rt, rn, operand);
+}
+
+/* Write a LDRSW instruction into *BUF. The register size is 64-bit.
+
+ LDRSW xt, [rn, #offset]
+ LDRSW xt, [rn, #index]!
+
+ RT is the register to store.
+ RN is the base address register.
+ OFFSET is the immediate to add to the base address. It is limited to
+ 0 .. 16380 range (12 bits << 2). */
+
+static int
+emit_ldrsw (uint32_t *buf, struct aarch64_register rt,
+ struct aarch64_register rn,
+ struct aarch64_memory_operand operand)
+{
+ return emit_load_store (buf, 3, LDRSW, rt, rn, operand);
+}
+
+/* Write a STR instruction into *BUF.
+
+ STR rt, [rn, #offset]
+ STR rt, [rn, #index]!
+
+ RT is the register to store.
+ RN is the base address register.
+ OFFSET is the immediate to add to the base address. It is limited to
+ 0 .. 32760 range (12 bits << 3). */
+
+static int
+emit_str (uint32_t *buf, struct aarch64_register rt,
+ struct aarch64_register rn,
+ struct aarch64_memory_operand operand)
+{
+ return emit_load_store (buf, rt.is64 ? 3 : 2, STR, rt, rn, operand);
+}
+
+/* Helper function emitting an exclusive load or store instruction. */
+
+static int
+emit_load_store_exclusive (uint32_t *buf, uint32_t size,
+ enum aarch64_opcodes opcode,
+ struct aarch64_register rs,
+ struct aarch64_register rt,
+ struct aarch64_register rt2,
+ struct aarch64_register rn)
+{
+ return emit_insn (buf, opcode | ENCODE (size, 2, 30)
+ | ENCODE (rs.num, 5, 16) | ENCODE (rt2.num, 5, 10)
+ | ENCODE (rn.num, 5, 5) | ENCODE (rt.num, 5, 0));
+}
+
+/* Write a LAXR instruction into *BUF.
+
+ LDAXR rt, [xn]
+
+ RT is the destination register.
+ RN is the base address register. */
+
+static int
+emit_ldaxr (uint32_t *buf, struct aarch64_register rt,
+ struct aarch64_register rn)
+{
+ return emit_load_store_exclusive (buf, rt.is64 ? 3 : 2, LDAXR, xzr, rt,
+ xzr, rn);
+}
+
+/* Write a STXR instruction into *BUF.
+
+ STXR ws, rt, [xn]
+
+ RS is the result register, it indicates if the store succeeded or not.
+ RT is the destination register.
+ RN is the base address register. */
+
+static int
+emit_stxr (uint32_t *buf, struct aarch64_register rs,
+ struct aarch64_register rt, struct aarch64_register rn)
+{
+ return emit_load_store_exclusive (buf, rt.is64 ? 3 : 2, STXR, rs, rt,
+ xzr, rn);
+}
+
+/* Write a STLR instruction into *BUF.
+
+ STLR rt, [xn]
+
+ RT is the register to store.
+ RN is the base address register. */
+
+static int
+emit_stlr (uint32_t *buf, struct aarch64_register rt,
+ struct aarch64_register rn)
+{
+ return emit_load_store_exclusive (buf, rt.is64 ? 3 : 2, STLR, xzr, rt,
+ xzr, rn);
+}
+
+/* Helper function for data processing instructions with register sources. */
+
+static int
+emit_data_processing_reg (uint32_t *buf, enum aarch64_opcodes opcode,
+ struct aarch64_register rd,
+ struct aarch64_register rn,
+ struct aarch64_register rm)
+{
+ uint32_t size = ENCODE (rd.is64, 1, 31);
+
+ return emit_insn (buf, opcode | size | ENCODE (rm.num, 5, 16)
+ | ENCODE (rn.num, 5, 5) | ENCODE (rd.num, 5, 0));
+}
+
+/* Helper function for data processing instructions taking either a register
+ or an immediate. */
+
+static int
+emit_data_processing (uint32_t *buf, enum aarch64_opcodes opcode,
+ struct aarch64_register rd,
+ struct aarch64_register rn,
+ struct aarch64_operand operand)
+{
+ uint32_t size = ENCODE (rd.is64, 1, 31);
+ /* The opcode is different for register and immediate source operands. */
+ uint32_t operand_opcode;
+
+ if (operand.type == OPERAND_IMMEDIATE)
+ {
+ /* xxx1 000x xxxx xxxx xxxx xxxx xxxx xxxx */
+ operand_opcode = ENCODE (8, 4, 25);
+
+ return emit_insn (buf, opcode | operand_opcode | size
+ | ENCODE (operand.imm, 12, 10)
+ | ENCODE (rn.num, 5, 5) | ENCODE (rd.num, 5, 0));
+ }
+ else
+ {
+ /* xxx0 101x xxxx xxxx xxxx xxxx xxxx xxxx */
+ operand_opcode = ENCODE (5, 4, 25);
+
+ return emit_data_processing_reg (buf, opcode | operand_opcode, rd,
+ rn, operand.reg);
+ }
+}
+
+/* Write an ADD instruction into *BUF.
+
+ ADD rd, rn, #imm
+ ADD rd, rn, rm
+
+ This function handles both an immediate and register add.
+
+ RD is the destination register.
+ RN is the input register.
+ OPERAND is the source operand, either of type OPERAND_IMMEDIATE or
+ OPERAND_REGISTER. */
+
+static int
+emit_add (uint32_t *buf, struct aarch64_register rd,
+ struct aarch64_register rn, struct aarch64_operand operand)
+{
+ return emit_data_processing (buf, ADD, rd, rn, operand);
+}
+
+/* Write a SUB instruction into *BUF.
+
+ SUB rd, rn, #imm
+ SUB rd, rn, rm
+
+ This function handles both an immediate and register sub.
+
+ RD is the destination register.
+ RN is the input register.
+ IMM is the immediate to substract to RN. */
+
+static int
+emit_sub (uint32_t *buf, struct aarch64_register rd,
+ struct aarch64_register rn, struct aarch64_operand operand)
+{
+ return emit_data_processing (buf, SUB, rd, rn, operand);
+}
+
+/* Write a MOV instruction into *BUF.
+
+ MOV rd, #imm
+ MOV rd, rm
+
+ This function handles both a wide immediate move and a register move,
+ with the condition that the source register is not xzr. xzr and the
+ stack pointer share the same encoding and this function only supports
+ the stack pointer.
+
+ RD is the destination register.
+ OPERAND is the source operand, either of type OPERAND_IMMEDIATE or
+ OPERAND_REGISTER. */
+
+static int
+emit_mov (uint32_t *buf, struct aarch64_register rd,
+ struct aarch64_operand operand)
+{
+ if (operand.type == OPERAND_IMMEDIATE)
+ {
+ uint32_t size = ENCODE (rd.is64, 1, 31);
+ /* Do not shift the immediate. */
+ uint32_t shift = ENCODE (0, 2, 21);
+
+ return emit_insn (buf, MOV | size | shift
+ | ENCODE (operand.imm, 16, 5)
+ | ENCODE (rd.num, 5, 0));
+ }
+ else
+ return emit_add (buf, rd, operand.reg, immediate_operand (0));
+}
+
+/* Write a MOVK instruction into *BUF.
+
+ MOVK rd, #imm, lsl #shift
+
+ RD is the destination register.
+ IMM is the immediate.
+ SHIFT is the logical shift left to apply to IMM. */
+
+static int
+emit_movk (uint32_t *buf, struct aarch64_register rd, uint32_t imm, unsigned shift)
+{
+ uint32_t size = ENCODE (rd.is64, 1, 31);
+
+ return emit_insn (buf, MOVK | size | ENCODE (shift, 2, 21) |
+ ENCODE (imm, 16, 5) | ENCODE (rd.num, 5, 0));
+}
+
+/* Write instructions into *BUF in order to move ADDR into a register.
+ ADDR can be a 64-bit value.
+
+ This function will emit a series of MOV and MOVK instructions, such as:
+
+ MOV xd, #(addr)
+ MOVK xd, #(addr >> 16), lsl #16
+ MOVK xd, #(addr >> 32), lsl #32
+ MOVK xd, #(addr >> 48), lsl #48 */
+
+static int
+emit_mov_addr (uint32_t *buf, struct aarch64_register rd, CORE_ADDR addr)
+{
+ uint32_t *p = buf;
+
+ /* The MOV (wide immediate) instruction clears to top bits of the
+ register. */
+ p += emit_mov (p, rd, immediate_operand (addr & 0xffff));
+
+ if ((addr >> 16) != 0)
+ p += emit_movk (p, rd, (addr >> 16) & 0xffff, 1);
+ else
+ return p - buf;
+
+ if ((addr >> 32) != 0)
+ p += emit_movk (p, rd, (addr >> 32) & 0xffff, 2);
+ else
+ return p - buf;
+
+ if ((addr >> 48) != 0)
+ p += emit_movk (p, rd, (addr >> 48) & 0xffff, 3);
+
+ return p - buf;
+}
+
+/* Write a MRS instruction into *BUF. The register size is 64-bit.
+
+ MRS xt, system_reg
+
+ RT is the destination register.
+ SYSTEM_REG is special purpose register to read. */
+
+static int
+emit_mrs (uint32_t *buf, struct aarch64_register rt,
+ enum aarch64_system_control_registers system_reg)
+{
+ return emit_insn (buf, MRS | ENCODE (system_reg, 15, 5)
+ | ENCODE (rt.num, 5, 0));
+}
+
+/* Write a MSR instruction into *BUF. The register size is 64-bit.
+
+ MSR system_reg, xt
+
+ SYSTEM_REG is special purpose register to write.
+ RT is the input register. */
+
+static int
+emit_msr (uint32_t *buf, enum aarch64_system_control_registers system_reg,
+ struct aarch64_register rt)
+{
+ return emit_insn (buf, MSR | ENCODE (system_reg, 15, 5)
+ | ENCODE (rt.num, 5, 0));
+}
+
+/* Write a SEVL instruction into *BUF.
+
+ This is a hint instruction telling the hardware to trigger an event. */
+
+static int
+emit_sevl (uint32_t *buf)
+{
+ return emit_insn (buf, SEVL);
+}
+
+/* Write a WFE instruction into *BUF.
+
+ This is a hint instruction telling the hardware to wait for an event. */
+
+static int
+emit_wfe (uint32_t *buf)
+{
+ return emit_insn (buf, WFE);
+}
+
+/* Write LEN instructions from BUF into the inferior memory at *TO.
+
+ Note instructions are always little endian on AArch64, unlike data. */
+
+static void
+append_insns (CORE_ADDR *to, size_t len, const uint32_t *buf)
+{
+ size_t byte_len = len * sizeof (uint32_t);
+#if (__BYTE_ORDER == __BIG_ENDIAN)
+ uint32_t *le_buf = xmalloc (byte_len);
+ size_t i;
+
+ for (i = 0; i < len; i++)
+ le_buf[i] = htole32 (buf[i]);
+
+ write_inferior_memory (*to, (const unsigned char *) le_buf, byte_len);
+
+ xfree (le_buf);
+#else
+ write_inferior_memory (*to, (const unsigned char *) buf, byte_len);
+#endif
+
+ *to += byte_len;
+}
+
+/* Helper function. Return 1 if VAL can be encoded in BITS bits. */
+
+static int
+can_encode_int32 (int32_t val, unsigned bits)
+{
+ /* This must be an arithemic shift. */
+ int32_t rest = val >> bits;
+
+ return rest == 0 || rest == -1;
+}
+
+/* Relocate an instruction from OLDLOC to *TO. This function will also
+ increment TO by the number of bytes the new instruction(s) take(s).
+
+ PC relative instructions need to be handled specifically:
+
+ - B/BL
+ - B.COND
+ - CBZ/CBNZ
+ - TBZ/TBNZ
+ - ADR/ADRP
+ - LDR/LDRSW (literal) */
+
+static void
+aarch64_relocate_instruction (CORE_ADDR *to, CORE_ADDR oldloc)
+{
+ uint32_t buf[32];
+ uint32_t *p = buf;
+ uint32_t insn;
+
+ int is_bl;
+ int is64;
+ int is_sw;
+ int is_cbnz;
+ int is_tbnz;
+ int is_adrp;
+ unsigned rn;
+ unsigned rt;
+ unsigned rd;
+ unsigned cond;
+ unsigned bit;
+ int32_t offset;
+
+ target_read_uint32 (oldloc, &insn);
+
+ if (aarch64_decode_b (oldloc, insn, &is_bl, &offset))
+ {
+ offset = (oldloc - *to + offset);
+
+ if (can_encode_int32 (offset, 28))
+ p += emit_b (p, is_bl, offset);
+ else
+ return;
+ }
+ else if (aarch64_decode_bcond (oldloc, insn, &cond, &offset))
+ {
+ offset = (oldloc - *to + offset);
+
+ if (can_encode_int32 (offset, 21))
+ p += emit_bcond (p, cond, offset);
+ else if (can_encode_int32 (offset, 28))
+ {
+ /* The offset is out of range for a conditional branch
+ instruction but not for a unconditional branch. We can use
+ the following instructions instead:
+
+ B.COND TAKEN ; If cond is true, then jump to TAKEN.
+ B NOT_TAKEN ; Else jump over TAKEN and continue.
+ TAKEN:
+ B #(offset - 8)
+ NOT_TAKEN:
+
+ */
+
+ p += emit_bcond (p, cond, 8);
+ p += emit_b (p, 0, 8);
+ p += emit_b (p, 0, offset - 8);
+ }
+ else
+ return;
+ }
+ else if (aarch64_decode_cb (oldloc, insn, &is64, &is_cbnz, &rn, &offset))
+ {
+ offset = (oldloc - *to + offset);
+
+ if (can_encode_int32 (offset, 21))
+ p += emit_cb (p, is_cbnz, aarch64_register (rn, is64), offset);
+ else if (can_encode_int32 (offset, 28))
+ {
+ /* The offset is out of range for a compare and branch
+ instruction but not for a unconditional branch. We can use
+ the following instructions instead:
+
+ CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
+ B NOT_TAKEN ; Else jump over TAKEN and continue.
+ TAKEN:
+ B #(offset - 8)
+ NOT_TAKEN:
+
+ */
+ p += emit_cb (p, is_cbnz, aarch64_register (rn, is64), 8);
+ p += emit_b (p, 0, 8);
+ p += emit_b (p, 0, offset - 8);
+ }
+ else
+ return;
+ }
+ else if (aarch64_decode_tb (oldloc, insn, &is_tbnz, &bit, &rt, &offset))
+ {
+ offset = (oldloc - *to + offset);
+
+ if (can_encode_int32 (offset, 16))
+ p += emit_tb (p, is_tbnz, bit, aarch64_register (rt, 1), offset);
+ else if (can_encode_int32 (offset, 28))
+ {
+ /* The offset is out of range for a test bit and branch
+ instruction but not for a unconditional branch. We can use
+ the following instructions instead:
+
+ TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
+ B NOT_TAKEN ; Else jump over TAKEN and continue.
+ TAKEN:
+ B #(offset - 8)
+ NOT_TAKEN:
+
+ */
+ p += emit_tb (p, is_tbnz, bit, aarch64_register (rt, 1), 8);
+ p += emit_b (p, 0, 8);
+ p += emit_b (p, 0, offset - 8);
+ }
+ else
+ return;
+ }
+ else if (aarch64_decode_adr (oldloc, insn, &is_adrp, &rd, &offset))
+ {
+
+ /* We know exactly the address the ADR{P,} instruction will compute.
+ We can just write it to the destination register. */
+ CORE_ADDR address = oldloc + offset;
+
+ if (is_adrp)
+ {
+ /* Clear the lower 12 bits of the offset to get the 4K page. */
+ p += emit_mov_addr (p, aarch64_register (rd, 1),
+ address & ~0xfff);
+ }
+ else
+ p += emit_mov_addr (p, aarch64_register (rd, 1), address);
+ }
+ else if (aarch64_decode_ldr_literal (oldloc, insn, &is_sw, &is64, &rt,
+ &offset))
+ {
+ /* We know exactly what address to load from, and what register we
+ can use:
+
+ MOV xd, #(oldloc + offset)
+ MOVK xd, #((oldloc + offset) >> 16), lsl #16
+ ...
+
+ LDR xd, [xd] ; or LDRSW xd, [xd]
+
+ */
+ CORE_ADDR address = oldloc + offset;
+
+ p += emit_mov_addr (p, aarch64_register (rt, 1), address);
+
+ if (is_sw)
+ p += emit_ldrsw (p, aarch64_register (rt, 1),
+ aarch64_register (rt, 1),
+ offset_memory_operand (0));
+ else
+ p += emit_ldr (p, aarch64_register (rt, is64),
+ aarch64_register (rt, 1),
+ offset_memory_operand (0));
+ }
+ else
+ {
+ /* The instruction is not PC relative. Just re-emit it at the new
+ location. */
+ p += emit_insn (p, insn);
+ }
+
+ append_insns (to, p - buf, buf);
+}
+
+/* Implementation of linux_target_ops method
+ "install_fast_tracepoint_jump_pad". */
+
+static int
+aarch64_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint,
+ CORE_ADDR tpaddr,
+ CORE_ADDR collector,
+ CORE_ADDR lockaddr,
+ ULONGEST orig_size,
+ CORE_ADDR *jump_entry,
+ CORE_ADDR *trampoline,
+ ULONGEST *trampoline_size,
+ unsigned char *jjump_pad_insn,
+ ULONGEST *jjump_pad_insn_size,
+ CORE_ADDR *adjusted_insn_addr,
+ CORE_ADDR *adjusted_insn_addr_end,
+ char *err)
+{
+ uint32_t buf[256];
+ uint32_t *p = buf;
+ int32_t offset;
+ int i;
+ CORE_ADDR buildaddr = *jump_entry;
+
+ /* We need to save the current state on the stack both to restore it
+ later and to collect register values when the tracepoint is hit.
+
+ The saved registers are pushed in a layout that needs to be in sync
+ with aarch64_ft_collect_regmap (see linux-aarch64-ipa.c). Later on
+ the supply_fast_tracepoint_registers function will fill in the
+ register cache from a pointer to saved registers on the stack we build
+ here.
+
+ For simplicity, we set the size of each cell on the stack to 16 bytes.
+ This way one cell can hold any register type, from system registers
+ to the 128 bit SIMD&FP registers. Furthermore, the stack pointer
+ has to be 16 bytes aligned anyway.
+
+ Note that the CPSR register does not exist on AArch64. Instead we
+ can access system bits describing the process state with the
+ MRS/MSR instructions, namely the condition flags. We save them as
+ if they are part of a CPSR register because that's how GDB
+ interprets these system bits. At the moment, only the condition
+ flags are saved in CPSR (NZCV).
+
+ Stack layout, each cell is 16 bytes (descending):
+
+ High *-------- SIMD&FP registers from 31 down to 0. --------*
+ | q31 |
+ . .
+ . . 32 cells
+ . .
+ | q0 |
+ *---- General purpose registers from 30 down to 0. ----*
+ | x30 |
+ . .
+ . . 31 cells
+ . .
+ | x0 |
+ *------------- Special purpose registers. -------------*
+ | SP |
+ | PC |
+ | CPSR (NZCV) | 5 cells
+ | FPSR |
+ | FPCR | <- SP + 16
+ *------------- collecting_t object --------------------*
+ | TPIDR_EL0 | struct tracepoint * |
+ Low *------------------------------------------------------*
+
+ After this stack is set up, we issue a call to the collector, passing
+ it the saved registers at (SP + 16). */
+
+ /* Push SIMD&FP registers on the stack:
+
+ SUB sp, sp, #(32 * 16)
+
+ STP q30, q31, [sp, #(30 * 16)]
+ ...
+ STP q0, q1, [sp]
+
+ */
+ p += emit_sub (p, sp, sp, immediate_operand (32 * 16));
+ for (i = 30; i >= 0; i -= 2)
+ p += emit_stp_q_offset (p, i, i + 1, sp, i * 16);
+
+ /* Push general puspose registers on the stack. Note that we do not need
+ to push x31 as it represents the xzr register and not the stack
+ pointer in a STR instruction.
+
+ SUB sp, sp, #(31 * 16)
+
+ STR x30, [sp, #(30 * 16)]
+ ...
+ STR x0, [sp]
+
+ */
+ p += emit_sub (p, sp, sp, immediate_operand (31 * 16));
+ for (i = 30; i >= 0; i -= 1)
+ p += emit_str (p, aarch64_register (i, 1), sp,
+ offset_memory_operand (i * 16));
+
+ /* Make space for 5 more cells.
+
+ SUB sp, sp, #(5 * 16)
+
+ */
+ p += emit_sub (p, sp, sp, immediate_operand (5 * 16));
+
+
+ /* Save SP:
+
+ ADD x4, sp, #((32 + 31 + 5) * 16)
+ STR x4, [sp, #(4 * 16)]
+
+ */
+ p += emit_add (p, x4, sp, immediate_operand ((32 + 31 + 5) * 16));
+ p += emit_str (p, x4, sp, offset_memory_operand (4 * 16));
+
+ /* Save PC (tracepoint address):
+
+ MOV x3, #(tpaddr)
+ ...
+
+ STR x3, [sp, #(3 * 16)]
+
+ */
+
+ p += emit_mov_addr (p, x3, tpaddr);
+ p += emit_str (p, x3, sp, offset_memory_operand (3 * 16));
+
+ /* Save CPSR (NZCV), FPSR and FPCR:
+
+ MRS x2, nzcv
+ MRS x1, fpsr
+ MRS x0, fpcr
+
+ STR x2, [sp, #(2 * 16)]
+ STR x1, [sp, #(1 * 16)]
+ STR x0, [sp, #(0 * 16)]
+
+ */
+ p += emit_mrs (p, x2, NZCV);
+ p += emit_mrs (p, x1, FPSR);
+ p += emit_mrs (p, x0, FPCR);
+ p += emit_str (p, x2, sp, offset_memory_operand (2 * 16));
+ p += emit_str (p, x1, sp, offset_memory_operand (1 * 16));
+ p += emit_str (p, x0, sp, offset_memory_operand (0 * 16));
+
+ /* Push the collecting_t object. It consist of the address of the
+ tracepoint and an ID for the current thread. We get the latter by
+ reading the tpidr_el0 system register. It corresponds to the
+ NT_ARM_TLS register accessible with ptrace.
+
+ MOV x0, #(tpoint)
+ ...
+
+ MRS x1, tpidr_el0
+
+ STP x0, x1, [sp, #-16]!
+
+ */
+
+ p += emit_mov_addr (p, x0, tpoint);
+ p += emit_mrs (p, x1, TPIDR_EL0);
+ p += emit_stp (p, x0, x1, sp, preindex_memory_operand (-16));
+
+ /* Spin-lock:
+
+ The shared memory for the lock is at lockaddr. It will hold zero
+ if no-one is holding the lock, otherwise it contains the address of
+ the collecting_t object on the stack of the thread which acquired it.
+
+ At this stage, the stack pointer points to this thread's collecting_t
+ object.
+
+ We use the following registers:
+ - x0: Address of the lock.
+ - x1: Pointer to collecting_t object.
+ - x2: Scratch register.
+
+ MOV x0, #(lockaddr)
+ ...
+ MOV x1, sp
+
+ ; Trigger an event local to this core. So the following WFE
+ ; instruction is ignored.
+ SEVL
+ again:
+ ; Wait for an event. The event is triggered by either the SEVL
+ ; or STLR instructions (store release).
+ WFE
+
+ ; Atomically read at lockaddr. This marks the memory location as
+ ; exclusive. This instruction also has memory constraints which
+ ; make sure all previous data reads and writes are done before
+ ; executing it.
+ LDAXR x2, [x0]
+
+ ; Try again if another thread holds the lock.
+ CBNZ x2, again
+
+ ; We can lock it! Write the address of the collecting_t object.
+ ; This instruction will fail if the memory location is not marked
+ ; as exclusive anymore. If it succeeds, it will remove the
+ ; exclusive mark on the memory location. This way, if another
+ ; thread executes this instruction before us, we will fail and try
+ ; all over again.
+ STXR w2, x1, [x0]
+ CBNZ w2, again
+
+ */
+
+ p += emit_mov_addr (p, x0, lockaddr);
+ p += emit_mov (p, x1, register_operand (sp));
+
+ p += emit_sevl (p);
+ p += emit_wfe (p);
+ p += emit_ldaxr (p, x2, x0);
+ p += emit_cb (p, 1, w2, -2 * 4);
+ p += emit_stxr (p, w2, x1, x0);
+ p += emit_cb (p, 1, x2, -4 * 4);
+
+ /* Call collector (struct tracepoint *, unsigned char *):
+
+ MOV x0, #(tpoint)
+ ...
+
+ ; Saved registers start after the collecting_t object.
+ ADD x1, sp, #16
+
+ ; We use an intra-procedure-call scratch register.
+ MOV ip0, #(collector)
+ ...
+
+ ; And call back to C!
+ BLR ip0
+
+ */
+
+ p += emit_mov_addr (p, x0, tpoint);
+ p += emit_add (p, x1, sp, immediate_operand (16));
+
+ p += emit_mov_addr (p, ip0, collector);
+ p += emit_blr (p, ip0);
+
+ /* Release the lock.
+
+ MOV x0, #(lockaddr)
+ ...
+
+ ; This instruction is a normal store with memory ordering
+ ; constraints. Thanks to this we do not have to put a data
+ ; barrier instruction to make sure all data read and writes are done
+ ; before this instruction is executed. Furthermore, this instrucion
+ ; will trigger an event, letting other threads know they can grab
+ ; the lock.
+ STLR xzr, [x0]
+
+ */
+ p += emit_mov_addr (p, x0, lockaddr);
+ p += emit_stlr (p, xzr, x0);
+
+ /* Free collecting_t object:
+
+ ADD sp, sp, #16
+
+ */
+ p += emit_add (p, sp, sp, immediate_operand (16));
+
+ /* Restore CPSR (NZCV), FPSR and FPCR. And free all special purpose
+ registers from the stack.
+
+ LDR x2, [sp, #(2 * 16)]
+ LDR x1, [sp, #(1 * 16)]
+ LDR x0, [sp, #(0 * 16)]
+
+ MSR NZCV, x2
+ MSR FPSR, x1
+ MSR FPCR, x0
+
+ ADD sp, sp #(5 * 16)
+
+ */
+ p += emit_ldr (p, x2, sp, offset_memory_operand (2 * 16));
+ p += emit_ldr (p, x1, sp, offset_memory_operand (1 * 16));
+ p += emit_ldr (p, x0, sp, offset_memory_operand (0 * 16));
+ p += emit_msr (p, NZCV, x2);
+ p += emit_msr (p, FPSR, x1);
+ p += emit_msr (p, FPCR, x0);
+
+ p += emit_add (p, sp, sp, immediate_operand (5 * 16));
+
+ /* Pop general purpose registers:
+
+ LDR x0, [sp]
+ ...
+ LDR x30, [sp, #(30 * 16)]
+
+ ADD sp, sp, #(31 * 16)
+
+ */
+ for (i = 0; i <= 30; i += 1)
+ p += emit_ldr (p, aarch64_register (i, 1), sp,
+ offset_memory_operand (i * 16));
+ p += emit_add (p, sp, sp, immediate_operand (31 * 16));
+
+ /* Pop SIMD&FP registers:
+
+ LDP q0, q1, [sp]
+ ...
+ LDP q30, q31, [sp, #(30 * 16)]
+
+ ADD sp, sp, #(32 * 16)
+
+ */
+ for (i = 0; i <= 30; i += 2)
+ p += emit_ldp_q_offset (p, i, i + 1, sp, i * 16);
+ p += emit_add (p, sp, sp, immediate_operand (32 * 16));
+
+ /* Write the code into the inferior memory. */
+ append_insns (&buildaddr, p - buf, buf);
+
+ /* Now emit the relocated instruction. */
+ *adjusted_insn_addr = buildaddr;
+ aarch64_relocate_instruction (&buildaddr, tpaddr);
+ *adjusted_insn_addr_end = buildaddr;
+
+ /* We may not have been able to relocate the instruction. */
+ if (*adjusted_insn_addr == *adjusted_insn_addr_end)
+ {
+ sprintf (err,
+ "E.Could not relocate instruction from %s to %s.",
+ core_addr_to_string_nz (tpaddr),
+ core_addr_to_string_nz (buildaddr));
+ return 1;
+ }
+
+ /* Go back to the start of the buffer. */
+ p = buf;
+
+ /* Emit a branch back from the jump pad. */
+ offset = (tpaddr + orig_size - buildaddr);
+ if (!can_encode_int32 (offset, 28))
+ {
+ sprintf (err,
+ "E.Jump back from jump pad too far from tracepoint "
+ "(offset 0x%" PRIx32 " cannot be encoded in 28 bits).",
+ offset);
+ return 1;
+ }
+
+ p += emit_b (p, 0, offset);
+ append_insns (&buildaddr, p - buf, buf);
+
+ /* Give the caller a branch instruction into the jump pad. */
+ offset = (*jump_entry - tpaddr);
+ if (!can_encode_int32 (offset, 28))
+ {
+ sprintf (err,
+ "E.Jump pad too far from tracepoint "
+ "(offset 0x%" PRIx32 " cannot be encoded in 28 bits).",
+ offset);
+ return 1;
+ }
+
+ emit_b ((uint32_t *) jjump_pad_insn, 0, offset);
+ *jjump_pad_insn_size = 4;
+
+ /* Return the end address of our pad. */
+ *jump_entry = buildaddr;
+
+ return 0;
+}
+
+/* Implementation of linux_target_ops method
+ "get_min_fast_tracepoint_insn_len". */
+
+static int
+aarch64_get_min_fast_tracepoint_insn_len (void)
+{
+ return 4;
+}
+
/* Implementation of linux_target_ops method "supports_range_stepping". */
static int
@@ -588,10 +2048,10 @@ struct linux_target_ops the_low_target =
aarch64_linux_prepare_to_resume,
NULL, /* process_qsupported */
aarch64_supports_tracepoints,
- NULL, /* get_thread_area */
- NULL, /* install_fast_tracepoint_jump_pad */
+ aarch64_get_thread_area,
+ aarch64_install_fast_tracepoint_jump_pad,
NULL, /* emit_ops */
- NULL, /* get_min_fast_tracepoint_insn_len */
+ aarch64_get_min_fast_tracepoint_insn_len,
aarch64_supports_range_stepping,
};
--
2.4.6
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [PATCH 4/8] [GDBserver][AArch64] Add support for fast tracepoints
2015-09-14 11:33 ` [PATCH 4/8] [GDBserver][AArch64] Add support for fast tracepoints Pierre Langlois
@ 2015-09-15 13:01 ` Yao Qi
0 siblings, 0 replies; 37+ messages in thread
From: Yao Qi @ 2015-09-15 13:01 UTC (permalink / raw)
To: Pierre Langlois; +Cc: gdb-patches
Pierre Langlois <pierre.langlois@arm.com> writes:
> /* List of registers that we are currently using, we can add more here as
> + we need to use them. */
> +
> +/* General purpose scratch registers (64 bit). */
> +static struct aarch64_register x0 = { 0, 1 };
> +static struct aarch64_register x1 = { 1, 1 };
> +static struct aarch64_register x2 = { 2, 1 };
> +static struct aarch64_register x3 = { 3, 1 };
> +static struct aarch64_register x4 = { 4, 1 };
> +
> +/* General purpose scratch registers (32 bit). */
> +static struct aarch64_register w2 = { 2, 0 };
> +
> +/* Intra-procedure scratch registers. */
> +static struct aarch64_register ip0 = { 16, 1 };
> +
> +/* Special purpose registers. */
> +static struct aarch64_register sp = { 31, 1 };
> +static struct aarch64_register xzr = { 31, 1 };
Add "const"? like "static const struct aarch64_register xzr".
I go through it quickly, and it looks good to me.
--
Yao (齐尧)
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 2/8] [AArch64] Move instruction decoding into new arch/ directory
2015-09-14 11:31 [PATCH 0/8] [AArch64] Support fast tracepoints Pierre Langlois
` (5 preceding siblings ...)
2015-09-14 11:33 ` [PATCH 4/8] [GDBserver][AArch64] Add support for fast tracepoints Pierre Langlois
@ 2015-09-14 11:38 ` Pierre Langlois
2015-09-15 10:10 ` Yao Qi
2015-09-14 11:38 ` [PATCH 8/8] [testsuite] Add a test case for fast tracepoints' locking mechanism Pierre Langlois
` (2 subsequent siblings)
9 siblings, 1 reply; 37+ messages in thread
From: Pierre Langlois @ 2015-09-14 11:38 UTC (permalink / raw)
To: gdb-patches; +Cc: Pierre Langlois
This patch moves the following functions into the arch/ common
directory, in new files arch/aarch64-insn.{h,c}. They are prefixed with
'aarch64_':
- aarch64_decode_adrp
- aarch64_decode_b
- aarch64_decode_cb
- aarch64_decode_tb
We will need them to implement fast tracepoints in GDBserver.
For consistency, this patch also adds the 'aarch64_' prefix to static
decoding functions that do not need to be shared right now.
gdb/ChangeLog:
* Makefile.in (ALL_64_TARGET_OBS): Add aarch64-insn.o.
(HFILES_NO_SRCDIR): Add arch/aarch64-insn.h.
(aarch64-insn.o): New rule.
* configure.tgt (aarch64*-*-elf): Add aarch64-insn.o.
(aarch64*-*-linux*): Likewise.
* arch/aarch64-insn.c: New file.
* arch/aarch64-insn.h: New file.
* aarch64-tdep.c: Include arch/aarch64-insn.h.
(aarch64_debug): Move to arch/aarch64-insn.c. Declare in
arch/aarch64-insn.h.
(decode_add_sub_imm): Rename to ...
(aarch64_decode_add_sub_imm): ... this.
(decode_adrp): Rename to ...
(aarch64_decode_adrp): ... this. Move to arch/aarch64-insn.c.
Declare in arch/aarch64-insn.h.
(decode_b): Rename to ...
(aarch64_decode_b): ... this. Move to arch/aarch64-insn.c.
Declare in arch/aarch64-insn.h.
(decode_bcond): Rename to ...
(aarch64_decode_bcond): ... this. Move to arch/aarch64-insn.c.
Declare in arch/aarch64-insn.h.
(decode_br): Rename to ...
(aarch64_decode_br): ... this.
(decode_cb): Rename to ...
(aarch64_decode_cb): ... this. Move to arch/aarch64-insn.c.
Declare in arch/aarch64-insn.h.
(decode_eret): Rename to ...
(aarch64_decode_eret): ... this.
(decode_movz): Rename to ...
(aarch64_decode_movz): ... this.
(decode_orr_shifted_register_x): Rename to ...
(aarch64_decode_orr_shifted_register_x): ... this.
(decode_ret): Rename to ...
(aarch64_decode_ret): ... this.
(decode_stp_offset): Rename to ...
(aarch64_decode_stp_offset): ... this.
(decode_stp_offset_wb): Rename to ...
(aarch64_decode_stp_offset_wb): ... this.
(decode_stur): Rename to ...
(aarch64_decode_stur): ... this.
(decode_tb): Rename to ...
(aarch64_decode_tb): ... this. Move to arch/aarch64-insn.c.
Declare in arch/aarch64-insn.h.
(aarch64_analyze_prologue): Adjust calls to renamed functions.
gdb/gdbserver/ChangeLog:
* gdb/gdbserver/Makefile.in (aarch64-insn.o): New rule.
* gdb/gdbserver/configure.srv (aarch64*-*-linux*): Add
aarch64-insn.o.
---
gdb/Makefile.in | 13 ++-
gdb/aarch64-tdep.c | 225 ++++++++------------------------------------
gdb/arch/aarch64-insn.c | 208 ++++++++++++++++++++++++++++++++++++++++
gdb/arch/aarch64-insn.h | 38 ++++++++
gdb/configure.tgt | 4 +-
gdb/gdbserver/Makefile.in | 6 ++
gdb/gdbserver/configure.srv | 2 +-
7 files changed, 304 insertions(+), 192 deletions(-)
create mode 100644 gdb/arch/aarch64-insn.c
create mode 100644 gdb/arch/aarch64-insn.h
diff --git a/gdb/Makefile.in b/gdb/Makefile.in
index 5659116..d5ca2ee 100644
--- a/gdb/Makefile.in
+++ b/gdb/Makefile.in
@@ -644,7 +644,7 @@ TARGET_OBS = @TARGET_OBS@
# All target-dependent objects files that require 64-bit CORE_ADDR
# (used with --enable-targets=all --enable-64-bit-bfd).
ALL_64_TARGET_OBS = \
- aarch64-tdep.o aarch64-linux-tdep.o aarch64-newlib-tdep.o \
+ aarch64-tdep.o aarch64-linux-tdep.o aarch64-newlib-tdep.o aarch64-insn.o \
alphabsd-tdep.o alphafbsd-tdep.o alpha-linux-tdep.o alpha-mdebug-tdep.o \
alphanbsd-tdep.o alphaobsd-tdep.o alpha-tdep.o \
amd64fbsd-tdep.o amd64-darwin-tdep.o amd64-dicos-tdep.o \
@@ -986,7 +986,7 @@ common/common-debug.h common/cleanups.h common/gdb_setjmp.h \
common/common-exceptions.h target/target.h common/symbol.h \
common/common-regcache.h fbsd-tdep.h nat/linux-personality.h \
common/fileio.h nat/x86-linux.h nat/x86-linux-dregs.h \
-nat/linux-namespaces.h arch/arm.h common/gdb_sys_time.h
+nat/linux-namespaces.h arch/arm.h common/gdb_sys_time.h arch/aarch64-insn.h
# Header files that already have srcdir in them, or which are in objdir.
@@ -2336,6 +2336,15 @@ aarch64-linux.o: ${srcdir}/nat/aarch64-linux.c
$(COMPILE) $(srcdir)/nat/aarch64-linux.c
$(POSTCOMPILE)
+# gdb/arch/ dependencies
+#
+# Need to explicitly specify the compile rule as make will do nothing
+# or try to compile the object file into the sub-directory.
+
+aarch64-insn.o: ${srcdir}/arch/aarch64-insn.c
+ $(COMPILE) $(srcdir)/arch/aarch64-insn.c
+ $(POSTCOMPILE)
+
#
# gdb/tui/ dependencies
#
diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index ed6e83f..e3340bd 100644
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -57,6 +57,8 @@
#include "features/aarch64.c"
+#include "arch/aarch64-insn.h"
+
/* Pseudo register base numbers. */
#define AARCH64_Q0_REGNUM 0
#define AARCH64_D0_REGNUM (AARCH64_Q0_REGNUM + 32)
@@ -179,9 +181,6 @@ struct aarch64_prologue_cache
struct trad_frame_saved_reg *saved_regs;
};
-/* Toggle this file's internal debugging dump. */
-static int aarch64_debug;
-
static void
show_aarch64_debug (struct ui_file *file, int from_tty,
struct cmd_list_element *c, const char *value)
@@ -231,8 +230,8 @@ decode_masked_match (uint32_t insn, uint32_t mask, uint32_t pattern)
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
-decode_add_sub_imm (CORE_ADDR addr, uint32_t insn, unsigned *rd, unsigned *rn,
- int32_t *imm)
+aarch64_decode_add_sub_imm (CORE_ADDR addr, uint32_t insn, unsigned *rd,
+ unsigned *rn, int32_t *imm)
{
if ((insn & 0x9f000000) == 0x91000000)
{
@@ -268,88 +267,6 @@ decode_add_sub_imm (CORE_ADDR addr, uint32_t insn, unsigned *rd, unsigned *rn,
return 0;
}
-/* Decode an opcode if it represents an ADRP instruction.
-
- ADDR specifies the address of the opcode.
- INSN specifies the opcode to test.
- RD receives the 'rd' field from the decoded instruction.
-
- Return 1 if the opcodes matches and is decoded, otherwise 0. */
-
-static int
-decode_adrp (CORE_ADDR addr, uint32_t insn, unsigned *rd)
-{
- if (decode_masked_match (insn, 0x9f000000, 0x90000000))
- {
- *rd = (insn >> 0) & 0x1f;
-
- if (aarch64_debug)
- debug_printf ("decode: 0x%s 0x%x adrp x%u, #?\n",
- core_addr_to_string_nz (addr), insn, *rd);
- return 1;
- }
- return 0;
-}
-
-/* Decode an opcode if it represents an branch immediate or branch
- and link immediate instruction.
-
- ADDR specifies the address of the opcode.
- INSN specifies the opcode to test.
- IS_BL receives the 'op' bit from the decoded instruction.
- OFFSET receives the immediate offset from the decoded instruction.
-
- Return 1 if the opcodes matches and is decoded, otherwise 0. */
-
-static int
-decode_b (CORE_ADDR addr, uint32_t insn, int *is_bl, int32_t *offset)
-{
- /* b 0001 01ii iiii iiii iiii iiii iiii iiii */
- /* bl 1001 01ii iiii iiii iiii iiii iiii iiii */
- if (decode_masked_match (insn, 0x7c000000, 0x14000000))
- {
- *is_bl = (insn >> 31) & 0x1;
- *offset = extract_signed_bitfield (insn, 26, 0) << 2;
-
- if (aarch64_debug)
- debug_printf ("decode: 0x%s 0x%x %s 0x%s\n",
- core_addr_to_string_nz (addr), insn,
- *is_bl ? "bl" : "b",
- core_addr_to_string_nz (addr + *offset));
-
- return 1;
- }
- return 0;
-}
-
-/* Decode an opcode if it represents a conditional branch instruction.
-
- ADDR specifies the address of the opcode.
- INSN specifies the opcode to test.
- COND receives the branch condition field from the decoded
- instruction.
- OFFSET receives the immediate offset from the decoded instruction.
-
- Return 1 if the opcodes matches and is decoded, otherwise 0. */
-
-static int
-decode_bcond (CORE_ADDR addr, uint32_t insn, unsigned *cond, int32_t *offset)
-{
- /* b.cond 0101 0100 iiii iiii iiii iiii iii0 cccc */
- if (decode_masked_match (insn, 0xff000010, 0x54000000))
- {
- *cond = (insn >> 0) & 0xf;
- *offset = extract_signed_bitfield (insn, 19, 5) << 2;
-
- if (aarch64_debug)
- debug_printf ("decode: 0x%s 0x%x b<%u> 0x%s\n",
- core_addr_to_string_nz (addr), insn, *cond,
- core_addr_to_string_nz (addr + *offset));
- return 1;
- }
- return 0;
-}
-
/* Decode an opcode if it represents a branch via register instruction.
ADDR specifies the address of the opcode.
@@ -360,7 +277,8 @@ decode_bcond (CORE_ADDR addr, uint32_t insn, unsigned *cond, int32_t *offset)
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
-decode_br (CORE_ADDR addr, uint32_t insn, int *is_blr, unsigned *rn)
+aarch64_decode_br (CORE_ADDR addr, uint32_t insn, int *is_blr,
+ unsigned *rn)
{
/* 8 4 0 6 2 8 4 0 */
/* blr 110101100011111100000000000rrrrr */
@@ -380,40 +298,6 @@ decode_br (CORE_ADDR addr, uint32_t insn, int *is_blr, unsigned *rn)
return 0;
}
-/* Decode an opcode if it represents a CBZ or CBNZ instruction.
-
- ADDR specifies the address of the opcode.
- INSN specifies the opcode to test.
- IS64 receives the 'sf' field from the decoded instruction.
- IS_CBNZ receives the 'op' field from the decoded instruction.
- RN receives the 'rn' field from the decoded instruction.
- OFFSET receives the 'imm19' field from the decoded instruction.
-
- Return 1 if the opcodes matches and is decoded, otherwise 0. */
-
-static int
-decode_cb (CORE_ADDR addr, uint32_t insn, int *is64, int *is_cbnz,
- unsigned *rn, int32_t *offset)
-{
- /* cbz T011 010o iiii iiii iiii iiii iiir rrrr */
- /* cbnz T011 010o iiii iiii iiii iiii iiir rrrr */
- if (decode_masked_match (insn, 0x7e000000, 0x34000000))
- {
- *rn = (insn >> 0) & 0x1f;
- *is64 = (insn >> 31) & 0x1;
- *is_cbnz = (insn >> 24) & 0x1;
- *offset = extract_signed_bitfield (insn, 19, 5) << 2;
-
- if (aarch64_debug)
- debug_printf ("decode: 0x%s 0x%x %s 0x%s\n",
- core_addr_to_string_nz (addr), insn,
- *is_cbnz ? "cbnz" : "cbz",
- core_addr_to_string_nz (addr + *offset));
- return 1;
- }
- return 0;
-}
-
/* Decode an opcode if it represents a ERET instruction.
ADDR specifies the address of the opcode.
@@ -422,7 +306,7 @@ decode_cb (CORE_ADDR addr, uint32_t insn, int *is64, int *is_cbnz,
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
-decode_eret (CORE_ADDR addr, uint32_t insn)
+aarch64_decode_eret (CORE_ADDR addr, uint32_t insn)
{
/* eret 1101 0110 1001 1111 0000 0011 1110 0000 */
if (insn == 0xd69f03e0)
@@ -444,7 +328,7 @@ decode_eret (CORE_ADDR addr, uint32_t insn)
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
-decode_movz (CORE_ADDR addr, uint32_t insn, unsigned *rd)
+aarch64_decode_movz (CORE_ADDR addr, uint32_t insn, unsigned *rd)
{
if (decode_masked_match (insn, 0xff800000, 0x52800000))
{
@@ -471,9 +355,9 @@ decode_movz (CORE_ADDR addr, uint32_t insn, unsigned *rd)
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
-decode_orr_shifted_register_x (CORE_ADDR addr,
- uint32_t insn, unsigned *rd, unsigned *rn,
- unsigned *rm, int32_t *imm)
+aarch64_decode_orr_shifted_register_x (CORE_ADDR addr, uint32_t insn,
+ unsigned *rd, unsigned *rn,
+ unsigned *rm, int32_t *imm)
{
if (decode_masked_match (insn, 0xff200000, 0xaa000000))
{
@@ -500,7 +384,7 @@ decode_orr_shifted_register_x (CORE_ADDR addr,
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
-decode_ret (CORE_ADDR addr, uint32_t insn, unsigned *rn)
+aarch64_decode_ret (CORE_ADDR addr, uint32_t insn, unsigned *rn)
{
if (decode_masked_match (insn, 0xfffffc1f, 0xd65f0000))
{
@@ -526,9 +410,8 @@ decode_ret (CORE_ADDR addr, uint32_t insn, unsigned *rn)
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
-decode_stp_offset (CORE_ADDR addr,
- uint32_t insn,
- unsigned *rt1, unsigned *rt2, unsigned *rn, int32_t *imm)
+aarch64_decode_stp_offset (CORE_ADDR addr, uint32_t insn, unsigned *rt1,
+ unsigned *rt2, unsigned *rn, int32_t *imm)
{
if (decode_masked_match (insn, 0xffc00000, 0xa9000000))
{
@@ -560,10 +443,8 @@ decode_stp_offset (CORE_ADDR addr,
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
-decode_stp_offset_wb (CORE_ADDR addr,
- uint32_t insn,
- unsigned *rt1, unsigned *rt2, unsigned *rn,
- int32_t *imm)
+aarch64_decode_stp_offset_wb (CORE_ADDR addr, uint32_t insn, unsigned *rt1,
+ unsigned *rt2, unsigned *rn, int32_t *imm)
{
if (decode_masked_match (insn, 0xffc00000, 0xa9800000))
{
@@ -595,8 +476,8 @@ decode_stp_offset_wb (CORE_ADDR addr,
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
-decode_stur (CORE_ADDR addr, uint32_t insn, int *is64, unsigned *rt,
- unsigned *rn, int32_t *imm)
+aarch64_decode_stur (CORE_ADDR addr, uint32_t insn, int *is64,
+ unsigned *rt, unsigned *rn, int32_t *imm)
{
if (decode_masked_match (insn, 0xbfe00c00, 0xb8000000))
{
@@ -614,40 +495,6 @@ decode_stur (CORE_ADDR addr, uint32_t insn, int *is64, unsigned *rt,
return 0;
}
-/* Decode an opcode if it represents a TBZ or TBNZ instruction.
-
- ADDR specifies the address of the opcode.
- INSN specifies the opcode to test.
- IS_TBNZ receives the 'op' field from the decoded instruction.
- BIT receives the bit position field from the decoded instruction.
- RT receives 'rt' field from the decoded instruction.
- IMM receives 'imm' field from the decoded instruction.
-
- Return 1 if the opcodes matches and is decoded, otherwise 0. */
-
-static int
-decode_tb (CORE_ADDR addr, uint32_t insn, int *is_tbnz, unsigned *bit,
- unsigned *rt, int32_t *imm)
-{
- /* tbz b011 0110 bbbb biii iiii iiii iiir rrrr */
- /* tbnz B011 0111 bbbb biii iiii iiii iiir rrrr */
- if (decode_masked_match (insn, 0x7e000000, 0x36000000))
- {
- *rt = (insn >> 0) & 0x1f;
- *is_tbnz = (insn >> 24) & 0x1;
- *bit = ((insn >> (31 - 4)) & 0x20) | ((insn >> 19) & 0x1f);
- *imm = extract_signed_bitfield (insn, 14, 5) << 2;
-
- if (aarch64_debug)
- debug_printf ("decode: 0x%s 0x%x %s x%u, #%u, 0x%s\n",
- core_addr_to_string_nz (addr), insn,
- *is_tbnz ? "tbnz" : "tbz", *rt, *bit,
- core_addr_to_string_nz (addr + *imm));
- return 1;
- }
- return 0;
-}
-
/* Analyze a prologue, looking for a recognizable stack frame
and frame pointer. Scan until we encounter a store that could
clobber the stack frame unexpectedly, or an unknown instruction. */
@@ -689,39 +536,40 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
insn = read_memory_unsigned_integer (start, 4, byte_order_for_code);
- if (decode_add_sub_imm (start, insn, &rd, &rn, &imm))
+ if (aarch64_decode_add_sub_imm (start, insn, &rd, &rn, &imm))
regs[rd] = pv_add_constant (regs[rn], imm);
- else if (decode_adrp (start, insn, &rd))
+ else if (aarch64_decode_adrp (start, insn, &rd))
regs[rd] = pv_unknown ();
- else if (decode_b (start, insn, &is_link, &offset))
+ else if (aarch64_decode_b (start, insn, &is_link, &offset))
{
/* Stop analysis on branch. */
break;
}
- else if (decode_bcond (start, insn, &cond, &offset))
+ else if (aarch64_decode_bcond (start, insn, &cond, &offset))
{
/* Stop analysis on branch. */
break;
}
- else if (decode_br (start, insn, &is_link, &rn))
+ else if (aarch64_decode_br (start, insn, &is_link, &rn))
{
/* Stop analysis on branch. */
break;
}
- else if (decode_cb (start, insn, &is64, &is_cbnz, &rn, &offset))
+ else if (aarch64_decode_cb (start, insn, &is64, &is_cbnz, &rn,
+ &offset))
{
/* Stop analysis on branch. */
break;
}
- else if (decode_eret (start, insn))
+ else if (aarch64_decode_eret (start, insn))
{
/* Stop analysis on branch. */
break;
}
- else if (decode_movz (start, insn, &rd))
+ else if (aarch64_decode_movz (start, insn, &rd))
regs[rd] = pv_unknown ();
- else
- if (decode_orr_shifted_register_x (start, insn, &rd, &rn, &rm, &imm))
+ else if (aarch64_decode_orr_shifted_register_x (start, insn, &rd,
+ &rn, &rm, &imm))
{
if (imm == 0 && rn == 31)
regs[rd] = regs[rm];
@@ -734,17 +582,18 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
break;
}
}
- else if (decode_ret (start, insn, &rn))
+ else if (aarch64_decode_ret (start, insn, &rn))
{
/* Stop analysis on branch. */
break;
}
- else if (decode_stur (start, insn, &is64, &rt, &rn, &offset))
+ else if (aarch64_decode_stur (start, insn, &is64, &rt, &rn, &offset))
{
pv_area_store (stack, pv_add_constant (regs[rn], offset),
is64 ? 8 : 4, regs[rt]);
}
- else if (decode_stp_offset (start, insn, &rt1, &rt2, &rn, &imm))
+ else if (aarch64_decode_stp_offset (start, insn, &rt1, &rt2, &rn,
+ &imm))
{
/* If recording this store would invalidate the store area
(perhaps because rn is not known) then we should abandon
@@ -762,7 +611,8 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
pv_area_store (stack, pv_add_constant (regs[rn], imm + 8), 8,
regs[rt2]);
}
- else if (decode_stp_offset_wb (start, insn, &rt1, &rt2, &rn, &imm))
+ else if (aarch64_decode_stp_offset_wb (start, insn, &rt1, &rt2, &rn,
+ &imm))
{
/* If recording this store would invalidate the store area
(perhaps because rn is not known) then we should abandon
@@ -781,7 +631,8 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
regs[rt2]);
regs[rn] = pv_add_constant (regs[rn], imm);
}
- else if (decode_tb (start, insn, &is_tbnz, &bit, &rn, &offset))
+ else if (aarch64_decode_tb (start, insn, &is_tbnz, &bit, &rn,
+ &offset))
{
/* Stop analysis on branch. */
break;
@@ -2616,7 +2467,7 @@ aarch64_software_single_step (struct frame_info *frame)
byte_order_for_code);
/* Check if the instruction is a conditional branch. */
- if (decode_bcond (loc, insn, &cond, &offset))
+ if (aarch64_decode_bcond (loc, insn, &cond, &offset))
{
if (bc_insn_count >= 1)
return 0;
diff --git a/gdb/arch/aarch64-insn.c b/gdb/arch/aarch64-insn.c
new file mode 100644
index 0000000..9834b9d
--- /dev/null
+++ b/gdb/arch/aarch64-insn.c
@@ -0,0 +1,208 @@
+/* Copyright (C) 2009-2015 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#include "common-defs.h"
+#include "aarch64-insn.h"
+
+/* Toggle this file's internal debugging dump. */
+int aarch64_debug = 0;
+
+/* Extract a signed value from a bit field within an instruction
+ encoding.
+
+ INSN is the instruction opcode.
+
+ WIDTH specifies the width of the bit field to extract (in bits).
+
+ OFFSET specifies the least significant bit of the field where bits
+ are numbered zero counting from least to most significant. */
+
+static int32_t
+extract_signed_bitfield (uint32_t insn, unsigned width, unsigned offset)
+{
+ unsigned shift_l = sizeof (int32_t) * 8 - (offset + width);
+ unsigned shift_r = sizeof (int32_t) * 8 - width;
+
+ return ((int32_t) insn << shift_l) >> shift_r;
+}
+
+/* Determine if specified bits within an instruction opcode matches a
+ specific pattern.
+
+ INSN is the instruction opcode.
+
+ MASK specifies the bits within the opcode that are to be tested
+ agsinst for a match with PATTERN. */
+
+static int
+decode_masked_match (uint32_t insn, uint32_t mask, uint32_t pattern)
+{
+ return (insn & mask) == pattern;
+}
+
+/* Decode an opcode if it represents an ADRP instruction.
+
+ ADDR specifies the address of the opcode.
+ INSN specifies the opcode to test.
+ RD receives the 'rd' field from the decoded instruction.
+
+ Return 1 if the opcodes matches and is decoded, otherwise 0. */
+
+int
+aarch64_decode_adrp (CORE_ADDR addr, uint32_t insn, unsigned *rd)
+{
+ if (decode_masked_match (insn, 0x9f000000, 0x90000000))
+ {
+ *rd = (insn >> 0) & 0x1f;
+
+ if (aarch64_debug)
+ debug_printf ("decode: 0x%s 0x%x adrp x%u, #?\n",
+ core_addr_to_string_nz (addr), insn, *rd);
+ return 1;
+ }
+ return 0;
+}
+
+/* Decode an opcode if it represents an branch immediate or branch
+ and link immediate instruction.
+
+ ADDR specifies the address of the opcode.
+ INSN specifies the opcode to test.
+ IS_BL receives the 'op' bit from the decoded instruction.
+ OFFSET receives the immediate offset from the decoded instruction.
+
+ Return 1 if the opcodes matches and is decoded, otherwise 0. */
+
+int
+aarch64_decode_b (CORE_ADDR addr, uint32_t insn, int *is_bl,
+ int32_t *offset)
+{
+ /* b 0001 01ii iiii iiii iiii iiii iiii iiii */
+ /* bl 1001 01ii iiii iiii iiii iiii iiii iiii */
+ if (decode_masked_match (insn, 0x7c000000, 0x14000000))
+ {
+ *is_bl = (insn >> 31) & 0x1;
+ *offset = extract_signed_bitfield (insn, 26, 0) << 2;
+
+ if (aarch64_debug)
+ debug_printf ("decode: 0x%s 0x%x %s 0x%s\n",
+ core_addr_to_string_nz (addr), insn,
+ *is_bl ? "bl" : "b",
+ core_addr_to_string_nz (addr + *offset));
+
+ return 1;
+ }
+ return 0;
+}
+
+/* Decode an opcode if it represents a conditional branch instruction.
+
+ ADDR specifies the address of the opcode.
+ INSN specifies the opcode to test.
+ COND receives the branch condition field from the decoded
+ instruction.
+ OFFSET receives the immediate offset from the decoded instruction.
+
+ Return 1 if the opcodes matches and is decoded, otherwise 0. */
+
+int
+aarch64_decode_bcond (CORE_ADDR addr, uint32_t insn, unsigned *cond,
+ int32_t *offset)
+{
+ /* b.cond 0101 0100 iiii iiii iiii iiii iii0 cccc */
+ if (decode_masked_match (insn, 0xff000010, 0x54000000))
+ {
+ *cond = (insn >> 0) & 0xf;
+ *offset = extract_signed_bitfield (insn, 19, 5) << 2;
+
+ if (aarch64_debug)
+ debug_printf ("decode: 0x%s 0x%x b<%u> 0x%s\n",
+ core_addr_to_string_nz (addr), insn, *cond,
+ core_addr_to_string_nz (addr + *offset));
+ return 1;
+ }
+ return 0;
+}
+
+/* Decode an opcode if it represents a CBZ or CBNZ instruction.
+
+ ADDR specifies the address of the opcode.
+ INSN specifies the opcode to test.
+ IS64 receives the 'sf' field from the decoded instruction.
+ IS_CBNZ receives the 'op' field from the decoded instruction.
+ RN receives the 'rn' field from the decoded instruction.
+ OFFSET receives the 'imm19' field from the decoded instruction.
+
+ Return 1 if the opcodes matches and is decoded, otherwise 0. */
+
+int
+aarch64_decode_cb (CORE_ADDR addr, uint32_t insn, int *is64, int *is_cbnz,
+ unsigned *rn, int32_t *offset)
+{
+ /* cbz T011 010o iiii iiii iiii iiii iiir rrrr */
+ /* cbnz T011 010o iiii iiii iiii iiii iiir rrrr */
+ if (decode_masked_match (insn, 0x7e000000, 0x34000000))
+ {
+ *rn = (insn >> 0) & 0x1f;
+ *is64 = (insn >> 31) & 0x1;
+ *is_cbnz = (insn >> 24) & 0x1;
+ *offset = extract_signed_bitfield (insn, 19, 5) << 2;
+
+ if (aarch64_debug)
+ debug_printf ("decode: 0x%s 0x%x %s 0x%s\n",
+ core_addr_to_string_nz (addr), insn,
+ *is_cbnz ? "cbnz" : "cbz",
+ core_addr_to_string_nz (addr + *offset));
+ return 1;
+ }
+ return 0;
+}
+
+/* Decode an opcode if it represents a TBZ or TBNZ instruction.
+
+ ADDR specifies the address of the opcode.
+ INSN specifies the opcode to test.
+ IS_TBNZ receives the 'op' field from the decoded instruction.
+ BIT receives the bit position field from the decoded instruction.
+ RT receives 'rt' field from the decoded instruction.
+ IMM receives 'imm' field from the decoded instruction.
+
+ Return 1 if the opcodes matches and is decoded, otherwise 0. */
+
+int
+aarch64_decode_tb (CORE_ADDR addr, uint32_t insn, int *is_tbnz,
+ unsigned *bit, unsigned *rt, int32_t *imm)
+{
+ /* tbz b011 0110 bbbb biii iiii iiii iiir rrrr */
+ /* tbnz B011 0111 bbbb biii iiii iiii iiir rrrr */
+ if (decode_masked_match (insn, 0x7e000000, 0x36000000))
+ {
+ *rt = (insn >> 0) & 0x1f;
+ *is_tbnz = (insn >> 24) & 0x1;
+ *bit = ((insn >> (31 - 4)) & 0x20) | ((insn >> 19) & 0x1f);
+ *imm = extract_signed_bitfield (insn, 14, 5) << 2;
+
+ if (aarch64_debug)
+ debug_printf ("decode: 0x%s 0x%x %s x%u, #%u, 0x%s\n",
+ core_addr_to_string_nz (addr), insn,
+ *is_tbnz ? "tbnz" : "tbz", *rt, *bit,
+ core_addr_to_string_nz (addr + *imm));
+ return 1;
+ }
+ return 0;
+}
diff --git a/gdb/arch/aarch64-insn.h b/gdb/arch/aarch64-insn.h
new file mode 100644
index 0000000..7775a34
--- /dev/null
+++ b/gdb/arch/aarch64-insn.h
@@ -0,0 +1,38 @@
+/* Copyright (C) 2009-2015 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#ifndef AARCH64_INSN_H
+#define AARCH64_INSN_H 1
+
+extern int aarch64_debug;
+
+int aarch64_decode_adrp (CORE_ADDR addr, uint32_t insn, unsigned *rd);
+
+int aarch64_decode_b (CORE_ADDR addr, uint32_t insn, int *is_bl,
+ int32_t *offset);
+
+int aarch64_decode_bcond (CORE_ADDR addr, uint32_t insn, unsigned *cond,
+ int32_t *offset);
+
+int aarch64_decode_cb (CORE_ADDR addr, uint32_t insn, int *is64,
+ int *is_cbnz, unsigned *rn, int32_t *offset);
+
+int aarch64_decode_tb (CORE_ADDR addr, uint32_t insn, int *is_tbnz,
+ unsigned *bit, unsigned *rt, int32_t *imm);
+
+#endif
diff --git a/gdb/configure.tgt b/gdb/configure.tgt
index c42b4df..33d4cfc 100644
--- a/gdb/configure.tgt
+++ b/gdb/configure.tgt
@@ -38,12 +38,12 @@ esac
case "${targ}" in
aarch64*-*-elf)
# Target: AArch64 embedded system
- gdb_target_obs="aarch64-tdep.o aarch64-newlib-tdep.o"
+ gdb_target_obs="aarch64-tdep.o aarch64-newlib-tdep.o aarch64-insn.o"
;;
aarch64*-*-linux*)
# Target: AArch64 linux
- gdb_target_obs="aarch64-tdep.o aarch64-linux-tdep.o \
+ gdb_target_obs="aarch64-tdep.o aarch64-linux-tdep.o aarch64-insn.o \
arm-tdep.o arm-linux-tdep.o \
glibc-tdep.o linux-tdep.o solib-svr4.o \
symfile-mem.o linux-record.o"
diff --git a/gdb/gdbserver/Makefile.in b/gdb/gdbserver/Makefile.in
index b715a32..d096663 100644
--- a/gdb/gdbserver/Makefile.in
+++ b/gdb/gdbserver/Makefile.in
@@ -625,6 +625,12 @@ linux-namespaces.o: ../nat/linux-namespaces.c
$(COMPILE) $<
$(POSTCOMPILE)
+# Architecture specific object files rules from ../arch
+
+aarch64-insn.o: ../arch/aarch64-insn.c
+ $(COMPILE) $<
+ $(POSTCOMPILE)
+
aarch64.c : $(srcdir)/../regformats/aarch64.dat $(regdat_sh)
$(SHELL) $(regdat_sh) $(srcdir)/../regformats/aarch64.dat aarch64.c
reg-arm.c : $(srcdir)/../regformats/reg-arm.dat $(regdat_sh)
diff --git a/gdb/gdbserver/configure.srv b/gdb/gdbserver/configure.srv
index aa232f8..d263381 100644
--- a/gdb/gdbserver/configure.srv
+++ b/gdb/gdbserver/configure.srv
@@ -50,7 +50,7 @@ case "${target}" in
aarch64*-*-linux*)
srv_regobj="aarch64.o"
srv_regobj="${srv_regobj} arm-with-neon.o"
- srv_tgtobj="linux-aarch64-low.o aarch64-linux-hw-point.o"
+ srv_tgtobj="linux-aarch64-low.o aarch64-linux-hw-point.o aarch64-insn.o"
srv_tgtobj="$srv_tgtobj linux-aarch32-low.o"
srv_tgtobj="$srv_tgtobj aarch64-linux.o"
srv_tgtobj="${srv_tgtobj} $srv_linux_obj"
--
2.4.6
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [PATCH 2/8] [AArch64] Move instruction decoding into new arch/ directory
2015-09-14 11:38 ` [PATCH 2/8] [AArch64] Move instruction decoding into new arch/ directory Pierre Langlois
@ 2015-09-15 10:10 ` Yao Qi
2015-09-15 12:02 ` [PATCH 2/8 v2] " Pierre Langlois
0 siblings, 1 reply; 37+ messages in thread
From: Yao Qi @ 2015-09-15 10:10 UTC (permalink / raw)
To: Pierre Langlois; +Cc: gdb-patches
Pierre Langlois <pierre.langlois@arm.com> writes:
> diff --git a/gdb/gdbserver/configure.srv b/gdb/gdbserver/configure.srv
> index aa232f8..d263381 100644
> --- a/gdb/gdbserver/configure.srv
> +++ b/gdb/gdbserver/configure.srv
> @@ -50,7 +50,7 @@ case "${target}" in
> aarch64*-*-linux*)
> srv_regobj="aarch64.o"
> srv_regobj="${srv_regobj} arm-with-neon.o"
> - srv_tgtobj="linux-aarch64-low.o aarch64-linux-hw-point.o"
> + srv_tgtobj="linux-aarch64-low.o aarch64-linux-hw-point.o aarch64-insn.o"
This line is too lone. Please shorten it like what are doing below.
> srv_tgtobj="$srv_tgtobj linux-aarch32-low.o"
> srv_tgtobj="$srv_tgtobj aarch64-linux.o"
> srv_tgtobj="${srv_tgtobj} $srv_linux_obj"
Otherwise, that patch is OK.
--
Yao (齐尧)
^ permalink raw reply [flat|nested] 37+ messages in thread* [PATCH 2/8 v2] [AArch64] Move instruction decoding into new arch/ directory
2015-09-15 10:10 ` Yao Qi
@ 2015-09-15 12:02 ` Pierre Langlois
0 siblings, 0 replies; 37+ messages in thread
From: Pierre Langlois @ 2015-09-15 12:02 UTC (permalink / raw)
To: gdb-patches; +Cc: Pierre Langlois
Here is the rebased patch, making sure the formatting issues propagated
through moving file. I've also fixed `gdbserver/configure.srv'.
Thanks,
Pierre
---
This patch moves the following functions into the arch/ common
directory, in new files arch/aarch64-insn.{h,c}. They are prefixed with
'aarch64_':
- aarch64_decode_adrp
- aarch64_decode_b
- aarch64_decode_cb
- aarch64_decode_tb
We will need them to implement fast tracepoints in GDBserver.
For consistency, this patch also adds the 'aarch64_' prefix to static
decoding functions that do not need to be shared right now.
gdb/ChangeLog:
* Makefile.in (ALL_64_TARGET_OBS): Add aarch64-insn.o.
(HFILES_NO_SRCDIR): Add arch/aarch64-insn.h.
(aarch64-insn.o): New rule.
* configure.tgt (aarch64*-*-elf): Add aarch64-insn.o.
(aarch64*-*-linux*): Likewise.
* arch/aarch64-insn.c: New file.
* arch/aarch64-insn.h: New file.
* aarch64-tdep.c: Include arch/aarch64-insn.h.
(aarch64_debug): Move to arch/aarch64-insn.c. Declare in
arch/aarch64-insn.h.
(decode_add_sub_imm): Rename to ...
(aarch64_decode_add_sub_imm): ... this.
(decode_adrp): Rename to ...
(aarch64_decode_adrp): ... this. Move to arch/aarch64-insn.c.
Declare in arch/aarch64-insn.h.
(decode_b): Rename to ...
(aarch64_decode_b): ... this. Move to arch/aarch64-insn.c.
Declare in arch/aarch64-insn.h.
(decode_bcond): Rename to ...
(aarch64_decode_bcond): ... this. Move to arch/aarch64-insn.c.
Declare in arch/aarch64-insn.h.
(decode_br): Rename to ...
(aarch64_decode_br): ... this.
(decode_cb): Rename to ...
(aarch64_decode_cb): ... this. Move to arch/aarch64-insn.c.
Declare in arch/aarch64-insn.h.
(decode_eret): Rename to ...
(aarch64_decode_eret): ... this.
(decode_movz): Rename to ...
(aarch64_decode_movz): ... this.
(decode_orr_shifted_register_x): Rename to ...
(aarch64_decode_orr_shifted_register_x): ... this.
(decode_ret): Rename to ...
(aarch64_decode_ret): ... this.
(decode_stp_offset): Rename to ...
(aarch64_decode_stp_offset): ... this.
(decode_stp_offset_wb): Rename to ...
(aarch64_decode_stp_offset_wb): ... this.
(decode_stur): Rename to ...
(aarch64_decode_stur): ... this.
(decode_tb): Rename to ...
(aarch64_decode_tb): ... this. Move to arch/aarch64-insn.c.
Declare in arch/aarch64-insn.h.
(aarch64_analyze_prologue): Adjust calls to renamed functions.
gdb/gdbserver/ChangeLog:
* gdb/gdbserver/Makefile.in (aarch64-insn.o): New rule.
* gdb/gdbserver/configure.srv (aarch64*-*-linux*): Add
aarch64-insn.o.
---
gdb/Makefile.in | 13 ++-
gdb/aarch64-tdep.c | 235 +++++++-------------------------------------
gdb/arch/aarch64-insn.c | 218 ++++++++++++++++++++++++++++++++++++++++
gdb/arch/aarch64-insn.h | 38 +++++++
gdb/configure.tgt | 4 +-
gdb/gdbserver/Makefile.in | 6 ++
gdb/gdbserver/configure.srv | 1 +
7 files changed, 314 insertions(+), 201 deletions(-)
create mode 100644 gdb/arch/aarch64-insn.c
create mode 100644 gdb/arch/aarch64-insn.h
diff --git a/gdb/Makefile.in b/gdb/Makefile.in
index 5659116..d5ca2ee 100644
--- a/gdb/Makefile.in
+++ b/gdb/Makefile.in
@@ -644,7 +644,7 @@ TARGET_OBS = @TARGET_OBS@
# All target-dependent objects files that require 64-bit CORE_ADDR
# (used with --enable-targets=all --enable-64-bit-bfd).
ALL_64_TARGET_OBS = \
- aarch64-tdep.o aarch64-linux-tdep.o aarch64-newlib-tdep.o \
+ aarch64-tdep.o aarch64-linux-tdep.o aarch64-newlib-tdep.o aarch64-insn.o \
alphabsd-tdep.o alphafbsd-tdep.o alpha-linux-tdep.o alpha-mdebug-tdep.o \
alphanbsd-tdep.o alphaobsd-tdep.o alpha-tdep.o \
amd64fbsd-tdep.o amd64-darwin-tdep.o amd64-dicos-tdep.o \
@@ -986,7 +986,7 @@ common/common-debug.h common/cleanups.h common/gdb_setjmp.h \
common/common-exceptions.h target/target.h common/symbol.h \
common/common-regcache.h fbsd-tdep.h nat/linux-personality.h \
common/fileio.h nat/x86-linux.h nat/x86-linux-dregs.h \
-nat/linux-namespaces.h arch/arm.h common/gdb_sys_time.h
+nat/linux-namespaces.h arch/arm.h common/gdb_sys_time.h arch/aarch64-insn.h
# Header files that already have srcdir in them, or which are in objdir.
@@ -2336,6 +2336,15 @@ aarch64-linux.o: ${srcdir}/nat/aarch64-linux.c
$(COMPILE) $(srcdir)/nat/aarch64-linux.c
$(POSTCOMPILE)
+# gdb/arch/ dependencies
+#
+# Need to explicitly specify the compile rule as make will do nothing
+# or try to compile the object file into the sub-directory.
+
+aarch64-insn.o: ${srcdir}/arch/aarch64-insn.c
+ $(COMPILE) $(srcdir)/arch/aarch64-insn.c
+ $(POSTCOMPILE)
+
#
# gdb/tui/ dependencies
#
diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index 9a4eda2..92e2404 100644
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -57,6 +57,8 @@
#include "features/aarch64.c"
+#include "arch/aarch64-insn.h"
+
/* Pseudo register base numbers. */
#define AARCH64_Q0_REGNUM 0
#define AARCH64_D0_REGNUM (AARCH64_Q0_REGNUM + 32)
@@ -179,9 +181,6 @@ struct aarch64_prologue_cache
struct trad_frame_saved_reg *saved_regs;
};
-/* Toggle this file's internal debugging dump. */
-static int aarch64_debug;
-
static void
show_aarch64_debug (struct ui_file *file, int from_tty,
struct cmd_list_element *c, const char *value)
@@ -231,8 +230,8 @@ decode_masked_match (uint32_t insn, uint32_t mask, uint32_t pattern)
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
-decode_add_sub_imm (CORE_ADDR addr, uint32_t insn, unsigned *rd, unsigned *rn,
- int32_t *imm)
+aarch64_decode_add_sub_imm (CORE_ADDR addr, uint32_t insn, unsigned *rd,
+ unsigned *rn, int32_t *imm)
{
if ((insn & 0x9f000000) == 0x91000000)
{
@@ -271,94 +270,6 @@ decode_add_sub_imm (CORE_ADDR addr, uint32_t insn, unsigned *rd, unsigned *rn,
return 0;
}
-/* Decode an opcode if it represents an ADRP instruction.
-
- ADDR specifies the address of the opcode.
- INSN specifies the opcode to test.
- RD receives the 'rd' field from the decoded instruction.
-
- Return 1 if the opcodes matches and is decoded, otherwise 0. */
-
-static int
-decode_adrp (CORE_ADDR addr, uint32_t insn, unsigned *rd)
-{
- if (decode_masked_match (insn, 0x9f000000, 0x90000000))
- {
- *rd = (insn >> 0) & 0x1f;
-
- if (aarch64_debug)
- {
- debug_printf ("decode: 0x%s 0x%x adrp x%u, #?\n",
- core_addr_to_string_nz (addr), insn, *rd);
- }
- return 1;
- }
- return 0;
-}
-
-/* Decode an opcode if it represents an branch immediate or branch
- and link immediate instruction.
-
- ADDR specifies the address of the opcode.
- INSN specifies the opcode to test.
- IS_BL receives the 'op' bit from the decoded instruction.
- OFFSET receives the immediate offset from the decoded instruction.
-
- Return 1 if the opcodes matches and is decoded, otherwise 0. */
-
-static int
-decode_b (CORE_ADDR addr, uint32_t insn, int *is_bl, int32_t *offset)
-{
- /* b 0001 01ii iiii iiii iiii iiii iiii iiii */
- /* bl 1001 01ii iiii iiii iiii iiii iiii iiii */
- if (decode_masked_match (insn, 0x7c000000, 0x14000000))
- {
- *is_bl = (insn >> 31) & 0x1;
- *offset = extract_signed_bitfield (insn, 26, 0) << 2;
-
- if (aarch64_debug)
- {
- debug_printf ("decode: 0x%s 0x%x %s 0x%s\n",
- core_addr_to_string_nz (addr), insn,
- *is_bl ? "bl" : "b",
- core_addr_to_string_nz (addr + *offset));
- }
-
- return 1;
- }
- return 0;
-}
-
-/* Decode an opcode if it represents a conditional branch instruction.
-
- ADDR specifies the address of the opcode.
- INSN specifies the opcode to test.
- COND receives the branch condition field from the decoded
- instruction.
- OFFSET receives the immediate offset from the decoded instruction.
-
- Return 1 if the opcodes matches and is decoded, otherwise 0. */
-
-static int
-decode_bcond (CORE_ADDR addr, uint32_t insn, unsigned *cond, int32_t *offset)
-{
- /* b.cond 0101 0100 iiii iiii iiii iiii iii0 cccc */
- if (decode_masked_match (insn, 0xff000010, 0x54000000))
- {
- *cond = (insn >> 0) & 0xf;
- *offset = extract_signed_bitfield (insn, 19, 5) << 2;
-
- if (aarch64_debug)
- {
- debug_printf ("decode: 0x%s 0x%x b<%u> 0x%s\n",
- core_addr_to_string_nz (addr), insn, *cond,
- core_addr_to_string_nz (addr + *offset));
- }
- return 1;
- }
- return 0;
-}
-
/* Decode an opcode if it represents a branch via register instruction.
ADDR specifies the address of the opcode.
@@ -369,7 +280,8 @@ decode_bcond (CORE_ADDR addr, uint32_t insn, unsigned *cond, int32_t *offset)
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
-decode_br (CORE_ADDR addr, uint32_t insn, int *is_blr, unsigned *rn)
+aarch64_decode_br (CORE_ADDR addr, uint32_t insn, int *is_blr,
+ unsigned *rn)
{
/* 8 4 0 6 2 8 4 0 */
/* blr 110101100011111100000000000rrrrr */
@@ -391,42 +303,6 @@ decode_br (CORE_ADDR addr, uint32_t insn, int *is_blr, unsigned *rn)
return 0;
}
-/* Decode an opcode if it represents a CBZ or CBNZ instruction.
-
- ADDR specifies the address of the opcode.
- INSN specifies the opcode to test.
- IS64 receives the 'sf' field from the decoded instruction.
- IS_CBNZ receives the 'op' field from the decoded instruction.
- RN receives the 'rn' field from the decoded instruction.
- OFFSET receives the 'imm19' field from the decoded instruction.
-
- Return 1 if the opcodes matches and is decoded, otherwise 0. */
-
-static int
-decode_cb (CORE_ADDR addr, uint32_t insn, int *is64, int *is_cbnz,
- unsigned *rn, int32_t *offset)
-{
- /* cbz T011 010o iiii iiii iiii iiii iiir rrrr */
- /* cbnz T011 010o iiii iiii iiii iiii iiir rrrr */
- if (decode_masked_match (insn, 0x7e000000, 0x34000000))
- {
- *rn = (insn >> 0) & 0x1f;
- *is64 = (insn >> 31) & 0x1;
- *is_cbnz = (insn >> 24) & 0x1;
- *offset = extract_signed_bitfield (insn, 19, 5) << 2;
-
- if (aarch64_debug)
- {
- debug_printf ("decode: 0x%s 0x%x %s 0x%s\n",
- core_addr_to_string_nz (addr), insn,
- *is_cbnz ? "cbnz" : "cbz",
- core_addr_to_string_nz (addr + *offset));
- }
- return 1;
- }
- return 0;
-}
-
/* Decode an opcode if it represents a ERET instruction.
ADDR specifies the address of the opcode.
@@ -435,7 +311,7 @@ decode_cb (CORE_ADDR addr, uint32_t insn, int *is64, int *is_cbnz,
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
-decode_eret (CORE_ADDR addr, uint32_t insn)
+aarch64_decode_eret (CORE_ADDR addr, uint32_t insn)
{
/* eret 1101 0110 1001 1111 0000 0011 1110 0000 */
if (insn == 0xd69f03e0)
@@ -459,7 +335,7 @@ decode_eret (CORE_ADDR addr, uint32_t insn)
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
-decode_movz (CORE_ADDR addr, uint32_t insn, unsigned *rd)
+aarch64_decode_movz (CORE_ADDR addr, uint32_t insn, unsigned *rd)
{
if (decode_masked_match (insn, 0xff800000, 0x52800000))
{
@@ -488,9 +364,9 @@ decode_movz (CORE_ADDR addr, uint32_t insn, unsigned *rd)
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
-decode_orr_shifted_register_x (CORE_ADDR addr,
- uint32_t insn, unsigned *rd, unsigned *rn,
- unsigned *rm, int32_t *imm)
+aarch64_decode_orr_shifted_register_x (CORE_ADDR addr, uint32_t insn,
+ unsigned *rd, unsigned *rn,
+ unsigned *rm, int32_t *imm)
{
if (decode_masked_match (insn, 0xff200000, 0xaa000000))
{
@@ -519,7 +395,7 @@ decode_orr_shifted_register_x (CORE_ADDR addr,
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
-decode_ret (CORE_ADDR addr, uint32_t insn, unsigned *rn)
+aarch64_decode_ret (CORE_ADDR addr, uint32_t insn, unsigned *rn)
{
if (decode_masked_match (insn, 0xfffffc1f, 0xd65f0000))
{
@@ -547,9 +423,8 @@ decode_ret (CORE_ADDR addr, uint32_t insn, unsigned *rn)
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
-decode_stp_offset (CORE_ADDR addr,
- uint32_t insn,
- unsigned *rt1, unsigned *rt2, unsigned *rn, int32_t *imm)
+aarch64_decode_stp_offset (CORE_ADDR addr, uint32_t insn, unsigned *rt1,
+ unsigned *rt2, unsigned *rn, int32_t *imm)
{
if (decode_masked_match (insn, 0xffc00000, 0xa9000000))
{
@@ -583,10 +458,8 @@ decode_stp_offset (CORE_ADDR addr,
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
-decode_stp_offset_wb (CORE_ADDR addr,
- uint32_t insn,
- unsigned *rt1, unsigned *rt2, unsigned *rn,
- int32_t *imm)
+aarch64_decode_stp_offset_wb (CORE_ADDR addr, uint32_t insn, unsigned *rt1,
+ unsigned *rt2, unsigned *rn, int32_t *imm)
{
if (decode_masked_match (insn, 0xffc00000, 0xa9800000))
{
@@ -620,8 +493,8 @@ decode_stp_offset_wb (CORE_ADDR addr,
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
-decode_stur (CORE_ADDR addr, uint32_t insn, int *is64, unsigned *rt,
- unsigned *rn, int32_t *imm)
+aarch64_decode_stur (CORE_ADDR addr, uint32_t insn, int *is64,
+ unsigned *rt, unsigned *rn, int32_t *imm)
{
if (decode_masked_match (insn, 0xbfe00c00, 0xb8000000))
{
@@ -641,42 +514,6 @@ decode_stur (CORE_ADDR addr, uint32_t insn, int *is64, unsigned *rt,
return 0;
}
-/* Decode an opcode if it represents a TBZ or TBNZ instruction.
-
- ADDR specifies the address of the opcode.
- INSN specifies the opcode to test.
- IS_TBNZ receives the 'op' field from the decoded instruction.
- BIT receives the bit position field from the decoded instruction.
- RT receives 'rt' field from the decoded instruction.
- IMM receives 'imm' field from the decoded instruction.
-
- Return 1 if the opcodes matches and is decoded, otherwise 0. */
-
-static int
-decode_tb (CORE_ADDR addr, uint32_t insn, int *is_tbnz, unsigned *bit,
- unsigned *rt, int32_t *imm)
-{
- /* tbz b011 0110 bbbb biii iiii iiii iiir rrrr */
- /* tbnz B011 0111 bbbb biii iiii iiii iiir rrrr */
- if (decode_masked_match (insn, 0x7e000000, 0x36000000))
- {
- *rt = (insn >> 0) & 0x1f;
- *is_tbnz = (insn >> 24) & 0x1;
- *bit = ((insn >> (31 - 4)) & 0x20) | ((insn >> 19) & 0x1f);
- *imm = extract_signed_bitfield (insn, 14, 5) << 2;
-
- if (aarch64_debug)
- {
- debug_printf ("decode: 0x%s 0x%x %s x%u, #%u, 0x%s\n",
- core_addr_to_string_nz (addr), insn,
- *is_tbnz ? "tbnz" : "tbz", *rt, *bit,
- core_addr_to_string_nz (addr + *imm));
- }
- return 1;
- }
- return 0;
-}
-
/* Analyze a prologue, looking for a recognizable stack frame
and frame pointer. Scan until we encounter a store that could
clobber the stack frame unexpectedly, or an unknown instruction. */
@@ -718,39 +555,40 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
insn = read_memory_unsigned_integer (start, 4, byte_order_for_code);
- if (decode_add_sub_imm (start, insn, &rd, &rn, &imm))
+ if (aarch64_decode_add_sub_imm (start, insn, &rd, &rn, &imm))
regs[rd] = pv_add_constant (regs[rn], imm);
- else if (decode_adrp (start, insn, &rd))
+ else if (aarch64_decode_adrp (start, insn, &rd))
regs[rd] = pv_unknown ();
- else if (decode_b (start, insn, &is_link, &offset))
+ else if (aarch64_decode_b (start, insn, &is_link, &offset))
{
/* Stop analysis on branch. */
break;
}
- else if (decode_bcond (start, insn, &cond, &offset))
+ else if (aarch64_decode_bcond (start, insn, &cond, &offset))
{
/* Stop analysis on branch. */
break;
}
- else if (decode_br (start, insn, &is_link, &rn))
+ else if (aarch64_decode_br (start, insn, &is_link, &rn))
{
/* Stop analysis on branch. */
break;
}
- else if (decode_cb (start, insn, &is64, &is_cbnz, &rn, &offset))
+ else if (aarch64_decode_cb (start, insn, &is64, &is_cbnz, &rn,
+ &offset))
{
/* Stop analysis on branch. */
break;
}
- else if (decode_eret (start, insn))
+ else if (aarch64_decode_eret (start, insn))
{
/* Stop analysis on branch. */
break;
}
- else if (decode_movz (start, insn, &rd))
+ else if (aarch64_decode_movz (start, insn, &rd))
regs[rd] = pv_unknown ();
- else
- if (decode_orr_shifted_register_x (start, insn, &rd, &rn, &rm, &imm))
+ else if (aarch64_decode_orr_shifted_register_x (start, insn, &rd,
+ &rn, &rm, &imm))
{
if (imm == 0 && rn == 31)
regs[rd] = regs[rm];
@@ -765,17 +603,18 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
break;
}
}
- else if (decode_ret (start, insn, &rn))
+ else if (aarch64_decode_ret (start, insn, &rn))
{
/* Stop analysis on branch. */
break;
}
- else if (decode_stur (start, insn, &is64, &rt, &rn, &offset))
+ else if (aarch64_decode_stur (start, insn, &is64, &rt, &rn, &offset))
{
pv_area_store (stack, pv_add_constant (regs[rn], offset),
is64 ? 8 : 4, regs[rt]);
}
- else if (decode_stp_offset (start, insn, &rt1, &rt2, &rn, &imm))
+ else if (aarch64_decode_stp_offset (start, insn, &rt1, &rt2, &rn,
+ &imm))
{
/* If recording this store would invalidate the store area
(perhaps because rn is not known) then we should abandon
@@ -793,7 +632,8 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
pv_area_store (stack, pv_add_constant (regs[rn], imm + 8), 8,
regs[rt2]);
}
- else if (decode_stp_offset_wb (start, insn, &rt1, &rt2, &rn, &imm))
+ else if (aarch64_decode_stp_offset_wb (start, insn, &rt1, &rt2, &rn,
+ &imm))
{
/* If recording this store would invalidate the store area
(perhaps because rn is not known) then we should abandon
@@ -812,7 +652,8 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
regs[rt2]);
regs[rn] = pv_add_constant (regs[rn], imm);
}
- else if (decode_tb (start, insn, &is_tbnz, &bit, &rn, &offset))
+ else if (aarch64_decode_tb (start, insn, &is_tbnz, &bit, &rn,
+ &offset))
{
/* Stop analysis on branch. */
break;
@@ -2663,7 +2504,7 @@ aarch64_software_single_step (struct frame_info *frame)
byte_order_for_code);
/* Check if the instruction is a conditional branch. */
- if (decode_bcond (loc, insn, &cond, &offset))
+ if (aarch64_decode_bcond (loc, insn, &cond, &offset))
{
if (bc_insn_count >= 1)
return 0;
diff --git a/gdb/arch/aarch64-insn.c b/gdb/arch/aarch64-insn.c
new file mode 100644
index 0000000..3a289a2
--- /dev/null
+++ b/gdb/arch/aarch64-insn.c
@@ -0,0 +1,218 @@
+/* Copyright (C) 2009-2015 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#include "common-defs.h"
+#include "aarch64-insn.h"
+
+/* Toggle this file's internal debugging dump. */
+int aarch64_debug = 0;
+
+/* Extract a signed value from a bit field within an instruction
+ encoding.
+
+ INSN is the instruction opcode.
+
+ WIDTH specifies the width of the bit field to extract (in bits).
+
+ OFFSET specifies the least significant bit of the field where bits
+ are numbered zero counting from least to most significant. */
+
+static int32_t
+extract_signed_bitfield (uint32_t insn, unsigned width, unsigned offset)
+{
+ unsigned shift_l = sizeof (int32_t) * 8 - (offset + width);
+ unsigned shift_r = sizeof (int32_t) * 8 - width;
+
+ return ((int32_t) insn << shift_l) >> shift_r;
+}
+
+/* Determine if specified bits within an instruction opcode matches a
+ specific pattern.
+
+ INSN is the instruction opcode.
+
+ MASK specifies the bits within the opcode that are to be tested
+ agsinst for a match with PATTERN. */
+
+static int
+decode_masked_match (uint32_t insn, uint32_t mask, uint32_t pattern)
+{
+ return (insn & mask) == pattern;
+}
+
+/* Decode an opcode if it represents an ADRP instruction.
+
+ ADDR specifies the address of the opcode.
+ INSN specifies the opcode to test.
+ RD receives the 'rd' field from the decoded instruction.
+
+ Return 1 if the opcodes matches and is decoded, otherwise 0. */
+
+int
+aarch64_decode_adrp (CORE_ADDR addr, uint32_t insn, unsigned *rd)
+{
+ if (decode_masked_match (insn, 0x9f000000, 0x90000000))
+ {
+ *rd = (insn >> 0) & 0x1f;
+
+ if (aarch64_debug)
+ {
+ debug_printf ("decode: 0x%s 0x%x adrp x%u, #?\n",
+ core_addr_to_string_nz (addr), insn, *rd);
+ }
+ return 1;
+ }
+ return 0;
+}
+
+/* Decode an opcode if it represents an branch immediate or branch
+ and link immediate instruction.
+
+ ADDR specifies the address of the opcode.
+ INSN specifies the opcode to test.
+ IS_BL receives the 'op' bit from the decoded instruction.
+ OFFSET receives the immediate offset from the decoded instruction.
+
+ Return 1 if the opcodes matches and is decoded, otherwise 0. */
+
+int
+aarch64_decode_b (CORE_ADDR addr, uint32_t insn, int *is_bl,
+ int32_t *offset)
+{
+ /* b 0001 01ii iiii iiii iiii iiii iiii iiii */
+ /* bl 1001 01ii iiii iiii iiii iiii iiii iiii */
+ if (decode_masked_match (insn, 0x7c000000, 0x14000000))
+ {
+ *is_bl = (insn >> 31) & 0x1;
+ *offset = extract_signed_bitfield (insn, 26, 0) << 2;
+
+ if (aarch64_debug)
+ {
+ debug_printf ("decode: 0x%s 0x%x %s 0x%s\n",
+ core_addr_to_string_nz (addr), insn,
+ *is_bl ? "bl" : "b",
+ core_addr_to_string_nz (addr + *offset));
+ }
+
+ return 1;
+ }
+ return 0;
+}
+
+/* Decode an opcode if it represents a conditional branch instruction.
+
+ ADDR specifies the address of the opcode.
+ INSN specifies the opcode to test.
+ COND receives the branch condition field from the decoded
+ instruction.
+ OFFSET receives the immediate offset from the decoded instruction.
+
+ Return 1 if the opcodes matches and is decoded, otherwise 0. */
+
+int
+aarch64_decode_bcond (CORE_ADDR addr, uint32_t insn, unsigned *cond,
+ int32_t *offset)
+{
+ /* b.cond 0101 0100 iiii iiii iiii iiii iii0 cccc */
+ if (decode_masked_match (insn, 0xff000010, 0x54000000))
+ {
+ *cond = (insn >> 0) & 0xf;
+ *offset = extract_signed_bitfield (insn, 19, 5) << 2;
+
+ if (aarch64_debug)
+ {
+ debug_printf ("decode: 0x%s 0x%x b<%u> 0x%s\n",
+ core_addr_to_string_nz (addr), insn, *cond,
+ core_addr_to_string_nz (addr + *offset));
+ }
+ return 1;
+ }
+ return 0;
+}
+
+/* Decode an opcode if it represents a CBZ or CBNZ instruction.
+
+ ADDR specifies the address of the opcode.
+ INSN specifies the opcode to test.
+ IS64 receives the 'sf' field from the decoded instruction.
+ IS_CBNZ receives the 'op' field from the decoded instruction.
+ RN receives the 'rn' field from the decoded instruction.
+ OFFSET receives the 'imm19' field from the decoded instruction.
+
+ Return 1 if the opcodes matches and is decoded, otherwise 0. */
+
+int
+aarch64_decode_cb (CORE_ADDR addr, uint32_t insn, int *is64, int *is_cbnz,
+ unsigned *rn, int32_t *offset)
+{
+ /* cbz T011 010o iiii iiii iiii iiii iiir rrrr */
+ /* cbnz T011 010o iiii iiii iiii iiii iiir rrrr */
+ if (decode_masked_match (insn, 0x7e000000, 0x34000000))
+ {
+ *rn = (insn >> 0) & 0x1f;
+ *is64 = (insn >> 31) & 0x1;
+ *is_cbnz = (insn >> 24) & 0x1;
+ *offset = extract_signed_bitfield (insn, 19, 5) << 2;
+
+ if (aarch64_debug)
+ {
+ debug_printf ("decode: 0x%s 0x%x %s 0x%s\n",
+ core_addr_to_string_nz (addr), insn,
+ *is_cbnz ? "cbnz" : "cbz",
+ core_addr_to_string_nz (addr + *offset));
+ }
+ return 1;
+ }
+ return 0;
+}
+
+/* Decode an opcode if it represents a TBZ or TBNZ instruction.
+
+ ADDR specifies the address of the opcode.
+ INSN specifies the opcode to test.
+ IS_TBNZ receives the 'op' field from the decoded instruction.
+ BIT receives the bit position field from the decoded instruction.
+ RT receives 'rt' field from the decoded instruction.
+ IMM receives 'imm' field from the decoded instruction.
+
+ Return 1 if the opcodes matches and is decoded, otherwise 0. */
+
+int
+aarch64_decode_tb (CORE_ADDR addr, uint32_t insn, int *is_tbnz,
+ unsigned *bit, unsigned *rt, int32_t *imm)
+{
+ /* tbz b011 0110 bbbb biii iiii iiii iiir rrrr */
+ /* tbnz B011 0111 bbbb biii iiii iiii iiir rrrr */
+ if (decode_masked_match (insn, 0x7e000000, 0x36000000))
+ {
+ *rt = (insn >> 0) & 0x1f;
+ *is_tbnz = (insn >> 24) & 0x1;
+ *bit = ((insn >> (31 - 4)) & 0x20) | ((insn >> 19) & 0x1f);
+ *imm = extract_signed_bitfield (insn, 14, 5) << 2;
+
+ if (aarch64_debug)
+ {
+ debug_printf ("decode: 0x%s 0x%x %s x%u, #%u, 0x%s\n",
+ core_addr_to_string_nz (addr), insn,
+ *is_tbnz ? "tbnz" : "tbz", *rt, *bit,
+ core_addr_to_string_nz (addr + *imm));
+ }
+ return 1;
+ }
+ return 0;
+}
diff --git a/gdb/arch/aarch64-insn.h b/gdb/arch/aarch64-insn.h
new file mode 100644
index 0000000..7775a34
--- /dev/null
+++ b/gdb/arch/aarch64-insn.h
@@ -0,0 +1,38 @@
+/* Copyright (C) 2009-2015 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#ifndef AARCH64_INSN_H
+#define AARCH64_INSN_H 1
+
+extern int aarch64_debug;
+
+int aarch64_decode_adrp (CORE_ADDR addr, uint32_t insn, unsigned *rd);
+
+int aarch64_decode_b (CORE_ADDR addr, uint32_t insn, int *is_bl,
+ int32_t *offset);
+
+int aarch64_decode_bcond (CORE_ADDR addr, uint32_t insn, unsigned *cond,
+ int32_t *offset);
+
+int aarch64_decode_cb (CORE_ADDR addr, uint32_t insn, int *is64,
+ int *is_cbnz, unsigned *rn, int32_t *offset);
+
+int aarch64_decode_tb (CORE_ADDR addr, uint32_t insn, int *is_tbnz,
+ unsigned *bit, unsigned *rt, int32_t *imm);
+
+#endif
diff --git a/gdb/configure.tgt b/gdb/configure.tgt
index c42b4df..33d4cfc 100644
--- a/gdb/configure.tgt
+++ b/gdb/configure.tgt
@@ -38,12 +38,12 @@ esac
case "${targ}" in
aarch64*-*-elf)
# Target: AArch64 embedded system
- gdb_target_obs="aarch64-tdep.o aarch64-newlib-tdep.o"
+ gdb_target_obs="aarch64-tdep.o aarch64-newlib-tdep.o aarch64-insn.o"
;;
aarch64*-*-linux*)
# Target: AArch64 linux
- gdb_target_obs="aarch64-tdep.o aarch64-linux-tdep.o \
+ gdb_target_obs="aarch64-tdep.o aarch64-linux-tdep.o aarch64-insn.o \
arm-tdep.o arm-linux-tdep.o \
glibc-tdep.o linux-tdep.o solib-svr4.o \
symfile-mem.o linux-record.o"
diff --git a/gdb/gdbserver/Makefile.in b/gdb/gdbserver/Makefile.in
index b715a32..d096663 100644
--- a/gdb/gdbserver/Makefile.in
+++ b/gdb/gdbserver/Makefile.in
@@ -625,6 +625,12 @@ linux-namespaces.o: ../nat/linux-namespaces.c
$(COMPILE) $<
$(POSTCOMPILE)
+# Architecture specific object files rules from ../arch
+
+aarch64-insn.o: ../arch/aarch64-insn.c
+ $(COMPILE) $<
+ $(POSTCOMPILE)
+
aarch64.c : $(srcdir)/../regformats/aarch64.dat $(regdat_sh)
$(SHELL) $(regdat_sh) $(srcdir)/../regformats/aarch64.dat aarch64.c
reg-arm.c : $(srcdir)/../regformats/reg-arm.dat $(regdat_sh)
diff --git a/gdb/gdbserver/configure.srv b/gdb/gdbserver/configure.srv
index aa232f8..a62df83 100644
--- a/gdb/gdbserver/configure.srv
+++ b/gdb/gdbserver/configure.srv
@@ -53,6 +53,7 @@ case "${target}" in
srv_tgtobj="linux-aarch64-low.o aarch64-linux-hw-point.o"
srv_tgtobj="$srv_tgtobj linux-aarch32-low.o"
srv_tgtobj="$srv_tgtobj aarch64-linux.o"
+ srv_tgtobj="$srv_tgtobj aarch64-insn.o"
srv_tgtobj="${srv_tgtobj} $srv_linux_obj"
srv_xmlfiles="aarch64.xml"
srv_xmlfiles="${srv_xmlfiles} aarch64-core.xml"
--
2.4.6
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 8/8] [testsuite] Add a test case for fast tracepoints' locking mechanism
2015-09-14 11:31 [PATCH 0/8] [AArch64] Support fast tracepoints Pierre Langlois
` (6 preceding siblings ...)
2015-09-14 11:38 ` [PATCH 2/8] [AArch64] Move instruction decoding into new arch/ directory Pierre Langlois
@ 2015-09-14 11:38 ` Pierre Langlois
2015-09-14 16:45 ` [PATCH] Add NEWS entry for fast tracepoint support on aarch64-linux Pierre Langlois
2015-09-18 12:43 ` [PATCH 0/8 V2] [AArch64] Support fast tracepoints Yao Qi
9 siblings, 0 replies; 37+ messages in thread
From: Pierre Langlois @ 2015-09-14 11:38 UTC (permalink / raw)
To: gdb-patches; +Cc: Pierre Langlois
When installing a fast tracepoint, we create a jump pad with a
spin-lock. This way, only one thread can collect a given tracepoint at
any time. This test case checks that this lock actually works as
expected.
This test works by creating a function which overrides the in-process
agent library's gdb_collect function. On start up, GDBserver will ask
GDB with the 'qSymbol' packet about symbols present in the inferior.
GDB will reply with the gdb_agent_gdb_collect function from the test
case instead of the one from the agent.
gdb/testsuite/ChangeLog:
* gdb.trace/ftrace-lock.c: New file.
* gdb.trace/ftrace-lock.exp: New file.
---
gdb/testsuite/gdb.trace/ftrace-lock.c | 106 ++++++++++++++++++++++++++++++++
gdb/testsuite/gdb.trace/ftrace-lock.exp | 95 ++++++++++++++++++++++++++++
2 files changed, 201 insertions(+)
create mode 100644 gdb/testsuite/gdb.trace/ftrace-lock.c
create mode 100644 gdb/testsuite/gdb.trace/ftrace-lock.exp
diff --git a/gdb/testsuite/gdb.trace/ftrace-lock.c b/gdb/testsuite/gdb.trace/ftrace-lock.c
new file mode 100644
index 0000000..8ed45f4
--- /dev/null
+++ b/gdb/testsuite/gdb.trace/ftrace-lock.c
@@ -0,0 +1,106 @@
+/* This testcase is part of GDB, the GNU debugger.
+
+ Copyright 2015 Free Software Foundation, Inc.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#include <pthread.h>
+
+#ifdef SYMBOL_PREFIX
+#define SYMBOL(str) SYMBOL_PREFIX #str
+#else
+#define SYMBOL(str) #str
+#endif
+
+/* Called if the testcase failed. */
+static void
+fail (void)
+{
+}
+
+static pthread_mutex_t mutex = PTHREAD_MUTEX_INITIALIZER;
+
+/* This function overrides gdb_collect in the in-process agent library.
+ See gdbserver/tracepoint.c (gdb_collect). We want this function to
+ be ran instead of the one from the library to easily check that only
+ one thread is tracing at a time.
+
+ This works as expected because GDBserver will ask GDB about symbols
+ present in the inferior with the 'qSymbol' packet. And GDB will
+ reply with the address of this function instead of the one from the
+ in-process agent library. */
+
+void
+gdb_agent_gdb_collect (void *tpoint, unsigned char *regs)
+{
+ /* If we cannot acquire a lock, then this means another thread is
+ tracing and the lock implemented by the jump pad is not working! */
+ if (pthread_mutex_trylock (&mutex) != 0)
+ {
+ fail ();
+ return;
+ }
+
+ sleep (1);
+
+ if (pthread_mutex_unlock (&mutex) != 0)
+ {
+ fail ();
+ return;
+ }
+}
+
+/* Called from asm. */
+static void __attribute__((used))
+func (void)
+{
+}
+
+static void *
+thread_function (void *arg)
+{
+ /* `set_point' is the label at which to set a fast tracepoint. The
+ insn at the label must be large enough to fit a fast tracepoint
+ jump. */
+ asm (" .global " SYMBOL (set_point) "\n"
+ SYMBOL (set_point) ":\n"
+#if (defined __x86_64__ || defined __i386__)
+ " call " SYMBOL (func) "\n"
+#elif (defined __aarch64__)
+ " nop\n"
+#endif
+ );
+}
+
+static void
+end (void)
+{
+}
+
+int
+main (int argc, char *argv[], char *envp[])
+{
+ pthread_t threads[NUM_THREADS];
+ int i;
+
+ for (i = 0; i < NUM_THREADS; i++)
+ pthread_create (&threads[i], NULL, thread_function, NULL);
+
+ for (i = 0; i < NUM_THREADS; i++)
+ pthread_join (threads[i], NULL);
+
+ end ();
+
+ return 0;
+}
diff --git a/gdb/testsuite/gdb.trace/ftrace-lock.exp b/gdb/testsuite/gdb.trace/ftrace-lock.exp
new file mode 100644
index 0000000..1b3c35a
--- /dev/null
+++ b/gdb/testsuite/gdb.trace/ftrace-lock.exp
@@ -0,0 +1,95 @@
+# Copyright 2015 Free Software Foundation, Inc.
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+load_lib "trace-support.exp"
+
+standard_testfile
+set executable $testfile
+set expfile $testfile.exp
+
+# make check RUNTESTFLAGS='gdb.trace/ftrace-lock.exp NUM_THREADS=2'
+if ![info exists NUM_THREADS] {
+ set NUM_THREADS 2
+}
+
+# If NUM_THREADS is high then this test case may timeout. Increase the
+# timeout temporarily.
+global timeout
+set savedtimeout $timeout
+set timeout [expr $NUM_THREADS * $timeout]
+
+# Some targets have leading underscores on assembly symbols.
+set additional_flags [gdb_target_symbol_prefix_flags]
+set options [list debug [gdb_target_symbol_prefix_flags] \
+ additional_flags=-DNUM_THREADS=$NUM_THREADS]
+
+# Check that the target supports trace.
+if { [gdb_compile_pthreads "$srcdir/$subdir/$srcfile" $binfile executable $options] != "" } {
+ untested "Couldn't compile test program"
+ return -1
+}
+
+clean_restart ${testfile}
+
+if ![runto_main] {
+ fail "Can't run to main to check for trace support"
+ return -1
+}
+
+if ![gdb_target_supports_trace] {
+ unsupported "target does not support trace"
+ return -1
+}
+
+# Compile the test case with the in-process agent library.
+set libipa [get_in_proc_agent]
+gdb_load_shlibs $libipa
+
+lappend options shlib=$libipa
+
+if { [gdb_compile_pthreads "$srcdir/$subdir/$srcfile" $binfile executable $options] != "" } {
+ untested "Couldn't compile test program with in-process agent library"
+ return -1
+}
+
+clean_restart ${executable}
+
+if ![runto_main] {
+ fail "Can't run to main to check for trace support"
+ return -1
+}
+
+gdb_reinitialize_dir $srcdir/$subdir
+
+if { [gdb_test "info sharedlibrary" ".*${libipa}.*" "IPA loaded"] != 0 } {
+ untested "Could not find IPA lib loaded"
+ return 1
+}
+
+gdb_test "break end" ""
+gdb_test "break fail" ""
+
+gdb_test "ftrace set_point" "Fast tracepoint .*" \
+ "fast tracepoint at a long insn"
+
+gdb_test "tstart" ""
+
+# If the fail function is hit, then the testcase will fail.
+gdb_test "continue" ".*Breakpoint \[0-9\]+, end \(\).*" \
+ "do not hit the fail function"
+
+gdb_test "tstop" ""
+
+# Reset the timeout to its previous value.
+set timeout $savedtimeout
--
2.4.6
^ permalink raw reply [flat|nested] 37+ messages in thread* [PATCH] Add NEWS entry for fast tracepoint support on aarch64-linux
2015-09-14 11:31 [PATCH 0/8] [AArch64] Support fast tracepoints Pierre Langlois
` (7 preceding siblings ...)
2015-09-14 11:38 ` [PATCH 8/8] [testsuite] Add a test case for fast tracepoints' locking mechanism Pierre Langlois
@ 2015-09-14 16:45 ` Pierre Langlois
2015-09-18 12:43 ` [PATCH 0/8 V2] [AArch64] Support fast tracepoints Yao Qi
9 siblings, 0 replies; 37+ messages in thread
From: Pierre Langlois @ 2015-09-14 16:45 UTC (permalink / raw)
To: gdb-patches; +Cc: Pierre Langlois
Here is a NEWS entry for this series:
gdb/ChangeLog:
* NEWS: Mention support for fast tracepoints on aarch64-linux.
---
gdb/NEWS | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/gdb/NEWS b/gdb/NEWS
index 0cf51e1..505d648 100644
--- a/gdb/NEWS
+++ b/gdb/NEWS
@@ -16,6 +16,10 @@
GDB now is able to debug both AArch64 applications and ARM applications
at the same time.
+* Support for fast tracepoints on aarch64-linux was added in GDBserver,
+ including JIT compiling fast tracepoint's conditional expression bytecode
+ into native code.
+
* New commands
maint set target-non-stop (on|off|auto)
--
2.4.6
^ permalink raw reply [flat|nested] 37+ messages in thread* [PATCH 0/8 V2] [AArch64] Support fast tracepoints
2015-09-14 11:31 [PATCH 0/8] [AArch64] Support fast tracepoints Pierre Langlois
` (8 preceding siblings ...)
2015-09-14 16:45 ` [PATCH] Add NEWS entry for fast tracepoint support on aarch64-linux Pierre Langlois
@ 2015-09-18 12:43 ` Yao Qi
2015-09-18 12:43 ` [PATCH 8/8] Add NEWS entry for fast tracepoint support on aarch64-linux Yao Qi
` (8 more replies)
9 siblings, 9 replies; 37+ messages in thread
From: Yao Qi @ 2015-09-18 12:43 UTC (permalink / raw)
To: gdb-patches
Hi,
Here is the V2 of aarch64 fast tracepoint support. V1 can be found
https://sourceware.org/ml/gdb-patches/2015-09/msg00274.html
Some changes in V2:
- Implement gdb_agent_get_raw_reg for aarch64,
- Pass argument regs to gdb_agent_get_reg instead of
fast_tracepoint_ctx,
- Move gdb.trace/ftrace-insn-reloc.c and gdb.trace/ftrace-insn-reloc.exp
to gdb.arch, so that it can be reused for displaced stepping test,
- Use with_timeout_factor in gdb.trace/ftrace-lock.exp,
- Adjust one ChangeLog entry,
- Include NEWS entry in V2,
The whole series is tested on aarch64-linux with GDBserver.
*** BLURB HERE ***
Pierre Langlois (8):
Move instruction decoding into new arch/ directory
Make aarch64_decode_adrp handle both ADR and ADRP instructions
Add support for fast tracepoints
Implement target_emit_ops
Enable fast tracepoint tests
Add a gdb.trace test for instruction relocation
Add a test case for fast tracepoints' locking mechanism
Add NEWS entry for fast tracepoint support on aarch64-linux
gdb/Makefile.in | 13 +-
gdb/NEWS | 4 +
gdb/aarch64-tdep.c | 237 +--
gdb/arch/aarch64-insn.c | 237 +++
gdb/arch/aarch64-insn.h | 39 +
gdb/configure.tgt | 4 +-
gdb/gdbserver/Makefile.in | 12 +
gdb/gdbserver/configure.srv | 2 +
gdb/gdbserver/linux-aarch64-ipa.c | 151 ++
gdb/gdbserver/linux-aarch64-low.c | 2667 +++++++++++++++++++++++++-
gdb/testsuite/gdb.arch/ftrace-insn-reloc.exp | 114 ++
gdb/testsuite/gdb.arch/insn-reloc.c | 508 +++++
gdb/testsuite/gdb.trace/change-loc.h | 2 +
gdb/testsuite/gdb.trace/ftrace-lock.c | 106 +
gdb/testsuite/gdb.trace/ftrace-lock.exp | 95 +
gdb/testsuite/gdb.trace/ftrace.c | 2 +
gdb/testsuite/gdb.trace/ftrace.exp | 2 +-
gdb/testsuite/gdb.trace/pendshr1.c | 2 +
gdb/testsuite/gdb.trace/pendshr2.c | 2 +
gdb/testsuite/gdb.trace/range-stepping.c | 2 +
gdb/testsuite/gdb.trace/trace-break.c | 4 +
gdb/testsuite/gdb.trace/trace-condition.c | 2 +
gdb/testsuite/gdb.trace/trace-condition.exp | 2 +
gdb/testsuite/gdb.trace/trace-mt.c | 2 +
24 files changed, 4005 insertions(+), 206 deletions(-)
create mode 100644 gdb/arch/aarch64-insn.c
create mode 100644 gdb/arch/aarch64-insn.h
create mode 100644 gdb/gdbserver/linux-aarch64-ipa.c
create mode 100644 gdb/testsuite/gdb.arch/ftrace-insn-reloc.exp
create mode 100644 gdb/testsuite/gdb.arch/insn-reloc.c
create mode 100644 gdb/testsuite/gdb.trace/ftrace-lock.c
create mode 100644 gdb/testsuite/gdb.trace/ftrace-lock.exp
--
1.9.1
^ permalink raw reply [flat|nested] 37+ messages in thread* [PATCH 8/8] Add NEWS entry for fast tracepoint support on aarch64-linux
2015-09-18 12:43 ` [PATCH 0/8 V2] [AArch64] Support fast tracepoints Yao Qi
@ 2015-09-18 12:43 ` Yao Qi
2015-09-18 14:07 ` Eli Zaretskii
2015-09-18 12:43 ` [PATCH 2/8] Make aarch64_decode_adrp handle both ADR and ADRP instructions Yao Qi
` (7 subsequent siblings)
8 siblings, 1 reply; 37+ messages in thread
From: Yao Qi @ 2015-09-18 12:43 UTC (permalink / raw)
To: gdb-patches
From: Pierre Langlois <pierre.langlois@arm.com>
Here is a NEWS entry for this series:
gdb/ChangeLog:
* NEWS: Mention support for fast tracepoints on aarch64-linux.
---
gdb/NEWS | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/gdb/NEWS b/gdb/NEWS
index f563b8c..c819226 100644
--- a/gdb/NEWS
+++ b/gdb/NEWS
@@ -16,6 +16,10 @@
GDB now is able to debug both AArch64 applications and ARM applications
at the same time.
+* Support for fast tracepoints on aarch64-linux was added in GDBserver,
+ including JIT compiling fast tracepoint's conditional expression bytecode
+ into native code.
+
* New commands
maint set target-non-stop (on|off|auto)
--
1.9.1
^ permalink raw reply [flat|nested] 37+ messages in thread* [PATCH 2/8] Make aarch64_decode_adrp handle both ADR and ADRP instructions
2015-09-18 12:43 ` [PATCH 0/8 V2] [AArch64] Support fast tracepoints Yao Qi
2015-09-18 12:43 ` [PATCH 8/8] Add NEWS entry for fast tracepoint support on aarch64-linux Yao Qi
@ 2015-09-18 12:43 ` Yao Qi
2015-09-18 12:43 ` [PATCH 7/8] Add a test case for fast tracepoints' locking mechanism Yao Qi
` (6 subsequent siblings)
8 siblings, 0 replies; 37+ messages in thread
From: Yao Qi @ 2015-09-18 12:43 UTC (permalink / raw)
To: gdb-patches
From: Pierre Langlois <pierre.langlois@arm.com>
We will need to decode both ADR and ADRP instructions in GDBserver.
This patch makes common code handle both cases, even if GDB only needs
to decode the ADRP instruction.
gdb/ChangeLog:
* aarch64-tdep.c (aarch64_analyze_prologue): New is_adrp
variable. Call aarch64_decode_adr instead of
aarch64_decode_adrp.
* arch/aarch64-insn.h (aarch64_decode_adrp): Delete.
(aarch64_decode_adr): New function declaration.
* arch/aarch64-insn.c (aarch64_decode_adrp): Delete.
(aarch64_decode_adr): New function, factored out from
aarch64_decode_adrp to decode both adr and adrp instructions.
---
gdb/aarch64-tdep.c | 4 +++-
gdb/arch/aarch64-insn.c | 29 ++++++++++++++++++++++++-----
gdb/arch/aarch64-insn.h | 3 ++-
3 files changed, 29 insertions(+), 7 deletions(-)
diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index 92e2404..da61e54 100644
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -551,13 +551,15 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
int is_cbnz;
int is_tbnz;
unsigned bit;
+ int is_adrp;
int32_t offset;
insn = read_memory_unsigned_integer (start, 4, byte_order_for_code);
if (aarch64_decode_add_sub_imm (start, insn, &rd, &rn, &imm))
regs[rd] = pv_add_constant (regs[rn], imm);
- else if (aarch64_decode_adrp (start, insn, &rd))
+ else if (aarch64_decode_adr (start, insn, &is_adrp, &rd, &offset)
+ && is_adrp)
regs[rd] = pv_unknown ();
else if (aarch64_decode_b (start, insn, &is_link, &offset))
{
diff --git a/gdb/arch/aarch64-insn.c b/gdb/arch/aarch64-insn.c
index 3a289a2..13d0013 100644
--- a/gdb/arch/aarch64-insn.c
+++ b/gdb/arch/aarch64-insn.c
@@ -55,25 +55,44 @@ decode_masked_match (uint32_t insn, uint32_t mask, uint32_t pattern)
return (insn & mask) == pattern;
}
-/* Decode an opcode if it represents an ADRP instruction.
+/* Decode an opcode if it represents an ADR or ADRP instruction.
ADDR specifies the address of the opcode.
INSN specifies the opcode to test.
+ IS_ADRP receives the 'op' field from the decoded instruction.
RD receives the 'rd' field from the decoded instruction.
+ OFFSET receives the 'immhi:immlo' field from the decoded instruction.
Return 1 if the opcodes matches and is decoded, otherwise 0. */
int
-aarch64_decode_adrp (CORE_ADDR addr, uint32_t insn, unsigned *rd)
+aarch64_decode_adr (CORE_ADDR addr, uint32_t insn, int *is_adrp,
+ unsigned *rd, int32_t *offset)
{
- if (decode_masked_match (insn, 0x9f000000, 0x90000000))
+ /* adr 0ii1 0000 iiii iiii iiii iiii iiir rrrr */
+ /* adrp 1ii1 0000 iiii iiii iiii iiii iiir rrrr */
+ if (decode_masked_match (insn, 0x1f000000, 0x10000000))
{
+ uint32_t immlo = (insn >> 29) & 0x3;
+ int32_t immhi = extract_signed_bitfield (insn, 19, 5) << 2;
+
+ *is_adrp = (insn >> 31) & 0x1;
*rd = (insn >> 0) & 0x1f;
+ if (*is_adrp)
+ {
+ /* The ADRP instruction has an offset with a -/+ 4GB range,
+ encoded as (immhi:immlo * 4096). */
+ *offset = (immhi | immlo) * 4096;
+ }
+ else
+ *offset = (immhi | immlo);
+
if (aarch64_debug)
{
- debug_printf ("decode: 0x%s 0x%x adrp x%u, #?\n",
- core_addr_to_string_nz (addr), insn, *rd);
+ debug_printf ("decode: 0x%s 0x%x %s x%u, #?\n",
+ core_addr_to_string_nz (addr), insn,
+ *is_adrp ? "adrp" : "adr", *rd);
}
return 1;
}
diff --git a/gdb/arch/aarch64-insn.h b/gdb/arch/aarch64-insn.h
index 7775a34..2facb44 100644
--- a/gdb/arch/aarch64-insn.h
+++ b/gdb/arch/aarch64-insn.h
@@ -21,7 +21,8 @@
extern int aarch64_debug;
-int aarch64_decode_adrp (CORE_ADDR addr, uint32_t insn, unsigned *rd);
+int aarch64_decode_adr (CORE_ADDR addr, uint32_t insn, int *is_adrp,
+ unsigned *rd, int32_t *offset);
int aarch64_decode_b (CORE_ADDR addr, uint32_t insn, int *is_bl,
int32_t *offset);
--
1.9.1
^ permalink raw reply [flat|nested] 37+ messages in thread* [PATCH 7/8] Add a test case for fast tracepoints' locking mechanism
2015-09-18 12:43 ` [PATCH 0/8 V2] [AArch64] Support fast tracepoints Yao Qi
2015-09-18 12:43 ` [PATCH 8/8] Add NEWS entry for fast tracepoint support on aarch64-linux Yao Qi
2015-09-18 12:43 ` [PATCH 2/8] Make aarch64_decode_adrp handle both ADR and ADRP instructions Yao Qi
@ 2015-09-18 12:43 ` Yao Qi
2015-09-18 12:43 ` [PATCH 1/8] Move instruction decoding into new arch/ directory Yao Qi
` (5 subsequent siblings)
8 siblings, 0 replies; 37+ messages in thread
From: Yao Qi @ 2015-09-18 12:43 UTC (permalink / raw)
To: gdb-patches
From: Pierre Langlois <pierre.langlois@arm.com>
When installing a fast tracepoint, we create a jump pad with a
spin-lock. This way, only one thread can collect a given tracepoint at
any time. This test case checks that this lock actually works as
expected.
This test works by creating a function which overrides the in-process
agent library's gdb_collect function. On start up, GDBserver will ask
GDB with the 'qSymbol' packet about symbols present in the inferior.
GDB will reply with the gdb_agent_gdb_collect function from the test
case instead of the one from the agent.
gdb/testsuite/ChangeLog:
* gdb.trace/ftrace-lock.c: New file.
* gdb.trace/ftrace-lock.exp: New file.
---
gdb/testsuite/gdb.trace/ftrace-lock.c | 106 ++++++++++++++++++++++++++++++++
gdb/testsuite/gdb.trace/ftrace-lock.exp | 88 ++++++++++++++++++++++++++
2 files changed, 194 insertions(+)
create mode 100644 gdb/testsuite/gdb.trace/ftrace-lock.c
create mode 100644 gdb/testsuite/gdb.trace/ftrace-lock.exp
diff --git a/gdb/testsuite/gdb.trace/ftrace-lock.c b/gdb/testsuite/gdb.trace/ftrace-lock.c
new file mode 100644
index 0000000..8ed45f4
--- /dev/null
+++ b/gdb/testsuite/gdb.trace/ftrace-lock.c
@@ -0,0 +1,106 @@
+/* This testcase is part of GDB, the GNU debugger.
+
+ Copyright 2015 Free Software Foundation, Inc.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#include <pthread.h>
+
+#ifdef SYMBOL_PREFIX
+#define SYMBOL(str) SYMBOL_PREFIX #str
+#else
+#define SYMBOL(str) #str
+#endif
+
+/* Called if the testcase failed. */
+static void
+fail (void)
+{
+}
+
+static pthread_mutex_t mutex = PTHREAD_MUTEX_INITIALIZER;
+
+/* This function overrides gdb_collect in the in-process agent library.
+ See gdbserver/tracepoint.c (gdb_collect). We want this function to
+ be ran instead of the one from the library to easily check that only
+ one thread is tracing at a time.
+
+ This works as expected because GDBserver will ask GDB about symbols
+ present in the inferior with the 'qSymbol' packet. And GDB will
+ reply with the address of this function instead of the one from the
+ in-process agent library. */
+
+void
+gdb_agent_gdb_collect (void *tpoint, unsigned char *regs)
+{
+ /* If we cannot acquire a lock, then this means another thread is
+ tracing and the lock implemented by the jump pad is not working! */
+ if (pthread_mutex_trylock (&mutex) != 0)
+ {
+ fail ();
+ return;
+ }
+
+ sleep (1);
+
+ if (pthread_mutex_unlock (&mutex) != 0)
+ {
+ fail ();
+ return;
+ }
+}
+
+/* Called from asm. */
+static void __attribute__((used))
+func (void)
+{
+}
+
+static void *
+thread_function (void *arg)
+{
+ /* `set_point' is the label at which to set a fast tracepoint. The
+ insn at the label must be large enough to fit a fast tracepoint
+ jump. */
+ asm (" .global " SYMBOL (set_point) "\n"
+ SYMBOL (set_point) ":\n"
+#if (defined __x86_64__ || defined __i386__)
+ " call " SYMBOL (func) "\n"
+#elif (defined __aarch64__)
+ " nop\n"
+#endif
+ );
+}
+
+static void
+end (void)
+{
+}
+
+int
+main (int argc, char *argv[], char *envp[])
+{
+ pthread_t threads[NUM_THREADS];
+ int i;
+
+ for (i = 0; i < NUM_THREADS; i++)
+ pthread_create (&threads[i], NULL, thread_function, NULL);
+
+ for (i = 0; i < NUM_THREADS; i++)
+ pthread_join (threads[i], NULL);
+
+ end ();
+
+ return 0;
+}
diff --git a/gdb/testsuite/gdb.trace/ftrace-lock.exp b/gdb/testsuite/gdb.trace/ftrace-lock.exp
new file mode 100644
index 0000000..c67739d
--- /dev/null
+++ b/gdb/testsuite/gdb.trace/ftrace-lock.exp
@@ -0,0 +1,88 @@
+# Copyright 2015 Free Software Foundation, Inc.
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+load_lib "trace-support.exp"
+
+standard_testfile
+set executable $testfile
+set expfile $testfile.exp
+
+# make check RUNTESTFLAGS='gdb.trace/ftrace-lock.exp NUM_THREADS=2'
+if ![info exists NUM_THREADS] {
+ set NUM_THREADS 2
+}
+
+# Some targets have leading underscores on assembly symbols.
+set additional_flags [gdb_target_symbol_prefix_flags]
+set options [list debug [gdb_target_symbol_prefix_flags] \
+ additional_flags=-DNUM_THREADS=$NUM_THREADS]
+
+# Check that the target supports trace.
+if { [gdb_compile_pthreads "$srcdir/$subdir/$srcfile" $binfile executable $options] != "" } {
+ untested "Couldn't compile test program"
+ return -1
+}
+
+clean_restart ${testfile}
+
+if ![runto_main] {
+ fail "Can't run to main to check for trace support"
+ return -1
+}
+
+if ![gdb_target_supports_trace] {
+ unsupported "target does not support trace"
+ return -1
+}
+
+# Compile the test case with the in-process agent library.
+set libipa [get_in_proc_agent]
+gdb_load_shlibs $libipa
+
+lappend options shlib=$libipa
+
+if { [gdb_compile_pthreads "$srcdir/$subdir/$srcfile" $binfile executable $options] != "" } {
+ untested "Couldn't compile test program with in-process agent library"
+ return -1
+}
+
+clean_restart ${executable}
+
+if ![runto_main] {
+ fail "Can't run to main to check for trace support"
+ return -1
+}
+
+if { [gdb_test "info sharedlibrary" ".*${libipa}.*" "IPA loaded"] != 0 } {
+ untested "Could not find IPA lib loaded"
+ return 1
+}
+
+gdb_test "break end" ""
+gdb_test "break fail" ""
+
+gdb_test "ftrace set_point" "Fast tracepoint .*" \
+ "fast tracepoint at a long insn"
+
+gdb_test "tstart" ""
+
+# If NUM_THREADS is high then this test case may timeout. Increase the
+# timeout temporarily.
+with_timeout_factor $NUM_THREADS {
+ # If the fail function is hit, then the testcase will fail.
+ gdb_test "continue" ".*Breakpoint \[0-9\]+, end \(\).*" \
+ "do not hit the fail function"
+}
+
+gdb_test "tstop" ""
--
1.9.1
^ permalink raw reply [flat|nested] 37+ messages in thread* [PATCH 1/8] Move instruction decoding into new arch/ directory
2015-09-18 12:43 ` [PATCH 0/8 V2] [AArch64] Support fast tracepoints Yao Qi
` (2 preceding siblings ...)
2015-09-18 12:43 ` [PATCH 7/8] Add a test case for fast tracepoints' locking mechanism Yao Qi
@ 2015-09-18 12:43 ` Yao Qi
2015-09-18 12:43 ` [PATCH 4/8] Implement target_emit_ops Yao Qi
` (4 subsequent siblings)
8 siblings, 0 replies; 37+ messages in thread
From: Yao Qi @ 2015-09-18 12:43 UTC (permalink / raw)
To: gdb-patches
From: Pierre Langlois <pierre.langlois@arm.com>
This patch moves the following functions into the arch/ common
directory, in new files arch/aarch64-insn.{h,c}. They are prefixed with
'aarch64_':
- aarch64_decode_adrp
- aarch64_decode_b
- aarch64_decode_cb
- aarch64_decode_tb
We will need them to implement fast tracepoints in GDBserver.
For consistency, this patch also adds the 'aarch64_' prefix to static
decoding functions that do not need to be shared right now.
V2:
make sure the formatting issues propagated
fix `gdbserver/configure.srv'.
gdb/ChangeLog:
* Makefile.in (ALL_64_TARGET_OBS): Add aarch64-insn.o.
(HFILES_NO_SRCDIR): Add arch/aarch64-insn.h.
(aarch64-insn.o): New rule.
* configure.tgt (aarch64*-*-elf): Add aarch64-insn.o.
(aarch64*-*-linux*): Likewise.
* arch/aarch64-insn.c: New file.
* arch/aarch64-insn.h: New file.
* aarch64-tdep.c: Include arch/aarch64-insn.h.
(aarch64_debug): Move to arch/aarch64-insn.c. Declare in
arch/aarch64-insn.h.
(decode_add_sub_imm): Rename to ...
(aarch64_decode_add_sub_imm): ... this.
(decode_adrp): Rename to ...
(aarch64_decode_adrp): ... this. Move to arch/aarch64-insn.c.
Declare in arch/aarch64-insn.h.
(decode_b): Rename to ...
(aarch64_decode_b): ... this. Move to arch/aarch64-insn.c.
Declare in arch/aarch64-insn.h.
(decode_bcond): Rename to ...
(aarch64_decode_bcond): ... this. Move to arch/aarch64-insn.c.
Declare in arch/aarch64-insn.h.
(decode_br): Rename to ...
(aarch64_decode_br): ... this.
(decode_cb): Rename to ...
(aarch64_decode_cb): ... this. Move to arch/aarch64-insn.c.
Declare in arch/aarch64-insn.h.
(decode_eret): Rename to ...
(aarch64_decode_eret): ... this.
(decode_movz): Rename to ...
(aarch64_decode_movz): ... this.
(decode_orr_shifted_register_x): Rename to ...
(aarch64_decode_orr_shifted_register_x): ... this.
(decode_ret): Rename to ...
(aarch64_decode_ret): ... this.
(decode_stp_offset): Rename to ...
(aarch64_decode_stp_offset): ... this.
(decode_stp_offset_wb): Rename to ...
(aarch64_decode_stp_offset_wb): ... this.
(decode_stur): Rename to ...
(aarch64_decode_stur): ... this.
(decode_tb): Rename to ...
(aarch64_decode_tb): ... this. Move to arch/aarch64-insn.c.
Declare in arch/aarch64-insn.h.
(aarch64_analyze_prologue): Adjust calls to renamed functions.
gdb/gdbserver/ChangeLog:
* gdb/gdbserver/Makefile.in (aarch64-insn.o): New rule.
* gdb/gdbserver/configure.srv (aarch64*-*-linux*): Add
aarch64-insn.o.
---
gdb/Makefile.in | 13 ++-
gdb/aarch64-tdep.c | 235 +++++++-------------------------------------
gdb/arch/aarch64-insn.c | 218 ++++++++++++++++++++++++++++++++++++++++
gdb/arch/aarch64-insn.h | 38 +++++++
gdb/configure.tgt | 4 +-
gdb/gdbserver/Makefile.in | 6 ++
gdb/gdbserver/configure.srv | 1 +
7 files changed, 314 insertions(+), 201 deletions(-)
create mode 100644 gdb/arch/aarch64-insn.c
create mode 100644 gdb/arch/aarch64-insn.h
diff --git a/gdb/Makefile.in b/gdb/Makefile.in
index 5659116..d5ca2ee 100644
--- a/gdb/Makefile.in
+++ b/gdb/Makefile.in
@@ -644,7 +644,7 @@ TARGET_OBS = @TARGET_OBS@
# All target-dependent objects files that require 64-bit CORE_ADDR
# (used with --enable-targets=all --enable-64-bit-bfd).
ALL_64_TARGET_OBS = \
- aarch64-tdep.o aarch64-linux-tdep.o aarch64-newlib-tdep.o \
+ aarch64-tdep.o aarch64-linux-tdep.o aarch64-newlib-tdep.o aarch64-insn.o \
alphabsd-tdep.o alphafbsd-tdep.o alpha-linux-tdep.o alpha-mdebug-tdep.o \
alphanbsd-tdep.o alphaobsd-tdep.o alpha-tdep.o \
amd64fbsd-tdep.o amd64-darwin-tdep.o amd64-dicos-tdep.o \
@@ -986,7 +986,7 @@ common/common-debug.h common/cleanups.h common/gdb_setjmp.h \
common/common-exceptions.h target/target.h common/symbol.h \
common/common-regcache.h fbsd-tdep.h nat/linux-personality.h \
common/fileio.h nat/x86-linux.h nat/x86-linux-dregs.h \
-nat/linux-namespaces.h arch/arm.h common/gdb_sys_time.h
+nat/linux-namespaces.h arch/arm.h common/gdb_sys_time.h arch/aarch64-insn.h
# Header files that already have srcdir in them, or which are in objdir.
@@ -2336,6 +2336,15 @@ aarch64-linux.o: ${srcdir}/nat/aarch64-linux.c
$(COMPILE) $(srcdir)/nat/aarch64-linux.c
$(POSTCOMPILE)
+# gdb/arch/ dependencies
+#
+# Need to explicitly specify the compile rule as make will do nothing
+# or try to compile the object file into the sub-directory.
+
+aarch64-insn.o: ${srcdir}/arch/aarch64-insn.c
+ $(COMPILE) $(srcdir)/arch/aarch64-insn.c
+ $(POSTCOMPILE)
+
#
# gdb/tui/ dependencies
#
diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index 9a4eda2..92e2404 100644
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -57,6 +57,8 @@
#include "features/aarch64.c"
+#include "arch/aarch64-insn.h"
+
/* Pseudo register base numbers. */
#define AARCH64_Q0_REGNUM 0
#define AARCH64_D0_REGNUM (AARCH64_Q0_REGNUM + 32)
@@ -179,9 +181,6 @@ struct aarch64_prologue_cache
struct trad_frame_saved_reg *saved_regs;
};
-/* Toggle this file's internal debugging dump. */
-static int aarch64_debug;
-
static void
show_aarch64_debug (struct ui_file *file, int from_tty,
struct cmd_list_element *c, const char *value)
@@ -231,8 +230,8 @@ decode_masked_match (uint32_t insn, uint32_t mask, uint32_t pattern)
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
-decode_add_sub_imm (CORE_ADDR addr, uint32_t insn, unsigned *rd, unsigned *rn,
- int32_t *imm)
+aarch64_decode_add_sub_imm (CORE_ADDR addr, uint32_t insn, unsigned *rd,
+ unsigned *rn, int32_t *imm)
{
if ((insn & 0x9f000000) == 0x91000000)
{
@@ -271,94 +270,6 @@ decode_add_sub_imm (CORE_ADDR addr, uint32_t insn, unsigned *rd, unsigned *rn,
return 0;
}
-/* Decode an opcode if it represents an ADRP instruction.
-
- ADDR specifies the address of the opcode.
- INSN specifies the opcode to test.
- RD receives the 'rd' field from the decoded instruction.
-
- Return 1 if the opcodes matches and is decoded, otherwise 0. */
-
-static int
-decode_adrp (CORE_ADDR addr, uint32_t insn, unsigned *rd)
-{
- if (decode_masked_match (insn, 0x9f000000, 0x90000000))
- {
- *rd = (insn >> 0) & 0x1f;
-
- if (aarch64_debug)
- {
- debug_printf ("decode: 0x%s 0x%x adrp x%u, #?\n",
- core_addr_to_string_nz (addr), insn, *rd);
- }
- return 1;
- }
- return 0;
-}
-
-/* Decode an opcode if it represents an branch immediate or branch
- and link immediate instruction.
-
- ADDR specifies the address of the opcode.
- INSN specifies the opcode to test.
- IS_BL receives the 'op' bit from the decoded instruction.
- OFFSET receives the immediate offset from the decoded instruction.
-
- Return 1 if the opcodes matches and is decoded, otherwise 0. */
-
-static int
-decode_b (CORE_ADDR addr, uint32_t insn, int *is_bl, int32_t *offset)
-{
- /* b 0001 01ii iiii iiii iiii iiii iiii iiii */
- /* bl 1001 01ii iiii iiii iiii iiii iiii iiii */
- if (decode_masked_match (insn, 0x7c000000, 0x14000000))
- {
- *is_bl = (insn >> 31) & 0x1;
- *offset = extract_signed_bitfield (insn, 26, 0) << 2;
-
- if (aarch64_debug)
- {
- debug_printf ("decode: 0x%s 0x%x %s 0x%s\n",
- core_addr_to_string_nz (addr), insn,
- *is_bl ? "bl" : "b",
- core_addr_to_string_nz (addr + *offset));
- }
-
- return 1;
- }
- return 0;
-}
-
-/* Decode an opcode if it represents a conditional branch instruction.
-
- ADDR specifies the address of the opcode.
- INSN specifies the opcode to test.
- COND receives the branch condition field from the decoded
- instruction.
- OFFSET receives the immediate offset from the decoded instruction.
-
- Return 1 if the opcodes matches and is decoded, otherwise 0. */
-
-static int
-decode_bcond (CORE_ADDR addr, uint32_t insn, unsigned *cond, int32_t *offset)
-{
- /* b.cond 0101 0100 iiii iiii iiii iiii iii0 cccc */
- if (decode_masked_match (insn, 0xff000010, 0x54000000))
- {
- *cond = (insn >> 0) & 0xf;
- *offset = extract_signed_bitfield (insn, 19, 5) << 2;
-
- if (aarch64_debug)
- {
- debug_printf ("decode: 0x%s 0x%x b<%u> 0x%s\n",
- core_addr_to_string_nz (addr), insn, *cond,
- core_addr_to_string_nz (addr + *offset));
- }
- return 1;
- }
- return 0;
-}
-
/* Decode an opcode if it represents a branch via register instruction.
ADDR specifies the address of the opcode.
@@ -369,7 +280,8 @@ decode_bcond (CORE_ADDR addr, uint32_t insn, unsigned *cond, int32_t *offset)
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
-decode_br (CORE_ADDR addr, uint32_t insn, int *is_blr, unsigned *rn)
+aarch64_decode_br (CORE_ADDR addr, uint32_t insn, int *is_blr,
+ unsigned *rn)
{
/* 8 4 0 6 2 8 4 0 */
/* blr 110101100011111100000000000rrrrr */
@@ -391,42 +303,6 @@ decode_br (CORE_ADDR addr, uint32_t insn, int *is_blr, unsigned *rn)
return 0;
}
-/* Decode an opcode if it represents a CBZ or CBNZ instruction.
-
- ADDR specifies the address of the opcode.
- INSN specifies the opcode to test.
- IS64 receives the 'sf' field from the decoded instruction.
- IS_CBNZ receives the 'op' field from the decoded instruction.
- RN receives the 'rn' field from the decoded instruction.
- OFFSET receives the 'imm19' field from the decoded instruction.
-
- Return 1 if the opcodes matches and is decoded, otherwise 0. */
-
-static int
-decode_cb (CORE_ADDR addr, uint32_t insn, int *is64, int *is_cbnz,
- unsigned *rn, int32_t *offset)
-{
- /* cbz T011 010o iiii iiii iiii iiii iiir rrrr */
- /* cbnz T011 010o iiii iiii iiii iiii iiir rrrr */
- if (decode_masked_match (insn, 0x7e000000, 0x34000000))
- {
- *rn = (insn >> 0) & 0x1f;
- *is64 = (insn >> 31) & 0x1;
- *is_cbnz = (insn >> 24) & 0x1;
- *offset = extract_signed_bitfield (insn, 19, 5) << 2;
-
- if (aarch64_debug)
- {
- debug_printf ("decode: 0x%s 0x%x %s 0x%s\n",
- core_addr_to_string_nz (addr), insn,
- *is_cbnz ? "cbnz" : "cbz",
- core_addr_to_string_nz (addr + *offset));
- }
- return 1;
- }
- return 0;
-}
-
/* Decode an opcode if it represents a ERET instruction.
ADDR specifies the address of the opcode.
@@ -435,7 +311,7 @@ decode_cb (CORE_ADDR addr, uint32_t insn, int *is64, int *is_cbnz,
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
-decode_eret (CORE_ADDR addr, uint32_t insn)
+aarch64_decode_eret (CORE_ADDR addr, uint32_t insn)
{
/* eret 1101 0110 1001 1111 0000 0011 1110 0000 */
if (insn == 0xd69f03e0)
@@ -459,7 +335,7 @@ decode_eret (CORE_ADDR addr, uint32_t insn)
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
-decode_movz (CORE_ADDR addr, uint32_t insn, unsigned *rd)
+aarch64_decode_movz (CORE_ADDR addr, uint32_t insn, unsigned *rd)
{
if (decode_masked_match (insn, 0xff800000, 0x52800000))
{
@@ -488,9 +364,9 @@ decode_movz (CORE_ADDR addr, uint32_t insn, unsigned *rd)
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
-decode_orr_shifted_register_x (CORE_ADDR addr,
- uint32_t insn, unsigned *rd, unsigned *rn,
- unsigned *rm, int32_t *imm)
+aarch64_decode_orr_shifted_register_x (CORE_ADDR addr, uint32_t insn,
+ unsigned *rd, unsigned *rn,
+ unsigned *rm, int32_t *imm)
{
if (decode_masked_match (insn, 0xff200000, 0xaa000000))
{
@@ -519,7 +395,7 @@ decode_orr_shifted_register_x (CORE_ADDR addr,
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
-decode_ret (CORE_ADDR addr, uint32_t insn, unsigned *rn)
+aarch64_decode_ret (CORE_ADDR addr, uint32_t insn, unsigned *rn)
{
if (decode_masked_match (insn, 0xfffffc1f, 0xd65f0000))
{
@@ -547,9 +423,8 @@ decode_ret (CORE_ADDR addr, uint32_t insn, unsigned *rn)
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
-decode_stp_offset (CORE_ADDR addr,
- uint32_t insn,
- unsigned *rt1, unsigned *rt2, unsigned *rn, int32_t *imm)
+aarch64_decode_stp_offset (CORE_ADDR addr, uint32_t insn, unsigned *rt1,
+ unsigned *rt2, unsigned *rn, int32_t *imm)
{
if (decode_masked_match (insn, 0xffc00000, 0xa9000000))
{
@@ -583,10 +458,8 @@ decode_stp_offset (CORE_ADDR addr,
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
-decode_stp_offset_wb (CORE_ADDR addr,
- uint32_t insn,
- unsigned *rt1, unsigned *rt2, unsigned *rn,
- int32_t *imm)
+aarch64_decode_stp_offset_wb (CORE_ADDR addr, uint32_t insn, unsigned *rt1,
+ unsigned *rt2, unsigned *rn, int32_t *imm)
{
if (decode_masked_match (insn, 0xffc00000, 0xa9800000))
{
@@ -620,8 +493,8 @@ decode_stp_offset_wb (CORE_ADDR addr,
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
-decode_stur (CORE_ADDR addr, uint32_t insn, int *is64, unsigned *rt,
- unsigned *rn, int32_t *imm)
+aarch64_decode_stur (CORE_ADDR addr, uint32_t insn, int *is64,
+ unsigned *rt, unsigned *rn, int32_t *imm)
{
if (decode_masked_match (insn, 0xbfe00c00, 0xb8000000))
{
@@ -641,42 +514,6 @@ decode_stur (CORE_ADDR addr, uint32_t insn, int *is64, unsigned *rt,
return 0;
}
-/* Decode an opcode if it represents a TBZ or TBNZ instruction.
-
- ADDR specifies the address of the opcode.
- INSN specifies the opcode to test.
- IS_TBNZ receives the 'op' field from the decoded instruction.
- BIT receives the bit position field from the decoded instruction.
- RT receives 'rt' field from the decoded instruction.
- IMM receives 'imm' field from the decoded instruction.
-
- Return 1 if the opcodes matches and is decoded, otherwise 0. */
-
-static int
-decode_tb (CORE_ADDR addr, uint32_t insn, int *is_tbnz, unsigned *bit,
- unsigned *rt, int32_t *imm)
-{
- /* tbz b011 0110 bbbb biii iiii iiii iiir rrrr */
- /* tbnz B011 0111 bbbb biii iiii iiii iiir rrrr */
- if (decode_masked_match (insn, 0x7e000000, 0x36000000))
- {
- *rt = (insn >> 0) & 0x1f;
- *is_tbnz = (insn >> 24) & 0x1;
- *bit = ((insn >> (31 - 4)) & 0x20) | ((insn >> 19) & 0x1f);
- *imm = extract_signed_bitfield (insn, 14, 5) << 2;
-
- if (aarch64_debug)
- {
- debug_printf ("decode: 0x%s 0x%x %s x%u, #%u, 0x%s\n",
- core_addr_to_string_nz (addr), insn,
- *is_tbnz ? "tbnz" : "tbz", *rt, *bit,
- core_addr_to_string_nz (addr + *imm));
- }
- return 1;
- }
- return 0;
-}
-
/* Analyze a prologue, looking for a recognizable stack frame
and frame pointer. Scan until we encounter a store that could
clobber the stack frame unexpectedly, or an unknown instruction. */
@@ -718,39 +555,40 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
insn = read_memory_unsigned_integer (start, 4, byte_order_for_code);
- if (decode_add_sub_imm (start, insn, &rd, &rn, &imm))
+ if (aarch64_decode_add_sub_imm (start, insn, &rd, &rn, &imm))
regs[rd] = pv_add_constant (regs[rn], imm);
- else if (decode_adrp (start, insn, &rd))
+ else if (aarch64_decode_adrp (start, insn, &rd))
regs[rd] = pv_unknown ();
- else if (decode_b (start, insn, &is_link, &offset))
+ else if (aarch64_decode_b (start, insn, &is_link, &offset))
{
/* Stop analysis on branch. */
break;
}
- else if (decode_bcond (start, insn, &cond, &offset))
+ else if (aarch64_decode_bcond (start, insn, &cond, &offset))
{
/* Stop analysis on branch. */
break;
}
- else if (decode_br (start, insn, &is_link, &rn))
+ else if (aarch64_decode_br (start, insn, &is_link, &rn))
{
/* Stop analysis on branch. */
break;
}
- else if (decode_cb (start, insn, &is64, &is_cbnz, &rn, &offset))
+ else if (aarch64_decode_cb (start, insn, &is64, &is_cbnz, &rn,
+ &offset))
{
/* Stop analysis on branch. */
break;
}
- else if (decode_eret (start, insn))
+ else if (aarch64_decode_eret (start, insn))
{
/* Stop analysis on branch. */
break;
}
- else if (decode_movz (start, insn, &rd))
+ else if (aarch64_decode_movz (start, insn, &rd))
regs[rd] = pv_unknown ();
- else
- if (decode_orr_shifted_register_x (start, insn, &rd, &rn, &rm, &imm))
+ else if (aarch64_decode_orr_shifted_register_x (start, insn, &rd,
+ &rn, &rm, &imm))
{
if (imm == 0 && rn == 31)
regs[rd] = regs[rm];
@@ -765,17 +603,18 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
break;
}
}
- else if (decode_ret (start, insn, &rn))
+ else if (aarch64_decode_ret (start, insn, &rn))
{
/* Stop analysis on branch. */
break;
}
- else if (decode_stur (start, insn, &is64, &rt, &rn, &offset))
+ else if (aarch64_decode_stur (start, insn, &is64, &rt, &rn, &offset))
{
pv_area_store (stack, pv_add_constant (regs[rn], offset),
is64 ? 8 : 4, regs[rt]);
}
- else if (decode_stp_offset (start, insn, &rt1, &rt2, &rn, &imm))
+ else if (aarch64_decode_stp_offset (start, insn, &rt1, &rt2, &rn,
+ &imm))
{
/* If recording this store would invalidate the store area
(perhaps because rn is not known) then we should abandon
@@ -793,7 +632,8 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
pv_area_store (stack, pv_add_constant (regs[rn], imm + 8), 8,
regs[rt2]);
}
- else if (decode_stp_offset_wb (start, insn, &rt1, &rt2, &rn, &imm))
+ else if (aarch64_decode_stp_offset_wb (start, insn, &rt1, &rt2, &rn,
+ &imm))
{
/* If recording this store would invalidate the store area
(perhaps because rn is not known) then we should abandon
@@ -812,7 +652,8 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
regs[rt2]);
regs[rn] = pv_add_constant (regs[rn], imm);
}
- else if (decode_tb (start, insn, &is_tbnz, &bit, &rn, &offset))
+ else if (aarch64_decode_tb (start, insn, &is_tbnz, &bit, &rn,
+ &offset))
{
/* Stop analysis on branch. */
break;
@@ -2663,7 +2504,7 @@ aarch64_software_single_step (struct frame_info *frame)
byte_order_for_code);
/* Check if the instruction is a conditional branch. */
- if (decode_bcond (loc, insn, &cond, &offset))
+ if (aarch64_decode_bcond (loc, insn, &cond, &offset))
{
if (bc_insn_count >= 1)
return 0;
diff --git a/gdb/arch/aarch64-insn.c b/gdb/arch/aarch64-insn.c
new file mode 100644
index 0000000..3a289a2
--- /dev/null
+++ b/gdb/arch/aarch64-insn.c
@@ -0,0 +1,218 @@
+/* Copyright (C) 2009-2015 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#include "common-defs.h"
+#include "aarch64-insn.h"
+
+/* Toggle this file's internal debugging dump. */
+int aarch64_debug = 0;
+
+/* Extract a signed value from a bit field within an instruction
+ encoding.
+
+ INSN is the instruction opcode.
+
+ WIDTH specifies the width of the bit field to extract (in bits).
+
+ OFFSET specifies the least significant bit of the field where bits
+ are numbered zero counting from least to most significant. */
+
+static int32_t
+extract_signed_bitfield (uint32_t insn, unsigned width, unsigned offset)
+{
+ unsigned shift_l = sizeof (int32_t) * 8 - (offset + width);
+ unsigned shift_r = sizeof (int32_t) * 8 - width;
+
+ return ((int32_t) insn << shift_l) >> shift_r;
+}
+
+/* Determine if specified bits within an instruction opcode matches a
+ specific pattern.
+
+ INSN is the instruction opcode.
+
+ MASK specifies the bits within the opcode that are to be tested
+ agsinst for a match with PATTERN. */
+
+static int
+decode_masked_match (uint32_t insn, uint32_t mask, uint32_t pattern)
+{
+ return (insn & mask) == pattern;
+}
+
+/* Decode an opcode if it represents an ADRP instruction.
+
+ ADDR specifies the address of the opcode.
+ INSN specifies the opcode to test.
+ RD receives the 'rd' field from the decoded instruction.
+
+ Return 1 if the opcodes matches and is decoded, otherwise 0. */
+
+int
+aarch64_decode_adrp (CORE_ADDR addr, uint32_t insn, unsigned *rd)
+{
+ if (decode_masked_match (insn, 0x9f000000, 0x90000000))
+ {
+ *rd = (insn >> 0) & 0x1f;
+
+ if (aarch64_debug)
+ {
+ debug_printf ("decode: 0x%s 0x%x adrp x%u, #?\n",
+ core_addr_to_string_nz (addr), insn, *rd);
+ }
+ return 1;
+ }
+ return 0;
+}
+
+/* Decode an opcode if it represents an branch immediate or branch
+ and link immediate instruction.
+
+ ADDR specifies the address of the opcode.
+ INSN specifies the opcode to test.
+ IS_BL receives the 'op' bit from the decoded instruction.
+ OFFSET receives the immediate offset from the decoded instruction.
+
+ Return 1 if the opcodes matches and is decoded, otherwise 0. */
+
+int
+aarch64_decode_b (CORE_ADDR addr, uint32_t insn, int *is_bl,
+ int32_t *offset)
+{
+ /* b 0001 01ii iiii iiii iiii iiii iiii iiii */
+ /* bl 1001 01ii iiii iiii iiii iiii iiii iiii */
+ if (decode_masked_match (insn, 0x7c000000, 0x14000000))
+ {
+ *is_bl = (insn >> 31) & 0x1;
+ *offset = extract_signed_bitfield (insn, 26, 0) << 2;
+
+ if (aarch64_debug)
+ {
+ debug_printf ("decode: 0x%s 0x%x %s 0x%s\n",
+ core_addr_to_string_nz (addr), insn,
+ *is_bl ? "bl" : "b",
+ core_addr_to_string_nz (addr + *offset));
+ }
+
+ return 1;
+ }
+ return 0;
+}
+
+/* Decode an opcode if it represents a conditional branch instruction.
+
+ ADDR specifies the address of the opcode.
+ INSN specifies the opcode to test.
+ COND receives the branch condition field from the decoded
+ instruction.
+ OFFSET receives the immediate offset from the decoded instruction.
+
+ Return 1 if the opcodes matches and is decoded, otherwise 0. */
+
+int
+aarch64_decode_bcond (CORE_ADDR addr, uint32_t insn, unsigned *cond,
+ int32_t *offset)
+{
+ /* b.cond 0101 0100 iiii iiii iiii iiii iii0 cccc */
+ if (decode_masked_match (insn, 0xff000010, 0x54000000))
+ {
+ *cond = (insn >> 0) & 0xf;
+ *offset = extract_signed_bitfield (insn, 19, 5) << 2;
+
+ if (aarch64_debug)
+ {
+ debug_printf ("decode: 0x%s 0x%x b<%u> 0x%s\n",
+ core_addr_to_string_nz (addr), insn, *cond,
+ core_addr_to_string_nz (addr + *offset));
+ }
+ return 1;
+ }
+ return 0;
+}
+
+/* Decode an opcode if it represents a CBZ or CBNZ instruction.
+
+ ADDR specifies the address of the opcode.
+ INSN specifies the opcode to test.
+ IS64 receives the 'sf' field from the decoded instruction.
+ IS_CBNZ receives the 'op' field from the decoded instruction.
+ RN receives the 'rn' field from the decoded instruction.
+ OFFSET receives the 'imm19' field from the decoded instruction.
+
+ Return 1 if the opcodes matches and is decoded, otherwise 0. */
+
+int
+aarch64_decode_cb (CORE_ADDR addr, uint32_t insn, int *is64, int *is_cbnz,
+ unsigned *rn, int32_t *offset)
+{
+ /* cbz T011 010o iiii iiii iiii iiii iiir rrrr */
+ /* cbnz T011 010o iiii iiii iiii iiii iiir rrrr */
+ if (decode_masked_match (insn, 0x7e000000, 0x34000000))
+ {
+ *rn = (insn >> 0) & 0x1f;
+ *is64 = (insn >> 31) & 0x1;
+ *is_cbnz = (insn >> 24) & 0x1;
+ *offset = extract_signed_bitfield (insn, 19, 5) << 2;
+
+ if (aarch64_debug)
+ {
+ debug_printf ("decode: 0x%s 0x%x %s 0x%s\n",
+ core_addr_to_string_nz (addr), insn,
+ *is_cbnz ? "cbnz" : "cbz",
+ core_addr_to_string_nz (addr + *offset));
+ }
+ return 1;
+ }
+ return 0;
+}
+
+/* Decode an opcode if it represents a TBZ or TBNZ instruction.
+
+ ADDR specifies the address of the opcode.
+ INSN specifies the opcode to test.
+ IS_TBNZ receives the 'op' field from the decoded instruction.
+ BIT receives the bit position field from the decoded instruction.
+ RT receives 'rt' field from the decoded instruction.
+ IMM receives 'imm' field from the decoded instruction.
+
+ Return 1 if the opcodes matches and is decoded, otherwise 0. */
+
+int
+aarch64_decode_tb (CORE_ADDR addr, uint32_t insn, int *is_tbnz,
+ unsigned *bit, unsigned *rt, int32_t *imm)
+{
+ /* tbz b011 0110 bbbb biii iiii iiii iiir rrrr */
+ /* tbnz B011 0111 bbbb biii iiii iiii iiir rrrr */
+ if (decode_masked_match (insn, 0x7e000000, 0x36000000))
+ {
+ *rt = (insn >> 0) & 0x1f;
+ *is_tbnz = (insn >> 24) & 0x1;
+ *bit = ((insn >> (31 - 4)) & 0x20) | ((insn >> 19) & 0x1f);
+ *imm = extract_signed_bitfield (insn, 14, 5) << 2;
+
+ if (aarch64_debug)
+ {
+ debug_printf ("decode: 0x%s 0x%x %s x%u, #%u, 0x%s\n",
+ core_addr_to_string_nz (addr), insn,
+ *is_tbnz ? "tbnz" : "tbz", *rt, *bit,
+ core_addr_to_string_nz (addr + *imm));
+ }
+ return 1;
+ }
+ return 0;
+}
diff --git a/gdb/arch/aarch64-insn.h b/gdb/arch/aarch64-insn.h
new file mode 100644
index 0000000..7775a34
--- /dev/null
+++ b/gdb/arch/aarch64-insn.h
@@ -0,0 +1,38 @@
+/* Copyright (C) 2009-2015 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#ifndef AARCH64_INSN_H
+#define AARCH64_INSN_H 1
+
+extern int aarch64_debug;
+
+int aarch64_decode_adrp (CORE_ADDR addr, uint32_t insn, unsigned *rd);
+
+int aarch64_decode_b (CORE_ADDR addr, uint32_t insn, int *is_bl,
+ int32_t *offset);
+
+int aarch64_decode_bcond (CORE_ADDR addr, uint32_t insn, unsigned *cond,
+ int32_t *offset);
+
+int aarch64_decode_cb (CORE_ADDR addr, uint32_t insn, int *is64,
+ int *is_cbnz, unsigned *rn, int32_t *offset);
+
+int aarch64_decode_tb (CORE_ADDR addr, uint32_t insn, int *is_tbnz,
+ unsigned *bit, unsigned *rt, int32_t *imm);
+
+#endif
diff --git a/gdb/configure.tgt b/gdb/configure.tgt
index c42b4df..33d4cfc 100644
--- a/gdb/configure.tgt
+++ b/gdb/configure.tgt
@@ -38,12 +38,12 @@ esac
case "${targ}" in
aarch64*-*-elf)
# Target: AArch64 embedded system
- gdb_target_obs="aarch64-tdep.o aarch64-newlib-tdep.o"
+ gdb_target_obs="aarch64-tdep.o aarch64-newlib-tdep.o aarch64-insn.o"
;;
aarch64*-*-linux*)
# Target: AArch64 linux
- gdb_target_obs="aarch64-tdep.o aarch64-linux-tdep.o \
+ gdb_target_obs="aarch64-tdep.o aarch64-linux-tdep.o aarch64-insn.o \
arm-tdep.o arm-linux-tdep.o \
glibc-tdep.o linux-tdep.o solib-svr4.o \
symfile-mem.o linux-record.o"
diff --git a/gdb/gdbserver/Makefile.in b/gdb/gdbserver/Makefile.in
index b715a32..d096663 100644
--- a/gdb/gdbserver/Makefile.in
+++ b/gdb/gdbserver/Makefile.in
@@ -625,6 +625,12 @@ linux-namespaces.o: ../nat/linux-namespaces.c
$(COMPILE) $<
$(POSTCOMPILE)
+# Architecture specific object files rules from ../arch
+
+aarch64-insn.o: ../arch/aarch64-insn.c
+ $(COMPILE) $<
+ $(POSTCOMPILE)
+
aarch64.c : $(srcdir)/../regformats/aarch64.dat $(regdat_sh)
$(SHELL) $(regdat_sh) $(srcdir)/../regformats/aarch64.dat aarch64.c
reg-arm.c : $(srcdir)/../regformats/reg-arm.dat $(regdat_sh)
diff --git a/gdb/gdbserver/configure.srv b/gdb/gdbserver/configure.srv
index aa232f8..a62df83 100644
--- a/gdb/gdbserver/configure.srv
+++ b/gdb/gdbserver/configure.srv
@@ -53,6 +53,7 @@ case "${target}" in
srv_tgtobj="linux-aarch64-low.o aarch64-linux-hw-point.o"
srv_tgtobj="$srv_tgtobj linux-aarch32-low.o"
srv_tgtobj="$srv_tgtobj aarch64-linux.o"
+ srv_tgtobj="$srv_tgtobj aarch64-insn.o"
srv_tgtobj="${srv_tgtobj} $srv_linux_obj"
srv_xmlfiles="aarch64.xml"
srv_xmlfiles="${srv_xmlfiles} aarch64-core.xml"
--
1.9.1
^ permalink raw reply [flat|nested] 37+ messages in thread* [PATCH 4/8] Implement target_emit_ops
2015-09-18 12:43 ` [PATCH 0/8 V2] [AArch64] Support fast tracepoints Yao Qi
` (3 preceding siblings ...)
2015-09-18 12:43 ` [PATCH 1/8] Move instruction decoding into new arch/ directory Yao Qi
@ 2015-09-18 12:43 ` Yao Qi
2015-09-18 12:57 ` Pierre Langlois
2016-02-05 20:09 ` Antoine Tremblay
2015-09-18 12:43 ` [PATCH 5/8] Enable fast tracepoint tests Yao Qi
` (3 subsequent siblings)
8 siblings, 2 replies; 37+ messages in thread
From: Yao Qi @ 2015-09-18 12:43 UTC (permalink / raw)
To: gdb-patches
From: Pierre Langlois <pierre.langlois@arm.com>
This patch implements compiling agent expressions to native code for
AArch64. This allows us to compile conditions set on fast tracepoints.
The compiled function has the following prologue:
High *------------------------------------------------------*
| LR |
| FP | <- FP
| x1 (ULONGEST *value) |
| x0 (unsigned char *regs) |
Low *------------------------------------------------------*
We save the function's argument on the stack as well as the return
address and the frame pointer. We then set the current frame pointer to
point to the previous one.
The generated code for the expression will freely update the stack
pointer so we use the frame pointer to refer to `*value' and `*regs'.
`*value' needs to be accessed in the epilogue of the function, in order
to set it to whatever is on top of the stack. `*regs' needs to be passed
down to the `gdb_agent_get_reg' function with the `reg' operation.
gdb/gdbserver/ChangeLog:
* linux-aarch64-low-.c: Include ax.h and tracepoint.h.
(enum aarch64_opcodes) <RET>, <SUBS>, <AND>, <ORR>, <ORN>,
<EOR>, <LSLV>, <LSRV>, <ASRV>, <SBFM>, <UBFM>, <CSINC>, <MUL>,
<NOP>: New.
(enum aarch64_condition_codes): New enum.
(w0): New static global.
(fp): Likewise.
(lr): Likewise.
(struct aarch64_memory_operand) <type>: New
MEMORY_OPERAND_POSTINDEX type.
(postindex_memory_operand): New helper function.
(emit_ret): New function.
(emit_load_store_pair): New function, factored out of emit_stp
with support for MEMORY_OPERAND_POSTINDEX.
(emit_stp): Rewrite using emit_load_store_pair.
(emit_ldp): New function.
(emit_load_store): Likewise.
(emit_ldr): Mention post-index instruction in comment.
(emit_ldrh): New function.
(emit_ldrb): New function.
(emit_ldrsw): Mention post-index instruction in comment.
(emit_str): Likewise.
(emit_subs): New function.
(emit_cmp): Likewise.
(emit_and): Likewise.
(emit_orr): Likewise.
(emit_orn): Likewise.
(emit_eor): Likewise.
(emit_mvn): Likewise.
(emit_lslv): Likewise.
(emit_lsrv): Likewise.
(emit_asrv): Likewise.
(emit_mul): Likewise.
(emit_sbfm): Likewise.
(emit_sbfx): Likewise.
(emit_ubfm): Likewise.
(emit_ubfx): Likewise.
(emit_csinc): Likewise.
(emit_cset): Likewise.
(emit_nop): Likewise.
(emit_ops_insns): New helper function.
(emit_pop): Likewise.
(emit_push): Likewise.
(aarch64_emit_prologue): New function.
(aarch64_emit_epilogue): Likewise.
(aarch64_emit_add): Likewise.
(aarch64_emit_sub): Likewise.
(aarch64_emit_mul): Likewise.
(aarch64_emit_lsh): Likewise.
(aarch64_emit_rsh_signed): Likewise.
(aarch64_emit_rsh_unsigned): Likewise.
(aarch64_emit_ext): Likewise.
(aarch64_emit_log_not): Likewise.
(aarch64_emit_bit_and): Likewise.
(aarch64_emit_bit_or): Likewise.
(aarch64_emit_bit_xor): Likewise.
(aarch64_emit_bit_not): Likewise.
(aarch64_emit_equal): Likewise.
(aarch64_emit_less_signed): Likewise.
(aarch64_emit_less_unsigned): Likewise.
(aarch64_emit_ref): Likewise.
(aarch64_emit_if_goto): Likewise.
(aarch64_emit_goto): Likewise.
(aarch64_write_goto_address): Likewise.
(aarch64_emit_const): Likewise.
(aarch64_emit_call): Likewise.
(aarch64_emit_reg): Likewise.
(aarch64_emit_pop): Likewise.
(aarch64_emit_stack_flush): Likewise.
(aarch64_emit_zero_ext): Likewise.
(aarch64_emit_swap): Likewise.
(aarch64_emit_stack_adjust): Likewise.
(aarch64_emit_int_call_1): Likewise.
(aarch64_emit_void_call_2): Likewise.
(aarch64_emit_eq_goto): Likewise.
(aarch64_emit_ne_goto): Likewise.
(aarch64_emit_lt_goto): Likewise.
(aarch64_emit_le_goto): Likewise.
(aarch64_emit_gt_goto): Likewise.
(aarch64_emit_ge_got): Likewise.
(aarch64_emit_ops_impl): New static global variable.
(aarch64_emit_ops): New target function, return
&aarch64_emit_ops_impl.
(struct linux_target_ops): Install it.
---
gdb/gdbserver/linux-aarch64-low.c | 1227 ++++++++++++++++++++++++++++++++++++-
1 file changed, 1213 insertions(+), 14 deletions(-)
diff --git a/gdb/gdbserver/linux-aarch64-low.c b/gdb/gdbserver/linux-aarch64-low.c
index e2d738b..669a1e6 100644
--- a/gdb/gdbserver/linux-aarch64-low.c
+++ b/gdb/gdbserver/linux-aarch64-low.c
@@ -26,6 +26,8 @@
#include "arch/aarch64-insn.h"
#include "linux-aarch32-low.h"
#include "elf/common.h"
+#include "ax.h"
+#include "tracepoint.h"
#include <signal.h>
#include <sys/user.h>
@@ -680,6 +682,8 @@ enum aarch64_opcodes
TBNZ = 0x37000000 | B,
/* BLR 1101 0110 0011 1111 0000 00rr rrr0 0000 */
BLR = 0xd63f0000,
+ /* RET 1101 0110 0101 1111 0000 00rr rrr0 0000 */
+ RET = 0xd65f0000,
/* STP s010 100o o0ii iiii irrr rrrr rrrr rrrr */
/* LDP s010 100o o1ii iiii irrr rrrr rrrr rrrr */
/* STP (SIMD&VFP) ss10 110o o0ii iiii irrr rrrr rrrr rrrr */
@@ -709,6 +713,29 @@ enum aarch64_opcodes
/* SUBS s11o ooo1 xxxx xxxx xxxx xxxx xxxx xxxx */
ADD = 0x01000000,
SUB = 0x40000000 | ADD,
+ SUBS = 0x20000000 | SUB,
+ /* AND s000 1010 xx0x xxxx xxxx xxxx xxxx xxxx */
+ /* ORR s010 1010 xx0x xxxx xxxx xxxx xxxx xxxx */
+ /* ORN s010 1010 xx1x xxxx xxxx xxxx xxxx xxxx */
+ /* EOR s100 1010 xx0x xxxx xxxx xxxx xxxx xxxx */
+ AND = 0x0a000000,
+ ORR = 0x20000000 | AND,
+ ORN = 0x00200000 | ORR,
+ EOR = 0x40000000 | AND,
+ /* LSLV s001 1010 110r rrrr 0010 00rr rrrr rrrr */
+ /* LSRV s001 1010 110r rrrr 0010 01rr rrrr rrrr */
+ /* ASRV s001 1010 110r rrrr 0010 10rr rrrr rrrr */
+ LSLV = 0x1ac02000,
+ LSRV = 0x00000400 | LSLV,
+ ASRV = 0x00000800 | LSLV,
+ /* SBFM s001 0011 0nii iiii iiii iirr rrrr rrrr */
+ SBFM = 0x13000000,
+ /* UBFM s101 0011 0nii iiii iiii iirr rrrr rrrr */
+ UBFM = 0x40000000 | SBFM,
+ /* CSINC s001 1010 100r rrrr cccc 01rr rrrr rrrr */
+ CSINC = 0x9a800400,
+ /* MUL s001 1011 000r rrrr 0111 11rr rrrr rrrr */
+ MUL = 0x1b007c00,
/* MSR (register) 1101 0101 0001 oooo oooo oooo ooor rrrr */
/* MRS 1101 0101 0011 oooo oooo oooo ooor rrrr */
MSR = 0xd5100000,
@@ -717,6 +744,20 @@ enum aarch64_opcodes
HINT = 0xd503201f,
SEVL = (5 << 5) | HINT,
WFE = (2 << 5) | HINT,
+ NOP = (0 << 5) | HINT,
+};
+
+/* List of condition codes that we need. */
+
+enum aarch64_condition_codes
+{
+ EQ = 0x0,
+ NE = 0x1,
+ LO = 0x3,
+ GE = 0xa,
+ LT = 0xb,
+ GT = 0xc,
+ LE = 0xd,
};
/* Representation of a general purpose register of the form xN or wN.
@@ -759,12 +800,15 @@ static const struct aarch64_register x3 = { 3, 1 };
static const struct aarch64_register x4 = { 4, 1 };
/* General purpose scratch registers (32 bit). */
+static const struct aarch64_register w0 = { 0, 0 };
static const struct aarch64_register w2 = { 2, 0 };
/* Intra-procedure scratch registers. */
static const struct aarch64_register ip0 = { 16, 1 };
/* Special purpose registers. */
+static const struct aarch64_register fp = { 29, 1 };
+static const struct aarch64_register lr = { 30, 1 };
static const struct aarch64_register sp = { 31, 1 };
static const struct aarch64_register xzr = { 31, 1 };
@@ -817,8 +861,9 @@ immediate_operand (uint32_t imm)
The types correspond to the following variants:
- MEMORY_OPERAND_OFFSET: LDR rt, [rn, #offset]
- MEMORY_OPERAND_PREINDEX: LDR rt, [rn, #index]! */
+ MEMORY_OPERAND_OFFSET: LDR rt, [rn, #offset]
+ MEMORY_OPERAND_PREINDEX: LDR rt, [rn, #index]!
+ MEMORY_OPERAND_POSTINDEX: LDR rt, [rn], #index */
struct aarch64_memory_operand
{
@@ -827,6 +872,7 @@ struct aarch64_memory_operand
{
MEMORY_OPERAND_OFFSET,
MEMORY_OPERAND_PREINDEX,
+ MEMORY_OPERAND_POSTINDEX,
} type;
/* Index from the base register. */
int32_t index;
@@ -854,6 +900,17 @@ preindex_memory_operand (int32_t index)
return (struct aarch64_memory_operand) { MEMORY_OPERAND_PREINDEX, index };
}
+/* Helper function to create a post-index memory operand.
+
+ For example:
+ p += emit_ldr (p, x0, sp, postindex_memory_operand (16)); */
+
+static struct aarch64_memory_operand
+postindex_memory_operand (int32_t index)
+{
+ return (struct aarch64_memory_operand) { MEMORY_OPERAND_POSTINDEX, index };
+}
+
/* System control registers. These special registers can be written and
read with the MRS and MSR instructions.
@@ -986,20 +1043,24 @@ emit_blr (uint32_t *buf, struct aarch64_register rn)
return emit_insn (buf, BLR | ENCODE (rn.num, 5, 5));
}
-/* Write a STP instruction into *BUF.
+/* Write a RET instruction into *BUF.
- STP rt, rt2, [rn, #offset]
- STP rt, rt2, [rn, #index]!
+ RET xn
- RT and RT2 are the registers to store.
- RN is the base address register.
- OFFSET is the immediate to add to the base address. It is limited to a
- -512 .. 504 range (7 bits << 3). */
+ RN is the register to branch to. */
static int
-emit_stp (uint32_t *buf, struct aarch64_register rt,
- struct aarch64_register rt2, struct aarch64_register rn,
- struct aarch64_memory_operand operand)
+emit_ret (uint32_t *buf, struct aarch64_register rn)
+{
+ return emit_insn (buf, RET | ENCODE (rn.num, 5, 5));
+}
+
+static int
+emit_load_store_pair (uint32_t *buf, enum aarch64_opcodes opcode,
+ struct aarch64_register rt,
+ struct aarch64_register rt2,
+ struct aarch64_register rn,
+ struct aarch64_memory_operand operand)
{
uint32_t opc;
uint32_t pre_index;
@@ -1018,6 +1079,12 @@ emit_stp (uint32_t *buf, struct aarch64_register rt,
write_back = ENCODE (0, 1, 23);
break;
}
+ case MEMORY_OPERAND_POSTINDEX:
+ {
+ pre_index = ENCODE (0, 1, 24);
+ write_back = ENCODE (1, 1, 23);
+ break;
+ }
case MEMORY_OPERAND_PREINDEX:
{
pre_index = ENCODE (1, 1, 24);
@@ -1028,11 +1095,49 @@ emit_stp (uint32_t *buf, struct aarch64_register rt,
return 0;
}
- return emit_insn (buf, STP | opc | pre_index | write_back
+ return emit_insn (buf, opcode | opc | pre_index | write_back
| ENCODE (operand.index >> 3, 7, 15) | ENCODE (rt2.num, 5, 10)
| ENCODE (rn.num, 5, 5) | ENCODE (rt.num, 5, 0));
}
+/* Write a STP instruction into *BUF.
+
+ STP rt, rt2, [rn, #offset]
+ STP rt, rt2, [rn, #index]!
+ STP rt, rt2, [rn], #index
+
+ RT and RT2 are the registers to store.
+ RN is the base address register.
+ OFFSET is the immediate to add to the base address. It is limited to a
+ -512 .. 504 range (7 bits << 3). */
+
+static int
+emit_stp (uint32_t *buf, struct aarch64_register rt,
+ struct aarch64_register rt2, struct aarch64_register rn,
+ struct aarch64_memory_operand operand)
+{
+ return emit_load_store_pair (buf, STP, rt, rt2, rn, operand);
+}
+
+/* Write a LDP instruction into *BUF.
+
+ LDP rt, rt2, [rn, #offset]
+ LDP rt, rt2, [rn, #index]!
+ LDP rt, rt2, [rn], #index
+
+ RT and RT2 are the registers to store.
+ RN is the base address register.
+ OFFSET is the immediate to add to the base address. It is limited to a
+ -512 .. 504 range (7 bits << 3). */
+
+static int
+emit_ldp (uint32_t *buf, struct aarch64_register rt,
+ struct aarch64_register rt2, struct aarch64_register rn,
+ struct aarch64_memory_operand operand)
+{
+ return emit_load_store_pair (buf, LDP, rt, rt2, rn, operand);
+}
+
/* Write a LDP (SIMD&VFP) instruction using Q registers into *BUF.
LDP qt, qt2, [rn, #offset]
@@ -1094,6 +1199,16 @@ emit_load_store (uint32_t *buf, uint32_t size, enum aarch64_opcodes opcode,
| ENCODE (operand.index >> 3, 12, 10)
| ENCODE (rn.num, 5, 5) | ENCODE (rt.num, 5, 0));
}
+ case MEMORY_OPERAND_POSTINDEX:
+ {
+ uint32_t post_index = ENCODE (1, 2, 10);
+
+ op = ENCODE (0, 1, 24);
+
+ return emit_insn (buf, opcode | ENCODE (size, 2, 30) | op
+ | post_index | ENCODE (operand.index, 9, 12)
+ | ENCODE (rn.num, 5, 5) | ENCODE (rt.num, 5, 0));
+ }
case MEMORY_OPERAND_PREINDEX:
{
uint32_t pre_index = ENCODE (3, 2, 10);
@@ -1113,6 +1228,7 @@ emit_load_store (uint32_t *buf, uint32_t size, enum aarch64_opcodes opcode,
LDR rt, [rn, #offset]
LDR rt, [rn, #index]!
+ LDR rt, [rn], #index
RT is the register to store.
RN is the base address register.
@@ -1126,10 +1242,49 @@ emit_ldr (uint32_t *buf, struct aarch64_register rt,
return emit_load_store (buf, rt.is64 ? 3 : 2, LDR, rt, rn, operand);
}
+/* Write a LDRH instruction into *BUF.
+
+ LDRH wt, [xn, #offset]
+ LDRH wt, [xn, #index]!
+ LDRH wt, [xn], #index
+
+ RT is the register to store.
+ RN is the base address register.
+ OFFSET is the immediate to add to the base address. It is limited to
+ 0 .. 32760 range (12 bits << 3). */
+
+static int
+emit_ldrh (uint32_t *buf, struct aarch64_register rt,
+ struct aarch64_register rn,
+ struct aarch64_memory_operand operand)
+{
+ return emit_load_store (buf, 1, LDR, rt, rn, operand);
+}
+
+/* Write a LDRB instruction into *BUF.
+
+ LDRB wt, [xn, #offset]
+ LDRB wt, [xn, #index]!
+ LDRB wt, [xn], #index
+
+ RT is the register to store.
+ RN is the base address register.
+ OFFSET is the immediate to add to the base address. It is limited to
+ 0 .. 32760 range (12 bits << 3). */
+
+static int
+emit_ldrb (uint32_t *buf, struct aarch64_register rt,
+ struct aarch64_register rn,
+ struct aarch64_memory_operand operand)
+{
+ return emit_load_store (buf, 0, LDR, rt, rn, operand);
+}
+
/* Write a LDRSW instruction into *BUF. The register size is 64-bit.
LDRSW xt, [rn, #offset]
LDRSW xt, [rn, #index]!
+ LDRSW xt, [rn], #index
RT is the register to store.
RN is the base address register.
@@ -1148,6 +1303,7 @@ emit_ldrsw (uint32_t *buf, struct aarch64_register rt,
STR rt, [rn, #offset]
STR rt, [rn, #index]!
+ STR rt, [rn], #index
RT is the register to store.
RN is the base address register.
@@ -1390,6 +1546,165 @@ emit_mov_addr (uint32_t *buf, struct aarch64_register rd, CORE_ADDR addr)
return p - buf;
}
+/* Write a SUBS instruction into *BUF.
+
+ SUBS rd, rn, rm
+
+ This instruction update the condition flags.
+
+ RD is the destination register.
+ RN and RM are the source registers. */
+
+static int
+emit_subs (uint32_t *buf, struct aarch64_register rd,
+ struct aarch64_register rn, struct aarch64_operand operand)
+{
+ return emit_data_processing (buf, SUBS, rd, rn, operand);
+}
+
+/* Write a CMP instruction into *BUF.
+
+ CMP rn, rm
+
+ This instruction is an alias of SUBS xzr, rn, rm.
+
+ RN and RM are the registers to compare. */
+
+static int
+emit_cmp (uint32_t *buf, struct aarch64_register rn,
+ struct aarch64_operand operand)
+{
+ return emit_subs (buf, xzr, rn, operand);
+}
+
+/* Write a AND instruction into *BUF.
+
+ AND rd, rn, rm
+
+ RD is the destination register.
+ RN and RM are the source registers. */
+
+static int
+emit_and (uint32_t *buf, struct aarch64_register rd,
+ struct aarch64_register rn, struct aarch64_register rm)
+{
+ return emit_data_processing_reg (buf, AND, rd, rn, rm);
+}
+
+/* Write a ORR instruction into *BUF.
+
+ ORR rd, rn, rm
+
+ RD is the destination register.
+ RN and RM are the source registers. */
+
+static int
+emit_orr (uint32_t *buf, struct aarch64_register rd,
+ struct aarch64_register rn, struct aarch64_register rm)
+{
+ return emit_data_processing_reg (buf, ORR, rd, rn, rm);
+}
+
+/* Write a ORN instruction into *BUF.
+
+ ORN rd, rn, rm
+
+ RD is the destination register.
+ RN and RM are the source registers. */
+
+static int
+emit_orn (uint32_t *buf, struct aarch64_register rd,
+ struct aarch64_register rn, struct aarch64_register rm)
+{
+ return emit_data_processing_reg (buf, ORN, rd, rn, rm);
+}
+
+/* Write a EOR instruction into *BUF.
+
+ EOR rd, rn, rm
+
+ RD is the destination register.
+ RN and RM are the source registers. */
+
+static int
+emit_eor (uint32_t *buf, struct aarch64_register rd,
+ struct aarch64_register rn, struct aarch64_register rm)
+{
+ return emit_data_processing_reg (buf, EOR, rd, rn, rm);
+}
+
+/* Write a MVN instruction into *BUF.
+
+ MVN rd, rm
+
+ This is an alias for ORN rd, xzr, rm.
+
+ RD is the destination register.
+ RM is the source register. */
+
+static int
+emit_mvn (uint32_t *buf, struct aarch64_register rd,
+ struct aarch64_register rm)
+{
+ return emit_orn (buf, rd, xzr, rm);
+}
+
+/* Write a LSLV instruction into *BUF.
+
+ LSLV rd, rn, rm
+
+ RD is the destination register.
+ RN and RM are the source registers. */
+
+static int
+emit_lslv (uint32_t *buf, struct aarch64_register rd,
+ struct aarch64_register rn, struct aarch64_register rm)
+{
+ return emit_data_processing_reg (buf, LSLV, rd, rn, rm);
+}
+
+/* Write a LSRV instruction into *BUF.
+
+ LSRV rd, rn, rm
+
+ RD is the destination register.
+ RN and RM are the source registers. */
+
+static int
+emit_lsrv (uint32_t *buf, struct aarch64_register rd,
+ struct aarch64_register rn, struct aarch64_register rm)
+{
+ return emit_data_processing_reg (buf, LSRV, rd, rn, rm);
+}
+
+/* Write a ASRV instruction into *BUF.
+
+ ASRV rd, rn, rm
+
+ RD is the destination register.
+ RN and RM are the source registers. */
+
+static int
+emit_asrv (uint32_t *buf, struct aarch64_register rd,
+ struct aarch64_register rn, struct aarch64_register rm)
+{
+ return emit_data_processing_reg (buf, ASRV, rd, rn, rm);
+}
+
+/* Write a MUL instruction into *BUF.
+
+ MUL rd, rn, rm
+
+ RD is the destination register.
+ RN and RM are the source registers. */
+
+static int
+emit_mul (uint32_t *buf, struct aarch64_register rd,
+ struct aarch64_register rn, struct aarch64_register rm)
+{
+ return emit_data_processing_reg (buf, MUL, rd, rn, rm);
+}
+
/* Write a MRS instruction into *BUF. The register size is 64-bit.
MRS xt, system_reg
@@ -1440,6 +1755,150 @@ emit_wfe (uint32_t *buf)
return emit_insn (buf, WFE);
}
+/* Write a SBFM instruction into *BUF.
+
+ SBFM rd, rn, #immr, #imms
+
+ This instruction moves the bits from #immr to #imms into the
+ destination, sign extending the result.
+
+ RD is the destination register.
+ RN is the source register.
+ IMMR is the bit number to start at (least significant bit).
+ IMMS is the bit number to stop at (most significant bit). */
+
+static int
+emit_sbfm (uint32_t *buf, struct aarch64_register rd,
+ struct aarch64_register rn, uint32_t immr, uint32_t imms)
+{
+ uint32_t size = ENCODE (rd.is64, 1, 31);
+ uint32_t n = ENCODE (rd.is64, 1, 22);
+
+ return emit_insn (buf, SBFM | size | n | ENCODE (immr, 6, 16)
+ | ENCODE (imms, 6, 10) | ENCODE (rn.num, 5, 5)
+ | ENCODE (rd.num, 5, 0));
+}
+
+/* Write a SBFX instruction into *BUF.
+
+ SBFX rd, rn, #lsb, #width
+
+ This instruction moves #width bits from #lsb into the destination, sign
+ extending the result. This is an alias for:
+
+ SBFM rd, rn, #lsb, #(lsb + width - 1)
+
+ RD is the destination register.
+ RN is the source register.
+ LSB is the bit number to start at (least significant bit).
+ WIDTH is the number of bits to move. */
+
+static int
+emit_sbfx (uint32_t *buf, struct aarch64_register rd,
+ struct aarch64_register rn, uint32_t lsb, uint32_t width)
+{
+ return emit_sbfm (buf, rd, rn, lsb, lsb + width - 1);
+}
+
+/* Write a UBFM instruction into *BUF.
+
+ UBFM rd, rn, #immr, #imms
+
+ This instruction moves the bits from #immr to #imms into the
+ destination, extending the result with zeros.
+
+ RD is the destination register.
+ RN is the source register.
+ IMMR is the bit number to start at (least significant bit).
+ IMMS is the bit number to stop at (most significant bit). */
+
+static int
+emit_ubfm (uint32_t *buf, struct aarch64_register rd,
+ struct aarch64_register rn, uint32_t immr, uint32_t imms)
+{
+ uint32_t size = ENCODE (rd.is64, 1, 31);
+ uint32_t n = ENCODE (rd.is64, 1, 22);
+
+ return emit_insn (buf, UBFM | size | n | ENCODE (immr, 6, 16)
+ | ENCODE (imms, 6, 10) | ENCODE (rn.num, 5, 5)
+ | ENCODE (rd.num, 5, 0));
+}
+
+/* Write a UBFX instruction into *BUF.
+
+ UBFX rd, rn, #lsb, #width
+
+ This instruction moves #width bits from #lsb into the destination,
+ extending the result with zeros. This is an alias for:
+
+ UBFM rd, rn, #lsb, #(lsb + width - 1)
+
+ RD is the destination register.
+ RN is the source register.
+ LSB is the bit number to start at (least significant bit).
+ WIDTH is the number of bits to move. */
+
+static int
+emit_ubfx (uint32_t *buf, struct aarch64_register rd,
+ struct aarch64_register rn, uint32_t lsb, uint32_t width)
+{
+ return emit_ubfm (buf, rd, rn, lsb, lsb + width - 1);
+}
+
+/* Write a CSINC instruction into *BUF.
+
+ CSINC rd, rn, rm, cond
+
+ This instruction conditionally increments rn or rm and places the result
+ in rd. rn is chosen is the condition is true.
+
+ RD is the destination register.
+ RN and RM are the source registers.
+ COND is the encoded condition. */
+
+static int
+emit_csinc (uint32_t *buf, struct aarch64_register rd,
+ struct aarch64_register rn, struct aarch64_register rm,
+ unsigned cond)
+{
+ uint32_t size = ENCODE (rd.is64, 1, 31);
+
+ return emit_insn (buf, CSINC | size | ENCODE (rm.num, 5, 16)
+ | ENCODE (cond, 4, 12) | ENCODE (rn.num, 5, 5)
+ | ENCODE (rd.num, 5, 0));
+}
+
+/* Write a CSET instruction into *BUF.
+
+ CSET rd, cond
+
+ This instruction conditionally write 1 or 0 in the destination register.
+ 1 is written if the condition is true. This is an alias for:
+
+ CSINC rd, xzr, xzr, !cond
+
+ Note that the condition needs to be inverted.
+
+ RD is the destination register.
+ RN and RM are the source registers.
+ COND is the encoded condition. */
+
+static int
+emit_cset (uint32_t *buf, struct aarch64_register rd, unsigned cond)
+{
+ /* The least significant bit of the condition needs toggling in order to
+ invert it. */
+ return emit_csinc (buf, rd, xzr, xzr, cond ^ 0x1);
+}
+
+/* Write a NOP instruction into *BUF. */
+
+static int
+emit_nop (uint32_t *buf)
+{
+ return emit_insn (buf, NOP);
+}
+
/* Write LEN instructions from BUF into the inferior memory at *TO.
Note instructions are always little endian on AArch64, unlike data. */
@@ -2024,6 +2483,746 @@ aarch64_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint,
return 0;
}
+/* Helper function writing LEN instructions from START into
+ current_insn_ptr. */
+
+static void
+emit_ops_insns (const uint32_t *start, int len)
+{
+ CORE_ADDR buildaddr = current_insn_ptr;
+
+ if (debug_threads)
+ debug_printf ("Adding %d instrucions at %s\n",
+ len, paddress (buildaddr));
+
+ append_insns (&buildaddr, len, start);
+ current_insn_ptr = buildaddr;
+}
+
+/* Pop a register from the stack. */
+
+static int
+emit_pop (uint32_t *buf, struct aarch64_register rt)
+{
+ return emit_ldr (buf, rt, sp, postindex_memory_operand (1 * 16));
+}
+
+/* Push a register on the stack. */
+
+static int
+emit_push (uint32_t *buf, struct aarch64_register rt)
+{
+ return emit_str (buf, rt, sp, preindex_memory_operand (-1 * 16));
+}
+
+/* Implementation of emit_ops method "emit_prologue". */
+
+static void
+aarch64_emit_prologue (void)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ /* This function emit a prologue for the following function prototype:
+
+ enum eval_result_type f (unsigned char *regs,
+ ULONGEST *value);
+
+ The first argument is a buffer of raw registers. The second
+ argument is the result of
+ evaluating the expression, which will be set to whatever is on top of
+ the stack at the end.
+
+ The stack set up by the prologue is as such:
+
+ High *------------------------------------------------------*
+ | LR |
+ | FP | <- FP
+ | x1 (ULONGEST *value) |
+ | x0 (unsigned char *regs) |
+ Low *------------------------------------------------------*
+
+ As we are implementing a stack machine, each opcode can expand the
+ stack so we never know how far we are from the data saved by this
+ prologue. In order to be able refer to value and regs later, we save
+ the current stack pointer in the frame pointer. This way, it is not
+ clobbered when calling C functions.
+
+ Finally, throughtout every operation, we are using register x0 as the
+ top of the stack, and x1 as a scratch register. */
+
+ p += emit_stp (p, x0, x1, sp, preindex_memory_operand (-2 * 16));
+ p += emit_str (p, lr, sp, offset_memory_operand (3 * 8));
+ p += emit_str (p, fp, sp, offset_memory_operand (2 * 8));
+
+ p += emit_add (p, fp, sp, immediate_operand (2 * 8));
+
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_epilogue". */
+
+static void
+aarch64_emit_epilogue (void)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ /* Store the result of the expression (x0) in *value. */
+ p += emit_sub (p, x1, fp, immediate_operand (1 * 8));
+ p += emit_ldr (p, x1, x1, offset_memory_operand (0));
+ p += emit_str (p, x0, x1, offset_memory_operand (0));
+
+ /* Restore the previous state. */
+ p += emit_add (p, sp, fp, immediate_operand (2 * 8));
+ p += emit_ldp (p, fp, lr, fp, offset_memory_operand (0));
+
+ /* Return expr_eval_no_error. */
+ p += emit_mov (p, x0, immediate_operand (expr_eval_no_error));
+ p += emit_ret (p, lr);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_add". */
+
+static void
+aarch64_emit_add (void)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_pop (p, x1);
+ p += emit_add (p, x0, x0, register_operand (x1));
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_sub". */
+
+static void
+aarch64_emit_sub (void)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_pop (p, x1);
+ p += emit_sub (p, x0, x0, register_operand (x1));
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_mul". */
+
+static void
+aarch64_emit_mul (void)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_pop (p, x1);
+ p += emit_mul (p, x0, x1, x0);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_lsh". */
+
+static void
+aarch64_emit_lsh (void)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_pop (p, x1);
+ p += emit_lslv (p, x0, x1, x0);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_rsh_signed". */
+
+static void
+aarch64_emit_rsh_signed (void)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_pop (p, x1);
+ p += emit_asrv (p, x0, x1, x0);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_rsh_unsigned". */
+
+static void
+aarch64_emit_rsh_unsigned (void)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_pop (p, x1);
+ p += emit_lsrv (p, x0, x1, x0);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_ext". */
+
+static void
+aarch64_emit_ext (int arg)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_sbfx (p, x0, x0, 0, arg);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_log_not". */
+
+static void
+aarch64_emit_log_not (void)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ /* If the top of the stack is 0, replace it with 1. Else replace it with
+ 0. */
+
+ p += emit_cmp (p, x0, immediate_operand (0));
+ p += emit_cset (p, x0, EQ);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_bit_and". */
+
+static void
+aarch64_emit_bit_and (void)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_pop (p, x1);
+ p += emit_and (p, x0, x0, x1);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_bit_or". */
+
+static void
+aarch64_emit_bit_or (void)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_pop (p, x1);
+ p += emit_orr (p, x0, x0, x1);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_bit_xor". */
+
+static void
+aarch64_emit_bit_xor (void)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_pop (p, x1);
+ p += emit_eor (p, x0, x0, x1);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_bit_not". */
+
+static void
+aarch64_emit_bit_not (void)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_mvn (p, x0, x0);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_equal". */
+
+static void
+aarch64_emit_equal (void)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_pop (p, x1);
+ p += emit_cmp (p, x0, register_operand (x1));
+ p += emit_cset (p, x0, EQ);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_less_signed". */
+
+static void
+aarch64_emit_less_signed (void)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_pop (p, x1);
+ p += emit_cmp (p, x1, register_operand (x0));
+ p += emit_cset (p, x0, LT);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_less_unsigned". */
+
+static void
+aarch64_emit_less_unsigned (void)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_pop (p, x1);
+ p += emit_cmp (p, x1, register_operand (x0));
+ p += emit_cset (p, x0, LO);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_ref". */
+
+static void
+aarch64_emit_ref (int size)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ switch (size)
+ {
+ case 1:
+ p += emit_ldrb (p, w0, x0, offset_memory_operand (0));
+ break;
+ case 2:
+ p += emit_ldrh (p, w0, x0, offset_memory_operand (0));
+ break;
+ case 4:
+ p += emit_ldr (p, w0, x0, offset_memory_operand (0));
+ break;
+ case 8:
+ p += emit_ldr (p, x0, x0, offset_memory_operand (0));
+ break;
+ default:
+ /* Unknown size, bail on compilation. */
+ emit_error = 1;
+ break;
+ }
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_if_goto". */
+
+static void
+aarch64_emit_if_goto (int *offset_p, int *size_p)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ /* The Z flag is set or cleared here. */
+ p += emit_cmp (p, x0, immediate_operand (0));
+ /* This instruction must not change the Z flag. */
+ p += emit_pop (p, x0);
+ /* Branch over the next instruction if x0 == 0. */
+ p += emit_bcond (p, EQ, 8);
+
+ /* The NOP instruction will be patched with an unconditional branch. */
+ if (offset_p)
+ *offset_p = (p - buf) * 4;
+ if (size_p)
+ *size_p = 4;
+ p += emit_nop (p);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_goto". */
+
+static void
+aarch64_emit_goto (int *offset_p, int *size_p)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ /* The NOP instruction will be patched with an unconditional branch. */
+ if (offset_p)
+ *offset_p = 0;
+ if (size_p)
+ *size_p = 4;
+ p += emit_nop (p);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "write_goto_address". */
+
+void
+aarch64_write_goto_address (CORE_ADDR from, CORE_ADDR to, int size)
+{
+ uint32_t insn;
+
+ emit_b (&insn, 0, to - from);
+ append_insns (&from, 1, &insn);
+}
+
+/* Implementation of emit_ops method "emit_const". */
+
+static void
+aarch64_emit_const (LONGEST num)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_mov_addr (p, x0, num);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_call". */
+
+static void
+aarch64_emit_call (CORE_ADDR fn)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_mov_addr (p, ip0, fn);
+ p += emit_blr (p, ip0);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_reg". */
+
+static void
+aarch64_emit_reg (int reg)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ /* Set x0 to struct fast_tracepoint_ctx *ctx->regs. */
+ p += emit_sub (p, x0, fp, immediate_operand (2 * 8));
+ p += emit_ldr (p, x0, x0, offset_memory_operand (0));
+ p += emit_mov (p, x1, immediate_operand (reg));
+
+ emit_ops_insns (buf, p - buf);
+
+ aarch64_emit_call (get_raw_reg_func_addr ());
+}
+
+/* Implementation of emit_ops method "emit_pop". */
+
+static void
+aarch64_emit_pop (void)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_pop (p, x0);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_stack_flush". */
+
+static void
+aarch64_emit_stack_flush (void)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_push (p, x0);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_zero_ext". */
+
+static void
+aarch64_emit_zero_ext (int arg)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_ubfx (p, x0, x0, 0, arg);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_swap". */
+
+static void
+aarch64_emit_swap (void)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_ldr (p, x1, sp, offset_memory_operand (0 * 16));
+ p += emit_str (p, x0, sp, offset_memory_operand (0 * 16));
+ p += emit_mov (p, x0, register_operand (x1));
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_stack_adjust". */
+
+static void
+aarch64_emit_stack_adjust (int n)
+{
+ /* This is not needed with our design. */
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_add (p, sp, sp, immediate_operand (n * 16));
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_int_call_1". */
+
+static void
+aarch64_emit_int_call_1 (CORE_ADDR fn, int arg1)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_mov (p, x0, immediate_operand (arg1));
+
+ emit_ops_insns (buf, p - buf);
+
+ aarch64_emit_call (fn);
+}
+
+/* Implementation of emit_ops method "emit_void_call_2". */
+
+static void
+aarch64_emit_void_call_2 (CORE_ADDR fn, int arg1)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ /* Push x0 on the stack. */
+ aarch64_emit_stack_flush ();
+
+ /* Setup arguments for the function call:
+
+ x0: arg1
+ x1: top of the stack
+
+ MOV x1, x0
+ MOV x0, #arg1 */
+
+ p += emit_mov (p, x1, register_operand (x0));
+ p += emit_mov (p, x0, immediate_operand (arg1));
+
+ emit_ops_insns (buf, p - buf);
+
+ aarch64_emit_call (fn);
+
+ /* Restore x0. */
+ aarch64_emit_pop ();
+}
+
+/* Implementation of emit_ops method "emit_eq_goto". */
+
+static void
+aarch64_emit_eq_goto (int *offset_p, int *size_p)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_pop (p, x1);
+ p += emit_cmp (p, x1, register_operand (x0));
+ /* Branch over the next instruction if x0 != x1. */
+ p += emit_bcond (p, NE, 8);
+ /* The NOP instruction will be patched with an unconditional branch. */
+ if (offset_p)
+ *offset_p = (p - buf) * 4;
+ if (size_p)
+ *size_p = 4;
+ p += emit_nop (p);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_ne_goto". */
+
+static void
+aarch64_emit_ne_goto (int *offset_p, int *size_p)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_pop (p, x1);
+ p += emit_cmp (p, x1, register_operand (x0));
+ /* Branch over the next instruction if x0 == x1. */
+ p += emit_bcond (p, EQ, 8);
+ /* The NOP instruction will be patched with an unconditional branch. */
+ if (offset_p)
+ *offset_p = (p - buf) * 4;
+ if (size_p)
+ *size_p = 4;
+ p += emit_nop (p);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_lt_goto". */
+
+static void
+aarch64_emit_lt_goto (int *offset_p, int *size_p)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_pop (p, x1);
+ p += emit_cmp (p, x1, register_operand (x0));
+ /* Branch over the next instruction if x0 >= x1. */
+ p += emit_bcond (p, GE, 8);
+ /* The NOP instruction will be patched with an unconditional branch. */
+ if (offset_p)
+ *offset_p = (p - buf) * 4;
+ if (size_p)
+ *size_p = 4;
+ p += emit_nop (p);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_le_goto". */
+
+static void
+aarch64_emit_le_goto (int *offset_p, int *size_p)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_pop (p, x1);
+ p += emit_cmp (p, x1, register_operand (x0));
+ /* Branch over the next instruction if x0 > x1. */
+ p += emit_bcond (p, GT, 8);
+ /* The NOP instruction will be patched with an unconditional branch. */
+ if (offset_p)
+ *offset_p = (p - buf) * 4;
+ if (size_p)
+ *size_p = 4;
+ p += emit_nop (p);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_gt_goto". */
+
+static void
+aarch64_emit_gt_goto (int *offset_p, int *size_p)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_pop (p, x1);
+ p += emit_cmp (p, x1, register_operand (x0));
+ /* Branch over the next instruction if x0 <= x1. */
+ p += emit_bcond (p, LE, 8);
+ /* The NOP instruction will be patched with an unconditional branch. */
+ if (offset_p)
+ *offset_p = (p - buf) * 4;
+ if (size_p)
+ *size_p = 4;
+ p += emit_nop (p);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+/* Implementation of emit_ops method "emit_ge_got". */
+
+static void
+aarch64_emit_ge_got (int *offset_p, int *size_p)
+{
+ uint32_t buf[16];
+ uint32_t *p = buf;
+
+ p += emit_pop (p, x1);
+ p += emit_cmp (p, x1, register_operand (x0));
+ /* Branch over the next instruction if x0 <= x1. */
+ p += emit_bcond (p, LT, 8);
+ /* The NOP instruction will be patched with an unconditional branch. */
+ if (offset_p)
+ *offset_p = (p - buf) * 4;
+ if (size_p)
+ *size_p = 4;
+ p += emit_nop (p);
+
+ emit_ops_insns (buf, p - buf);
+}
+
+static struct emit_ops aarch64_emit_ops_impl =
+{
+ aarch64_emit_prologue,
+ aarch64_emit_epilogue,
+ aarch64_emit_add,
+ aarch64_emit_sub,
+ aarch64_emit_mul,
+ aarch64_emit_lsh,
+ aarch64_emit_rsh_signed,
+ aarch64_emit_rsh_unsigned,
+ aarch64_emit_ext,
+ aarch64_emit_log_not,
+ aarch64_emit_bit_and,
+ aarch64_emit_bit_or,
+ aarch64_emit_bit_xor,
+ aarch64_emit_bit_not,
+ aarch64_emit_equal,
+ aarch64_emit_less_signed,
+ aarch64_emit_less_unsigned,
+ aarch64_emit_ref,
+ aarch64_emit_if_goto,
+ aarch64_emit_goto,
+ aarch64_write_goto_address,
+ aarch64_emit_const,
+ aarch64_emit_call,
+ aarch64_emit_reg,
+ aarch64_emit_pop,
+ aarch64_emit_stack_flush,
+ aarch64_emit_zero_ext,
+ aarch64_emit_swap,
+ aarch64_emit_stack_adjust,
+ aarch64_emit_int_call_1,
+ aarch64_emit_void_call_2,
+ aarch64_emit_eq_goto,
+ aarch64_emit_ne_goto,
+ aarch64_emit_lt_goto,
+ aarch64_emit_le_goto,
+ aarch64_emit_gt_goto,
+ aarch64_emit_ge_got,
+};
+
+/* Implementation of linux_target_ops method "emit_ops". */
+
+static struct emit_ops *
+aarch64_emit_ops (void)
+{
+ return &aarch64_emit_ops_impl;
+}
+
/* Implementation of linux_target_ops method
"get_min_fast_tracepoint_insn_len". */
@@ -2071,7 +3270,7 @@ struct linux_target_ops the_low_target =
aarch64_supports_tracepoints,
aarch64_get_thread_area,
aarch64_install_fast_tracepoint_jump_pad,
- NULL, /* emit_ops */
+ aarch64_emit_ops,
aarch64_get_min_fast_tracepoint_insn_len,
aarch64_supports_range_stepping,
};
--
1.9.1
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [PATCH 4/8] Implement target_emit_ops
2015-09-18 12:43 ` [PATCH 4/8] Implement target_emit_ops Yao Qi
@ 2015-09-18 12:57 ` Pierre Langlois
2016-02-05 20:09 ` Antoine Tremblay
1 sibling, 0 replies; 37+ messages in thread
From: Pierre Langlois @ 2015-09-18 12:57 UTC (permalink / raw)
To: Yao Qi, gdb-patches; +Cc: pierre.langlois
Hi Yao,
Thank you for doing this! I've pointed out a couple of nits below.
On 18/09/15 13:43, Yao Qi wrote:
> From: Pierre Langlois <pierre.langlois@arm.com>
>
> This patch implements compiling agent expressions to native code for
> AArch64. This allows us to compile conditions set on fast tracepoints.
>
> The compiled function has the following prologue:
>
> High *------------------------------------------------------*
> | LR |
> | FP | <- FP
> | x1 (ULONGEST *value) |
> | x0 (unsigned char *regs) |
> Low *------------------------------------------------------*
>
> We save the function's argument on the stack as well as the return
> address and the frame pointer. We then set the current frame pointer to
> point to the previous one.
>
> The generated code for the expression will freely update the stack
> pointer so we use the frame pointer to refer to `*value' and `*regs'.
> `*value' needs to be accessed in the epilogue of the function, in order
> to set it to whatever is on top of the stack. `*regs' needs to be passed
> down to the `gdb_agent_get_reg' function with the `reg' operation.
gdb_agent_get_reg -> gdb_agent_get_raw_reg
>
> gdb/gdbserver/ChangeLog:
>
> * linux-aarch64-low-.c: Include ax.h and tracepoint.h.
> (enum aarch64_opcodes) <RET>, <SUBS>, <AND>, <ORR>, <ORN>,
> <EOR>, <LSLV>, <LSRV>, <ASRV>, <SBFM>, <UBFM>, <CSINC>, <MUL>,
> <NOP>: New.
> (enum aarch64_condition_codes): New enum.
> (w0): New static global.
> (fp): Likewise.
> (lr): Likewise.
> (struct aarch64_memory_operand) <type>: New
> MEMORY_OPERAND_POSTINDEX type.
> (postindex_memory_operand): New helper function.
> (emit_ret): New function.
> (emit_load_store_pair): New function, factored out of emit_stp
> with support for MEMORY_OPERAND_POSTINDEX.
> (emit_stp): Rewrite using emit_load_store_pair.
> (emit_ldp): New function.
> (emit_load_store): Likewise.
> (emit_ldr): Mention post-index instruction in comment.
> (emit_ldrh): New function.
> (emit_ldrb): New function.
> (emit_ldrsw): Mention post-index instruction in comment.
> (emit_str): Likewise.
> (emit_subs): New function.
> (emit_cmp): Likewise.
> (emit_and): Likewise.
> (emit_orr): Likewise.
> (emit_orn): Likewise.
> (emit_eor): Likewise.
> (emit_mvn): Likewise.
> (emit_lslv): Likewise.
> (emit_lsrv): Likewise.
> (emit_asrv): Likewise.
> (emit_mul): Likewise.
> (emit_sbfm): Likewise.
> (emit_sbfx): Likewise.
> (emit_ubfm): Likewise.
> (emit_ubfx): Likewise.
> (emit_csinc): Likewise.
> (emit_cset): Likewise.
> (emit_nop): Likewise.
> (emit_ops_insns): New helper function.
> (emit_pop): Likewise.
> (emit_push): Likewise.
> (aarch64_emit_prologue): New function.
> (aarch64_emit_epilogue): Likewise.
> (aarch64_emit_add): Likewise.
> (aarch64_emit_sub): Likewise.
> (aarch64_emit_mul): Likewise.
> (aarch64_emit_lsh): Likewise.
> (aarch64_emit_rsh_signed): Likewise.
> (aarch64_emit_rsh_unsigned): Likewise.
> (aarch64_emit_ext): Likewise.
> (aarch64_emit_log_not): Likewise.
> (aarch64_emit_bit_and): Likewise.
> (aarch64_emit_bit_or): Likewise.
> (aarch64_emit_bit_xor): Likewise.
> (aarch64_emit_bit_not): Likewise.
> (aarch64_emit_equal): Likewise.
> (aarch64_emit_less_signed): Likewise.
> (aarch64_emit_less_unsigned): Likewise.
> (aarch64_emit_ref): Likewise.
> (aarch64_emit_if_goto): Likewise.
> (aarch64_emit_goto): Likewise.
> (aarch64_write_goto_address): Likewise.
> (aarch64_emit_const): Likewise.
> (aarch64_emit_call): Likewise.
> (aarch64_emit_reg): Likewise.
> (aarch64_emit_pop): Likewise.
> (aarch64_emit_stack_flush): Likewise.
> (aarch64_emit_zero_ext): Likewise.
> (aarch64_emit_swap): Likewise.
> (aarch64_emit_stack_adjust): Likewise.
> (aarch64_emit_int_call_1): Likewise.
> (aarch64_emit_void_call_2): Likewise.
> (aarch64_emit_eq_goto): Likewise.
> (aarch64_emit_ne_goto): Likewise.
> (aarch64_emit_lt_goto): Likewise.
> (aarch64_emit_le_goto): Likewise.
> (aarch64_emit_gt_goto): Likewise.
> (aarch64_emit_ge_got): Likewise.
> (aarch64_emit_ops_impl): New static global variable.
> (aarch64_emit_ops): New target function, return
> &aarch64_emit_ops_impl.
> (struct linux_target_ops): Install it.
> ---
> gdb/gdbserver/linux-aarch64-low.c | 1227 ++++++++++++++++++++++++++++++++++++-
> 1 file changed, 1213 insertions(+), 14 deletions(-)
>
> diff --git a/gdb/gdbserver/linux-aarch64-low.c b/gdb/gdbserver/linux-aarch64-low.c
> index e2d738b..669a1e6 100644
> --- a/gdb/gdbserver/linux-aarch64-low.c
> +++ b/gdb/gdbserver/linux-aarch64-low.c
> @@ -26,6 +26,8 @@
> #include "arch/aarch64-insn.h"
> #include "linux-aarch32-low.h"
> #include "elf/common.h"
> +#include "ax.h"
> +#include "tracepoint.h"
>
> #include <signal.h>
> #include <sys/user.h>
> @@ -680,6 +682,8 @@ enum aarch64_opcodes
> TBNZ = 0x37000000 | B,
> /* BLR 1101 0110 0011 1111 0000 00rr rrr0 0000 */
> BLR = 0xd63f0000,
> + /* RET 1101 0110 0101 1111 0000 00rr rrr0 0000 */
> + RET = 0xd65f0000,
> /* STP s010 100o o0ii iiii irrr rrrr rrrr rrrr */
> /* LDP s010 100o o1ii iiii irrr rrrr rrrr rrrr */
> /* STP (SIMD&VFP) ss10 110o o0ii iiii irrr rrrr rrrr rrrr */
> @@ -709,6 +713,29 @@ enum aarch64_opcodes
> /* SUBS s11o ooo1 xxxx xxxx xxxx xxxx xxxx xxxx */
> ADD = 0x01000000,
> SUB = 0x40000000 | ADD,
> + SUBS = 0x20000000 | SUB,
> + /* AND s000 1010 xx0x xxxx xxxx xxxx xxxx xxxx */
> + /* ORR s010 1010 xx0x xxxx xxxx xxxx xxxx xxxx */
> + /* ORN s010 1010 xx1x xxxx xxxx xxxx xxxx xxxx */
> + /* EOR s100 1010 xx0x xxxx xxxx xxxx xxxx xxxx */
> + AND = 0x0a000000,
> + ORR = 0x20000000 | AND,
> + ORN = 0x00200000 | ORR,
> + EOR = 0x40000000 | AND,
> + /* LSLV s001 1010 110r rrrr 0010 00rr rrrr rrrr */
> + /* LSRV s001 1010 110r rrrr 0010 01rr rrrr rrrr */
> + /* ASRV s001 1010 110r rrrr 0010 10rr rrrr rrrr */
> + LSLV = 0x1ac02000,
> + LSRV = 0x00000400 | LSLV,
> + ASRV = 0x00000800 | LSLV,
> + /* SBFM s001 0011 0nii iiii iiii iirr rrrr rrrr */
> + SBFM = 0x13000000,
> + /* UBFM s101 0011 0nii iiii iiii iirr rrrr rrrr */
> + UBFM = 0x40000000 | SBFM,
> + /* CSINC s001 1010 100r rrrr cccc 01rr rrrr rrrr */
> + CSINC = 0x9a800400,
> + /* MUL s001 1011 000r rrrr 0111 11rr rrrr rrrr */
> + MUL = 0x1b007c00,
> /* MSR (register) 1101 0101 0001 oooo oooo oooo ooor rrrr */
> /* MRS 1101 0101 0011 oooo oooo oooo ooor rrrr */
> MSR = 0xd5100000,
> @@ -717,6 +744,20 @@ enum aarch64_opcodes
> HINT = 0xd503201f,
> SEVL = (5 << 5) | HINT,
> WFE = (2 << 5) | HINT,
> + NOP = (0 << 5) | HINT,
> +};
> +
> +/* List of condition codes that we need. */
> +
> +enum aarch64_condition_codes
> +{
> + EQ = 0x0,
> + NE = 0x1,
> + LO = 0x3,
> + GE = 0xa,
> + LT = 0xb,
> + GT = 0xc,
> + LE = 0xd,
> };
>
> /* Representation of a general purpose register of the form xN or wN.
> @@ -759,12 +800,15 @@ static const struct aarch64_register x3 = { 3, 1 };
> static const struct aarch64_register x4 = { 4, 1 };
>
> /* General purpose scratch registers (32 bit). */
> +static const struct aarch64_register w0 = { 0, 0 };
> static const struct aarch64_register w2 = { 2, 0 };
>
> /* Intra-procedure scratch registers. */
> static const struct aarch64_register ip0 = { 16, 1 };
>
> /* Special purpose registers. */
> +static const struct aarch64_register fp = { 29, 1 };
> +static const struct aarch64_register lr = { 30, 1 };
> static const struct aarch64_register sp = { 31, 1 };
> static const struct aarch64_register xzr = { 31, 1 };
>
> @@ -817,8 +861,9 @@ immediate_operand (uint32_t imm)
>
> The types correspond to the following variants:
>
> - MEMORY_OPERAND_OFFSET: LDR rt, [rn, #offset]
> - MEMORY_OPERAND_PREINDEX: LDR rt, [rn, #index]! */
> + MEMORY_OPERAND_OFFSET: LDR rt, [rn, #offset]
> + MEMORY_OPERAND_PREINDEX: LDR rt, [rn, #index]!
> + MEMORY_OPERAND_POSTINDEX: LDR rt, [rn], #index */
>
> struct aarch64_memory_operand
> {
> @@ -827,6 +872,7 @@ struct aarch64_memory_operand
> {
> MEMORY_OPERAND_OFFSET,
> MEMORY_OPERAND_PREINDEX,
> + MEMORY_OPERAND_POSTINDEX,
> } type;
> /* Index from the base register. */
> int32_t index;
> @@ -854,6 +900,17 @@ preindex_memory_operand (int32_t index)
> return (struct aarch64_memory_operand) { MEMORY_OPERAND_PREINDEX, index };
> }
>
> +/* Helper function to create a post-index memory operand.
> +
> + For example:
> + p += emit_ldr (p, x0, sp, postindex_memory_operand (16)); */
> +
> +static struct aarch64_memory_operand
> +postindex_memory_operand (int32_t index)
> +{
> + return (struct aarch64_memory_operand) { MEMORY_OPERAND_POSTINDEX, index };
> +}
> +
> /* System control registers. These special registers can be written and
> read with the MRS and MSR instructions.
>
> @@ -986,20 +1043,24 @@ emit_blr (uint32_t *buf, struct aarch64_register rn)
> return emit_insn (buf, BLR | ENCODE (rn.num, 5, 5));
> }
>
> -/* Write a STP instruction into *BUF.
> +/* Write a RET instruction into *BUF.
>
> - STP rt, rt2, [rn, #offset]
> - STP rt, rt2, [rn, #index]!
> + RET xn
>
> - RT and RT2 are the registers to store.
> - RN is the base address register.
> - OFFSET is the immediate to add to the base address. It is limited to a
> - -512 .. 504 range (7 bits << 3). */
> + RN is the register to branch to. */
>
> static int
> -emit_stp (uint32_t *buf, struct aarch64_register rt,
> - struct aarch64_register rt2, struct aarch64_register rn,
> - struct aarch64_memory_operand operand)
> +emit_ret (uint32_t *buf, struct aarch64_register rn)
> +{
> + return emit_insn (buf, RET | ENCODE (rn.num, 5, 5));
> +}
> +
> +static int
> +emit_load_store_pair (uint32_t *buf, enum aarch64_opcodes opcode,
> + struct aarch64_register rt,
> + struct aarch64_register rt2,
> + struct aarch64_register rn,
> + struct aarch64_memory_operand operand)
> {
> uint32_t opc;
> uint32_t pre_index;
> @@ -1018,6 +1079,12 @@ emit_stp (uint32_t *buf, struct aarch64_register rt,
> write_back = ENCODE (0, 1, 23);
> break;
> }
> + case MEMORY_OPERAND_POSTINDEX:
> + {
> + pre_index = ENCODE (0, 1, 24);
> + write_back = ENCODE (1, 1, 23);
> + break;
> + }
> case MEMORY_OPERAND_PREINDEX:
> {
> pre_index = ENCODE (1, 1, 24);
> @@ -1028,11 +1095,49 @@ emit_stp (uint32_t *buf, struct aarch64_register rt,
> return 0;
> }
>
> - return emit_insn (buf, STP | opc | pre_index | write_back
> + return emit_insn (buf, opcode | opc | pre_index | write_back
> | ENCODE (operand.index >> 3, 7, 15) | ENCODE (rt2.num, 5, 10)
> | ENCODE (rn.num, 5, 5) | ENCODE (rt.num, 5, 0));
> }
>
> +/* Write a STP instruction into *BUF.
> +
> + STP rt, rt2, [rn, #offset]
> + STP rt, rt2, [rn, #index]!
> + STP rt, rt2, [rn], #index
> +
> + RT and RT2 are the registers to store.
> + RN is the base address register.
> + OFFSET is the immediate to add to the base address. It is limited to a
> + -512 .. 504 range (7 bits << 3). */
> +
> +static int
> +emit_stp (uint32_t *buf, struct aarch64_register rt,
> + struct aarch64_register rt2, struct aarch64_register rn,
> + struct aarch64_memory_operand operand)
> +{
> + return emit_load_store_pair (buf, STP, rt, rt2, rn, operand);
> +}
> +
> +/* Write a LDP instruction into *BUF.
> +
> + LDP rt, rt2, [rn, #offset]
> + LDP rt, rt2, [rn, #index]!
> + LDP rt, rt2, [rn], #index
> +
> + RT and RT2 are the registers to store.
> + RN is the base address register.
> + OFFSET is the immediate to add to the base address. It is limited to a
> + -512 .. 504 range (7 bits << 3). */
> +
> +static int
> +emit_ldp (uint32_t *buf, struct aarch64_register rt,
> + struct aarch64_register rt2, struct aarch64_register rn,
> + struct aarch64_memory_operand operand)
> +{
> + return emit_load_store_pair (buf, LDP, rt, rt2, rn, operand);
> +}
> +
> /* Write a LDP (SIMD&VFP) instruction using Q registers into *BUF.
>
> LDP qt, qt2, [rn, #offset]
> @@ -1094,6 +1199,16 @@ emit_load_store (uint32_t *buf, uint32_t size, enum aarch64_opcodes opcode,
> | ENCODE (operand.index >> 3, 12, 10)
> | ENCODE (rn.num, 5, 5) | ENCODE (rt.num, 5, 0));
> }
> + case MEMORY_OPERAND_POSTINDEX:
> + {
> + uint32_t post_index = ENCODE (1, 2, 10);
> +
> + op = ENCODE (0, 1, 24);
> +
> + return emit_insn (buf, opcode | ENCODE (size, 2, 30) | op
> + | post_index | ENCODE (operand.index, 9, 12)
> + | ENCODE (rn.num, 5, 5) | ENCODE (rt.num, 5, 0));
> + }
> case MEMORY_OPERAND_PREINDEX:
> {
> uint32_t pre_index = ENCODE (3, 2, 10);
> @@ -1113,6 +1228,7 @@ emit_load_store (uint32_t *buf, uint32_t size, enum aarch64_opcodes opcode,
>
> LDR rt, [rn, #offset]
> LDR rt, [rn, #index]!
> + LDR rt, [rn], #index
>
> RT is the register to store.
> RN is the base address register.
> @@ -1126,10 +1242,49 @@ emit_ldr (uint32_t *buf, struct aarch64_register rt,
> return emit_load_store (buf, rt.is64 ? 3 : 2, LDR, rt, rn, operand);
> }
>
> +/* Write a LDRH instruction into *BUF.
> +
> + LDRH wt, [xn, #offset]
> + LDRH wt, [xn, #index]!
> + LDRH wt, [xn], #index
> +
> + RT is the register to store.
> + RN is the base address register.
> + OFFSET is the immediate to add to the base address. It is limited to
> + 0 .. 32760 range (12 bits << 3). */
> +
> +static int
> +emit_ldrh (uint32_t *buf, struct aarch64_register rt,
> + struct aarch64_register rn,
> + struct aarch64_memory_operand operand)
> +{
> + return emit_load_store (buf, 1, LDR, rt, rn, operand);
> +}
> +
> +/* Write a LDRB instruction into *BUF.
> +
> + LDRB wt, [xn, #offset]
> + LDRB wt, [xn, #index]!
> + LDRB wt, [xn], #index
> +
> + RT is the register to store.
> + RN is the base address register.
> + OFFSET is the immediate to add to the base address. It is limited to
> + 0 .. 32760 range (12 bits << 3). */
> +
> +static int
> +emit_ldrb (uint32_t *buf, struct aarch64_register rt,
> + struct aarch64_register rn,
> + struct aarch64_memory_operand operand)
> +{
> + return emit_load_store (buf, 0, LDR, rt, rn, operand);
> +}
> +
> /* Write a LDRSW instruction into *BUF. The register size is 64-bit.
>
> LDRSW xt, [rn, #offset]
> LDRSW xt, [rn, #index]!
> + LDRSW xt, [rn], #index
>
> RT is the register to store.
> RN is the base address register.
> @@ -1148,6 +1303,7 @@ emit_ldrsw (uint32_t *buf, struct aarch64_register rt,
>
> STR rt, [rn, #offset]
> STR rt, [rn, #index]!
> + STR rt, [rn], #index
>
> RT is the register to store.
> RN is the base address register.
> @@ -1390,6 +1546,165 @@ emit_mov_addr (uint32_t *buf, struct aarch64_register rd, CORE_ADDR addr)
> return p - buf;
> }
>
> +/* Write a SUBS instruction into *BUF.
> +
> + SUBS rd, rn, rm
> +
> + This instruction update the condition flags.
> +
> + RD is the destination register.
> + RN and RM are the source registers. */
> +
> +static int
> +emit_subs (uint32_t *buf, struct aarch64_register rd,
> + struct aarch64_register rn, struct aarch64_operand operand)
> +{
> + return emit_data_processing (buf, SUBS, rd, rn, operand);
> +}
> +
> +/* Write a CMP instruction into *BUF.
> +
> + CMP rn, rm
> +
> + This instruction is an alias of SUBS xzr, rn, rm.
> +
> + RN and RM are the registers to compare. */
> +
> +static int
> +emit_cmp (uint32_t *buf, struct aarch64_register rn,
> + struct aarch64_operand operand)
> +{
> + return emit_subs (buf, xzr, rn, operand);
> +}
> +
> +/* Write a AND instruction into *BUF.
> +
> + AND rd, rn, rm
> +
> + RD is the destination register.
> + RN and RM are the source registers. */
> +
> +static int
> +emit_and (uint32_t *buf, struct aarch64_register rd,
> + struct aarch64_register rn, struct aarch64_register rm)
> +{
> + return emit_data_processing_reg (buf, AND, rd, rn, rm);
> +}
> +
> +/* Write a ORR instruction into *BUF.
> +
> + ORR rd, rn, rm
> +
> + RD is the destination register.
> + RN and RM are the source registers. */
> +
> +static int
> +emit_orr (uint32_t *buf, struct aarch64_register rd,
> + struct aarch64_register rn, struct aarch64_register rm)
> +{
> + return emit_data_processing_reg (buf, ORR, rd, rn, rm);
> +}
> +
> +/* Write a ORN instruction into *BUF.
> +
> + ORN rd, rn, rm
> +
> + RD is the destination register.
> + RN and RM are the source registers. */
> +
> +static int
> +emit_orn (uint32_t *buf, struct aarch64_register rd,
> + struct aarch64_register rn, struct aarch64_register rm)
> +{
> + return emit_data_processing_reg (buf, ORN, rd, rn, rm);
> +}
> +
> +/* Write a EOR instruction into *BUF.
> +
> + EOR rd, rn, rm
> +
> + RD is the destination register.
> + RN and RM are the source registers. */
> +
> +static int
> +emit_eor (uint32_t *buf, struct aarch64_register rd,
> + struct aarch64_register rn, struct aarch64_register rm)
> +{
> + return emit_data_processing_reg (buf, EOR, rd, rn, rm);
> +}
> +
> +/* Write a MVN instruction into *BUF.
> +
> + MVN rd, rm
> +
> + This is an alias for ORN rd, xzr, rm.
> +
> + RD is the destination register.
> + RM is the source register. */
> +
> +static int
> +emit_mvn (uint32_t *buf, struct aarch64_register rd,
> + struct aarch64_register rm)
> +{
> + return emit_orn (buf, rd, xzr, rm);
> +}
> +
> +/* Write a LSLV instruction into *BUF.
> +
> + LSLV rd, rn, rm
> +
> + RD is the destination register.
> + RN and RM are the source registers. */
> +
> +static int
> +emit_lslv (uint32_t *buf, struct aarch64_register rd,
> + struct aarch64_register rn, struct aarch64_register rm)
> +{
> + return emit_data_processing_reg (buf, LSLV, rd, rn, rm);
> +}
> +
> +/* Write a LSRV instruction into *BUF.
> +
> + LSRV rd, rn, rm
> +
> + RD is the destination register.
> + RN and RM are the source registers. */
> +
> +static int
> +emit_lsrv (uint32_t *buf, struct aarch64_register rd,
> + struct aarch64_register rn, struct aarch64_register rm)
> +{
> + return emit_data_processing_reg (buf, LSRV, rd, rn, rm);
> +}
> +
> +/* Write a ASRV instruction into *BUF.
> +
> + ASRV rd, rn, rm
> +
> + RD is the destination register.
> + RN and RM are the source registers. */
> +
> +static int
> +emit_asrv (uint32_t *buf, struct aarch64_register rd,
> + struct aarch64_register rn, struct aarch64_register rm)
> +{
> + return emit_data_processing_reg (buf, ASRV, rd, rn, rm);
> +}
> +
> +/* Write a MUL instruction into *BUF.
> +
> + MUL rd, rn, rm
> +
> + RD is the destination register.
> + RN and RM are the source registers. */
> +
> +static int
> +emit_mul (uint32_t *buf, struct aarch64_register rd,
> + struct aarch64_register rn, struct aarch64_register rm)
> +{
> + return emit_data_processing_reg (buf, MUL, rd, rn, rm);
> +}
> +
> /* Write a MRS instruction into *BUF. The register size is 64-bit.
>
> MRS xt, system_reg
> @@ -1440,6 +1755,150 @@ emit_wfe (uint32_t *buf)
> return emit_insn (buf, WFE);
> }
>
> +/* Write a SBFM instruction into *BUF.
> +
> + SBFM rd, rn, #immr, #imms
> +
> + This instruction moves the bits from #immr to #imms into the
> + destination, sign extending the result.
> +
> + RD is the destination register.
> + RN is the source register.
> + IMMR is the bit number to start at (least significant bit).
> + IMMS is the bit number to stop at (most significant bit). */
> +
> +static int
> +emit_sbfm (uint32_t *buf, struct aarch64_register rd,
> + struct aarch64_register rn, uint32_t immr, uint32_t imms)
> +{
> + uint32_t size = ENCODE (rd.is64, 1, 31);
> + uint32_t n = ENCODE (rd.is64, 1, 22);
> +
> + return emit_insn (buf, SBFM | size | n | ENCODE (immr, 6, 16)
> + | ENCODE (imms, 6, 10) | ENCODE (rn.num, 5, 5)
> + | ENCODE (rd.num, 5, 0));
> +}
> +
> +/* Write a SBFX instruction into *BUF.
> +
> + SBFX rd, rn, #lsb, #width
> +
> + This instruction moves #width bits from #lsb into the destination, sign
> + extending the result. This is an alias for:
> +
> + SBFM rd, rn, #lsb, #(lsb + width - 1)
> +
> + RD is the destination register.
> + RN is the source register.
> + LSB is the bit number to start at (least significant bit).
> + WIDTH is the number of bits to move. */
> +
> +static int
> +emit_sbfx (uint32_t *buf, struct aarch64_register rd,
> + struct aarch64_register rn, uint32_t lsb, uint32_t width)
> +{
> + return emit_sbfm (buf, rd, rn, lsb, lsb + width - 1);
> +}
> +
> +/* Write a UBFM instruction into *BUF.
> +
> + UBFM rd, rn, #immr, #imms
> +
> + This instruction moves the bits from #immr to #imms into the
> + destination, extending the result with zeros.
> +
> + RD is the destination register.
> + RN is the source register.
> + IMMR is the bit number to start at (least significant bit).
> + IMMS is the bit number to stop at (most significant bit). */
> +
> +static int
> +emit_ubfm (uint32_t *buf, struct aarch64_register rd,
> + struct aarch64_register rn, uint32_t immr, uint32_t imms)
> +{
> + uint32_t size = ENCODE (rd.is64, 1, 31);
> + uint32_t n = ENCODE (rd.is64, 1, 22);
> +
> + return emit_insn (buf, UBFM | size | n | ENCODE (immr, 6, 16)
> + | ENCODE (imms, 6, 10) | ENCODE (rn.num, 5, 5)
> + | ENCODE (rd.num, 5, 0));
> +}
> +
> +/* Write a UBFX instruction into *BUF.
> +
> + UBFX rd, rn, #lsb, #width
> +
> + This instruction moves #width bits from #lsb into the destination,
> + extending the result with zeros. This is an alias for:
> +
> + UBFM rd, rn, #lsb, #(lsb + width - 1)
> +
> + RD is the destination register.
> + RN is the source register.
> + LSB is the bit number to start at (least significant bit).
> + WIDTH is the number of bits to move. */
> +
> +static int
> +emit_ubfx (uint32_t *buf, struct aarch64_register rd,
> + struct aarch64_register rn, uint32_t lsb, uint32_t width)
> +{
> + return emit_ubfm (buf, rd, rn, lsb, lsb + width - 1);
> +}
> +
> +/* Write a CSINC instruction into *BUF.
> +
> + CSINC rd, rn, rm, cond
> +
> + This instruction conditionally increments rn or rm and places the result
> + in rd. rn is chosen is the condition is true.
> +
> + RD is the destination register.
> + RN and RM are the source registers.
> + COND is the encoded condition. */
> +
> +static int
> +emit_csinc (uint32_t *buf, struct aarch64_register rd,
> + struct aarch64_register rn, struct aarch64_register rm,
> + unsigned cond)
> +{
> + uint32_t size = ENCODE (rd.is64, 1, 31);
> +
> + return emit_insn (buf, CSINC | size | ENCODE (rm.num, 5, 16)
> + | ENCODE (cond, 4, 12) | ENCODE (rn.num, 5, 5)
> + | ENCODE (rd.num, 5, 0));
> +}
> +
> +/* Write a CSET instruction into *BUF.
> +
> + CSET rd, cond
> +
> + This instruction conditionally write 1 or 0 in the destination register.
> + 1 is written if the condition is true. This is an alias for:
> +
> + CSINC rd, xzr, xzr, !cond
> +
> + Note that the condition needs to be inverted.
> +
> + RD is the destination register.
> + RN and RM are the source registers.
> + COND is the encoded condition. */
> +
> +static int
> +emit_cset (uint32_t *buf, struct aarch64_register rd, unsigned cond)
> +{
> + /* The least significant bit of the condition needs toggling in order to
> + invert it. */
> + return emit_csinc (buf, rd, xzr, xzr, cond ^ 0x1);
> +}
> +
> +/* Write a NOP instruction into *BUF. */
> +
> +static int
> +emit_nop (uint32_t *buf)
> +{
> + return emit_insn (buf, NOP);
> +}
> +
> /* Write LEN instructions from BUF into the inferior memory at *TO.
>
> Note instructions are always little endian on AArch64, unlike data. */
> @@ -2024,6 +2483,746 @@ aarch64_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint,
> return 0;
> }
>
> +/* Helper function writing LEN instructions from START into
> + current_insn_ptr. */
> +
> +static void
> +emit_ops_insns (const uint32_t *start, int len)
> +{
> + CORE_ADDR buildaddr = current_insn_ptr;
> +
> + if (debug_threads)
> + debug_printf ("Adding %d instrucions at %s\n",
> + len, paddress (buildaddr));
> +
> + append_insns (&buildaddr, len, start);
> + current_insn_ptr = buildaddr;
> +}
> +
> +/* Pop a register from the stack. */
> +
> +static int
> +emit_pop (uint32_t *buf, struct aarch64_register rt)
> +{
> + return emit_ldr (buf, rt, sp, postindex_memory_operand (1 * 16));
> +}
> +
> +/* Push a register on the stack. */
> +
> +static int
> +emit_push (uint32_t *buf, struct aarch64_register rt)
> +{
> + return emit_str (buf, rt, sp, preindex_memory_operand (-1 * 16));
> +}
> +
> +/* Implementation of emit_ops method "emit_prologue". */
> +
> +static void
> +aarch64_emit_prologue (void)
> +{
> + uint32_t buf[16];
> + uint32_t *p = buf;
> +
> + /* This function emit a prologue for the following function prototype:
> +
> + enum eval_result_type f (unsigned char *regs,
> + ULONGEST *value);
> +
> + The first argument is a buffer of raw registers. The second
> + argument is the result of
> + evaluating the expression, which will be set to whatever is on top of
> + the stack at the end.
> +
> + The stack set up by the prologue is as such:
> +
> + High *------------------------------------------------------*
> + | LR |
> + | FP | <- FP
> + | x1 (ULONGEST *value) |
> + | x0 (unsigned char *regs) |
> + Low *------------------------------------------------------*
> +
> + As we are implementing a stack machine, each opcode can expand the
> + stack so we never know how far we are from the data saved by this
> + prologue. In order to be able refer to value and regs later, we save
> + the current stack pointer in the frame pointer. This way, it is not
> + clobbered when calling C functions.
> +
> + Finally, throughtout every operation, we are using register x0 as the
> + top of the stack, and x1 as a scratch register. */
> +
> + p += emit_stp (p, x0, x1, sp, preindex_memory_operand (-2 * 16));
> + p += emit_str (p, lr, sp, offset_memory_operand (3 * 8));
> + p += emit_str (p, fp, sp, offset_memory_operand (2 * 8));
> +
> + p += emit_add (p, fp, sp, immediate_operand (2 * 8));
> +
> +
> + emit_ops_insns (buf, p - buf);
> +}
> +
> +/* Implementation of emit_ops method "emit_epilogue". */
> +
> +static void
> +aarch64_emit_epilogue (void)
> +{
> + uint32_t buf[16];
> + uint32_t *p = buf;
> +
> + /* Store the result of the expression (x0) in *value. */
> + p += emit_sub (p, x1, fp, immediate_operand (1 * 8));
> + p += emit_ldr (p, x1, x1, offset_memory_operand (0));
> + p += emit_str (p, x0, x1, offset_memory_operand (0));
> +
> + /* Restore the previous state. */
> + p += emit_add (p, sp, fp, immediate_operand (2 * 8));
> + p += emit_ldp (p, fp, lr, fp, offset_memory_operand (0));
> +
> + /* Return expr_eval_no_error. */
> + p += emit_mov (p, x0, immediate_operand (expr_eval_no_error));
> + p += emit_ret (p, lr);
> +
> + emit_ops_insns (buf, p - buf);
> +}
> +
> +/* Implementation of emit_ops method "emit_add". */
> +
> +static void
> +aarch64_emit_add (void)
> +{
> + uint32_t buf[16];
> + uint32_t *p = buf;
> +
> + p += emit_pop (p, x1);
> + p += emit_add (p, x0, x0, register_operand (x1));
> +
> + emit_ops_insns (buf, p - buf);
> +}
> +
> +/* Implementation of emit_ops method "emit_sub". */
> +
> +static void
> +aarch64_emit_sub (void)
> +{
> + uint32_t buf[16];
> + uint32_t *p = buf;
> +
> + p += emit_pop (p, x1);
> + p += emit_sub (p, x0, x0, register_operand (x1));
> +
> + emit_ops_insns (buf, p - buf);
> +}
> +
> +/* Implementation of emit_ops method "emit_mul". */
> +
> +static void
> +aarch64_emit_mul (void)
> +{
> + uint32_t buf[16];
> + uint32_t *p = buf;
> +
> + p += emit_pop (p, x1);
> + p += emit_mul (p, x0, x1, x0);
> +
> + emit_ops_insns (buf, p - buf);
> +}
> +
> +/* Implementation of emit_ops method "emit_lsh". */
> +
> +static void
> +aarch64_emit_lsh (void)
> +{
> + uint32_t buf[16];
> + uint32_t *p = buf;
> +
> + p += emit_pop (p, x1);
> + p += emit_lslv (p, x0, x1, x0);
> +
> + emit_ops_insns (buf, p - buf);
> +}
> +
> +/* Implementation of emit_ops method "emit_rsh_signed". */
> +
> +static void
> +aarch64_emit_rsh_signed (void)
> +{
> + uint32_t buf[16];
> + uint32_t *p = buf;
> +
> + p += emit_pop (p, x1);
> + p += emit_asrv (p, x0, x1, x0);
> +
> + emit_ops_insns (buf, p - buf);
> +}
> +
> +/* Implementation of emit_ops method "emit_rsh_unsigned". */
> +
> +static void
> +aarch64_emit_rsh_unsigned (void)
> +{
> + uint32_t buf[16];
> + uint32_t *p = buf;
> +
> + p += emit_pop (p, x1);
> + p += emit_lsrv (p, x0, x1, x0);
> +
> + emit_ops_insns (buf, p - buf);
> +}
> +
> +/* Implementation of emit_ops method "emit_ext". */
> +
> +static void
> +aarch64_emit_ext (int arg)
> +{
> + uint32_t buf[16];
> + uint32_t *p = buf;
> +
> + p += emit_sbfx (p, x0, x0, 0, arg);
> +
> + emit_ops_insns (buf, p - buf);
> +}
> +
> +/* Implementation of emit_ops method "emit_log_not". */
> +
> +static void
> +aarch64_emit_log_not (void)
> +{
> + uint32_t buf[16];
> + uint32_t *p = buf;
> +
> + /* If the top of the stack is 0, replace it with 1. Else replace it with
> + 0. */
> +
> + p += emit_cmp (p, x0, immediate_operand (0));
> + p += emit_cset (p, x0, EQ);
> +
> + emit_ops_insns (buf, p - buf);
> +}
> +
> +/* Implementation of emit_ops method "emit_bit_and". */
> +
> +static void
> +aarch64_emit_bit_and (void)
> +{
> + uint32_t buf[16];
> + uint32_t *p = buf;
> +
> + p += emit_pop (p, x1);
> + p += emit_and (p, x0, x0, x1);
> +
> + emit_ops_insns (buf, p - buf);
> +}
> +
> +/* Implementation of emit_ops method "emit_bit_or". */
> +
> +static void
> +aarch64_emit_bit_or (void)
> +{
> + uint32_t buf[16];
> + uint32_t *p = buf;
> +
> + p += emit_pop (p, x1);
> + p += emit_orr (p, x0, x0, x1);
> +
> + emit_ops_insns (buf, p - buf);
> +}
> +
> +/* Implementation of emit_ops method "emit_bit_xor". */
> +
> +static void
> +aarch64_emit_bit_xor (void)
> +{
> + uint32_t buf[16];
> + uint32_t *p = buf;
> +
> + p += emit_pop (p, x1);
> + p += emit_eor (p, x0, x0, x1);
> +
> + emit_ops_insns (buf, p - buf);
> +}
> +
> +/* Implementation of emit_ops method "emit_bit_not". */
> +
> +static void
> +aarch64_emit_bit_not (void)
> +{
> + uint32_t buf[16];
> + uint32_t *p = buf;
> +
> + p += emit_mvn (p, x0, x0);
> +
> + emit_ops_insns (buf, p - buf);
> +}
> +
> +/* Implementation of emit_ops method "emit_equal". */
> +
> +static void
> +aarch64_emit_equal (void)
> +{
> + uint32_t buf[16];
> + uint32_t *p = buf;
> +
> + p += emit_pop (p, x1);
> + p += emit_cmp (p, x0, register_operand (x1));
> + p += emit_cset (p, x0, EQ);
> +
> + emit_ops_insns (buf, p - buf);
> +}
> +
> +/* Implementation of emit_ops method "emit_less_signed". */
> +
> +static void
> +aarch64_emit_less_signed (void)
> +{
> + uint32_t buf[16];
> + uint32_t *p = buf;
> +
> + p += emit_pop (p, x1);
> + p += emit_cmp (p, x1, register_operand (x0));
> + p += emit_cset (p, x0, LT);
> +
> + emit_ops_insns (buf, p - buf);
> +}
> +
> +/* Implementation of emit_ops method "emit_less_unsigned". */
> +
> +static void
> +aarch64_emit_less_unsigned (void)
> +{
> + uint32_t buf[16];
> + uint32_t *p = buf;
> +
> + p += emit_pop (p, x1);
> + p += emit_cmp (p, x1, register_operand (x0));
> + p += emit_cset (p, x0, LO);
> +
> + emit_ops_insns (buf, p - buf);
> +}
> +
> +/* Implementation of emit_ops method "emit_ref". */
> +
> +static void
> +aarch64_emit_ref (int size)
> +{
> + uint32_t buf[16];
> + uint32_t *p = buf;
> +
> + switch (size)
> + {
> + case 1:
> + p += emit_ldrb (p, w0, x0, offset_memory_operand (0));
> + break;
> + case 2:
> + p += emit_ldrh (p, w0, x0, offset_memory_operand (0));
> + break;
> + case 4:
> + p += emit_ldr (p, w0, x0, offset_memory_operand (0));
> + break;
> + case 8:
> + p += emit_ldr (p, x0, x0, offset_memory_operand (0));
> + break;
> + default:
> + /* Unknown size, bail on compilation. */
> + emit_error = 1;
> + break;
> + }
> +
> + emit_ops_insns (buf, p - buf);
> +}
> +
> +/* Implementation of emit_ops method "emit_if_goto". */
> +
> +static void
> +aarch64_emit_if_goto (int *offset_p, int *size_p)
> +{
> + uint32_t buf[16];
> + uint32_t *p = buf;
> +
> + /* The Z flag is set or cleared here. */
> + p += emit_cmp (p, x0, immediate_operand (0));
> + /* This instruction must not change the Z flag. */
> + p += emit_pop (p, x0);
> + /* Branch over the next instruction if x0 == 0. */
> + p += emit_bcond (p, EQ, 8);
> +
> + /* The NOP instruction will be patched with an unconditional branch. */
> + if (offset_p)
> + *offset_p = (p - buf) * 4;
> + if (size_p)
> + *size_p = 4;
> + p += emit_nop (p);
> +
> + emit_ops_insns (buf, p - buf);
> +}
> +
> +/* Implementation of emit_ops method "emit_goto". */
> +
> +static void
> +aarch64_emit_goto (int *offset_p, int *size_p)
> +{
> + uint32_t buf[16];
> + uint32_t *p = buf;
> +
> + /* The NOP instruction will be patched with an unconditional branch. */
> + if (offset_p)
> + *offset_p = 0;
> + if (size_p)
> + *size_p = 4;
> + p += emit_nop (p);
> +
> + emit_ops_insns (buf, p - buf);
> +}
> +
> +/* Implementation of emit_ops method "write_goto_address". */
> +
> +void
> +aarch64_write_goto_address (CORE_ADDR from, CORE_ADDR to, int size)
> +{
> + uint32_t insn;
> +
> + emit_b (&insn, 0, to - from);
> + append_insns (&from, 1, &insn);
> +}
> +
> +/* Implementation of emit_ops method "emit_const". */
> +
> +static void
> +aarch64_emit_const (LONGEST num)
> +{
> + uint32_t buf[16];
> + uint32_t *p = buf;
> +
> + p += emit_mov_addr (p, x0, num);
> +
> + emit_ops_insns (buf, p - buf);
> +}
> +
> +/* Implementation of emit_ops method "emit_call". */
> +
> +static void
> +aarch64_emit_call (CORE_ADDR fn)
> +{
> + uint32_t buf[16];
> + uint32_t *p = buf;
> +
> + p += emit_mov_addr (p, ip0, fn);
> + p += emit_blr (p, ip0);
> +
> + emit_ops_insns (buf, p - buf);
> +}
> +
> +/* Implementation of emit_ops method "emit_reg". */
> +
> +static void
> +aarch64_emit_reg (int reg)
> +{
> + uint32_t buf[16];
> + uint32_t *p = buf;
> +
> + /* Set x0 to struct fast_tracepoint_ctx *ctx->regs. */
This comment should mention the saved raw registers instead of
fast_tracepoint_ctx.
/* Set x0 to unsigned char *regs. */
> + p += emit_sub (p, x0, fp, immediate_operand (2 * 8));
> + p += emit_ldr (p, x0, x0, offset_memory_operand (0));
> + p += emit_mov (p, x1, immediate_operand (reg));
> +
> + emit_ops_insns (buf, p - buf);
> +
> + aarch64_emit_call (get_raw_reg_func_addr ());
> +}
Thanks again!
Pierre
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [PATCH 4/8] Implement target_emit_ops
2015-09-18 12:43 ` [PATCH 4/8] Implement target_emit_ops Yao Qi
2015-09-18 12:57 ` Pierre Langlois
@ 2016-02-05 20:09 ` Antoine Tremblay
2016-02-08 17:30 ` Yao Qi
1 sibling, 1 reply; 37+ messages in thread
From: Antoine Tremblay @ 2016-02-05 20:09 UTC (permalink / raw)
To: Yao Qi, gdb-patches, Pierre Langlois
On 09/18/2015 08:43 AM, Yao Qi wrote:
> From: Pierre Langlois <pierre.langlois@arm.com>
>
> This patch implements compiling agent expressions to native code for
> AArch64. This allows us to compile conditions set on fast tracepoints.
>
> The compiled function has the following prologue:
>
> High *------------------------------------------------------*
> | LR |
> | FP | <- FP
> | x1 (ULONGEST *value) |
> | x0 (unsigned char *regs) |
> Low *------------------------------------------------------*
>
> We save the function's argument on the stack as well as the return
> address and the frame pointer. We then set the current frame pointer to
> point to the previous one.
>
> The generated code for the expression will freely update the stack
> pointer so we use the frame pointer to refer to `*value' and `*regs'.
> `*value' needs to be accessed in the epilogue of the function, in order
> to set it to whatever is on top of the stack. `*regs' needs to be passed
> down to the `gdb_agent_get_reg' function with the `reg' operation.
>
> +static void
> +aarch64_emit_prologue (void)
> +{
> + uint32_t buf[16];
> + uint32_t *p = buf;
> +
> + /* This function emit a prologue for the following function prototype:
> +
> + e
....
Hi,
I'm working on adding JIT compiling of agent expressions for ARM and
I've been looking at the aarch64 implementation.
I'm wondering is there a reason we don't use gcc to generate the
native bytecode like done on x86 ?
x86 has a macro like so :
#define EMIT_ASM(NAME, INSNS)
do
{
extern unsigned char start_ ## NAME, end_ ## NAME;
add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME);
__asm__ ("jmp end_" #NAME "\n"
"\t" "start_" #NAME ":"
"\t" INSNS "\n"
"\t" "end_" #NAME ":");
} while (0)
Could the same be done for armv7 or there's a reason that prevents it ?
Same question for aarch64 ?
Thanks,
Antoine
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [PATCH 4/8] Implement target_emit_ops
2016-02-05 20:09 ` Antoine Tremblay
@ 2016-02-08 17:30 ` Yao Qi
2016-02-08 17:59 ` Antoine Tremblay
0 siblings, 1 reply; 37+ messages in thread
From: Yao Qi @ 2016-02-08 17:30 UTC (permalink / raw)
To: Antoine Tremblay; +Cc: Yao Qi, gdb-patches, Pierre Langlois
Antoine Tremblay <antoine.tremblay@ericsson.com> writes:
> I'm wondering is there a reason we don't use gcc to generate the
> native bytecode like done on x86 ?
>
> x86 has a macro like so :
>
> #define EMIT_ASM(NAME, INSNS)
> do
> {
> extern unsigned char start_ ## NAME, end_ ## NAME;
> add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME);
> __asm__ ("jmp end_" #NAME "\n"
> "\t" "start_" #NAME ":"
> "\t" INSNS "\n"
> "\t" "end_" #NAME ":");
> } while (0)
>
The reason is about the code readability. We find the way we are using
in aarch64 is more readable than the way for x86.
p += emit_stp (p, x0, x1, sp, preindex_memory_operand (-2 * 16));
p += emit_str (p, lr, sp, offset_memory_operand (3 * 8));
p += emit_str (p, fp, sp, offset_memory_operand (2 * 8));
p += emit_add (p, fp, sp, immediate_operand (2 * 8));
vs.
EMIT_ASM (amd64_prologue,
"pushq %rbp\n\t"
"movq %rsp,%rbp\n\t"
"sub $0x20,%rsp\n\t"
"movq %rdi,-8(%rbp)\n\t"
"movq %rsi,-16(%rbp)");
> Could the same be done for armv7 or there's a reason that prevents it ?
>
No reason prevents it, but the code should be readable.
--
Yao (齐尧)
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [PATCH 4/8] Implement target_emit_ops
2016-02-08 17:30 ` Yao Qi
@ 2016-02-08 17:59 ` Antoine Tremblay
0 siblings, 0 replies; 37+ messages in thread
From: Antoine Tremblay @ 2016-02-08 17:59 UTC (permalink / raw)
To: Yao Qi; +Cc: gdb-patches, Pierre Langlois
On 02/08/2016 12:30 PM, Yao Qi wrote:
> Antoine Tremblay <antoine.tremblay@ericsson.com> writes:
>
>> I'm wondering is there a reason we don't use gcc to generate the
>> native bytecode like done on x86 ?
>>
>> x86 has a macro like so :
>>
>> #define EMIT_ASM(NAME, INSNS)
>> do
>> {
>> extern unsigned char start_ ## NAME, end_ ## NAME;
>> add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME);
>> __asm__ ("jmp end_" #NAME "\n"
>> "\t" "start_" #NAME ":"
>> "\t" INSNS "\n"
>> "\t" "end_" #NAME ":");
>> } while (0)
>>
>
> The reason is about the code readability. We find the way we are using
> in aarch64 is more readable than the way for x86.
>
OK.
> p += emit_stp (p, x0, x1, sp, preindex_memory_operand (-2 * 16));
> p += emit_str (p, lr, sp, offset_memory_operand (3 * 8));
> p += emit_str (p, fp, sp, offset_memory_operand (2 * 8));
> p += emit_add (p, fp, sp, immediate_operand (2 * 8));
>
> vs.
>
> EMIT_ASM (amd64_prologue,
> "pushq %rbp\n\t"
> "movq %rsp,%rbp\n\t"
> "sub $0x20,%rsp\n\t"
> "movq %rdi,-8(%rbp)\n\t"
> "movq %rsi,-16(%rbp)");
>
>> Could the same be done for armv7 or there's a reason that prevents it ?
>>
>
> No reason prevents it, but the code should be readable.
>
OK thanks, It is readable that way but I think I'll go with EMIT_ASM...
given that this should save me quite a bit of time considering thumb/arm
versions and that there's not much emit_ functions done at the moment.
It should still be readable.
Regards,
Antoine
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 5/8] Enable fast tracepoint tests
2015-09-18 12:43 ` [PATCH 0/8 V2] [AArch64] Support fast tracepoints Yao Qi
` (4 preceding siblings ...)
2015-09-18 12:43 ` [PATCH 4/8] Implement target_emit_ops Yao Qi
@ 2015-09-18 12:43 ` Yao Qi
2015-09-18 12:44 ` [PATCH 6/8] Add a gdb.trace test for instruction relocation Yao Qi
` (2 subsequent siblings)
8 siblings, 0 replies; 37+ messages in thread
From: Yao Qi @ 2015-09-18 12:43 UTC (permalink / raw)
To: gdb-patches
From: Pierre Langlois <pierre.langlois@arm.com>
gdb/testsuite/ChangeLog:
* gdb.trace/change-loc.h (func4) [__aarch64__]: Add a nop
instruction.
* gdb.trace/pendshr1.c (pendfunc): Likewise.
* gdb.trace/pendshr2.c (pendfunc2): Likewise.
* gdb.trace/range-stepping.c: Likewise.
* gdb.trace/trace-break.c: Likewise.
* gdb.trace/trace-mt.c (thread_function): Likewise.
* gdb.trace/ftrace.c (marker): Likewise.
* gdb.trace/trace-condition.c (marker): Likewise.
* gdb.trace/ftrace.exp: Enable ftrace test if is_aarch64_target.
* gdb.trace/trace-condition.exp: Set pcreg to "\$pc" if
is_aarch64_target.
---
gdb/testsuite/gdb.trace/change-loc.h | 2 ++
gdb/testsuite/gdb.trace/ftrace.c | 2 ++
gdb/testsuite/gdb.trace/ftrace.exp | 2 +-
gdb/testsuite/gdb.trace/pendshr1.c | 2 ++
gdb/testsuite/gdb.trace/pendshr2.c | 2 ++
gdb/testsuite/gdb.trace/range-stepping.c | 2 ++
gdb/testsuite/gdb.trace/trace-break.c | 4 ++++
gdb/testsuite/gdb.trace/trace-condition.c | 2 ++
gdb/testsuite/gdb.trace/trace-condition.exp | 2 ++
gdb/testsuite/gdb.trace/trace-mt.c | 2 ++
10 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/gdb/testsuite/gdb.trace/change-loc.h b/gdb/testsuite/gdb.trace/change-loc.h
index e8e2e86..8201455 100644
--- a/gdb/testsuite/gdb.trace/change-loc.h
+++ b/gdb/testsuite/gdb.trace/change-loc.h
@@ -36,6 +36,8 @@ func4 (void)
SYMBOL(set_tracepoint) ":\n"
#if (defined __x86_64__ || defined __i386__)
" call " SYMBOL(func5) "\n"
+#elif (defined __aarch64__)
+ " nop\n"
#endif
);
diff --git a/gdb/testsuite/gdb.trace/ftrace.c b/gdb/testsuite/gdb.trace/ftrace.c
index f522e6f..7373d66 100644
--- a/gdb/testsuite/gdb.trace/ftrace.c
+++ b/gdb/testsuite/gdb.trace/ftrace.c
@@ -42,6 +42,8 @@ marker (int anarg)
SYMBOL(set_point) ":\n"
#if (defined __x86_64__ || defined __i386__)
" call " SYMBOL(func) "\n"
+#elif (defined __aarch64__)
+ " nop\n"
#endif
);
diff --git a/gdb/testsuite/gdb.trace/ftrace.exp b/gdb/testsuite/gdb.trace/ftrace.exp
index a8eb515..4c81578 100644
--- a/gdb/testsuite/gdb.trace/ftrace.exp
+++ b/gdb/testsuite/gdb.trace/ftrace.exp
@@ -84,7 +84,7 @@ proc test_fast_tracepoints {} {
gdb_test "print gdb_agent_gdb_trampoline_buffer_error" ".*" ""
- if { [istarget "x86_64-*-*"] || [istarget "i\[34567\]86-*-*"] } {
+ if { [istarget "x86_64-*-*"] || [istarget "i\[34567\]86-*-*"] || [is_aarch64_target] } {
gdb_test "ftrace set_point" "Fast tracepoint .*" \
"fast tracepoint at a long insn"
diff --git a/gdb/testsuite/gdb.trace/pendshr1.c b/gdb/testsuite/gdb.trace/pendshr1.c
index d3b5463..f08fb91 100644
--- a/gdb/testsuite/gdb.trace/pendshr1.c
+++ b/gdb/testsuite/gdb.trace/pendshr1.c
@@ -38,6 +38,8 @@ pendfunc (int x)
SYMBOL(set_point1) ":\n"
#if (defined __x86_64__ || defined __i386__)
" call " SYMBOL(pendfunc1) "\n"
+#elif (defined __aarch64__)
+ " nop\n"
#endif
);
}
diff --git a/gdb/testsuite/gdb.trace/pendshr2.c b/gdb/testsuite/gdb.trace/pendshr2.c
index b8a51a5..f7ec733 100644
--- a/gdb/testsuite/gdb.trace/pendshr2.c
+++ b/gdb/testsuite/gdb.trace/pendshr2.c
@@ -35,6 +35,8 @@ pendfunc2 (int x)
SYMBOL(set_point2) ":\n"
#if (defined __x86_64__ || defined __i386__)
" call " SYMBOL(foo) "\n"
+#elif (defined __aarch64__)
+ " nop\n"
#endif
);
}
diff --git a/gdb/testsuite/gdb.trace/range-stepping.c b/gdb/testsuite/gdb.trace/range-stepping.c
index 113f0e2..41cd745 100644
--- a/gdb/testsuite/gdb.trace/range-stepping.c
+++ b/gdb/testsuite/gdb.trace/range-stepping.c
@@ -26,6 +26,8 @@
tracepoint jump. */
#if (defined __x86_64__ || defined __i386__)
# define NOP " .byte 0xe9,0x00,0x00,0x00,0x00\n" /* jmp $+5 (5-byte nop) */
+#elif (defined __aarch64__)
+# define NOP " nop\n"
#else
# define NOP "" /* port me */
#endif
diff --git a/gdb/testsuite/gdb.trace/trace-break.c b/gdb/testsuite/gdb.trace/trace-break.c
index f381ec6..66bbe53 100644
--- a/gdb/testsuite/gdb.trace/trace-break.c
+++ b/gdb/testsuite/gdb.trace/trace-break.c
@@ -41,6 +41,8 @@ marker (void)
SYMBOL(set_point) ":\n"
#if (defined __x86_64__ || defined __i386__)
" call " SYMBOL(func) "\n"
+#elif (defined __aarch64__)
+ " nop\n"
#endif
);
@@ -48,6 +50,8 @@ marker (void)
SYMBOL(after_set_point) ":\n"
#if (defined __x86_64__ || defined __i386__)
" call " SYMBOL(func) "\n"
+#elif (defined __aarch64__)
+ " nop\n"
#endif
);
}
diff --git a/gdb/testsuite/gdb.trace/trace-condition.c b/gdb/testsuite/gdb.trace/trace-condition.c
index 2e965c9..d988d76 100644
--- a/gdb/testsuite/gdb.trace/trace-condition.c
+++ b/gdb/testsuite/gdb.trace/trace-condition.c
@@ -44,6 +44,8 @@ marker (int anarg)
SYMBOL (set_point) ":\n"
#if (defined __x86_64__ || defined __i386__)
" call " SYMBOL (func) "\n"
+#elif (defined __aarch64__)
+ " nop\n"
#endif
);
}
diff --git a/gdb/testsuite/gdb.trace/trace-condition.exp b/gdb/testsuite/gdb.trace/trace-condition.exp
index d10fa9a..aec0401 100644
--- a/gdb/testsuite/gdb.trace/trace-condition.exp
+++ b/gdb/testsuite/gdb.trace/trace-condition.exp
@@ -25,6 +25,8 @@ if [is_amd64_regs_target] {
set pcreg "\$rip"
} elseif [is_x86_like_target] {
set pcreg "\$eip"
+} elseif [is_aarch64_target] {
+ set pcreg "\$pc"
} else {
set pcreg "\$pc"
}
diff --git a/gdb/testsuite/gdb.trace/trace-mt.c b/gdb/testsuite/gdb.trace/trace-mt.c
index 38aeff5..7ae0305 100644
--- a/gdb/testsuite/gdb.trace/trace-mt.c
+++ b/gdb/testsuite/gdb.trace/trace-mt.c
@@ -37,6 +37,8 @@ thread_function(void *arg)
SYMBOL(set_point1) ":\n"
#if (defined __x86_64__ || defined __i386__)
" call " SYMBOL(func) "\n"
+#elif (defined __aarch64__)
+ " nop\n"
#endif
);
}
--
1.9.1
^ permalink raw reply [flat|nested] 37+ messages in thread* [PATCH 6/8] Add a gdb.trace test for instruction relocation
2015-09-18 12:43 ` [PATCH 0/8 V2] [AArch64] Support fast tracepoints Yao Qi
` (5 preceding siblings ...)
2015-09-18 12:43 ` [PATCH 5/8] Enable fast tracepoint tests Yao Qi
@ 2015-09-18 12:44 ` Yao Qi
2015-09-18 12:44 ` [PATCH 3/8] Add support for fast tracepoints Yao Qi
2015-09-21 14:06 ` [PATCH 0/8 V2] [AArch64] Support " Yao Qi
8 siblings, 0 replies; 37+ messages in thread
From: Yao Qi @ 2015-09-18 12:44 UTC (permalink / raw)
To: gdb-patches
From: Pierre Langlois <pierre.langlois@arm.com>
This test case makes sure that relocating PC relative instructions does
not change their behaviors. All PC relative AArch64 instructions are
covered. While call and jump (32 bit relative) instructions are covered
on x86.
The test case creates a static array of function pointers for each
supported architecture. Each function in this array tests a specific
instruction using inline assembly. They all need to contain a symbol in
the form of 'set_point\[0-9\]+' and finish by either calling pass or
fail. The number of 'set_pointN' needs to go from 0 to
(ARRAY_SIZE - 1).
The test will:
- look up the number of function pointers in the static array.
- set fast tracepoints on each 'set_point\[0-9\]+' symbol, one in each
functions from 0 to (ARRAY_SIZE - 1).
- run the trace experiment and make sure the pass function is called for
every function.
gdb/testsuite/ChangeLog:
* gdb.arch/insn-reloc.c: New file.
* gdb.arch/ftrace-insn-reloc.exp: New file.
---
gdb/testsuite/gdb.arch/ftrace-insn-reloc.exp | 114 ++++++
gdb/testsuite/gdb.arch/insn-reloc.c | 508 +++++++++++++++++++++++++++
2 files changed, 622 insertions(+)
create mode 100644 gdb/testsuite/gdb.arch/ftrace-insn-reloc.exp
create mode 100644 gdb/testsuite/gdb.arch/insn-reloc.c
diff --git a/gdb/testsuite/gdb.arch/ftrace-insn-reloc.exp b/gdb/testsuite/gdb.arch/ftrace-insn-reloc.exp
new file mode 100644
index 0000000..bdd71e6
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/ftrace-insn-reloc.exp
@@ -0,0 +1,114 @@
+# Copyright 2015 Free Software Foundation, Inc.
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+load_lib "trace-support.exp"
+
+standard_testfile insn-reloc.c
+set executable $testfile
+set expfile $testfile.exp
+
+# Some targets have leading underscores on assembly symbols.
+set additional_flags [gdb_target_symbol_prefix_flags]
+
+if [prepare_for_testing $expfile $executable $srcfile \
+ [list debug $additional_flags]] {
+ untested "failed to prepare for trace tests"
+ return -1
+}
+
+if ![runto_main] {
+ fail "Can't run to main to check for trace support"
+ return -1
+}
+
+if ![gdb_target_supports_trace] {
+ unsupported "target does not support trace"
+ return -1
+}
+
+set libipa [get_in_proc_agent]
+gdb_load_shlibs $libipa
+
+# Can't use prepare_for_testing, because that splits compiling into
+# building objects and then linking, and we'd fail with "linker input
+# file unused because linking not done" when building the object.
+
+if { [gdb_compile "$srcdir/$subdir/$srcfile" $binfile \
+ executable [list debug $additional_flags shlib=$libipa] ] != "" } {
+ untested "failed to compile ftrace tests"
+ return -1
+}
+clean_restart ${executable}
+
+if ![runto_main] {
+ fail "Can't run to main for ftrace tests"
+ return 0
+}
+
+gdb_reinitialize_dir $srcdir/$subdir
+
+if { [gdb_test "info sharedlibrary" ".*${libipa}.*" "IPA loaded"] != 0 } {
+ untested "Could not find IPA lib loaded"
+ return 1
+}
+
+# Read function name from testcases[N].
+
+proc read_testcase { n } {
+ global gdb_prompt
+
+ set result -1
+ gdb_test_multiple "print testcases\[${n}\]" "read name of test case ${n}" {
+ -re "\[$\].*= .*<(.*)>.*$gdb_prompt $" {
+ set result $expect_out(1,string)
+ }
+ -re "$gdb_prompt $" { }
+ }
+
+ return $result
+}
+
+set n_testcases [gdb_readexpr "n_testcases"]
+
+if { ${n_testcases} == 0 } {
+ untested "No instruction relocation to test"
+ return 1
+}
+
+# Set a fast tracepoint on each set_point${i} symbol. There is one for
+# each testcase.
+for { set i 0 } { ${i} < ${n_testcases} } { incr i } {
+ set testcase [read_testcase $i]
+
+ gdb_test "ftrace *set_point$i" "Fast tracepoint .*" \
+ "fast tracepoint on ${testcase}"
+}
+
+gdb_test "break pass" ".*" ""
+gdb_test "break fail" ".*" ""
+
+gdb_test_no_output "tstart" "start trace experiment"
+
+# Make sure we have hit the pass breakpoint for each testcase.
+for { set i 0 } { ${i} < ${n_testcases} } { incr i } {
+ set testcase [read_testcase $i]
+
+ gdb_test "continue" \
+ ".*Breakpoint \[0-9\]+, pass \(\).*" \
+ "relocated instruction at ${testcase}"
+}
+
+gdb_test "tstatus" ".*Collected ${n_testcases} trace frames.*" "check on trace status"
+
+gdb_test "tstop" "" ""
diff --git a/gdb/testsuite/gdb.arch/insn-reloc.c b/gdb/testsuite/gdb.arch/insn-reloc.c
new file mode 100644
index 0000000..c7148a2
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/insn-reloc.c
@@ -0,0 +1,508 @@
+/* This testcase is part of GDB, the GNU debugger.
+
+ Copyright 2015 Free Software Foundation, Inc.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#include <stddef.h>
+#include <stdint.h>
+
+typedef void (*testcase_ftype)(void);
+
+/* Each function checks the correctness of the instruction being
+ relocated due to a fast tracepoint. Call function pass if it is
+ correct, otherwise call function fail. GDB sets a breakpoints on
+ pass and fail in order to check the correctness. */
+
+static void
+pass (void)
+{
+}
+
+static void
+fail (void)
+{
+}
+
+#if (defined __x86_64__ || defined __i386__)
+
+#ifdef SYMBOL_PREFIX
+#define SYMBOL(str) SYMBOL_PREFIX #str
+#else
+#define SYMBOL(str) #str
+#endif
+
+/* Make sure we can relocate a CALL instruction. CALL instructions are
+ 5 bytes long so we can always set a fast tracepoints on them.
+
+ JMP set_point0
+ f:
+ MOV $1, %[ok]
+ JMP end
+ set_point0:
+ CALL f ; tracepoint here.
+ end:
+
+ */
+
+static void
+can_relocate_call (void)
+{
+ int ok = 0;
+
+ asm (" .global " SYMBOL (set_point0) "\n"
+ " jmp " SYMBOL (set_point0) "\n"
+ "0:\n"
+ " mov $1, %[ok]\n"
+ " jmp 1f\n"
+ SYMBOL (set_point0) ":\n"
+ " call 0b\n"
+ "1:\n"
+ : [ok] "=r" (ok));
+
+ if (ok == 1)
+ pass ();
+ else
+ fail ();
+}
+
+/* Make sure we can relocate a JMP instruction. We need the JMP
+ instruction to be 5 bytes long in order to set a fast tracepoint on
+ it. To do this, we emit the opcode directly.
+
+ JMP next ; tracepoint here.
+ next:
+ MOV $1, %[ok]
+
+ */
+
+static void
+can_relocate_jump (void)
+{
+ int ok = 0;
+
+ asm (" .global " SYMBOL (set_point1) "\n"
+ SYMBOL (set_point1) ":\n"
+ ".byte 0xe9\n" /* jmp */
+ ".byte 0x00\n"
+ ".byte 0x00\n"
+ ".byte 0x00\n"
+ ".byte 0x00\n"
+ " mov $1, %[ok]\n"
+ : [ok] "=r" (ok));
+
+ if (ok == 1)
+ pass ();
+ else
+ fail ();
+}
+#elif (defined __aarch64__)
+
+/* Make sure we can relocate a B instruction.
+
+ B set_point0
+ set_ok:
+ MOV %[ok], #1
+ B end
+ set_point0:
+ B set_ok ; tracepoint here.
+ MOV %[ok], #0
+ end
+
+ */
+
+static void
+can_relocate_b (void)
+{
+ int ok = 0;
+
+ asm (" b set_point0\n"
+ "0:\n"
+ " mov %[ok], #1\n"
+ " b 1f\n"
+ "set_point0:\n"
+ " b 0b\n"
+ " mov %[ok], #0\n"
+ "1:\n"
+ : [ok] "=r" (ok));
+
+ if (ok == 1)
+ pass ();
+ else
+ fail ();
+}
+
+/* Make sure we can relocate a B.cond instruction.
+
+ MOV x0, #8
+ TST x0, #8 ; Clear the Z flag.
+ B set_point1
+ set_ok:
+ MOV %[ok], #1
+ B end
+ set_point1:
+ B.NE set_ok ; tracepoint here.
+ MOV %[ok], #0
+ end
+
+ */
+
+static void
+can_relocate_bcond (void)
+{
+ int ok = 0;
+
+ asm (" mov x0, #8\n"
+ " tst x0, #8\n"
+ " b set_point1\n"
+ "0:\n"
+ " mov %[ok], #1\n"
+ " b 1f\n"
+ "set_point1:\n"
+ " b.ne 0b\n"
+ " mov %[ok], #0\n"
+ "1:\n"
+ : [ok] "=r" (ok)
+ :
+ : "0", "cc");
+
+ if (ok == 1)
+ pass ();
+ else
+ fail ();
+}
+
+/* Make sure we can relocate a CBZ instruction.
+
+ MOV x0, #0
+ B set_point2
+ set_ok:
+ MOV %[ok], #1
+ B end
+ set_point2:
+ CBZ x0, set_ok ; tracepoint here.
+ MOV %[ok], #0
+ end
+
+ */
+
+static void
+can_relocate_cbz (void)
+{
+ int ok = 0;
+
+ asm (" mov x0, #0\n"
+ " b set_point2\n"
+ "0:\n"
+ " mov %[ok], #1\n"
+ " b 1f\n"
+ "set_point2:\n"
+ " cbz x0, 0b\n"
+ " mov %[ok], #0\n"
+ "1:\n"
+ : [ok] "=r" (ok)
+ :
+ : "0");
+
+ if (ok == 1)
+ pass ();
+ else
+ fail ();
+}
+
+/* Make sure we can relocate a CBNZ instruction.
+
+ MOV x0, #8
+ B set_point3
+ set_ok:
+ MOV %[ok], #1
+ B end
+ set_point3:
+ CBNZ x0, set_ok ; tracepoint here.
+ MOV %[ok], #0
+ end
+
+ */
+
+static void
+can_relocate_cbnz (void)
+{
+ int ok = 0;
+
+ asm (" mov x0, #8\n"
+ " b set_point3\n"
+ "0:\n"
+ " mov %[ok], #1\n"
+ " b 1f\n"
+ "set_point3:\n"
+ " cbnz x0, 0b\n"
+ " mov %[ok], #0\n"
+ "1:\n"
+ : [ok] "=r" (ok)
+ :
+ : "0");
+
+ if (ok == 1)
+ pass ();
+ else
+ fail ();
+}
+
+/* Make sure we can relocate a TBZ instruction.
+
+ MOV x0, #8
+ MVN x0, x0 ; Clear bit 3.
+ B set_point4
+ set_ok:
+ MOV %[ok], #1
+ B end
+ set_point4:
+ TBZ x0, #3, set_ok ; tracepoint here.
+ MOV %[ok], #0
+ end
+
+ */
+
+static void
+can_relocate_tbz (void)
+{
+ int ok = 0;
+
+ asm (" mov x0, #8\n"
+ " mvn x0, x0\n"
+ " b set_point4\n"
+ "0:\n"
+ " mov %[ok], #1\n"
+ " b 1f\n"
+ "set_point4:\n"
+ " tbz x0, #3, 0b\n"
+ " mov %[ok], #0\n"
+ "1:\n"
+ : [ok] "=r" (ok)
+ :
+ : "0");
+
+ if (ok == 1)
+ pass ();
+ else
+ fail ();
+}
+
+/* Make sure we can relocate a TBNZ instruction.
+
+ MOV x0, #8 ; Set bit 3.
+ B set_point5
+ set_ok:
+ MOV %[ok], #1
+ B end
+ set_point5:
+ TBNZ x0, #3, set_ok ; tracepoint here.
+ MOV %[ok], #0
+ end
+
+ */
+
+static void
+can_relocate_tbnz (void)
+{
+ int ok = 0;
+
+ asm (" mov x0, #8\n"
+ " b set_point5\n"
+ "0:\n"
+ " mov %[ok], #1\n"
+ " b 1f\n"
+ "set_point5:\n"
+ " tbnz x0, #3, 0b\n"
+ " mov %[ok], #0\n"
+ "1:\n"
+ : [ok] "=r" (ok)
+ :
+ : "0");
+
+ if (ok == 1)
+ pass ();
+ else
+ fail ();
+}
+
+/* Make sure we can relocate an ADR instruction with a positive offset.
+
+ set_point6:
+ ADR x0, target ; tracepoint here.
+ BR x0 ; jump to target
+ MOV %[ok], #0
+ B end
+ target:
+ MOV %[ok], #1
+ end
+
+ */
+
+static void
+can_relocate_adr_forward (void)
+{
+ int ok = 0;
+
+ asm ("set_point6:\n"
+ " adr x0, 0f\n"
+ " br x0\n"
+ " mov %[ok], #0\n"
+ " b 1f\n"
+ "0:\n"
+ " mov %[ok], #1\n"
+ "1:\n"
+ : [ok] "=r" (ok)
+ :
+ : "0");
+
+ if (ok == 1)
+ pass ();
+ else
+ fail ();
+}
+
+/* Make sure we can relocate an ADR instruction with a negative offset.
+
+ B set_point7
+ target:
+ MOV %[ok], #1
+ B end
+ set_point7:
+ ADR x0, target ; tracepoint here.
+ BR x0 ; jump to target
+ MOV %[ok], #0
+ end
+
+ */
+
+static void
+can_relocate_adr_backward (void)
+{
+ int ok = 0;
+
+ asm ("b set_point7\n"
+ "0:\n"
+ " mov %[ok], #1\n"
+ " b 1f\n"
+ "set_point7:\n"
+ " adr x0, 0b\n"
+ " br x0\n"
+ " mov %[ok], #0\n"
+ "1:\n"
+ : [ok] "=r" (ok)
+ :
+ : "0");
+
+ if (ok == 1)
+ pass ();
+ else
+ fail ();
+}
+
+/* Make sure we can relocate an ADRP instruction.
+
+ set_point8:
+ ADRP %[addr], set_point8 ; tracepoint here.
+ ADR %[pc], set_point8
+
+ ADR computes the address of the given label. While ADRP gives us its
+ page, on a 4K boundary. We can check ADRP executed normally by
+ making sure the result of ADR and ADRP are equivalent, except for the
+ 12 lowest bits which should be cleared.
+
+ */
+
+static void
+can_relocate_adrp (void)
+{
+ uintptr_t page;
+ uintptr_t pc;
+
+ asm ("set_point8:\n"
+ " adrp %[page], set_point8\n"
+ " adr %[pc], set_point8\n"
+ : [page] "=r" (page), [pc] "=r" (pc));
+
+ if (page == (pc & ~0xfff))
+ pass ();
+ else
+ fail ();
+}
+
+/* Make sure we can relocate an LDR instruction, where the memory to
+ read is an offset from the current PC.
+
+ B set_point9
+ data:
+ .word 0x0cabba9e
+ set_point9:
+ LDR %[result], data ; tracepoint here.
+
+ */
+
+static void
+can_relocate_ldr (void)
+{
+ uint32_t result = 0;
+
+ asm ("b set_point9\n"
+ "0:\n"
+ " .word 0x0cabba9e\n"
+ "set_point9:\n"
+ " ldr %w[result], 0b\n"
+ : [result] "=r" (result));
+
+ if (result == 0x0cabba9e)
+ pass ();
+ else
+ fail ();
+}
+#endif
+
+/* Functions testing relocations need to be placed here. GDB will read
+ n_testcases to know how many fast tracepoints to place. It will look
+ for symbols in the form of 'set_point\[0-9\]+' so each functions
+ needs one, starting at 0. */
+
+static testcase_ftype testcases[] = {
+#if (defined __x86_64__ || defined __i386__)
+ can_relocate_call,
+ can_relocate_jump
+#elif (defined __aarch64__)
+ can_relocate_b,
+ can_relocate_bcond,
+ can_relocate_cbz,
+ can_relocate_cbnz,
+ can_relocate_tbz,
+ can_relocate_tbnz,
+ can_relocate_adr_forward,
+ can_relocate_adr_backward,
+ can_relocate_adrp,
+ can_relocate_ldr
+#endif
+};
+
+static size_t n_testcases = (sizeof (testcases) / sizeof (testcase_ftype));
+
+int
+main ()
+{
+ int i = 0;
+
+ for (i = 0; i < n_testcases; i++)
+ testcases[i] ();
+
+ return 0;
+}
--
1.9.1
^ permalink raw reply [flat|nested] 37+ messages in thread* [PATCH 3/8] Add support for fast tracepoints
2015-09-18 12:43 ` [PATCH 0/8 V2] [AArch64] Support fast tracepoints Yao Qi
` (6 preceding siblings ...)
2015-09-18 12:44 ` [PATCH 6/8] Add a gdb.trace test for instruction relocation Yao Qi
@ 2015-09-18 12:44 ` Yao Qi
2015-09-21 14:06 ` [PATCH 0/8 V2] [AArch64] Support " Yao Qi
8 siblings, 0 replies; 37+ messages in thread
From: Yao Qi @ 2015-09-18 12:44 UTC (permalink / raw)
To: gdb-patches
From: Pierre Langlois <pierre.langlois@arm.com>
This patch adds support for fast tracepoints for aarch64-linux. With this
implementation, a tracepoint can only be placed in a +/- 128MB range of
the jump pad. This is due to the unconditional branch instruction
being limited to a (26 bit << 2) offset from the current PC.
Three target operations are implemented:
- target_install_fast_tracepoint_jump_pad
Building the jump pad the biggest change of this patch. We need to add
functions to emit all instructions needed to save and restore the
current state when the tracepoint is hit. As well as implementing a
lock and creating a collecting_t object identifying the current thread.
Steps performed by the jump pad:
* Save the current state on the stack.
* Push a collecting_t object on the stack. We read the special
tpidr_el0 system register to get the thread ID.
* Spin-lock on the shared memory location of all tracing threads. We
write the address of our collecting_t object there once we have the
lock.
* Call gdb_collect.
* Release the lock.
* Restore the state.
* Execute the replaced instruction which will have been relocated.
* Jump back to the program.
- target_get_thread_area
As implemented in ps_get_thread_area, target_get_thread_area uses ptrace
to fetch the NT_ARM_TLS register. At the architecture level, NT_ARM_TLS
represents the tpidr_el0 system register.
So this ptrace call (if lwpid is the current thread):
~~~
ptrace (PTRACE_GETREGSET, lwpid, NT_ARM_TLS, &iovec);
~~~
Is equivalent to the following instruction:
~~~
msr x0, tpidr_el0
~~~
This instruction is used when creating the collecting_t object that
GDBserver can read to know if a given thread is currently tracing.
So target_get_thread_area must get the same thread IDs as what the jump
pad writes into its collecting_t object.
- target_get_min_fast_tracepoint_insn_len
This just returns 4.
gdb/gdbserver/ChangeLog:
* Makefile.in (linux-aarch64-ipa.o, aarch64-ipa.o): New rules.
* configure.srv (aarch64*-*-linux*): Add linux-aarch64-ipa.o and
aarch64-ipa.o.
* linux-aarch64-ipa.c: New file.
* linux-aarch64-low.c: Include arch/aarch64-insn.h, inttypes.h
and endian.h.
(aarch64_get_thread_area): New target method.
(extract_signed_bitfield): New helper function.
(aarch64_decode_ldr_literal): New function.
(enum aarch64_opcodes): New enum.
(struct aarch64_register): New struct.
(struct aarch64_operand): New struct.
(x0): New static global.
(x1): Likewise.
(x2): Likewise.
(x3): Likewise.
(x4): Likewise.
(w2): Likewise.
(ip0): Likewise.
(sp): Likewise.
(xzr): Likewise.
(aarch64_register): New helper function.
(register_operand): Likewise.
(immediate_operand): Likewise.
(struct aarch64_memory_operand): New struct.
(offset_memory_operand): New helper function.
(preindex_memory_operand): Likewise.
(enum aarch64_system_control_registers): New enum.
(ENCODE): New macro.
(emit_insn): New helper function.
(emit_b): New function.
(emit_bcond): Likewise.
(emit_cb): Likewise.
(emit_tb): Likewise.
(emit_blr): Likewise.
(emit_stp): Likewise.
(emit_ldp_q_offset): Likewise.
(emit_stp_q_offset): Likewise.
(emit_load_store): Likewise.
(emit_ldr): Likewise.
(emit_ldrsw): Likewise.
(emit_str): Likewise.
(emit_ldaxr): Likewise.
(emit_stxr): Likewise.
(emit_stlr): Likewise.
(emit_data_processing_reg): Likewise.
(emit_data_processing): Likewise.
(emit_add): Likewise.
(emit_sub): Likewise.
(emit_mov): Likewise.
(emit_movk): Likewise.
(emit_mov_addr): Likewise.
(emit_mrs): Likewise.
(emit_msr): Likewise.
(emit_sevl): Likewise.
(emit_wfe): Likewise.
(append_insns): Likewise.
(can_encode_int32_in): New helper function.
(aarch64_relocate_instruction): New function.
(aarch64_install_fast_tracepoint_jump_pad): Likewise.
(aarch64_get_min_fast_tracepoint_insn_len): Likewise.
(struct linux_target_ops): Install aarch64_get_thread_area,
aarch64_install_fast_tracepoint_jump_pad and
aarch64_get_min_fast_tracepoint_insn_len.
---
gdb/gdbserver/Makefile.in | 6 +
gdb/gdbserver/configure.srv | 1 +
gdb/gdbserver/linux-aarch64-ipa.c | 151 ++++
gdb/gdbserver/linux-aarch64-low.c | 1466 ++++++++++++++++++++++++++++++++++++-
4 files changed, 1621 insertions(+), 3 deletions(-)
create mode 100644 gdb/gdbserver/linux-aarch64-ipa.c
diff --git a/gdb/gdbserver/Makefile.in b/gdb/gdbserver/Makefile.in
index d096663..cd146f4 100644
--- a/gdb/gdbserver/Makefile.in
+++ b/gdb/gdbserver/Makefile.in
@@ -499,6 +499,12 @@ linux-amd64-ipa.o: linux-amd64-ipa.c
amd64-linux-ipa.o: amd64-linux.c
$(IPAGENT_COMPILE) $<
$(POSTCOMPILE)
+linux-aarch64-ipa.o: linux-aarch64-ipa.c
+ $(IPAGENT_COMPILE) $<
+ $(POSTCOMPILE)
+aarch64-ipa.o: aarch64.c
+ $(IPAGENT_COMPILE) $<
+ $(POSTCOMPILE)
tdesc-ipa.o: tdesc.c
$(IPAGENT_COMPILE) $<
$(POSTCOMPILE)
diff --git a/gdb/gdbserver/configure.srv b/gdb/gdbserver/configure.srv
index a62df83..f187c9d 100644
--- a/gdb/gdbserver/configure.srv
+++ b/gdb/gdbserver/configure.srv
@@ -62,6 +62,7 @@ case "${target}" in
srv_xmlfiles="${srv_xmlfiles} arm-with-neon.xml"
srv_linux_regsets=yes
srv_linux_thread_db=yes
+ ipa_obj="linux-aarch64-ipa.o aarch64-ipa.o"
;;
arm*-*-linux*) srv_regobj="reg-arm.o arm-with-iwmmxt.o"
srv_regobj="${srv_regobj} arm-with-vfpv2.o"
diff --git a/gdb/gdbserver/linux-aarch64-ipa.c b/gdb/gdbserver/linux-aarch64-ipa.c
new file mode 100644
index 0000000..1aafc5f
--- /dev/null
+++ b/gdb/gdbserver/linux-aarch64-ipa.c
@@ -0,0 +1,151 @@
+/* GNU/Linux/AArch64 specific low level interface, for the in-process
+ agent library for GDB.
+
+ Copyright (C) 2015 Free Software Foundation, Inc.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#include "server.h"
+#include "tracepoint.h"
+
+/* Defined in auto-generated file aarch64.c. */
+void init_registers_aarch64 (void);
+extern const struct target_desc *tdesc_aarch64;
+
+/* Each register saved by the jump pad is in a 16 byte cell. */
+#define FT_CR_SIZE 16
+
+#define FT_CR_FPCR 0
+#define FT_CR_FPSR 1
+#define FT_CR_CPSR 2
+#define FT_CR_PC 3
+#define FT_CR_SP 4
+#define FT_CR_X0 5
+#define FT_CR_GPR(n) (FT_CR_X0 + (n))
+#define FT_CR_FPR(n) (FT_CR_GPR (31) + (n))
+
+/* Mapping between registers collected by the jump pad and GDB's register
+ array layout used by regcache.
+
+ See linux-aarch64-low.c (aarch64_install_fast_tracepoint_jump_pad) for
+ more details. */
+
+static const int aarch64_ft_collect_regmap[] = {
+ FT_CR_GPR (0),
+ FT_CR_GPR (1),
+ FT_CR_GPR (2),
+ FT_CR_GPR (3),
+ FT_CR_GPR (4),
+ FT_CR_GPR (5),
+ FT_CR_GPR (6),
+ FT_CR_GPR (7),
+ FT_CR_GPR (8),
+ FT_CR_GPR (9),
+ FT_CR_GPR (10),
+ FT_CR_GPR (11),
+ FT_CR_GPR (12),
+ FT_CR_GPR (13),
+ FT_CR_GPR (14),
+ FT_CR_GPR (15),
+ FT_CR_GPR (16),
+ FT_CR_GPR (17),
+ FT_CR_GPR (18),
+ FT_CR_GPR (19),
+ FT_CR_GPR (20),
+ FT_CR_GPR (21),
+ FT_CR_GPR (22),
+ FT_CR_GPR (23),
+ FT_CR_GPR (24),
+ FT_CR_GPR (25),
+ FT_CR_GPR (26),
+ FT_CR_GPR (27),
+ FT_CR_GPR (28),
+ /* FP */
+ FT_CR_GPR (29),
+ /* LR */
+ FT_CR_GPR (30),
+ FT_CR_SP,
+ FT_CR_PC,
+ FT_CR_CPSR,
+ FT_CR_FPR (0),
+ FT_CR_FPR (1),
+ FT_CR_FPR (2),
+ FT_CR_FPR (3),
+ FT_CR_FPR (4),
+ FT_CR_FPR (5),
+ FT_CR_FPR (6),
+ FT_CR_FPR (7),
+ FT_CR_FPR (8),
+ FT_CR_FPR (9),
+ FT_CR_FPR (10),
+ FT_CR_FPR (11),
+ FT_CR_FPR (12),
+ FT_CR_FPR (13),
+ FT_CR_FPR (14),
+ FT_CR_FPR (15),
+ FT_CR_FPR (16),
+ FT_CR_FPR (17),
+ FT_CR_FPR (18),
+ FT_CR_FPR (19),
+ FT_CR_FPR (20),
+ FT_CR_FPR (21),
+ FT_CR_FPR (22),
+ FT_CR_FPR (23),
+ FT_CR_FPR (24),
+ FT_CR_FPR (25),
+ FT_CR_FPR (26),
+ FT_CR_FPR (27),
+ FT_CR_FPR (28),
+ FT_CR_FPR (29),
+ FT_CR_FPR (30),
+ FT_CR_FPR (31),
+ FT_CR_FPSR,
+ FT_CR_FPCR
+};
+
+#define AARCH64_NUM_FT_COLLECT_GREGS \
+ (sizeof (aarch64_ft_collect_regmap) / sizeof(aarch64_ft_collect_regmap[0]))
+
+/* Fill in REGCACHE with registers saved by the jump pad in BUF. */
+
+void
+supply_fast_tracepoint_registers (struct regcache *regcache,
+ const unsigned char *buf)
+{
+ int i;
+
+ for (i = 0; i < AARCH64_NUM_FT_COLLECT_GREGS; i++)
+ supply_register (regcache, i,
+ ((char *) buf)
+ + (aarch64_ft_collect_regmap[i] * FT_CR_SIZE));
+}
+
+IP_AGENT_EXPORT_FUNC ULONGEST
+gdb_agent_get_raw_reg (const unsigned char *raw_regs, int regnum)
+{
+ if (regnum >= AARCH64_NUM_FT_COLLECT_GREGS)
+ return 0;
+
+ return *(ULONGEST *) (raw_regs
+ + aarch64_ft_collect_regmap[regnum] * FT_CR_SIZE);
+}
+
+void
+initialize_low_tracepoint (void)
+{
+ init_registers_aarch64 ();
+ ipa_tdesc = tdesc_aarch64;
+}
diff --git a/gdb/gdbserver/linux-aarch64-low.c b/gdb/gdbserver/linux-aarch64-low.c
index 73b248c..e2d738b 100644
--- a/gdb/gdbserver/linux-aarch64-low.c
+++ b/gdb/gdbserver/linux-aarch64-low.c
@@ -23,6 +23,7 @@
#include "linux-low.h"
#include "nat/aarch64-linux.h"
#include "nat/aarch64-linux-hw-point.h"
+#include "arch/aarch64-insn.h"
#include "linux-aarch32-low.h"
#include "elf/common.h"
@@ -31,6 +32,8 @@
#include "nat/gdb_ptrace.h"
#include <asm/ptrace.h>
#include <sys/uio.h>
+#include <inttypes.h>
+#include <endian.h>
#include "gdb_proc_service.h"
@@ -573,6 +576,1463 @@ aarch64_supports_tracepoints (void)
}
}
+/* Implementation of linux_target_ops method "get_thread_area". */
+
+static int
+aarch64_get_thread_area (int lwpid, CORE_ADDR *addrp)
+{
+ struct iovec iovec;
+ uint64_t reg;
+
+ iovec.iov_base = ®
+ iovec.iov_len = sizeof (reg);
+
+ if (ptrace (PTRACE_GETREGSET, lwpid, NT_ARM_TLS, &iovec) != 0)
+ return -1;
+
+ *addrp = reg;
+
+ return 0;
+}
+
+/* Extract a signed value from a bit field within an instruction
+ encoding.
+
+ INSN is the instruction opcode.
+
+ WIDTH specifies the width of the bit field to extract (in bits).
+
+ OFFSET specifies the least significant bit of the field where bits
+ are numbered zero counting from least to most significant. */
+
+static int32_t
+extract_signed_bitfield (uint32_t insn, unsigned width, unsigned offset)
+{
+ unsigned shift_l = sizeof (int32_t) * 8 - (offset + width);
+ unsigned shift_r = sizeof (int32_t) * 8 - width;
+
+ return ((int32_t) insn << shift_l) >> shift_r;
+}
+
+/* Decode an opcode if it represents an LDR or LDRSW instruction taking a
+ literal offset from the current PC.
+
+ ADDR specifies the address of the opcode.
+ INSN specifies the opcode to test.
+ IS_W is set if the instruction is LDRSW.
+ IS64 receives size field from the decoded instruction.
+ RT receives the 'rt' field from the decoded instruction.
+ OFFSET receives the 'imm' field from the decoded instruction.
+
+ Return 1 if the opcodes matches and is decoded, otherwise 0. */
+
+int
+aarch64_decode_ldr_literal (CORE_ADDR addr, uint32_t insn, int *is_w,
+ int *is64, unsigned *rt, int32_t *offset)
+{
+ /* LDR 0T01 1000 iiii iiii iiii iiii iiir rrrr */
+ /* LDRSW 1001 1000 iiii iiii iiii iiii iiir rrrr */
+ if ((insn & 0x3f000000) == 0x18000000)
+ {
+ *is_w = (insn >> 31) & 0x1;
+
+ if (*is_w)
+ {
+ /* LDRSW always takes a 64-bit destination registers. */
+ *is64 = 1;
+ }
+ else
+ *is64 = (insn >> 30) & 0x1;
+
+ *rt = (insn >> 0) & 0x1f;
+ *offset = extract_signed_bitfield (insn, 19, 5) << 2;
+
+ if (aarch64_debug)
+ debug_printf ("decode: %s 0x%x %s %s%u, #?\n",
+ core_addr_to_string_nz (addr), insn,
+ *is_w ? "ldrsw" : "ldr",
+ *is64 ? "x" : "w", *rt);
+
+ return 1;
+ }
+
+ return 0;
+}
+
+/* List of opcodes that we need for building the jump pad and relocating
+ an instruction. */
+
+enum aarch64_opcodes
+{
+ /* B 0001 01ii iiii iiii iiii iiii iiii iiii */
+ /* BL 1001 01ii iiii iiii iiii iiii iiii iiii */
+ /* B.COND 0101 0100 iiii iiii iiii iiii iii0 cccc */
+ /* CBZ s011 0100 iiii iiii iiii iiii iiir rrrr */
+ /* CBNZ s011 0101 iiii iiii iiii iiii iiir rrrr */
+ /* TBZ b011 0110 bbbb biii iiii iiii iiir rrrr */
+ /* TBNZ b011 0111 bbbb biii iiii iiii iiir rrrr */
+ B = 0x14000000,
+ BL = 0x80000000 | B,
+ BCOND = 0x40000000 | B,
+ CBZ = 0x20000000 | B,
+ CBNZ = 0x21000000 | B,
+ TBZ = 0x36000000 | B,
+ TBNZ = 0x37000000 | B,
+ /* BLR 1101 0110 0011 1111 0000 00rr rrr0 0000 */
+ BLR = 0xd63f0000,
+ /* STP s010 100o o0ii iiii irrr rrrr rrrr rrrr */
+ /* LDP s010 100o o1ii iiii irrr rrrr rrrr rrrr */
+ /* STP (SIMD&VFP) ss10 110o o0ii iiii irrr rrrr rrrr rrrr */
+ /* LDP (SIMD&VFP) ss10 110o o1ii iiii irrr rrrr rrrr rrrr */
+ STP = 0x28000000,
+ LDP = 0x28400000,
+ STP_SIMD_VFP = 0x04000000 | STP,
+ LDP_SIMD_VFP = 0x04000000 | LDP,
+ /* STR ss11 100o 00xi iiii iiii xxrr rrrr rrrr */
+ /* LDR ss11 100o 01xi iiii iiii xxrr rrrr rrrr */
+ /* LDRSW 1011 100o 10xi iiii iiii xxrr rrrr rrrr */
+ STR = 0x38000000,
+ LDR = 0x00400000 | STR,
+ LDRSW = 0x80800000 | STR,
+ /* LDAXR ss00 1000 0101 1111 1111 11rr rrrr rrrr */
+ LDAXR = 0x085ffc00,
+ /* STXR ss00 1000 000r rrrr 0111 11rr rrrr rrrr */
+ STXR = 0x08007c00,
+ /* STLR ss00 1000 1001 1111 1111 11rr rrrr rrrr */
+ STLR = 0x089ffc00,
+ /* MOV s101 0010 1xxi iiii iiii iiii iiir rrrr */
+ /* MOVK s111 0010 1xxi iiii iiii iiii iiir rrrr */
+ MOV = 0x52800000,
+ MOVK = 0x20000000 | MOV,
+ /* ADD s00o ooo1 xxxx xxxx xxxx xxxx xxxx xxxx */
+ /* SUB s10o ooo1 xxxx xxxx xxxx xxxx xxxx xxxx */
+ /* SUBS s11o ooo1 xxxx xxxx xxxx xxxx xxxx xxxx */
+ ADD = 0x01000000,
+ SUB = 0x40000000 | ADD,
+ /* MSR (register) 1101 0101 0001 oooo oooo oooo ooor rrrr */
+ /* MRS 1101 0101 0011 oooo oooo oooo ooor rrrr */
+ MSR = 0xd5100000,
+ MRS = 0x00200000 | MSR,
+ /* HINT 1101 0101 0000 0011 0010 oooo ooo1 1111 */
+ HINT = 0xd503201f,
+ SEVL = (5 << 5) | HINT,
+ WFE = (2 << 5) | HINT,
+};
+
+/* Representation of a general purpose register of the form xN or wN.
+
+ This type is used by emitting functions that take registers as operands. */
+
+struct aarch64_register
+{
+ unsigned num;
+ int is64;
+};
+
+/* Representation of an operand. At this time, it only supports register
+ and immediate types. */
+
+struct aarch64_operand
+{
+ /* Type of the operand. */
+ enum
+ {
+ OPERAND_IMMEDIATE,
+ OPERAND_REGISTER,
+ } type;
+ /* Value of the operand according to the type. */
+ union
+ {
+ uint32_t imm;
+ struct aarch64_register reg;
+ };
+};
+
+/* List of registers that we are currently using, we can add more here as
+ we need to use them. */
+
+/* General purpose scratch registers (64 bit). */
+static const struct aarch64_register x0 = { 0, 1 };
+static const struct aarch64_register x1 = { 1, 1 };
+static const struct aarch64_register x2 = { 2, 1 };
+static const struct aarch64_register x3 = { 3, 1 };
+static const struct aarch64_register x4 = { 4, 1 };
+
+/* General purpose scratch registers (32 bit). */
+static const struct aarch64_register w2 = { 2, 0 };
+
+/* Intra-procedure scratch registers. */
+static const struct aarch64_register ip0 = { 16, 1 };
+
+/* Special purpose registers. */
+static const struct aarch64_register sp = { 31, 1 };
+static const struct aarch64_register xzr = { 31, 1 };
+
+/* Dynamically allocate a new register. If we know the register
+ statically, we should make it a global as above instead of using this
+ helper function. */
+
+static struct aarch64_register
+aarch64_register (unsigned num, int is64)
+{
+ return (struct aarch64_register) { num, is64 };
+}
+
+/* Helper function to create a register operand, for instructions with
+ different types of operands.
+
+ For example:
+ p += emit_mov (p, x0, register_operand (x1)); */
+
+static struct aarch64_operand
+register_operand (struct aarch64_register reg)
+{
+ struct aarch64_operand operand;
+
+ operand.type = OPERAND_REGISTER;
+ operand.reg = reg;
+
+ return operand;
+}
+
+/* Helper function to create an immediate operand, for instructions with
+ different types of operands.
+
+ For example:
+ p += emit_mov (p, x0, immediate_operand (12)); */
+
+static struct aarch64_operand
+immediate_operand (uint32_t imm)
+{
+ struct aarch64_operand operand;
+
+ operand.type = OPERAND_IMMEDIATE;
+ operand.imm = imm;
+
+ return operand;
+}
+
+/* Representation of a memory operand, used for load and store
+ instructions.
+
+ The types correspond to the following variants:
+
+ MEMORY_OPERAND_OFFSET: LDR rt, [rn, #offset]
+ MEMORY_OPERAND_PREINDEX: LDR rt, [rn, #index]! */
+
+struct aarch64_memory_operand
+{
+ /* Type of the operand. */
+ enum
+ {
+ MEMORY_OPERAND_OFFSET,
+ MEMORY_OPERAND_PREINDEX,
+ } type;
+ /* Index from the base register. */
+ int32_t index;
+};
+
+/* Helper function to create an offset memory operand.
+
+ For example:
+ p += emit_ldr (p, x0, sp, offset_memory_operand (16)); */
+
+static struct aarch64_memory_operand
+offset_memory_operand (int32_t offset)
+{
+ return (struct aarch64_memory_operand) { MEMORY_OPERAND_OFFSET, offset };
+}
+
+/* Helper function to create a pre-index memory operand.
+
+ For example:
+ p += emit_ldr (p, x0, sp, preindex_memory_operand (16)); */
+
+static struct aarch64_memory_operand
+preindex_memory_operand (int32_t index)
+{
+ return (struct aarch64_memory_operand) { MEMORY_OPERAND_PREINDEX, index };
+}
+
+/* System control registers. These special registers can be written and
+ read with the MRS and MSR instructions.
+
+ - NZCV: Condition flags. GDB refers to this register under the CPSR
+ name.
+ - FPSR: Floating-point status register.
+ - FPCR: Floating-point control registers.
+ - TPIDR_EL0: Software thread ID register. */
+
+enum aarch64_system_control_registers
+{
+ /* op0 op1 crn crm op2 */
+ NZCV = (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x2 << 3) | 0x0,
+ FPSR = (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x4 << 3) | 0x1,
+ FPCR = (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x4 << 3) | 0x0,
+ TPIDR_EL0 = (0x1 << 14) | (0x3 << 11) | (0xd << 7) | (0x0 << 3) | 0x2
+};
+
+/* Helper macro to mask and shift a value into a bitfield. */
+
+#define ENCODE(val, size, offset) \
+ ((uint32_t) ((val & ((1ULL << size) - 1)) << offset))
+
+/* Write a 32-bit unsigned integer INSN info *BUF. Return the number of
+ instructions written (aka. 1). */
+
+static int
+emit_insn (uint32_t *buf, uint32_t insn)
+{
+ *buf = insn;
+ return 1;
+}
+
+/* Write a B or BL instruction into *BUF.
+
+ B #offset
+ BL #offset
+
+ IS_BL specifies if the link register should be updated.
+ OFFSET is the immediate offset from the current PC. It is
+ byte-addressed but should be 4 bytes aligned. It has a limited range of
+ +/- 128MB (26 bits << 2). */
+
+static int
+emit_b (uint32_t *buf, int is_bl, int32_t offset)
+{
+ uint32_t imm26 = ENCODE (offset >> 2, 26, 0);
+
+ if (is_bl)
+ return emit_insn (buf, BL | imm26);
+ else
+ return emit_insn (buf, B | imm26);
+}
+
+/* Write a BCOND instruction into *BUF.
+
+ B.COND #offset
+
+ COND specifies the condition field.
+ OFFSET is the immediate offset from the current PC. It is
+ byte-addressed but should be 4 bytes aligned. It has a limited range of
+ +/- 1MB (19 bits << 2). */
+
+static int
+emit_bcond (uint32_t *buf, unsigned cond, int32_t offset)
+{
+ return emit_insn (buf, BCOND | ENCODE (offset >> 2, 19, 5)
+ | ENCODE (cond, 4, 0));
+}
+
+/* Write a CBZ or CBNZ instruction into *BUF.
+
+ CBZ rt, #offset
+ CBNZ rt, #offset
+
+ IS_CBNZ distinguishes between CBZ and CBNZ instructions.
+ RN is the register to test.
+ OFFSET is the immediate offset from the current PC. It is
+ byte-addressed but should be 4 bytes aligned. It has a limited range of
+ +/- 1MB (19 bits << 2). */
+
+static int
+emit_cb (uint32_t *buf, int is_cbnz, struct aarch64_register rt,
+ int32_t offset)
+{
+ uint32_t imm19 = ENCODE (offset >> 2, 19, 5);
+ uint32_t sf = ENCODE (rt.is64, 1, 31);
+
+ if (is_cbnz)
+ return emit_insn (buf, CBNZ | sf | imm19 | ENCODE (rt.num, 5, 0));
+ else
+ return emit_insn (buf, CBZ | sf | imm19 | ENCODE (rt.num, 5, 0));
+}
+
+/* Write a TBZ or TBNZ instruction into *BUF.
+
+ TBZ rt, #bit, #offset
+ TBNZ rt, #bit, #offset
+
+ IS_TBNZ distinguishes between TBZ and TBNZ instructions.
+ RT is the register to test.
+ BIT is the index of the bit to test in register RT.
+ OFFSET is the immediate offset from the current PC. It is
+ byte-addressed but should be 4 bytes aligned. It has a limited range of
+ +/- 32KB (14 bits << 2). */
+
+static int
+emit_tb (uint32_t *buf, int is_tbnz, unsigned bit,
+ struct aarch64_register rt, int32_t offset)
+{
+ uint32_t imm14 = ENCODE (offset >> 2, 14, 5);
+ uint32_t b40 = ENCODE (bit, 5, 19);
+ uint32_t b5 = ENCODE (bit >> 5, 1, 31);
+
+ if (is_tbnz)
+ return emit_insn (buf, TBNZ | b5 | b40 | imm14 | ENCODE (rt.num, 5, 0));
+ else
+ return emit_insn (buf, TBZ | b5 | b40 | imm14 | ENCODE (rt.num, 5, 0));
+}
+
+/* Write a BLR instruction into *BUF.
+
+ BLR rn
+
+ RN is the register to branch to. */
+
+static int
+emit_blr (uint32_t *buf, struct aarch64_register rn)
+{
+ return emit_insn (buf, BLR | ENCODE (rn.num, 5, 5));
+}
+
+/* Write a STP instruction into *BUF.
+
+ STP rt, rt2, [rn, #offset]
+ STP rt, rt2, [rn, #index]!
+
+ RT and RT2 are the registers to store.
+ RN is the base address register.
+ OFFSET is the immediate to add to the base address. It is limited to a
+ -512 .. 504 range (7 bits << 3). */
+
+static int
+emit_stp (uint32_t *buf, struct aarch64_register rt,
+ struct aarch64_register rt2, struct aarch64_register rn,
+ struct aarch64_memory_operand operand)
+{
+ uint32_t opc;
+ uint32_t pre_index;
+ uint32_t write_back;
+
+ if (rt.is64)
+ opc = ENCODE (2, 2, 30);
+ else
+ opc = ENCODE (0, 2, 30);
+
+ switch (operand.type)
+ {
+ case MEMORY_OPERAND_OFFSET:
+ {
+ pre_index = ENCODE (1, 1, 24);
+ write_back = ENCODE (0, 1, 23);
+ break;
+ }
+ case MEMORY_OPERAND_PREINDEX:
+ {
+ pre_index = ENCODE (1, 1, 24);
+ write_back = ENCODE (1, 1, 23);
+ break;
+ }
+ default:
+ return 0;
+ }
+
+ return emit_insn (buf, STP | opc | pre_index | write_back
+ | ENCODE (operand.index >> 3, 7, 15) | ENCODE (rt2.num, 5, 10)
+ | ENCODE (rn.num, 5, 5) | ENCODE (rt.num, 5, 0));
+}
+
+/* Write a LDP (SIMD&VFP) instruction using Q registers into *BUF.
+
+ LDP qt, qt2, [rn, #offset]
+
+ RT and RT2 are the Q registers to store.
+ RN is the base address register.
+ OFFSET is the immediate to add to the base address. It is limited to
+ -1024 .. 1008 range (7 bits << 4). */
+
+static int
+emit_ldp_q_offset (uint32_t *buf, unsigned rt, unsigned rt2,
+ struct aarch64_register rn, int32_t offset)
+{
+ uint32_t opc = ENCODE (2, 2, 30);
+ uint32_t pre_index = ENCODE (1, 1, 24);
+
+ return emit_insn (buf, LDP_SIMD_VFP | opc | pre_index
+ | ENCODE (offset >> 4, 7, 15) | ENCODE (rt2, 5, 10)
+ | ENCODE (rn.num, 5, 5) | ENCODE (rt, 5, 0));
+}
+
+/* Write a STP (SIMD&VFP) instruction using Q registers into *BUF.
+
+ STP qt, qt2, [rn, #offset]
+
+ RT and RT2 are the Q registers to store.
+ RN is the base address register.
+ OFFSET is the immediate to add to the base address. It is limited to
+ -1024 .. 1008 range (7 bits << 4). */
+
+static int
+emit_stp_q_offset (uint32_t *buf, unsigned rt, unsigned rt2,
+ struct aarch64_register rn, int32_t offset)
+{
+ uint32_t opc = ENCODE (2, 2, 30);
+ uint32_t pre_index = ENCODE (1, 1, 24);
+
+ return emit_insn (buf, STP_SIMD_VFP | opc | pre_index
+ | ENCODE (offset >> 4, 7, 15) | ENCODE (rt2, 5, 10)
+ | ENCODE (rn.num, 5, 5) | ENCODE (rt, 5, 0));
+}
+
+/* Helper function emitting a load or store instruction. */
+
+static int
+emit_load_store (uint32_t *buf, uint32_t size, enum aarch64_opcodes opcode,
+ struct aarch64_register rt, struct aarch64_register rn,
+ struct aarch64_memory_operand operand)
+{
+ uint32_t op;
+
+ switch (operand.type)
+ {
+ case MEMORY_OPERAND_OFFSET:
+ {
+ op = ENCODE (1, 1, 24);
+
+ return emit_insn (buf, opcode | ENCODE (size, 2, 30) | op
+ | ENCODE (operand.index >> 3, 12, 10)
+ | ENCODE (rn.num, 5, 5) | ENCODE (rt.num, 5, 0));
+ }
+ case MEMORY_OPERAND_PREINDEX:
+ {
+ uint32_t pre_index = ENCODE (3, 2, 10);
+
+ op = ENCODE (0, 1, 24);
+
+ return emit_insn (buf, opcode | ENCODE (size, 2, 30) | op
+ | pre_index | ENCODE (operand.index, 9, 12)
+ | ENCODE (rn.num, 5, 5) | ENCODE (rt.num, 5, 0));
+ }
+ default:
+ return 0;
+ }
+}
+
+/* Write a LDR instruction into *BUF.
+
+ LDR rt, [rn, #offset]
+ LDR rt, [rn, #index]!
+
+ RT is the register to store.
+ RN is the base address register.
+ OFFSET is the immediate to add to the base address. It is limited to
+ 0 .. 32760 range (12 bits << 3). */
+
+static int
+emit_ldr (uint32_t *buf, struct aarch64_register rt,
+ struct aarch64_register rn, struct aarch64_memory_operand operand)
+{
+ return emit_load_store (buf, rt.is64 ? 3 : 2, LDR, rt, rn, operand);
+}
+
+/* Write a LDRSW instruction into *BUF. The register size is 64-bit.
+
+ LDRSW xt, [rn, #offset]
+ LDRSW xt, [rn, #index]!
+
+ RT is the register to store.
+ RN is the base address register.
+ OFFSET is the immediate to add to the base address. It is limited to
+ 0 .. 16380 range (12 bits << 2). */
+
+static int
+emit_ldrsw (uint32_t *buf, struct aarch64_register rt,
+ struct aarch64_register rn,
+ struct aarch64_memory_operand operand)
+{
+ return emit_load_store (buf, 3, LDRSW, rt, rn, operand);
+}
+
+/* Write a STR instruction into *BUF.
+
+ STR rt, [rn, #offset]
+ STR rt, [rn, #index]!
+
+ RT is the register to store.
+ RN is the base address register.
+ OFFSET is the immediate to add to the base address. It is limited to
+ 0 .. 32760 range (12 bits << 3). */
+
+static int
+emit_str (uint32_t *buf, struct aarch64_register rt,
+ struct aarch64_register rn,
+ struct aarch64_memory_operand operand)
+{
+ return emit_load_store (buf, rt.is64 ? 3 : 2, STR, rt, rn, operand);
+}
+
+/* Helper function emitting an exclusive load or store instruction. */
+
+static int
+emit_load_store_exclusive (uint32_t *buf, uint32_t size,
+ enum aarch64_opcodes opcode,
+ struct aarch64_register rs,
+ struct aarch64_register rt,
+ struct aarch64_register rt2,
+ struct aarch64_register rn)
+{
+ return emit_insn (buf, opcode | ENCODE (size, 2, 30)
+ | ENCODE (rs.num, 5, 16) | ENCODE (rt2.num, 5, 10)
+ | ENCODE (rn.num, 5, 5) | ENCODE (rt.num, 5, 0));
+}
+
+/* Write a LAXR instruction into *BUF.
+
+ LDAXR rt, [xn]
+
+ RT is the destination register.
+ RN is the base address register. */
+
+static int
+emit_ldaxr (uint32_t *buf, struct aarch64_register rt,
+ struct aarch64_register rn)
+{
+ return emit_load_store_exclusive (buf, rt.is64 ? 3 : 2, LDAXR, xzr, rt,
+ xzr, rn);
+}
+
+/* Write a STXR instruction into *BUF.
+
+ STXR ws, rt, [xn]
+
+ RS is the result register, it indicates if the store succeeded or not.
+ RT is the destination register.
+ RN is the base address register. */
+
+static int
+emit_stxr (uint32_t *buf, struct aarch64_register rs,
+ struct aarch64_register rt, struct aarch64_register rn)
+{
+ return emit_load_store_exclusive (buf, rt.is64 ? 3 : 2, STXR, rs, rt,
+ xzr, rn);
+}
+
+/* Write a STLR instruction into *BUF.
+
+ STLR rt, [xn]
+
+ RT is the register to store.
+ RN is the base address register. */
+
+static int
+emit_stlr (uint32_t *buf, struct aarch64_register rt,
+ struct aarch64_register rn)
+{
+ return emit_load_store_exclusive (buf, rt.is64 ? 3 : 2, STLR, xzr, rt,
+ xzr, rn);
+}
+
+/* Helper function for data processing instructions with register sources. */
+
+static int
+emit_data_processing_reg (uint32_t *buf, enum aarch64_opcodes opcode,
+ struct aarch64_register rd,
+ struct aarch64_register rn,
+ struct aarch64_register rm)
+{
+ uint32_t size = ENCODE (rd.is64, 1, 31);
+
+ return emit_insn (buf, opcode | size | ENCODE (rm.num, 5, 16)
+ | ENCODE (rn.num, 5, 5) | ENCODE (rd.num, 5, 0));
+}
+
+/* Helper function for data processing instructions taking either a register
+ or an immediate. */
+
+static int
+emit_data_processing (uint32_t *buf, enum aarch64_opcodes opcode,
+ struct aarch64_register rd,
+ struct aarch64_register rn,
+ struct aarch64_operand operand)
+{
+ uint32_t size = ENCODE (rd.is64, 1, 31);
+ /* The opcode is different for register and immediate source operands. */
+ uint32_t operand_opcode;
+
+ if (operand.type == OPERAND_IMMEDIATE)
+ {
+ /* xxx1 000x xxxx xxxx xxxx xxxx xxxx xxxx */
+ operand_opcode = ENCODE (8, 4, 25);
+
+ return emit_insn (buf, opcode | operand_opcode | size
+ | ENCODE (operand.imm, 12, 10)
+ | ENCODE (rn.num, 5, 5) | ENCODE (rd.num, 5, 0));
+ }
+ else
+ {
+ /* xxx0 101x xxxx xxxx xxxx xxxx xxxx xxxx */
+ operand_opcode = ENCODE (5, 4, 25);
+
+ return emit_data_processing_reg (buf, opcode | operand_opcode, rd,
+ rn, operand.reg);
+ }
+}
+
+/* Write an ADD instruction into *BUF.
+
+ ADD rd, rn, #imm
+ ADD rd, rn, rm
+
+ This function handles both an immediate and register add.
+
+ RD is the destination register.
+ RN is the input register.
+ OPERAND is the source operand, either of type OPERAND_IMMEDIATE or
+ OPERAND_REGISTER. */
+
+static int
+emit_add (uint32_t *buf, struct aarch64_register rd,
+ struct aarch64_register rn, struct aarch64_operand operand)
+{
+ return emit_data_processing (buf, ADD, rd, rn, operand);
+}
+
+/* Write a SUB instruction into *BUF.
+
+ SUB rd, rn, #imm
+ SUB rd, rn, rm
+
+ This function handles both an immediate and register sub.
+
+ RD is the destination register.
+ RN is the input register.
+ IMM is the immediate to substract to RN. */
+
+static int
+emit_sub (uint32_t *buf, struct aarch64_register rd,
+ struct aarch64_register rn, struct aarch64_operand operand)
+{
+ return emit_data_processing (buf, SUB, rd, rn, operand);
+}
+
+/* Write a MOV instruction into *BUF.
+
+ MOV rd, #imm
+ MOV rd, rm
+
+ This function handles both a wide immediate move and a register move,
+ with the condition that the source register is not xzr. xzr and the
+ stack pointer share the same encoding and this function only supports
+ the stack pointer.
+
+ RD is the destination register.
+ OPERAND is the source operand, either of type OPERAND_IMMEDIATE or
+ OPERAND_REGISTER. */
+
+static int
+emit_mov (uint32_t *buf, struct aarch64_register rd,
+ struct aarch64_operand operand)
+{
+ if (operand.type == OPERAND_IMMEDIATE)
+ {
+ uint32_t size = ENCODE (rd.is64, 1, 31);
+ /* Do not shift the immediate. */
+ uint32_t shift = ENCODE (0, 2, 21);
+
+ return emit_insn (buf, MOV | size | shift
+ | ENCODE (operand.imm, 16, 5)
+ | ENCODE (rd.num, 5, 0));
+ }
+ else
+ return emit_add (buf, rd, operand.reg, immediate_operand (0));
+}
+
+/* Write a MOVK instruction into *BUF.
+
+ MOVK rd, #imm, lsl #shift
+
+ RD is the destination register.
+ IMM is the immediate.
+ SHIFT is the logical shift left to apply to IMM. */
+
+static int
+emit_movk (uint32_t *buf, struct aarch64_register rd, uint32_t imm, unsigned shift)
+{
+ uint32_t size = ENCODE (rd.is64, 1, 31);
+
+ return emit_insn (buf, MOVK | size | ENCODE (shift, 2, 21) |
+ ENCODE (imm, 16, 5) | ENCODE (rd.num, 5, 0));
+}
+
+/* Write instructions into *BUF in order to move ADDR into a register.
+ ADDR can be a 64-bit value.
+
+ This function will emit a series of MOV and MOVK instructions, such as:
+
+ MOV xd, #(addr)
+ MOVK xd, #(addr >> 16), lsl #16
+ MOVK xd, #(addr >> 32), lsl #32
+ MOVK xd, #(addr >> 48), lsl #48 */
+
+static int
+emit_mov_addr (uint32_t *buf, struct aarch64_register rd, CORE_ADDR addr)
+{
+ uint32_t *p = buf;
+
+ /* The MOV (wide immediate) instruction clears to top bits of the
+ register. */
+ p += emit_mov (p, rd, immediate_operand (addr & 0xffff));
+
+ if ((addr >> 16) != 0)
+ p += emit_movk (p, rd, (addr >> 16) & 0xffff, 1);
+ else
+ return p - buf;
+
+ if ((addr >> 32) != 0)
+ p += emit_movk (p, rd, (addr >> 32) & 0xffff, 2);
+ else
+ return p - buf;
+
+ if ((addr >> 48) != 0)
+ p += emit_movk (p, rd, (addr >> 48) & 0xffff, 3);
+
+ return p - buf;
+}
+
+/* Write a MRS instruction into *BUF. The register size is 64-bit.
+
+ MRS xt, system_reg
+
+ RT is the destination register.
+ SYSTEM_REG is special purpose register to read. */
+
+static int
+emit_mrs (uint32_t *buf, struct aarch64_register rt,
+ enum aarch64_system_control_registers system_reg)
+{
+ return emit_insn (buf, MRS | ENCODE (system_reg, 15, 5)
+ | ENCODE (rt.num, 5, 0));
+}
+
+/* Write a MSR instruction into *BUF. The register size is 64-bit.
+
+ MSR system_reg, xt
+
+ SYSTEM_REG is special purpose register to write.
+ RT is the input register. */
+
+static int
+emit_msr (uint32_t *buf, enum aarch64_system_control_registers system_reg,
+ struct aarch64_register rt)
+{
+ return emit_insn (buf, MSR | ENCODE (system_reg, 15, 5)
+ | ENCODE (rt.num, 5, 0));
+}
+
+/* Write a SEVL instruction into *BUF.
+
+ This is a hint instruction telling the hardware to trigger an event. */
+
+static int
+emit_sevl (uint32_t *buf)
+{
+ return emit_insn (buf, SEVL);
+}
+
+/* Write a WFE instruction into *BUF.
+
+ This is a hint instruction telling the hardware to wait for an event. */
+
+static int
+emit_wfe (uint32_t *buf)
+{
+ return emit_insn (buf, WFE);
+}
+
+/* Write LEN instructions from BUF into the inferior memory at *TO.
+
+ Note instructions are always little endian on AArch64, unlike data. */
+
+static void
+append_insns (CORE_ADDR *to, size_t len, const uint32_t *buf)
+{
+ size_t byte_len = len * sizeof (uint32_t);
+#if (__BYTE_ORDER == __BIG_ENDIAN)
+ uint32_t *le_buf = xmalloc (byte_len);
+ size_t i;
+
+ for (i = 0; i < len; i++)
+ le_buf[i] = htole32 (buf[i]);
+
+ write_inferior_memory (*to, (const unsigned char *) le_buf, byte_len);
+
+ xfree (le_buf);
+#else
+ write_inferior_memory (*to, (const unsigned char *) buf, byte_len);
+#endif
+
+ *to += byte_len;
+}
+
+/* Helper function. Return 1 if VAL can be encoded in BITS bits. */
+
+static int
+can_encode_int32 (int32_t val, unsigned bits)
+{
+ /* This must be an arithemic shift. */
+ int32_t rest = val >> bits;
+
+ return rest == 0 || rest == -1;
+}
+
+/* Relocate an instruction from OLDLOC to *TO. This function will also
+ increment TO by the number of bytes the new instruction(s) take(s).
+
+ PC relative instructions need to be handled specifically:
+
+ - B/BL
+ - B.COND
+ - CBZ/CBNZ
+ - TBZ/TBNZ
+ - ADR/ADRP
+ - LDR/LDRSW (literal) */
+
+static void
+aarch64_relocate_instruction (CORE_ADDR *to, CORE_ADDR oldloc)
+{
+ uint32_t buf[32];
+ uint32_t *p = buf;
+ uint32_t insn;
+
+ int is_bl;
+ int is64;
+ int is_sw;
+ int is_cbnz;
+ int is_tbnz;
+ int is_adrp;
+ unsigned rn;
+ unsigned rt;
+ unsigned rd;
+ unsigned cond;
+ unsigned bit;
+ int32_t offset;
+
+ target_read_uint32 (oldloc, &insn);
+
+ if (aarch64_decode_b (oldloc, insn, &is_bl, &offset))
+ {
+ offset = (oldloc - *to + offset);
+
+ if (can_encode_int32 (offset, 28))
+ p += emit_b (p, is_bl, offset);
+ else
+ return;
+ }
+ else if (aarch64_decode_bcond (oldloc, insn, &cond, &offset))
+ {
+ offset = (oldloc - *to + offset);
+
+ if (can_encode_int32 (offset, 21))
+ p += emit_bcond (p, cond, offset);
+ else if (can_encode_int32 (offset, 28))
+ {
+ /* The offset is out of range for a conditional branch
+ instruction but not for a unconditional branch. We can use
+ the following instructions instead:
+
+ B.COND TAKEN ; If cond is true, then jump to TAKEN.
+ B NOT_TAKEN ; Else jump over TAKEN and continue.
+ TAKEN:
+ B #(offset - 8)
+ NOT_TAKEN:
+
+ */
+
+ p += emit_bcond (p, cond, 8);
+ p += emit_b (p, 0, 8);
+ p += emit_b (p, 0, offset - 8);
+ }
+ else
+ return;
+ }
+ else if (aarch64_decode_cb (oldloc, insn, &is64, &is_cbnz, &rn, &offset))
+ {
+ offset = (oldloc - *to + offset);
+
+ if (can_encode_int32 (offset, 21))
+ p += emit_cb (p, is_cbnz, aarch64_register (rn, is64), offset);
+ else if (can_encode_int32 (offset, 28))
+ {
+ /* The offset is out of range for a compare and branch
+ instruction but not for a unconditional branch. We can use
+ the following instructions instead:
+
+ CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
+ B NOT_TAKEN ; Else jump over TAKEN and continue.
+ TAKEN:
+ B #(offset - 8)
+ NOT_TAKEN:
+
+ */
+ p += emit_cb (p, is_cbnz, aarch64_register (rn, is64), 8);
+ p += emit_b (p, 0, 8);
+ p += emit_b (p, 0, offset - 8);
+ }
+ else
+ return;
+ }
+ else if (aarch64_decode_tb (oldloc, insn, &is_tbnz, &bit, &rt, &offset))
+ {
+ offset = (oldloc - *to + offset);
+
+ if (can_encode_int32 (offset, 16))
+ p += emit_tb (p, is_tbnz, bit, aarch64_register (rt, 1), offset);
+ else if (can_encode_int32 (offset, 28))
+ {
+ /* The offset is out of range for a test bit and branch
+ instruction but not for a unconditional branch. We can use
+ the following instructions instead:
+
+ TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
+ B NOT_TAKEN ; Else jump over TAKEN and continue.
+ TAKEN:
+ B #(offset - 8)
+ NOT_TAKEN:
+
+ */
+ p += emit_tb (p, is_tbnz, bit, aarch64_register (rt, 1), 8);
+ p += emit_b (p, 0, 8);
+ p += emit_b (p, 0, offset - 8);
+ }
+ else
+ return;
+ }
+ else if (aarch64_decode_adr (oldloc, insn, &is_adrp, &rd, &offset))
+ {
+
+ /* We know exactly the address the ADR{P,} instruction will compute.
+ We can just write it to the destination register. */
+ CORE_ADDR address = oldloc + offset;
+
+ if (is_adrp)
+ {
+ /* Clear the lower 12 bits of the offset to get the 4K page. */
+ p += emit_mov_addr (p, aarch64_register (rd, 1),
+ address & ~0xfff);
+ }
+ else
+ p += emit_mov_addr (p, aarch64_register (rd, 1), address);
+ }
+ else if (aarch64_decode_ldr_literal (oldloc, insn, &is_sw, &is64, &rt,
+ &offset))
+ {
+ /* We know exactly what address to load from, and what register we
+ can use:
+
+ MOV xd, #(oldloc + offset)
+ MOVK xd, #((oldloc + offset) >> 16), lsl #16
+ ...
+
+ LDR xd, [xd] ; or LDRSW xd, [xd]
+
+ */
+ CORE_ADDR address = oldloc + offset;
+
+ p += emit_mov_addr (p, aarch64_register (rt, 1), address);
+
+ if (is_sw)
+ p += emit_ldrsw (p, aarch64_register (rt, 1),
+ aarch64_register (rt, 1),
+ offset_memory_operand (0));
+ else
+ p += emit_ldr (p, aarch64_register (rt, is64),
+ aarch64_register (rt, 1),
+ offset_memory_operand (0));
+ }
+ else
+ {
+ /* The instruction is not PC relative. Just re-emit it at the new
+ location. */
+ p += emit_insn (p, insn);
+ }
+
+ append_insns (to, p - buf, buf);
+}
+
+/* Implementation of linux_target_ops method
+ "install_fast_tracepoint_jump_pad". */
+
+static int
+aarch64_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint,
+ CORE_ADDR tpaddr,
+ CORE_ADDR collector,
+ CORE_ADDR lockaddr,
+ ULONGEST orig_size,
+ CORE_ADDR *jump_entry,
+ CORE_ADDR *trampoline,
+ ULONGEST *trampoline_size,
+ unsigned char *jjump_pad_insn,
+ ULONGEST *jjump_pad_insn_size,
+ CORE_ADDR *adjusted_insn_addr,
+ CORE_ADDR *adjusted_insn_addr_end,
+ char *err)
+{
+ uint32_t buf[256];
+ uint32_t *p = buf;
+ int32_t offset;
+ int i;
+ CORE_ADDR buildaddr = *jump_entry;
+
+ /* We need to save the current state on the stack both to restore it
+ later and to collect register values when the tracepoint is hit.
+
+ The saved registers are pushed in a layout that needs to be in sync
+ with aarch64_ft_collect_regmap (see linux-aarch64-ipa.c). Later on
+ the supply_fast_tracepoint_registers function will fill in the
+ register cache from a pointer to saved registers on the stack we build
+ here.
+
+ For simplicity, we set the size of each cell on the stack to 16 bytes.
+ This way one cell can hold any register type, from system registers
+ to the 128 bit SIMD&FP registers. Furthermore, the stack pointer
+ has to be 16 bytes aligned anyway.
+
+ Note that the CPSR register does not exist on AArch64. Instead we
+ can access system bits describing the process state with the
+ MRS/MSR instructions, namely the condition flags. We save them as
+ if they are part of a CPSR register because that's how GDB
+ interprets these system bits. At the moment, only the condition
+ flags are saved in CPSR (NZCV).
+
+ Stack layout, each cell is 16 bytes (descending):
+
+ High *-------- SIMD&FP registers from 31 down to 0. --------*
+ | q31 |
+ . .
+ . . 32 cells
+ . .
+ | q0 |
+ *---- General purpose registers from 30 down to 0. ----*
+ | x30 |
+ . .
+ . . 31 cells
+ . .
+ | x0 |
+ *------------- Special purpose registers. -------------*
+ | SP |
+ | PC |
+ | CPSR (NZCV) | 5 cells
+ | FPSR |
+ | FPCR | <- SP + 16
+ *------------- collecting_t object --------------------*
+ | TPIDR_EL0 | struct tracepoint * |
+ Low *------------------------------------------------------*
+
+ After this stack is set up, we issue a call to the collector, passing
+ it the saved registers at (SP + 16). */
+
+ /* Push SIMD&FP registers on the stack:
+
+ SUB sp, sp, #(32 * 16)
+
+ STP q30, q31, [sp, #(30 * 16)]
+ ...
+ STP q0, q1, [sp]
+
+ */
+ p += emit_sub (p, sp, sp, immediate_operand (32 * 16));
+ for (i = 30; i >= 0; i -= 2)
+ p += emit_stp_q_offset (p, i, i + 1, sp, i * 16);
+
+ /* Push general puspose registers on the stack. Note that we do not need
+ to push x31 as it represents the xzr register and not the stack
+ pointer in a STR instruction.
+
+ SUB sp, sp, #(31 * 16)
+
+ STR x30, [sp, #(30 * 16)]
+ ...
+ STR x0, [sp]
+
+ */
+ p += emit_sub (p, sp, sp, immediate_operand (31 * 16));
+ for (i = 30; i >= 0; i -= 1)
+ p += emit_str (p, aarch64_register (i, 1), sp,
+ offset_memory_operand (i * 16));
+
+ /* Make space for 5 more cells.
+
+ SUB sp, sp, #(5 * 16)
+
+ */
+ p += emit_sub (p, sp, sp, immediate_operand (5 * 16));
+
+
+ /* Save SP:
+
+ ADD x4, sp, #((32 + 31 + 5) * 16)
+ STR x4, [sp, #(4 * 16)]
+
+ */
+ p += emit_add (p, x4, sp, immediate_operand ((32 + 31 + 5) * 16));
+ p += emit_str (p, x4, sp, offset_memory_operand (4 * 16));
+
+ /* Save PC (tracepoint address):
+
+ MOV x3, #(tpaddr)
+ ...
+
+ STR x3, [sp, #(3 * 16)]
+
+ */
+
+ p += emit_mov_addr (p, x3, tpaddr);
+ p += emit_str (p, x3, sp, offset_memory_operand (3 * 16));
+
+ /* Save CPSR (NZCV), FPSR and FPCR:
+
+ MRS x2, nzcv
+ MRS x1, fpsr
+ MRS x0, fpcr
+
+ STR x2, [sp, #(2 * 16)]
+ STR x1, [sp, #(1 * 16)]
+ STR x0, [sp, #(0 * 16)]
+
+ */
+ p += emit_mrs (p, x2, NZCV);
+ p += emit_mrs (p, x1, FPSR);
+ p += emit_mrs (p, x0, FPCR);
+ p += emit_str (p, x2, sp, offset_memory_operand (2 * 16));
+ p += emit_str (p, x1, sp, offset_memory_operand (1 * 16));
+ p += emit_str (p, x0, sp, offset_memory_operand (0 * 16));
+
+ /* Push the collecting_t object. It consist of the address of the
+ tracepoint and an ID for the current thread. We get the latter by
+ reading the tpidr_el0 system register. It corresponds to the
+ NT_ARM_TLS register accessible with ptrace.
+
+ MOV x0, #(tpoint)
+ ...
+
+ MRS x1, tpidr_el0
+
+ STP x0, x1, [sp, #-16]!
+
+ */
+
+ p += emit_mov_addr (p, x0, tpoint);
+ p += emit_mrs (p, x1, TPIDR_EL0);
+ p += emit_stp (p, x0, x1, sp, preindex_memory_operand (-16));
+
+ /* Spin-lock:
+
+ The shared memory for the lock is at lockaddr. It will hold zero
+ if no-one is holding the lock, otherwise it contains the address of
+ the collecting_t object on the stack of the thread which acquired it.
+
+ At this stage, the stack pointer points to this thread's collecting_t
+ object.
+
+ We use the following registers:
+ - x0: Address of the lock.
+ - x1: Pointer to collecting_t object.
+ - x2: Scratch register.
+
+ MOV x0, #(lockaddr)
+ ...
+ MOV x1, sp
+
+ ; Trigger an event local to this core. So the following WFE
+ ; instruction is ignored.
+ SEVL
+ again:
+ ; Wait for an event. The event is triggered by either the SEVL
+ ; or STLR instructions (store release).
+ WFE
+
+ ; Atomically read at lockaddr. This marks the memory location as
+ ; exclusive. This instruction also has memory constraints which
+ ; make sure all previous data reads and writes are done before
+ ; executing it.
+ LDAXR x2, [x0]
+
+ ; Try again if another thread holds the lock.
+ CBNZ x2, again
+
+ ; We can lock it! Write the address of the collecting_t object.
+ ; This instruction will fail if the memory location is not marked
+ ; as exclusive anymore. If it succeeds, it will remove the
+ ; exclusive mark on the memory location. This way, if another
+ ; thread executes this instruction before us, we will fail and try
+ ; all over again.
+ STXR w2, x1, [x0]
+ CBNZ w2, again
+
+ */
+
+ p += emit_mov_addr (p, x0, lockaddr);
+ p += emit_mov (p, x1, register_operand (sp));
+
+ p += emit_sevl (p);
+ p += emit_wfe (p);
+ p += emit_ldaxr (p, x2, x0);
+ p += emit_cb (p, 1, w2, -2 * 4);
+ p += emit_stxr (p, w2, x1, x0);
+ p += emit_cb (p, 1, x2, -4 * 4);
+
+ /* Call collector (struct tracepoint *, unsigned char *):
+
+ MOV x0, #(tpoint)
+ ...
+
+ ; Saved registers start after the collecting_t object.
+ ADD x1, sp, #16
+
+ ; We use an intra-procedure-call scratch register.
+ MOV ip0, #(collector)
+ ...
+
+ ; And call back to C!
+ BLR ip0
+
+ */
+
+ p += emit_mov_addr (p, x0, tpoint);
+ p += emit_add (p, x1, sp, immediate_operand (16));
+
+ p += emit_mov_addr (p, ip0, collector);
+ p += emit_blr (p, ip0);
+
+ /* Release the lock.
+
+ MOV x0, #(lockaddr)
+ ...
+
+ ; This instruction is a normal store with memory ordering
+ ; constraints. Thanks to this we do not have to put a data
+ ; barrier instruction to make sure all data read and writes are done
+ ; before this instruction is executed. Furthermore, this instrucion
+ ; will trigger an event, letting other threads know they can grab
+ ; the lock.
+ STLR xzr, [x0]
+
+ */
+ p += emit_mov_addr (p, x0, lockaddr);
+ p += emit_stlr (p, xzr, x0);
+
+ /* Free collecting_t object:
+
+ ADD sp, sp, #16
+
+ */
+ p += emit_add (p, sp, sp, immediate_operand (16));
+
+ /* Restore CPSR (NZCV), FPSR and FPCR. And free all special purpose
+ registers from the stack.
+
+ LDR x2, [sp, #(2 * 16)]
+ LDR x1, [sp, #(1 * 16)]
+ LDR x0, [sp, #(0 * 16)]
+
+ MSR NZCV, x2
+ MSR FPSR, x1
+ MSR FPCR, x0
+
+ ADD sp, sp #(5 * 16)
+
+ */
+ p += emit_ldr (p, x2, sp, offset_memory_operand (2 * 16));
+ p += emit_ldr (p, x1, sp, offset_memory_operand (1 * 16));
+ p += emit_ldr (p, x0, sp, offset_memory_operand (0 * 16));
+ p += emit_msr (p, NZCV, x2);
+ p += emit_msr (p, FPSR, x1);
+ p += emit_msr (p, FPCR, x0);
+
+ p += emit_add (p, sp, sp, immediate_operand (5 * 16));
+
+ /* Pop general purpose registers:
+
+ LDR x0, [sp]
+ ...
+ LDR x30, [sp, #(30 * 16)]
+
+ ADD sp, sp, #(31 * 16)
+
+ */
+ for (i = 0; i <= 30; i += 1)
+ p += emit_ldr (p, aarch64_register (i, 1), sp,
+ offset_memory_operand (i * 16));
+ p += emit_add (p, sp, sp, immediate_operand (31 * 16));
+
+ /* Pop SIMD&FP registers:
+
+ LDP q0, q1, [sp]
+ ...
+ LDP q30, q31, [sp, #(30 * 16)]
+
+ ADD sp, sp, #(32 * 16)
+
+ */
+ for (i = 0; i <= 30; i += 2)
+ p += emit_ldp_q_offset (p, i, i + 1, sp, i * 16);
+ p += emit_add (p, sp, sp, immediate_operand (32 * 16));
+
+ /* Write the code into the inferior memory. */
+ append_insns (&buildaddr, p - buf, buf);
+
+ /* Now emit the relocated instruction. */
+ *adjusted_insn_addr = buildaddr;
+ aarch64_relocate_instruction (&buildaddr, tpaddr);
+ *adjusted_insn_addr_end = buildaddr;
+
+ /* We may not have been able to relocate the instruction. */
+ if (*adjusted_insn_addr == *adjusted_insn_addr_end)
+ {
+ sprintf (err,
+ "E.Could not relocate instruction from %s to %s.",
+ core_addr_to_string_nz (tpaddr),
+ core_addr_to_string_nz (buildaddr));
+ return 1;
+ }
+
+ /* Go back to the start of the buffer. */
+ p = buf;
+
+ /* Emit a branch back from the jump pad. */
+ offset = (tpaddr + orig_size - buildaddr);
+ if (!can_encode_int32 (offset, 28))
+ {
+ sprintf (err,
+ "E.Jump back from jump pad too far from tracepoint "
+ "(offset 0x%" PRIx32 " cannot be encoded in 28 bits).",
+ offset);
+ return 1;
+ }
+
+ p += emit_b (p, 0, offset);
+ append_insns (&buildaddr, p - buf, buf);
+
+ /* Give the caller a branch instruction into the jump pad. */
+ offset = (*jump_entry - tpaddr);
+ if (!can_encode_int32 (offset, 28))
+ {
+ sprintf (err,
+ "E.Jump pad too far from tracepoint "
+ "(offset 0x%" PRIx32 " cannot be encoded in 28 bits).",
+ offset);
+ return 1;
+ }
+
+ emit_b ((uint32_t *) jjump_pad_insn, 0, offset);
+ *jjump_pad_insn_size = 4;
+
+ /* Return the end address of our pad. */
+ *jump_entry = buildaddr;
+
+ return 0;
+}
+
+/* Implementation of linux_target_ops method
+ "get_min_fast_tracepoint_insn_len". */
+
+static int
+aarch64_get_min_fast_tracepoint_insn_len (void)
+{
+ return 4;
+}
+
/* Implementation of linux_target_ops method "supports_range_stepping". */
static int
@@ -609,10 +2069,10 @@ struct linux_target_ops the_low_target =
aarch64_linux_prepare_to_resume,
NULL, /* process_qsupported */
aarch64_supports_tracepoints,
- NULL, /* get_thread_area */
- NULL, /* install_fast_tracepoint_jump_pad */
+ aarch64_get_thread_area,
+ aarch64_install_fast_tracepoint_jump_pad,
NULL, /* emit_ops */
- NULL, /* get_min_fast_tracepoint_insn_len */
+ aarch64_get_min_fast_tracepoint_insn_len,
aarch64_supports_range_stepping,
};
--
1.9.1
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [PATCH 0/8 V2] [AArch64] Support fast tracepoints
2015-09-18 12:43 ` [PATCH 0/8 V2] [AArch64] Support fast tracepoints Yao Qi
` (7 preceding siblings ...)
2015-09-18 12:44 ` [PATCH 3/8] Add support for fast tracepoints Yao Qi
@ 2015-09-21 14:06 ` Yao Qi
8 siblings, 0 replies; 37+ messages in thread
From: Yao Qi @ 2015-09-21 14:06 UTC (permalink / raw)
To: Yao Qi; +Cc: gdb-patches
Yao Qi <qiyaoltc@gmail.com> writes:
> Hi,
> Here is the V2 of aarch64 fast tracepoint support. V1 can be found
> https://sourceware.org/ml/gdb-patches/2015-09/msg00274.html
>
> Some changes in V2:
>
> - Implement gdb_agent_get_raw_reg for aarch64,
> - Pass argument regs to gdb_agent_get_reg instead of
> fast_tracepoint_ctx,
> - Move gdb.trace/ftrace-insn-reloc.c and gdb.trace/ftrace-insn-reloc.exp
> to gdb.arch, so that it can be reused for displaced stepping test,
> - Use with_timeout_factor in gdb.trace/ftrace-lock.exp,
> - Adjust one ChangeLog entry,
> - Include NEWS entry in V2,
>
> The whole series is tested on aarch64-linux with GDBserver.
I've pushed them in.
--
Yao (齐尧)
^ permalink raw reply [flat|nested] 37+ messages in thread