From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 70186 invoked by alias); 28 May 2018 22:18:36 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 70177 invoked by uid 89); 28 May 2018 22:18:35 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.4 required=5.0 tests=AWL,BAYES_00,SPF_HELO_PASS,SPF_PASS autolearn=ham version=3.3.2 spammy=wild X-HELO: smtp.polymtl.ca Received: from smtp.polymtl.ca (HELO smtp.polymtl.ca) (132.207.4.11) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 28 May 2018 22:18:33 +0000 Received: from simark.ca (simark.ca [158.69.221.121]) (authenticated bits=0) by smtp.polymtl.ca (8.14.7/8.14.7) with ESMTP id w4SMIRi7005075 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 28 May 2018 18:18:31 -0400 Received: by simark.ca (Postfix, from userid 112) id 193201F21C; Mon, 28 May 2018 18:18:27 -0400 (EDT) Received: from simark.ca (localhost [127.0.0.1]) by simark.ca (Postfix) with ESMTP id B2F471EF61; Mon, 28 May 2018 18:18:25 -0400 (EDT) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Tue, 29 May 2018 02:52:00 -0000 From: Simon Marchi To: Ulrich Weigand Cc: gdb-patches@sourceware.org, simon.marchi@ericsson.com Subject: Re: [RFC PATCH] Read pseudo registers from frame instead of regcache In-Reply-To: <13ad2ec8a2cd7b6393613e4728d70736@polymtl.ca> References: <20180528174715.A954AD804AD@oc3748833570.ibm.com> <13ad2ec8a2cd7b6393613e4728d70736@polymtl.ca> Message-ID: <145043fef77f5d64d115e5a83a5148b3@polymtl.ca> X-Sender: simon.marchi@polymtl.ca User-Agent: Roundcube Webmail/1.3.6 X-Poly-FromMTA: (simark.ca [158.69.221.121]) at Mon, 28 May 2018 22:18:27 +0000 X-IsSubscribed: yes X-SW-Source: 2018-05/txt/msg00748.txt.bz2 On 2018-05-28 15:13, Simon Marchi wrote: > Ok, I was assuming that it was never possible for the debug info to > describe how pseudo registers are saved, only raw registers. Do you > have an architecture in mind where it's possible to have a pseudo > register mentioned in the unwind information? GNU as doesn't accept > at all "ymm0" or "ymm0h" as an argument to .cfi_offset, so I don't > know how ymm0 would be represented if we wanted to save it (despite it > not being callee saved according to the ABI). I looked at ARMv7, and one case where this might happen is the VFP registers. The dX registers (64-bits) are the raw ones and the sX (32-bits) are the pseudo ones (where two sX registers make up one dX register). The GNU assembler accepts using s0 with .cfi_offset (for backwards compatibility, I guess?), so we end up with it in the unwind info. However, this is an obsolete way of doing it according to the "DWARF for the ARM Architecture" document [1]. They recommend to describe the sX registers as bit pieces of the dX registers. That recommendation would be in line with the "only raw registers in unwind info" assumption. But it means that we can encounter this in the wild. Simon [1] http://infocenter.arm.com/help/topic/com.arm.doc.ihi0040b/IHI0040B_aadwarf.pdf