From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 25256 invoked by alias); 22 Apr 2016 10:24:48 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 25218 invoked by uid 89); 22 Apr 2016 10:24:47 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 spammy=raz, RAZ, HX-Received:10.66.90.7, reserved X-HELO: mail-pa0-f50.google.com Received: from mail-pa0-f50.google.com (HELO mail-pa0-f50.google.com) (209.85.220.50) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Fri, 22 Apr 2016 10:24:37 +0000 Received: by mail-pa0-f50.google.com with SMTP id zm5so38697357pac.0 for ; Fri, 22 Apr 2016 03:24:37 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:subject:date:message-id; bh=Vsg1Wnh97bXCkoVpOtUIIBMan0DCowzknL7DB7qLlms=; b=Mlmb5Jy/G9Ehw20si1VFhL2V7TqbDBlMV7qeHWOAjPSM3F5ECjXXZE5W/8mPFidp5q ruK4rQV5zRbeR7wUeg8biQylfOJC2iF70yr6YrqXvVlvjkfr3nLXLst8/CdSHiZDnE1W puJQeE/xgop6d5j61q/wJrA1n9bIxZfFYx163rQhxOS6dMKcMwOlt2dn4EoAYxdrlMQG l18AJ9x+f7gl2IUzafQP6TqA/2u9SSjFliMU6eBEixyv+A4UB5OFwXlGif96w6DWWDUP o7uM+8/1aGxD0lhTp8a/qZy9i1WrK5+lXXR0w8bj8N44g4/e+kTS3i1NMtd/7ciK+I72 +aZw== X-Gm-Message-State: AOPr4FWuMVma3XMfDU0S1heD6Bg+GSaKr3xlyMfv8uaB9kyM8aTw43eSTTV4sp5W4tiE0g== X-Received: by 10.66.90.7 with SMTP id bs7mr27541295pab.118.1461320675695; Fri, 22 Apr 2016 03:24:35 -0700 (PDT) Received: from E107787-LIN.cambridge.arm.com (gcc1-power7.osuosl.org. [140.211.15.137]) by smtp.gmail.com with ESMTPSA id zu10sm8460605pab.31.2016.04.22.03.24.34 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 22 Apr 2016 03:24:34 -0700 (PDT) From: Yao Qi X-Google-Original-From: Yao Qi To: gdb-patches@sourceware.org Subject: [PATCH] [ARM] Clear reserved bits in CPSR Date: Fri, 22 Apr 2016 10:24:00 -0000 Message-Id: <1461320654-22274-1-git-send-email-yao.qi@linaro.org> X-IsSubscribed: yes X-SW-Source: 2016-04/txt/msg00512.txt.bz2 Bits 20 ~ 23 of CPSR are reserved (RAZ, read as zero), but they are not zero if the arm program runs on aarch64-linux. AArch64 tracer gets PSTATE from arm 32-bit tracee as CPSR, but bits 20 ~ 23 are used in PSTATE. I think kernel should clear these bits when it is read through ptrace, but the fix in user space is still needed. This patch fixes these two fails, -FAIL: gdb.reverse/insn-reverse.exp: ext_reg_push_pop: compare registers on insn 0:vldr d7, [r11, #-12] -FAIL: gdb.reverse/insn-reverse.exp: ext_reg_push_pop: compare registers on insn 0:vldr d7, [r7] Regression tested on both native and remote on aarch64-linux. gdb: 2016-04-22 Yao Qi * aarch32-linux-nat.c (aarch32_gp_regcache_supply): Clear CPSR bits 20 to 23. gdb/gdbserver: 2016-04-22 Yao Qi * linux-aarch32-low.c (arm_store_gregset): Clear CPSR bits 20 to 23. --- gdb/aarch32-linux-nat.c | 6 +++++- gdb/gdbserver/linux-aarch32-low.c | 5 ++++- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/gdb/aarch32-linux-nat.c b/gdb/aarch32-linux-nat.c index 568dfa6..97b319b 100644 --- a/gdb/aarch32-linux-nat.c +++ b/gdb/aarch32-linux-nat.c @@ -37,7 +37,11 @@ aarch32_gp_regcache_supply (struct regcache *regcache, uint32_t *regs, regcache_raw_supply (regcache, regno, ®s[regno]); if (arm_apcs_32) - regcache_raw_supply (regcache, ARM_PS_REGNUM, ®s[ARM_CPSR_GREGNUM]); + { + /* Clear reserved bits bit 20 to bit 23. */ + regs[ARM_CPSR_GREGNUM] = 0xff0fffff & regs[ARM_CPSR_GREGNUM]; + regcache_raw_supply (regcache, ARM_PS_REGNUM, ®s[ARM_CPSR_GREGNUM]); + } else regcache_raw_supply (regcache, ARM_PS_REGNUM, ®s[ARM_PC_REGNUM]); diff --git a/gdb/gdbserver/linux-aarch32-low.c b/gdb/gdbserver/linux-aarch32-low.c index 0c4b140..5087550 100644 --- a/gdb/gdbserver/linux-aarch32-low.c +++ b/gdb/gdbserver/linux-aarch32-low.c @@ -77,6 +77,7 @@ arm_store_gregset (struct regcache *regcache, const void *buf) int i; char zerobuf[8]; const uint32_t *regs = (const uint32_t *) buf; + uint32_t cpsr = regs[ARM_CPSR_GREGNUM]; memset (zerobuf, 0, 8); for (i = ARM_A1_REGNUM; i <= ARM_PC_REGNUM; i++) @@ -85,7 +86,9 @@ arm_store_gregset (struct regcache *regcache, const void *buf) for (; i < ARM_PS_REGNUM; i++) supply_register (regcache, i, zerobuf); - supply_register (regcache, ARM_PS_REGNUM, ®s[ARM_CPSR_GREGNUM]); + /* Clear reserved bits bit 20 to bit 23. */ + cpsr = 0xff0fffff & cpsr; + supply_register (regcache, ARM_PS_REGNUM, &cpsr); } /* Collect NUM number of VFP registers from REGCACHE to buffer BUF. */ -- 1.9.1