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From: Bhushan Attarde <bhushan.attarde@imgtec.com>
To: <gdb-patches@sourceware.org>
Cc: <Maciej.Rozycki@imgtec.com>, <Matthew.Fortune@imgtec.com>,
	<James.Hogan@imgtec.com>, <Andrew.Bennett@imgtec.com>,
	<Jaydeep.Patil@imgtec.com>,
	Bhushan Attarde <bhushan.attarde@imgtec.com>
Subject: [PATCH 20/24]     Drop FP and MSA control registers from default info registers
Date: Mon, 27 Jun 2016 14:51:00 -0000	[thread overview]
Message-ID: <1467038991-6600-20-git-send-email-bhushan.attarde@imgtec.com> (raw)
In-Reply-To: <1467038991-6600-1-git-send-email-bhushan.attarde@imgtec.com>

    gdb/ChangeLog:
        * mips-tdep.c (print_gp_register_row, mips_print_registers_info):
        Skip FP & MSA control registers.
---
 gdb/mips-tdep.c | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/gdb/mips-tdep.c b/gdb/mips-tdep.c
index 7a6d23d..14e3aa6 100644
--- a/gdb/mips-tdep.c
+++ b/gdb/mips-tdep.c
@@ -7650,6 +7650,9 @@ print_gp_register_row (struct ui_file *file, struct frame_info *frame,
       if (mips_float_register_p (gdbarch, regnum) ||
 	  mips_vector_register_p (gdbarch, regnum))
 	break;			/* End the row: reached FP register.  */
+      if (mips_register_reggroup_p (gdbarch, regnum, float_reggroup) ||
+	  mips_register_reggroup_p (gdbarch, regnum, vector_reggroup))
+	break;
       /* Large registers are handled separately.  */
       if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch))
 	{
@@ -7690,6 +7693,9 @@ print_gp_register_row (struct ui_file *file, struct frame_info *frame,
       if (mips_float_register_p (gdbarch, regnum) ||
 	  mips_vector_register_p (gdbarch, regnum))
 	break;			/* End row: reached FP register.  */
+      if (mips_register_reggroup_p (gdbarch, regnum, float_reggroup) ||
+	 mips_register_reggroup_p (gdbarch, regnum, vector_reggroup))
+	break;
       if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch))
 	break;			/* End row: large register.  */
 
@@ -7776,8 +7782,13 @@ mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
 	    }
 	  else if (mips_register_reggroup_p (gdbarch, regnum, float_reggroup) ||
 		   mips_register_reggroup_p (gdbarch, regnum, vector_reggroup))
-	    /* FP & MSA control registers */
-	    regnum = print_control_register_row (file, frame, regnum);
+	    {
+	      /* FP & MSA control registers */
+	      if (all)		/* True for "INFO ALL-REGISTERS" command.  */
+		regnum = print_control_register_row (file, frame, regnum);
+	      else
+		++regnum;
+	    }
 	  else
 	    regnum = print_gp_register_row (file, frame, regnum);
 	}
-- 
1.9-rc2

  parent reply	other threads:[~2016-06-27 14:51 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-06-27 14:50 [PATCH 01/24] MIPS: Handle run-time reconfigurable FPR size Bhushan Attarde
2016-06-27 14:50 ` [PATCH 11/24] MIPS: Add support for hybrid fp32/fp64 mode Bhushan Attarde
2016-06-27 14:50 ` [PATCH 06/24] mips-linux-nat: pick fp64 target description when appropriate Bhushan Attarde
2016-06-27 14:50 ` [PATCH 08/24] MIPS: Convert FP mode to enum and put fp registers into fp reggroup Bhushan Attarde
2016-06-27 14:50 ` [PATCH 03/24] regcache: handle invalidated regcache Bhushan Attarde
2016-10-21 22:42   ` Maciej W. Rozycki
2016-06-27 14:50 ` [PATCH 10/24] MIPS: override fscr/fir types and print control registers specially Bhushan Attarde
2016-06-27 14:51 ` [PATCH 14/24] Implement core MSA stuff Bhushan Attarde
2016-06-27 14:51 ` [PATCH 13/24] Add MIPS MSA GDB target descriptions Bhushan Attarde
2016-06-27 14:51 ` [PATCH 21/24] MIPSR6 support for GDB Bhushan Attarde
2016-07-29 21:10   ` Maciej W. Rozycki
2016-06-27 14:51 ` [PATCH 12/24] o32 sigframe unwinding with FR1 Bhushan Attarde
2016-06-27 14:51 ` [PATCH 18/24] mips-linux-nat: get msa registers Bhushan Attarde
2016-06-27 14:51 ` [PATCH 19/24] Add MIPS MSA vector branch instruction support Bhushan Attarde
2016-06-27 14:51 ` [PATCH 05/24] MIPS: Add config5 to MIPS GDB target descriptions Bhushan Attarde
2016-06-27 14:51 ` [PATCH 07/24] MIPS: Make Linux restart register more dynamic Bhushan Attarde
2016-06-27 14:51 ` [PATCH 23/24] MIPS R6 opcode table shuffle for LDC2/SDC2 Bhushan Attarde
2016-06-27 14:51 ` [PATCH 02/24] Add MIPS32 FPU64 GDB target descriptions Bhushan Attarde
2016-10-12 12:42   ` Maciej W. Rozycki
2016-10-12 13:58     ` James Hogan
2016-10-12 16:30       ` Maciej W. Rozycki
2016-10-12 18:05         ` James Hogan
2016-10-12 22:04           ` Maciej W. Rozycki
2016-10-13 10:09             ` Matthew Fortune
2016-10-21 19:17               ` Maciej W. Rozycki
2016-10-21 19:24                 ` Maciej W. Rozycki
2016-06-27 14:51 ` [PATCH 09/24] MIPS: Enhance cooked FP format Bhushan Attarde
2016-06-27 14:51 ` [PATCH 24/24] MIPS R6 forbidden slot support Bhushan Attarde
2016-06-27 14:51 ` Bhushan Attarde [this message]
2016-06-27 14:51 ` [PATCH 04/24] Add MIPS Config5 register related support Bhushan Attarde
2016-06-27 14:51 ` [PATCH 22/24] Support all new ABIs when detecting if an FPU is present Bhushan Attarde
2016-07-25 14:03 ` [PATCH 01/24] MIPS: Handle run-time reconfigurable FPR size Maciej W. Rozycki
2016-10-18 17:37   ` Maciej W. Rozycki
2016-11-08 19:46 ` Yao Qi
2016-11-10 12:43   ` Maciej W. Rozycki
2016-11-11 12:29     ` Yao Qi
2016-12-02  2:31       ` Maciej W. Rozycki

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