* [PATCH 1/5] Fix spelling in comments in C source files (sim)
2016-11-25 19:46 [PATCH 0/5] Fix spelling mistakes in comments - SIM Ambrogino Modigliani
2016-11-25 19:46 ` [PATCH 4/5] Fix spelling in comments in .in files (sim) Ambrogino Modigliani
2016-11-25 19:46 ` [PATCH 3/5] Fix spelling in comments in .igen " Ambrogino Modigliani
@ 2016-11-25 19:46 ` Ambrogino Modigliani
2016-11-25 19:47 ` [PATCH 5/5] Fix spelling in comments in .inc " Ambrogino Modigliani
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Ambrogino Modigliani @ 2016-11-25 19:46 UTC (permalink / raw)
To: gdb-patches, pedro_alves, ambrogino.modigliani, ambrogino.modigliani
sim/aarch64/ChangeLog:
* memory.c: Fix spelling in comments.
* simulator.c: Fix spelling in comments.
sim/arm/ChangeLog:
* armcopro.c: Fix spelling in comments.
* armemu.c: Fix spelling in comments.
* iwmmxt.c: Fix spelling in comments.
sim/bfin/ChangeLog:
* devices.h: Fix spelling in comments.
* dv-bfin_cec.c: Fix spelling in comments.
sim/common/ChangeLog:
* dv-glue.c: Fix spelling in comments.
* dv-pal.c: Fix spelling in comments.
* hw-base.h: Fix spelling in comments.
* hw-device.h: Fix spelling in comments.
* hw-instances.h: Fix spelling in comments.
* hw-ports.c: Fix spelling in comments.
* hw-tree.c: Fix spelling in comments.
* sim-alu.h: Fix spelling in comments.
* sim-arange.h: Fix spelling in comments.
* sim-basics.h: Fix spelling in comments.
* sim-bits.h: Fix spelling in comments.
* sim-config.h: Fix spelling in comments.
* sim-core.h: Fix spelling in comments.
* sim-engine.h: Fix spelling in comments.
* sim-events.h: Fix spelling in comments.
* sim-inline.h: Fix spelling in comments.
* sim-io.h: Fix spelling in comments.
* sim-resume.h: Fix spelling in comments.
sim/d10v/ChangeLog:
* interp.c: Fix spelling in comments.
sim/erc32/ChangeLog:
* exec.c: Fix spelling in comments.
* float.c: Fix spelling in comments.
* sis.h: Fix spelling in comments.
sim/frv/ChangeLog:
* frv-sim.h: Fix spelling in comments.
* interrupts.c: Fix spelling in comments.
* profile.c: Fix spelling in comments.
* registers.c: Fix spelling in comments.
* traps.c: Fix spelling in comments.
sim/h8300/ChangeLog:
* compile.c: Fix spelling in comments.
sim/igen/ChangeLog:
* gen-engine.c: Fix spelling in comments.
* gen-icache.c: Fix spelling in comments.
* gen-idecode.c: Fix spelling in comments.
* gen-semantics.c: Fix spelling in comments.
* gen-semantics.h: Fix spelling in comments.
* gen.c: Fix spelling in comments.
* igen.c: Fix spelling in comments.
* igen.h: Fix spelling in comments.
* ld-decode.h: Fix spelling in comments.
* ld-insn.c: Fix spelling in comments.
* lf.h: Fix spelling in comments.
sim/lm32/ChangeLog:
* dv-lm32uart.c: Fix spelling in comments.
sim/m32r/ChangeLog:
* dv-m32r_uart.h: Fix spelling in comments.
sim/m68hc11/ChangeLog:
* dv-m68hc11sio.c: Fix spelling in comments.
* dv-m68hc11spi.c: Fix spelling in comments.
* dv-m68hc11tim.c: Fix spelling in comments.
sim/mips/ChangeLog:
* sim-main.h: Fix spelling in comments.
sim/mn10300/ChangeLog:
* interp.c: Fix spelling in comments.
sim/ppc/ChangeLog:
* altivec_registers.h: Fix spelling in comments.
* basics.h: Fix spelling in comments.
* bits.h: Fix spelling in comments.
* corefile.h: Fix spelling in comments.
* cpu.c: Fix spelling in comments.
* cpu.h: Fix spelling in comments.
* device.h: Fix spelling in comments.
* emul_bugapi.c: Fix spelling in comments.
* emul_chirp.h: Fix spelling in comments.
* emul_unix.c: Fix spelling in comments.
* events.c: Fix spelling in comments.
* gen-icache.c: Fix spelling in comments.
* gen-idecode.c: Fix spelling in comments.
* gen-semantics.h: Fix spelling in comments.
* hw_cpu.c: Fix spelling in comments.
* hw_eeprom.c: Fix spelling in comments.
* hw_glue.c: Fix spelling in comments.
* hw_ide.c: Fix spelling in comments.
* hw_init.c: Fix spelling in comments.
* hw_opic.c: Fix spelling in comments.
* hw_pal.c: Fix spelling in comments.
* hw_phb.c: Fix spelling in comments.
* hw_trace.c: Fix spelling in comments.
* idecode_expression.h: Fix spelling in comments.
* igen.h: Fix spelling in comments.
* interrupts.h: Fix spelling in comments.
* ld-decode.h: Fix spelling in comments.
* main.c: Fix spelling in comments.
* os_emul.h: Fix spelling in comments.
* psim.c: Fix spelling in comments.
* sim-endian.h: Fix spelling in comments.
* sim_calls.c: Fix spelling in comments.
* std-config.h: Fix spelling in comments.
* tree.c: Fix spelling in comments.
* tree.h: Fix spelling in comments.
* vm.c: Fix spelling in comments.
* vm.h: Fix spelling in comments.
sim/sh/ChangeLog:
* interp.c: Fix spelling in comments.
* sim-main.h: Fix spelling in comments.
sim/v850/ChangeLog:
* sim-main.h: Fix spelling in comments.
* simops.c: Fix spelling in comments.
---
sim/aarch64/memory.c | 2 +-
sim/aarch64/simulator.c | 2 +-
sim/arm/armcopro.c | 6 +++---
sim/arm/armemu.c | 2 +-
sim/arm/iwmmxt.c | 2 +-
sim/bfin/devices.h | 2 +-
sim/bfin/dv-bfin_cec.c | 2 +-
sim/common/dv-glue.c | 4 ++--
sim/common/dv-pal.c | 8 ++++----
sim/common/hw-base.h | 2 +-
sim/common/hw-device.h | 2 +-
sim/common/hw-instances.h | 2 +-
sim/common/hw-ports.c | 2 +-
sim/common/hw-tree.c | 4 ++--
sim/common/sim-alu.h | 4 ++--
sim/common/sim-arange.c | 8 ++++----
sim/common/sim-basics.h | 2 +-
sim/common/sim-bits.h | 4 ++--
sim/common/sim-config.h | 4 ++--
sim/common/sim-core.h | 10 +++++-----
sim/common/sim-engine.h | 2 +-
sim/common/sim-events.h | 2 +-
sim/common/sim-inline.h | 2 +-
sim/common/sim-io.c | 2 +-
sim/common/sim-resume.c | 2 +-
sim/d10v/interp.c | 4 ++--
sim/erc32/exec.c | 2 +-
sim/erc32/float.c | 2 +-
sim/erc32/sis.h | 2 +-
sim/frv/frv-sim.h | 4 ++--
sim/frv/interrupts.c | 2 +-
sim/frv/profile.c | 4 ++--
sim/frv/registers.c | 4 ++--
sim/frv/traps.c | 2 +-
sim/h8300/compile.c | 2 +-
sim/igen/gen-engine.c | 4 ++--
sim/igen/gen-icache.c | 4 ++--
sim/igen/gen-idecode.c | 4 ++--
sim/igen/gen-semantics.c | 2 +-
sim/igen/gen-semantics.h | 6 +++---
sim/igen/gen.c | 6 +++---
sim/igen/igen.c | 2 +-
sim/igen/igen.h | 2 +-
sim/igen/ld-decode.h | 4 ++--
sim/igen/ld-insn.c | 8 ++++----
sim/igen/lf.h | 2 +-
sim/lm32/dv-lm32uart.c | 2 +-
sim/m32r/dv-m32r_uart.h | 2 +-
sim/m68hc11/dv-m68hc11sio.c | 2 +-
sim/m68hc11/dv-m68hc11spi.c | 2 +-
sim/m68hc11/dv-m68hc11tim.c | 2 +-
sim/mips/sim-main.h | 4 ++--
sim/mn10300/interp.c | 2 +-
sim/ppc/altivec_registers.h | 2 +-
sim/ppc/basics.h | 2 +-
sim/ppc/bits.h | 2 +-
sim/ppc/corefile.h | 10 +++++-----
sim/ppc/cpu.c | 2 +-
sim/ppc/cpu.h | 6 +++---
sim/ppc/device.h | 6 +++---
sim/ppc/emul_bugapi.c | 4 ++--
sim/ppc/emul_chirp.h | 2 +-
sim/ppc/emul_unix.c | 2 +-
sim/ppc/events.c | 4 ++--
sim/ppc/gen-icache.c | 6 +++---
sim/ppc/gen-idecode.c | 6 +++---
sim/ppc/gen-semantics.h | 6 +++---
sim/ppc/hw_cpu.c | 2 +-
sim/ppc/hw_eeprom.c | 4 ++--
sim/ppc/hw_glue.c | 4 ++--
sim/ppc/hw_ide.c | 6 +++---
sim/ppc/hw_init.c | 4 ++--
sim/ppc/hw_opic.c | 2 +-
sim/ppc/hw_pal.c | 2 +-
sim/ppc/hw_phb.c | 8 ++++----
sim/ppc/hw_trace.c | 2 +-
sim/ppc/idecode_expression.h | 2 +-
sim/ppc/igen.h | 4 ++--
sim/ppc/interrupts.h | 4 ++--
sim/ppc/ld-decode.h | 4 ++--
sim/ppc/main.c | 2 +-
sim/ppc/os_emul.h | 4 ++--
sim/ppc/psim.c | 4 ++--
sim/ppc/sim-endian.h | 2 +-
sim/ppc/sim_calls.c | 2 +-
sim/ppc/std-config.h | 12 ++++++------
sim/ppc/tree.c | 4 ++--
sim/ppc/tree.h | 4 ++--
sim/ppc/vm.c | 2 +-
sim/ppc/vm.h | 4 ++--
sim/sh/interp.c | 6 +++---
sim/sh/sim-main.h | 2 +-
sim/v850/sim-main.h | 2 +-
sim/v850/simops.c | 2 +-
94 files changed, 166 insertions(+), 166 deletions(-)
diff --git a/sim/aarch64/memory.c b/sim/aarch64/memory.c
index 744a76d..7599a1b 100644
--- a/sim/aarch64/memory.c
+++ b/sim/aarch64/memory.c
@@ -155,7 +155,7 @@ aarch64_get_mem_ptr (sim_cpu *cpu, uint64_t address)
an out-of-memory condition by noticing a stack/heap collision.
The heap starts at the end of loaded memory and carries on up
- to an arbitary 2Gb limit. */
+ to an arbitrary 2Gb limit. */
uint64_t
aarch64_get_heap_start (sim_cpu *cpu)
diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c
index e5ada18..26a6b04 100644
--- a/sim/aarch64/simulator.c
+++ b/sim/aarch64/simulator.c
@@ -1695,7 +1695,7 @@ set_flags_for_add64 (sim_cpu *cpu, uint64_t value1, uint64_t value2)
}
else
{
- /* Postive plus positive - overflow has happened if the
+ /* Positive plus positive - overflow has happened if the
result is smaller than either of the operands. */
if (result < value1 || result < value2)
flags |= V | C;
diff --git a/sim/arm/armcopro.c b/sim/arm/armcopro.c
index 9227fc0..c535911 100644
--- a/sim/arm/armcopro.c
+++ b/sim/arm/armcopro.c
@@ -131,7 +131,7 @@ check_cp15_access (ARMul_State * state,
return ARMul_CANT;
break;
case 7:
- /* Permissable combinations:
+ /* Permissible combinations:
Opcode_2 CRm
0 5
0 6
@@ -154,7 +154,7 @@ check_cp15_access (ARMul_State * state,
break;
case 8:
- /* Permissable combinations:
+ /* Permissible combinations:
Opcode_2 CRm
0 5
0 6
@@ -229,7 +229,7 @@ write_cp15_reg (ARMul_State * state,
/* Writes are not allowed. */
return;
- case 1: /* Auxillary Control. */
+ case 1: /* Auxiliary Control. */
/* Only BITS (5, 4) and BITS (1, 0) can be written. */
value &= 0x33;
break;
diff --git a/sim/arm/armemu.c b/sim/arm/armemu.c
index 76f398b..abe3db1 100644
--- a/sim/arm/armemu.c
+++ b/sim/arm/armemu.c
@@ -5974,7 +5974,7 @@ Multiply64 (ARMul_State * state, ARMword instr, int msigned, int scc)
hi = (((Rs >> 16) & 0xFFFF) * ((Rm >> 16) & 0xFFFF));
/* We now need to add all of these results together, taking
- care to propogate the carries from the additions. */
+ care to propagate the carries from the additions. */
RdLo = Add32 (lo, (mid1 << 16), &carry);
RdHi = carry;
RdLo = Add32 (RdLo, (mid2 << 16), &carry);
diff --git a/sim/arm/iwmmxt.c b/sim/arm/iwmmxt.c
index 5d289a0..25b5bde 100644
--- a/sim/arm/iwmmxt.c
+++ b/sim/arm/iwmmxt.c
@@ -3539,7 +3539,7 @@ WXOR (ARMword instr)
return ARMul_DONE;
}
-/* This switch table is moved to a seperate function in order
+/* This switch table is moved to a separate function in order
to work around a compiler bug in the host compiler... */
static int
diff --git a/sim/bfin/devices.h b/sim/bfin/devices.h
index 019f44e..404c8b2 100644
--- a/sim/bfin/devices.h
+++ b/sim/bfin/devices.h
@@ -26,7 +26,7 @@
#include "hw-device.h"
#include "hw-tree.h"
-/* We keep the same inital structure layout with DMA enabled devices. */
+/* We keep the same initial structure layout with DMA enabled devices. */
struct dv_bfin {
bu32 base;
struct hw *dma_master;
diff --git a/sim/bfin/dv-bfin_cec.c b/sim/bfin/dv-bfin_cec.c
index d4f96b2..915abbf 100644
--- a/sim/bfin/dv-bfin_cec.c
+++ b/sim/bfin/dv-bfin_cec.c
@@ -570,7 +570,7 @@ _cec_raise (SIM_CPU *cpu, struct bfin_cec *cec, int ivg)
/* XXX: what happens with 'raise 0' ? */
SET_RETEREG (oldpc);
excp_to_sim_halt (sim_stopped, SIM_SIGTRAP);
- /* XXX: Need an easy way for gdb to signal it isnt here. */
+ /* XXX: Need an easy way for gdb to signal it isn't here. */
cec->ipend &= ~IVG_EMU_B;
break;
case IVG_RST:
diff --git a/sim/common/dv-glue.c b/sim/common/dv-glue.c
index a1e2507..2790ab6 100644
--- a/sim/common/dv-glue.c
+++ b/sim/common/dv-glue.c
@@ -62,10 +62,10 @@
<<glue>>: In addition to driving its output interrupt port with any
value written to an interrupt input port is stored in the
corresponding <<output>> register. Such input interrupts, however,
- are not propogated to an output interrupt port.
+ are not propagated to an output interrupt port.
<<glue-and>>: The bit-wise AND of the interrupt inputs is computed
- and then both stored in <<output>> register zero and propogated to
+ and then both stored in <<output>> register zero and propagated to
output interrupt output port zero.
diff --git a/sim/common/dv-pal.c b/sim/common/dv-pal.c
index 43d0635..97c3ce1 100644
--- a/sim/common/dv-pal.c
+++ b/sim/common/dv-pal.c
@@ -52,7 +52,7 @@
DESCRIPTION
- Typical hardware dependant hack. This device allows the firmware
+ Typical hardware dependent hack. This device allows the firmware
to gain access to all the things the firmware needs (but the OS
doesn't).
@@ -104,8 +104,8 @@
zero value to this register clears the countdown timer. Writing a
non-zero 32 bit big-endian value to this register sets the
countdown timer to expire in VALUE ticks (ticks is target
- dependant). Reading the countdown register returns the last value
- writen.
+ dependent). Reading the countdown register returns the last value
+ written.
COUNTDOWN VALUE (read): Reading this 32 bit big-endian register
returns the number of ticks remaining until the countdown timer
@@ -115,7 +115,7 @@
interrupt source. Writing a 32 bit big-endian zero value to this
register clears the periodic timer. Writing a 32 bit non-zero
value to this register sets the periodic timer to triger every
- VALUE ticks (ticks is target dependant). Reading the timer
+ VALUE ticks (ticks is target dependent). Reading the timer
register returns the last value written.
TIMER VALUE (read): Reading this 32 bit big-endian register returns
diff --git a/sim/common/hw-base.h b/sim/common/hw-base.h
index e46a127..4994502 100644
--- a/sim/common/hw-base.h
+++ b/sim/common/hw-base.h
@@ -23,7 +23,7 @@
#ifndef HW_BASE
#define HW_BASE
-/* Create a primative device */
+/* Create a primitive device */
struct hw *hw_create
(struct sim_state *sd,
diff --git a/sim/common/hw-device.h b/sim/common/hw-device.h
index bf1e9e51..179b30c 100644
--- a/sim/common/hw-device.h
+++ b/sim/common/hw-device.h
@@ -167,7 +167,7 @@ typedef unsigned (hw_reset_method)
/* Hardware operations:
Connecting a parent to its children is a common bus. The parent
- node is described as the bus owner and is responisble for
+ node is described as the bus owner and is responsible for
co-ordinating bus operations. On the bus, a SPACE:ADDR pair is used
to specify an address. A device that is both a bus owner (parent)
and bus client (child) are referred to as a bridging device.
diff --git a/sim/common/hw-instances.h b/sim/common/hw-instances.h
index 9396ba9..15ee0eb 100644
--- a/sim/common/hw-instances.h
+++ b/sim/common/hw-instances.h
@@ -33,7 +33,7 @@
disks file system. The operations would be implemented using the
basic block I/O model provided by the disk.
- This model includes methods that faciliate the creation of device
+ This model includes methods that facilitate the creation of device
instance and (should a given device support it) standard operations
on those instances.
diff --git a/sim/common/hw-ports.c b/sim/common/hw-ports.c
index 861fd9b..571f057 100644
--- a/sim/common/hw-ports.c
+++ b/sim/common/hw-ports.c
@@ -130,7 +130,7 @@ detach_hw_port_edge (struct hw *me,
&& old_edge->my_port == my_port)
{
if (old_edge->disposition == permenant_object)
- hw_abort (me, "attempt to delete permenant port edge");
+ hw_abort (me, "attempt to delete permanent port edge");
*list = old_edge->next;
hw_free (me, old_edge);
return;
diff --git a/sim/common/hw-tree.c b/sim/common/hw-tree.c
index bf47d7b..d0e29c9 100644
--- a/sim/common/hw-tree.c
+++ b/sim/common/hw-tree.c
@@ -477,7 +477,7 @@ count_entries (struct hw *current,
-/* parse: <address> ::= <token> ; device dependant */
+/* parse: <address> ::= <token> ; device dependent */
static const char *
parse_address (struct hw *current,
@@ -1273,7 +1273,7 @@ hw_tree_find_device (struct hw *root,
/* parse the path */
split_device_specifier (root, path_to_device, &spec);
if (spec.value != NULL)
- return NULL; /* something wierd */
+ return NULL; /* something weird */
/* now find it */
node = split_find_device (root, &spec);
diff --git a/sim/common/sim-alu.h b/sim/common/sim-alu.h
index fa24720..4fd5d90 100644
--- a/sim/common/sim-alu.h
+++ b/sim/common/sim-alu.h
@@ -453,7 +453,7 @@ do { \
#define ALU8_CARRY_BORROW_RESULT ((unsigned8) alu8_cr)
#define ALU8_OVERFLOW_RESULT ((unsigned8) alu8_vr)
-/* #define ALU8_END ????? - target dependant */
+/* #define ALU8_END ????? - target dependent */
@@ -485,7 +485,7 @@ do { \
#define ALU16_CARRY_BORROW_RESULT ((unsigned16) alu16_cr)
#define ALU16_OVERFLOW_RESULT ((unsigned16) alu16_vr)
-/* #define ALU16_END ????? - target dependant */
+/* #define ALU16_END ????? - target dependent */
diff --git a/sim/common/sim-arange.c b/sim/common/sim-arange.c
index f7557d0..780be5a 100644
--- a/sim/common/sim-arange.c
+++ b/sim/common/sim-arange.c
@@ -88,12 +88,12 @@ frob_range (ADDR_RANGE *ar, address_word start, address_word end, int delete_p)
{
if (! delete_p)
{
- /* Try next range if current range preceeds new one and not
+ /* Try next range if current range precedes new one and not
adjacent or overlapping. */
if (asr->end < caller->start - 1)
goto next_range;
- /* Break out if new range preceeds current one and not
+ /* Break out if new range precedes current one and not
adjacent or overlapping. */
if (asr->start > caller->end + 1)
break;
@@ -120,11 +120,11 @@ frob_range (ADDR_RANGE *ar, address_word start, address_word end, int delete_p)
}
else /* deleting a range */
{
- /* Try next range if current range preceeds new one. */
+ /* Try next range if current range precedes new one. */
if (asr->end < caller->start)
goto next_range;
- /* Break out if new range preceeds current one. */
+ /* Break out if new range precedes current one. */
if (asr->start > caller->end)
break;
diff --git a/sim/common/sim-basics.h b/sim/common/sim-basics.h
index 9f34e2f..1f0f315 100644
--- a/sim/common/sim-basics.h
+++ b/sim/common/sim-basics.h
@@ -30,7 +30,7 @@
#include "config.h"
#endif
-/* Basic host dependant mess - hopefully <stdio.h> + <stdarg.h> will
+/* Basic host dependent mess - hopefully <stdio.h> + <stdarg.h> will
bring potential conflicts out in the open */
#include <stdarg.h>
diff --git a/sim/common/sim-bits.h b/sim/common/sim-bits.h
index d47f69f..457a632 100644
--- a/sim/common/sim-bits.h
+++ b/sim/common/sim-bits.h
@@ -441,7 +441,7 @@ INLINE_SIM_BITS(unsigned_word) MSEXTRACTED (unsigned_word val, int start, int st
/* move a single bit around */
-/* NB: the wierdness (N>O?N-O:0) is to stop a warning from GCC */
+/* NB: the weirdness (N>O?N-O:0) is to stop a warning from GCC */
#define _SHUFFLEDn(N, WORD, OLD, NEW) \
((OLD) < (NEW) \
? (((unsigned##N)(WORD) \
@@ -552,7 +552,7 @@ do { \
/* some rotate functions. The generic macro's ROT, ROTL, ROTR are
- intentionally omited. */
+ intentionally omitted. */
INLINE_SIM_BITS(unsigned8) ROT8 (unsigned8 val, int shift);
diff --git a/sim/common/sim-config.h b/sim/common/sim-config.h
index 88ecfd8..5e40508 100644
--- a/sim/common/sim-config.h
+++ b/sim/common/sim-config.h
@@ -24,7 +24,7 @@
#define SIM_CONFIG_H
-/* Host dependant:
+/* Host dependent:
The CPP below defines information about the compilation host. In
particular it defines the macro's:
@@ -146,7 +146,7 @@ extern enum bfd_endian current_target_byte_order;
expect to see (VEA includes things like coherency and the time
base) while OEA is what an operating system expects to see. By
setting these to specific values, the build process is able to
- eliminate non relevent environment code.
+ eliminate non relevant environment code.
STATE_ENVIRONMENT(sd) specifies which of vea or oea is required for
the current runtime.
diff --git a/sim/common/sim-core.h b/sim/common/sim-core.h
index 25e7cf3..aa8135b 100644
--- a/sim/common/sim-core.h
+++ b/sim/common/sim-core.h
@@ -129,7 +129,7 @@ extern SIM_RC sim_core_install (SIM_DESC sd);
such that the byte alignmed of OPTIONAL_BUFFER matches ADDR vis
(OPTIONAL_BUFFER % 8) == (ADDR % 8)). It is defined to be a sub-optimal
hook that allows clients to do nasty things that the interface doesn't
- accomodate. */
+ accommodate. */
extern void sim_core_attach
(SIM_DESC sd,
@@ -160,7 +160,7 @@ extern void sim_core_detach
Transfer a variable sized block of raw data between the host and
target. Should any problems occur, the number of bytes
- successfully transfered is returned.
+ successfully transferred is returned.
No host/target byte endian conversion is performed. No xor-endian
conversion is performed.
@@ -206,7 +206,7 @@ extern void sim_core_set_xor
Transfer a variable sized block of raw data between the host and
target. Should any problems occur, the number of bytes
- successfully transfered is returned.
+ successfully transferred is returned.
No host/target byte endian conversion is performed. If applicable
(WITH_XOR_ENDIAN and xor-endian set), xor-endian conversion *is*
@@ -244,11 +244,11 @@ extern void *sim_core_trans_addr
/* Fixed sized, processor oriented, read/write.
Transfer a fixed amout of memory between the host and target. The
- data transfered is translated from/to host to/from target byte
+ data transferred is translated from/to host to/from target byte
order (including xor endian). Should the transfer fail, the
operation shall abort (no return).
- ALIGNED assumes yhat the specified ADDRESS is correctly alligned
+ ALIGNED assumes yhat the specified ADDRESS is correctly aligned
for an N byte transfer (no alignment checks are made). Passing an
incorrectly aligned ADDRESS is erroneous.
diff --git a/sim/common/sim-engine.h b/sim/common/sim-engine.h
index 382093b..172a329 100644
--- a/sim/common/sim-engine.h
+++ b/sim/common/sim-engine.h
@@ -131,7 +131,7 @@ extern void sim_engine_vabort
/* Called by the generic sim_resume to run the simulation within the
- above safty net.
+ above safety net.
An example implementation of sim_engine_run can be found in the
file sim-run.c */
diff --git a/sim/common/sim-events.h b/sim/common/sim-events.h
index c01cea0..5098c89 100644
--- a/sim/common/sim-events.h
+++ b/sim/common/sim-events.h
@@ -140,7 +140,7 @@ extern void sim_events_schedule_after_signal
/* Schedule an event milli-seconds from NOW. The exact interpretation
- of wallclock is host dependant. */
+ of wallclock is host dependent. */
extern sim_event *sim_events_watch_clock
(SIM_DESC sd,
diff --git a/sim/common/sim-inline.h b/sim/common/sim-inline.h
index 2c5406e..57e6732 100644
--- a/sim/common/sim-inline.h
+++ b/sim/common/sim-inline.h
@@ -37,7 +37,7 @@
speed improvement (x3-x5). In the case of RISC (sparc) while the
performance gain isn't as great it is still significant.
- Each module is controled by the macro <module>_INLINE which can
+ Each module is controlled by the macro <module>_INLINE which can
have the values described below
0 (ZERO)
diff --git a/sim/common/sim-io.c b/sim/common/sim-io.c
index a04dfc2..d68d6c5 100644
--- a/sim/common/sim-io.c
+++ b/sim/common/sim-io.c
@@ -328,7 +328,7 @@ sim_io_poll_quit (SIM_DESC sd)
FIXME: Some completly new mechanism for handling the general
problem of asynchronous IO is needed.
- FIXME: This function does not supress the echoing (ECHO) of input.
+ FIXME: This function does not suppress the echoing (ECHO) of input.
Consequently polled input is always displayed.
FIXME: This function does not perform uncooked reads.
diff --git a/sim/common/sim-resume.c b/sim/common/sim-resume.c
index e9ec9c9..a23e844 100644
--- a/sim/common/sim-resume.c
+++ b/sim/common/sim-resume.c
@@ -31,7 +31,7 @@ has_stepped (SIM_DESC sd,
}
-/* Generic resume - assumes the existance of sim_engine_run */
+/* Generic resume - assumes the existence of sim_engine_run */
void
sim_resume (SIM_DESC sd,
diff --git a/sim/d10v/interp.c b/sim/d10v/interp.c
index cb8c6cf..902ec80 100644
--- a/sim/d10v/interp.c
+++ b/sim/d10v/interp.c
@@ -960,8 +960,8 @@ step_once (SIM_DESC sd, SIM_CPU *cpu)
{
if (PSW_RP && PC == RPT_E)
{
- /* Note: The behavour of a branch instruction at RPT_E
- is implementation dependant, this simulator takes the
+ /* Note: The behavior of a branch instruction at RPT_E
+ is implementation dependent, this simulator takes the
branch. Branching to RPT_E is valid, the instruction
must be executed before the loop is taken. */
if (RPT_C == 1)
diff --git a/sim/erc32/exec.c b/sim/erc32/exec.c
index a0ab0f9..2687b21 100644
--- a/sim/erc32/exec.c
+++ b/sim/erc32/exec.c
@@ -322,7 +322,7 @@ mul64 (uint32 n1, uint32 n2, uint32 *result_hi, uint32 *result_lo, int msigned)
hi = (((n1 >> 16) & 0xFFFF) * ((n2 >> 16) & 0xFFFF));
/* We now need to add all of these results together, taking care
- to propogate the carries from the additions: */
+ to propagate the carries from the additions: */
reg_lo = add32 (lo, (mid1 << 16), &carry);
reg_hi = carry;
reg_lo = add32 (reg_lo, (mid2 << 16), &carry);
diff --git a/sim/erc32/float.c b/sim/erc32/float.c
index c96b208..d117752 100644
--- a/sim/erc32/float.c
+++ b/sim/erc32/float.c
@@ -20,7 +20,7 @@
FPU. IEEE trap handling is done as follows:
1. In the host, all IEEE traps are masked
2. After each simulated FPU instruction, check if any exception
- occured by reading the exception bits from the host FPU status
+ occurred by reading the exception bits from the host FPU status
register (get_accex()).
3. Propagate any exceptions to the simulated FSR.
4. Clear host exception bits.
diff --git a/sim/erc32/sis.h b/sim/erc32/sis.h
index 5a909f5..396a104 100644
--- a/sim/erc32/sis.h
+++ b/sim/erc32/sis.h
@@ -121,7 +121,7 @@ struct pstate {
uint64 pwdtime; /* Cycles in power-down mode */
uint64 nstore; /* Number of load instructions */
uint64 nload; /* Number of store instructions */
- uint64 nannul; /* Number of annuled instructions */
+ uint64 nannul; /* Number of annulled instructions */
uint64 nbranch; /* Number of branch instructions */
uint32 ildreg; /* Destination of last load instruction */
uint64 ildtime; /* Last time point for load dependency */
diff --git a/sim/frv/frv-sim.h b/sim/frv/frv-sim.h
index 1e2fbc6..8a34f37 100644
--- a/sim/frv/frv-sim.h
+++ b/sim/frv/frv-sim.h
@@ -266,7 +266,7 @@ enum frv_ec
/* FR-V Interrupt.
This struct contains enough information to describe a particular interrupt
- occurance. */
+ occurrence. */
struct frv_interrupt
{
enum frv_interrupt_kind kind;
@@ -282,7 +282,7 @@ struct frv_interrupt
extern struct frv_interrupt frv_interrupt_table[];
/* FR-V Interrupt State.
- Interrupts are queued during execution of parallel insns and the interupt(s)
+ Interrupts are queued during execution of parallel insns and the interrupt(s)
to be handled determined by analysing the queue after each VLIW insn. */
#define FRV_INTERRUPT_QUEUE_SIZE (4 * 4) /* 4 interrupts x 4 insns for now. */
diff --git a/sim/frv/interrupts.c b/sim/frv/interrupts.c
index 3f071b8..a0ef993 100644
--- a/sim/frv/interrupts.c
+++ b/sim/frv/interrupts.c
@@ -830,7 +830,7 @@ set_exception_status_registers (
{
case FRV_DIVISION_EXCEPTION:
set_isr_exception_fields (current_cpu, item);
- /* fall thru to set reg_index. */
+ /* fallthru to set reg_index. */
case FRV_COMMIT_EXCEPTION:
/* For fr550, always use ESR0. */
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
diff --git a/sim/frv/profile.c b/sim/frv/profile.c
index 64c94a6..ebbd222 100644
--- a/sim/frv/profile.c
+++ b/sim/frv/profile.c
@@ -595,14 +595,14 @@ request_complete (SIM_CPU *cpu, CACHE_QUEUE_ELEMENT *q)
}
/* Run the insn and data caches through the given number of cycles, taking
- note of load requests which are fullfilled as a result. */
+ note of load requests which are fulfilled as a result. */
static void
run_caches (SIM_CPU *cpu, int cycles)
{
FRV_CACHE* data_cache = CPU_DATA_CACHE (cpu);
FRV_CACHE* insn_cache = CPU_INSN_CACHE (cpu);
int i;
- /* For each cycle, run the caches, noting which requests have been fullfilled
+ /* For each cycle, run the caches, noting which requests have been fulfilled
and submitting new requests on their designated cycles. */
for (i = 0; i < cycles; ++i)
{
diff --git a/sim/frv/registers.c b/sim/frv/registers.c
index 47154db..663d3f8 100644
--- a/sim/frv/registers.c
+++ b/sim/frv/registers.c
@@ -6432,7 +6432,7 @@ frv_initialize_spr (SIM_CPU *current_cpu)
}
}
- /* Now explicitely set PSR in order to get the correct setting for PSR.S. */
+ /* Now explicitly set PSR in order to get the correct setting for PSR.S. */
spr_control = & control->spr[H_SPR_PSR];
save_mask = spr_control->read_only_mask;
spr_control->read_only_mask = 0;
@@ -6473,7 +6473,7 @@ frv_reset_spr (SIM_CPU *current_cpu)
}
}
- /* Now explicitely set PSR in order to get the correct setting for PSR.S. */
+ /* Now explicitly set PSR in order to get the correct setting for PSR.S. */
spr_control = & control->spr[H_SPR_PSR];
mask = spr_control->reset_mask;
new_val = GET_H_SPR (H_SPR_PSR) & ~mask;
diff --git a/sim/frv/traps.c b/sim/frv/traps.c
index 39e0e34..7b2bf07 100644
--- a/sim/frv/traps.c
+++ b/sim/frv/traps.c
@@ -773,7 +773,7 @@ frvbf_check_swap_address (SIM_CPU *current_cpu, SI address)
if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550)
return;
- /* Adress must be aligned on a word boundary. */
+ /* Address must be aligned on a word boundary. */
if (address & 0x3)
frv_queue_data_access_exception_interrupt (current_cpu);
}
diff --git a/sim/h8300/compile.c b/sim/h8300/compile.c
index c1c61d8..6fe9a45 100644
--- a/sim/h8300/compile.c
+++ b/sim/h8300/compile.c
@@ -1906,7 +1906,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu)
case 0:
/*
* This opcode is a fake for when we get to an
- * instruction which hasnt been compiled
+ * instruction which hasn't been compiled
*/
compile (sd, pc);
goto top;
diff --git a/sim/igen/gen-engine.c b/sim/igen/gen-engine.c
index 829d6b0..5aced8f 100644
--- a/sim/igen/gen-engine.c
+++ b/sim/igen/gen-engine.c
@@ -67,7 +67,7 @@ print_run_body (lf *file, gen_entry *table)
{
/* Output the function to execute real code:
- Unfortunatly, there are multiple cases to consider vis:
+ Unfortunately, there are multiple cases to consider vis:
<icache> X <smp>
@@ -102,7 +102,7 @@ In this case, we can take advantage of the fact that the current\n\
instruction address (CIA) does not need to be read from / written to\n\
the CPU object after the execution of an instruction.\n\
\n\
-Instead, CIA is only saved when the main loop exits. This occures\n\
+Instead, CIA is only saved when the main loop exits. This occurs\n\
when either sim_engine_halt or sim_engine_restart is called. Both of\n\
these functions save the current instruction address before halting /\n\
restarting the simulator.\n\
diff --git a/sim/igen/gen-icache.c b/sim/igen/gen-icache.c
index 081fdb3..80151fa 100644
--- a/sim/igen/gen-icache.c
+++ b/sim/igen/gen-icache.c
@@ -150,7 +150,7 @@ print_icache_extraction (lf *file,
switch (what_to_declare)
{
case undef_variables:
- /* We've finished with the #define value - destory it */
+ /* We've finished with the #define value - destroy it */
lf_indent_suppress (file);
lf_printf (file, "#undef %s\n", entry_name);
return;
@@ -630,7 +630,7 @@ print_icache_struct (lf *file, insn_table *isa, cache_entry *cache_rules)
else
{
/* alernativly, since no cache, emit a dummy definition for
- idecode_cache so that code refering to the type can still compile */
+ idecode_cache so that code referring to the type can still compile */
lf_printf (file, "typedef void %sidecode_cache;\n",
options.module.global.prefix.l);
}
diff --git a/sim/igen/gen-idecode.c b/sim/igen/gen-idecode.c
index ad9d228..88db06f 100644
--- a/sim/igen/gen-idecode.c
+++ b/sim/igen/gen-idecode.c
@@ -629,7 +629,7 @@ idecode_declare_if_switch (lf *file, gen_entry *table, int depth, void *data)
{
print_idecode_switch_function_header (file,
table,
- 0 /*isnt function definition */ ,
+ 0 /* isn't function definition */ ,
0);
}
}
@@ -862,7 +862,7 @@ print_idecode_validate (lf *file,
proper.
The PowerPC spec requires a CSI after MSR[FP] is changed and when
- ever a CSI occures we flush the instruction cache. */
+ ever a CSI occurs we flush the instruction cache. */
{
if (filter_is_member (instruction->flags, "f"))
diff --git a/sim/igen/gen-semantics.c b/sim/igen/gen-semantics.c
index 0cd4f85..fbb827e 100644
--- a/sim/igen/gen-semantics.c
+++ b/sim/igen/gen-semantics.c
@@ -244,7 +244,7 @@ print_semantic_body (lf *file,
}
/* Architecture expects a REG to be zero. Instead of having to
- check every read to see if it is refering to that REG just zap it
+ check every read to see if it is referring to that REG just zap it
at the start of every instruction */
if (options.gen.zero_reg)
{
diff --git a/sim/igen/gen-semantics.h b/sim/igen/gen-semantics.h
index ed0d3ad..2b55dd3 100644
--- a/sim/igen/gen-semantics.h
+++ b/sim/igen/gen-semantics.h
@@ -34,9 +34,9 @@
o cached - separate cracker and semantic
- Two independant functions are created. Firstly the
+ Two independent functions are created. Firstly the
function that cracks an instruction entering it into a
- cache and secondly the semantic function propper that
+ cache and secondly the semantic function proper that
uses the cache.
o cached - semantic + cracking semantic
@@ -47,7 +47,7 @@
cracker and the semantic function when there is a
cache miss).
- For each of these general forms, several refinements can occure:
+ For each of these general forms, several refinements can occur:
o do/don't duplicate/expand semantic functions
diff --git a/sim/igen/gen.c b/sim/igen/gen.c
index f49b39b..605b78f 100644
--- a/sim/igen/gen.c
+++ b/sim/igen/gen.c
@@ -386,7 +386,7 @@ insn_list_insert (insn_list **cur_insn_ptr,
case report_duplicate_insns:
/* It would appear that we have two instructions with the
same constant field values across all words and bits.
- This error can also occure when insn_field_cmp() is
+ This error can also occur when insn_field_cmp() is
failing to differentiate between two instructions that
differ only in their conditional fields. */
warning (insn->line,
@@ -635,7 +635,7 @@ insns_bit_useless (insn_list *insns, decode_table *rule, int bit_nr)
/* Given only one constant value has been found, check through all
the instructions to see if at least one conditional makes it
- usefull */
+ useful */
if (value >= 0 && is_useless)
{
for (entry = insns; entry != NULL; entry = entry->next)
@@ -972,7 +972,7 @@ gen_entry_expand_opcode (gen_entry *table,
condition->field->last);
/* this is a requirement of
a conditonal field
- refering to another field */
+ referring to another field */
ASSERT ((condition->field->first -
condition->field->last) ==
(first_pos - last_pos));
diff --git a/sim/igen/igen.c b/sim/igen/igen.c
index 9dba48a..5d985a2 100644
--- a/sim/igen/igen.c
+++ b/sim/igen/igen.c
@@ -482,7 +482,7 @@ print_itrace (lf *file, insn_entry * insn, int idecode)
{
/* NB: Here we escape each EOLN. This is so that the the compiler
treats a trace function call as a single line. Consequently any
- errors in the line are refered back to the same igen assembler
+ errors in the line are referred back to the same igen assembler
source line */
const char *phase = (idecode) ? "DECODE" : "INSN";
lf_printf (file, "\n");
diff --git a/sim/igen/igen.h b/sim/igen/igen.h
index f5ccb21..d2980dd 100644
--- a/sim/igen/igen.h
+++ b/sim/igen/igen.h
@@ -136,7 +136,7 @@ struct _igen_decode_options
int combine;
/* Instruction expansion? Should the semantic code for each
- instruction, when the oportunity arrises, be expanded according
+ instruction, when the opportunity arrises, be expanded according
to the variable opcode files that the instruction decode process
renders constant */
int duplicate;
diff --git a/sim/igen/ld-decode.h b/sim/igen/ld-decode.h
index f66c7dc..93808cf 100644
--- a/sim/igen/ld-decode.h
+++ b/sim/igen/ld-decode.h
@@ -87,7 +87,7 @@
If an instruction field was found, enlarge the field size so that
it is forced to at least include bits starting from <force_first>
- (<force_last>). To stop this occuring, use <force_first> = <last>
+ (<force_last>). To stop this occurring, use <force_first> = <last>
+ 1 and <force_last> = <first> - 1.
<force_reserved>
@@ -99,7 +99,7 @@
Treat any contained register (string) fields as constant when
determining the instruction field. For the instruction decode (and
- controled by IDECODE_EXPAND_SEMANTICS) this forces the expansion of
+ controlled by IDECODE_EXPAND_SEMANTICS) this forces the expansion of
what would otherwize be non constant bits of an instruction.
<use_switch>
diff --git a/sim/igen/ld-insn.c b/sim/igen/ld-insn.c
index d30d083..6c061f0 100644
--- a/sim/igen/ld-insn.c
+++ b/sim/igen/ld-insn.c
@@ -201,7 +201,7 @@ parse_insn_word (line_ref *line, char *string, int word_nr)
{
if (strlen_pos == 0)
{
- /* when the length/pos field is omited, an integer field
+ /* when the length/pos field is omitted, an integer field
is always binary */
unsigned64 val = 0;
int i;
@@ -409,7 +409,7 @@ parse_insn_words (insn_entry * insn, char *formats)
insn->word[i] = word;
}
- /* Go over all fields that have conditionals refering to other
+ /* Go over all fields that have conditionals referring to other
fields. Link the fields up. Verify that the two fields have the
same size. Verify that the two fields are different */
{
@@ -442,9 +442,9 @@ parse_insn_words (insn_entry * insn, char *formats)
&& strcmp (refered_field->val_string,
cond->string) == 0)
{
- /* found field being refered to by conditonal */
+ /* found field being referred to by conditonal */
cond->field = refered_field;
- /* check refered to and this field are
+ /* check referred to and this field are
the same size */
if (f->width != refered_field->width)
error (insn->line,
diff --git a/sim/igen/lf.h b/sim/igen/lf.h
index f180c3c..8a0dfa5 100644
--- a/sim/igen/lf.h
+++ b/sim/igen/lf.h
@@ -43,7 +43,7 @@ lf_file_references;
/* Open the file NAME for writing ("-" for stdout). Use REAL_NAME
- when refering to the opened file. Line number information (in the
+ when referring to the opened file. Line number information (in the
output) can be suppressed with FILE_REFERENCES ==
LF_OMIT_REFERENCES. TYPE is to determine the formatting of some of
the print messages below. */
diff --git a/sim/lm32/dv-lm32uart.c b/sim/lm32/dv-lm32uart.c
index 121d9a8..db5d180 100644
--- a/sim/lm32/dv-lm32uart.c
+++ b/sim/lm32/dv-lm32uart.c
@@ -93,7 +93,7 @@ do_uart_tx_event (struct hw *me, void *data)
hw_port_event (me, INT_PORT, 1);
}
- /* Indicate which interrupt has occured. */
+ /* Indicate which interrupt has occurred. */
uart->iir = MICOUART_IIR_TXRDY;
/* Indicate THR is empty. */
diff --git a/sim/m32r/dv-m32r_uart.h b/sim/m32r/dv-m32r_uart.h
index ec0464a..f6ba624 100644
--- a/sim/m32r/dv-m32r_uart.h
+++ b/sim/m32r/dv-m32r_uart.h
@@ -21,7 +21,7 @@
#ifndef DV_M32R_UART_H
#define DV_M32R_UART_H
-/* Should move these settings to a flag to the uart device, and the adresses to
+/* Should move these settings to a flag to the uart device, and the addresses to
the sim-model framework. */
/* Serial device addresses. */
diff --git a/sim/m68hc11/dv-m68hc11sio.c b/sim/m68hc11/dv-m68hc11sio.c
index fe850e4..13e6edb 100644
--- a/sim/m68hc11/dv-m68hc11sio.c
+++ b/sim/m68hc11/dv-m68hc11sio.c
@@ -87,7 +87,7 @@ struct m68hc11sio
is used to find the number of cpu cycles to send/receive a data. */
unsigned int data_length;
- /* Information about next character to be transmited. */
+ /* Information about next character to be transmitted. */
unsigned char tx_has_char;
unsigned char tx_char;
diff --git a/sim/m68hc11/dv-m68hc11spi.c b/sim/m68hc11/dv-m68hc11spi.c
index f078f61..b930082 100644
--- a/sim/m68hc11/dv-m68hc11spi.c
+++ b/sim/m68hc11/dv-m68hc11spi.c
@@ -78,7 +78,7 @@ static const struct hw_port_descriptor m68hc11spi_ports[] =
/* SPI */
struct m68hc11spi
{
- /* Information about next character to be transmited. */
+ /* Information about next character to be transmitted. */
unsigned char tx_char;
int tx_bit;
unsigned char mode;
diff --git a/sim/m68hc11/dv-m68hc11tim.c b/sim/m68hc11/dv-m68hc11tim.c
index 17553b1..a93f2d8 100644
--- a/sim/m68hc11/dv-m68hc11tim.c
+++ b/sim/m68hc11/dv-m68hc11tim.c
@@ -343,7 +343,7 @@ m68hc11tim_timer_event (struct hw *me, void *data)
compare = (cpu->ios[i] << 8) + cpu->ios[i + 1];
- /* See if compare is reached; handle wrap arround. */
+ /* See if compare is reached; handle wrap around. */
if ((compare >= tcnt_prev && compare <= tcnt && tcnt_prev < tcnt)
|| (compare >= tcnt_prev && tcnt_prev > tcnt)
|| (compare < tcnt && tcnt_prev > tcnt))
diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h
index 0ea1234..9400559 100644
--- a/sim/mips/sim-main.h
+++ b/sim/mips/sim-main.h
@@ -108,7 +108,7 @@ typedef enum {
/* For some MIPS targets, the HI/LO registers have certain timing
restrictions in that, for instance, a read of a HI register must be
- separated by at least three instructions from a preceeding read.
+ separated by at least three instructions from the preceding read.
The struct below is used to record the last access by each of A MT,
MF or other OP instruction to a HI/LO register. See mips.igen for
@@ -281,7 +281,7 @@ struct _sim_cpu {
#define simPCOC1 (1 << 18) /* COC[1] from previous */
#define simDELAYSLOT (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
#define simSKIPNEXT (1 << 25) /* 0 = do nothing; 1 = skip instruction */
-#define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occured */
+#define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occurred */
#define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
#ifndef ENGINE_ISSUE_PREFIX_HOOK
diff --git a/sim/mn10300/interp.c b/sim/mn10300/interp.c
index 7f0655f..dbab458 100644
--- a/sim/mn10300/interp.c
+++ b/sim/mn10300/interp.c
@@ -180,7 +180,7 @@ sim_open (SIM_OPEN_KIND kind,
sim_hw_parse (sd, "/mn103cpu@0x20000000");
sim_hw_parse (sd, "/mn103cpu@0x20000000/reg 0x20000000 0x42");
- /* DEBUG: ACK output wired upto a glue device */
+ /* DEBUG: ACK output wired up to a glue device */
sim_hw_parse (sd, "/glue@0x20002000");
sim_hw_parse (sd, "/glue@0x20002000/reg 0x20002000 4");
sim_hw_parse (sd, "/mn103cpu > ack int0 /glue@0x20002000");
diff --git a/sim/ppc/altivec_registers.h b/sim/ppc/altivec_registers.h
index 5b2bd02..8155daa 100644
--- a/sim/ppc/altivec_registers.h
+++ b/sim/ppc/altivec_registers.h
@@ -46,7 +46,7 @@ struct altivec_regs {
/* AltiVec endian helpers, wrong endian hosts vs targets need to be
sure to get the right bytes/halfs/words when the order matters.
Note that many AltiVec instructions do not depend on byte order and
- work on N independant bits of data. This is only for the
+ work on N independent bits of data. This is only for the
instructions that actually move data around. */
#if (WITH_HOST_BYTE_ORDER == BIG_ENDIAN)
diff --git a/sim/ppc/basics.h b/sim/ppc/basics.h
index 2b923ea..d92eccb 100644
--- a/sim/ppc/basics.h
+++ b/sim/ppc/basics.h
@@ -90,7 +90,7 @@ typedef enum {
#include "inline.h"
-/* Basic host dependant mess - hopefully <stdio.h> + <stdarg.h> will
+/* Basic host dependent mess - hopefully <stdio.h> + <stdarg.h> will
bring potential conflicts out in the open */
#include <stdarg.h>
diff --git a/sim/ppc/bits.h b/sim/ppc/bits.h
index 58173f7..f31c57a 100644
--- a/sim/ppc/bits.h
+++ b/sim/ppc/bits.h
@@ -197,7 +197,7 @@ INLINE_BITS\
int stop);
/* move a single bit around */
-/* NB: the wierdness (N>O?N-O:0) is to stop a warning from GCC */
+/* NB: the weirdness (N>O?N-O:0) is to stop a warning from GCC */
#define _SHUFFLEDn(N, WORD, OLD, NEW) \
((OLD) < (NEW) \
? (((unsigned##N)(WORD) \
diff --git a/sim/ppc/corefile.h b/sim/ppc/corefile.h
index 9297f3e..e468109 100644
--- a/sim/ppc/corefile.h
+++ b/sim/ppc/corefile.h
@@ -85,7 +85,7 @@ INLINE_CORE\
restarting it.
For callback maps it is possible to further order them by
- specifiying specifying a callback level (eg callback + 1).
+ specifying specifying a callback level (eg callback + 1).
When the core is resolving an access it searches each of the maps
in order. First raw-memory and then callback maps (in assending
@@ -119,7 +119,7 @@ INLINE_CORE\
The operation of mapping between an address and its destination
device or memory array is currently implemented using a simple
linked list. The posibility of replacing this list with a more
- powerfull data structure exists.
+ powerful data structure exists.
*/
@@ -170,8 +170,8 @@ INLINE_CORE\
/* Variable sized read/write
Transfer (zero) a variable size block of data between the host and
- target (possibly byte swapping it). Should any problems occure,
- the number of bytes actually transfered is returned. */
+ target (possibly byte swapping it). Should any problems occur,
+ the number of bytes actually transferred is returned. */
INLINE_CORE\
(unsigned) core_map_read_buffer
@@ -192,7 +192,7 @@ INLINE_CORE\
Transfer a fixed amout of memory between the host and target. The
memory always being translated and the operation always aborting
- should a problem occure */
+ should a problem occur */
#define DECLARE_CORE_WRITE_N(N) \
INLINE_CORE\
diff --git a/sim/ppc/cpu.c b/sim/ppc/cpu.c
index c7e8bdf..9f93ffd 100644
--- a/sim/ppc/cpu.c
+++ b/sim/ppc/cpu.c
@@ -276,7 +276,7 @@ cpu_set_decrementer(cpu *processor,
processor->decrementer_local_time = (event_queue_time(processor->events)
+ decrementer);
if (decrementer < 0 && old_decrementer >= 0)
- /* A decrementer interrupt occures if the sign of the decrement
+ /* A decrementer interrupt occurs if the sign of the decrement
register is changed from positive to negative by the load
instruction */
decrementer_interrupt(processor);
diff --git a/sim/ppc/cpu.h b/sim/ppc/cpu.h
index cb141f2..63f938d 100644
--- a/sim/ppc/cpu.h
+++ b/sim/ppc/cpu.h
@@ -137,7 +137,7 @@ INLINE_CPU\
#if WITH_IDECODE_CACHE_SIZE
-/* Return the cache entry that matches the given CIA. No guarentee
+/* Return the cache entry that matches the given CIA. No guarantee
that the cache entry actually contains the instruction for that
address */
@@ -158,7 +158,7 @@ INLINE_CPU\
inner vm maps, to have the cpu its self provide memory manipulation
functions. (eg cpu_instruction_fetch() cpu_data_read_4())
- Unfortunatly in addition to these functions is the need (for the
+ Unfortunately in addition to these functions is the need (for the
debugger) to be able to read/write to memory in ways that violate
the vm protection (eg store breakpoint instruction in the
instruction map). */
@@ -204,7 +204,7 @@ INLINE_CPU\
/* Registers:
This model exploits the PowerPC's requirement for a synchronization
- to occure after (or before) the update of any context controlling
+ to occurs after (or before) the update of any context controlling
register. All context sync points must call the sync function
below to when ever a synchronization point is reached */
diff --git a/sim/ppc/device.h b/sim/ppc/device.h
index 6fd198d..a4a1e90 100644
--- a/sim/ppc/device.h
+++ b/sim/ppc/device.h
@@ -430,7 +430,7 @@ INLINE_DEVICE\
disks file system. The operations would be implemented using the
basic block I/O model provided by the disk.
- This model includes methods that faciliate the creation of device
+ This model includes methods that facilitate the creation of device
instance and (should a given device support it) standard operations
on those instances.
@@ -514,10 +514,10 @@ INLINE_DEVICE\
cpu *processor,
unsigned_word cia);
-/* This interrupt event will then be propogated to any attached
+/* This interrupt event will then be propagated to any attached
interrupt destinations.
- Any interpretation of PORT and VALUE is model dependant. However
+ Any interpretation of PORT and VALUE is model dependent. However
as guidelines the following are recommended: PCI interrupts a-d
correspond to lines 0-3; level sensative interrupts be requested
with a value of one and withdrawn with a value of 0; edge sensative
diff --git a/sim/ppc/emul_bugapi.c b/sim/ppc/emul_bugapi.c
index e33d0cf..306b177 100644
--- a/sim/ppc/emul_bugapi.c
+++ b/sim/ppc/emul_bugapi.c
@@ -46,7 +46,7 @@
/* EMULATION
- BUG - Motorola's embeded firmware BUG interface
+ BUG - Motorola's embedded firmware BUG interface
DESCRIPTION
@@ -71,7 +71,7 @@
#define _NETWR 0x019 /* Write to host */
#define _NETCFIG 0x01a /* Configure network parameters */
#define _NETOPN 0x01b /* Open file for reading */
-#define _NETFRD 0x01c /* Retreive specified file blocks */
+#define _NETFRD 0x01c /* Retrieve specified file blocks */
#define _NETCTRL 0x01d /* Implement special control functions */
#define _OUTCHR 0x020 /* Output character (pointer / pointer format) */
#define _OUTSTR 0x021 /* Output string (pointer / pointer format) */
diff --git a/sim/ppc/emul_chirp.h b/sim/ppc/emul_chirp.h
index 6e431ba..b4e7016 100644
--- a/sim/ppc/emul_chirp.h
+++ b/sim/ppc/emul_chirp.h
@@ -46,7 +46,7 @@
instruction. By doing this, emul_chirp is able to catch and handle
any invalid data accesses it makes while emulating a client call.
- When such an exception occures, emul_chirp is able to recover by
+ When such an exception occurs, emul_chirp is able to recover by
restoring the processor and then calling the clients callback
interface so that the client can recover from the data exception.
diff --git a/sim/ppc/emul_unix.c b/sim/ppc/emul_unix.c
index 1475474..7ca33e7 100644
--- a/sim/ppc/emul_unix.c
+++ b/sim/ppc/emul_unix.c
@@ -160,7 +160,7 @@ struct _os_emul_data {
\f
/* Emulation of simple UNIX system calls that are common on all systems. */
-/* Structures that are common agmonst the UNIX varients */
+/* Structures that are common among the UNIX variants */
struct unix_timeval {
signed32 tv_sec; /* seconds */
signed32 tv_usec; /* microseconds */
diff --git a/sim/ppc/events.c b/sim/ppc/events.c
index 130b28b..53fa8cc 100644
--- a/sim/ppc/events.c
+++ b/sim/ppc/events.c
@@ -37,7 +37,7 @@
variables.
TIME_OF_EVENT: this holds the time at which the next event is ment
- to occure. If no next event it will hold the time of the last
+ to occur. If no next event it will hold the time of the last
event.
TIME_FROM_EVENT: The current distance from TIME_OF_EVENT. If an
@@ -195,7 +195,7 @@ insert_event_entry(event_queue *events,
if (delta < 0)
error("what is past is past!\n");
- /* compute when the event should occure */
+ /* compute when the event should occur */
time_of_event = event_queue_time(events) + delta;
/* find the queue insertion point - things are time ordered */
diff --git a/sim/ppc/gen-icache.c b/sim/ppc/gen-icache.c
index 8acf3fb..81c4283 100644
--- a/sim/ppc/gen-icache.c
+++ b/sim/ppc/gen-icache.c
@@ -99,7 +99,7 @@ print_icache_extraction(lf *file,
/* Define a storage area for the cache element */
if (what_to_declare == undef_variables) {
- /* We've finished with the value - destory it */
+ /* We've finished with the value - destroy it */
lf_indent_suppress(file);
lf_printf(file, "#undef %s\n", entry_name);
return;
@@ -478,8 +478,8 @@ print_icache_struct(insn_table *instructions,
lf_printf(file, "} idecode_cache;\n");
}
else {
- /* alernativly, since no cache, emit a dummy definition for
- idecode_cache so that code refering to the type can still compile */
+ /* alernatively, since no cache, emit a dummy definition for
+ idecode_cache so that code referring to the type can still compile */
lf_printf(file, "typedef void idecode_cache;\n");
}
lf_printf(file, "\n");
diff --git a/sim/ppc/gen-idecode.c b/sim/ppc/gen-idecode.c
index 256ba75..20398ab 100644
--- a/sim/ppc/gen-idecode.c
+++ b/sim/ppc/gen-idecode.c
@@ -596,7 +596,7 @@ idecode_declare_if_switch(insn_table *table,
&& table->parent->opcode_rule->gen == array_gen) {
print_idecode_switch_function_header(file,
table,
- 0/*isnt function definition*/);
+ 0/* isn't function definition */);
}
}
@@ -691,7 +691,7 @@ print_run_until_stop_body(lf *file,
{
/* Output the function to execute real code:
- Unfortunatly, there are multiple cases to consider vis:
+ Unfortunately, there are multiple cases to consider vis:
<icache> X <smp> X <events> X <keep-running-flag> X ...
@@ -1422,7 +1422,7 @@ print_idecode_validate(lf *file,
proper.
The PowerPC spec requires a CSI after MSR[FP] is changed and when
- ever a CSI occures we flush the instruction cache. */
+ ever a CSI occurs we flush the instruction cache. */
{
if (it_is("f", instruction->file_entry->fields[insn_flags])) {
diff --git a/sim/ppc/gen-semantics.h b/sim/ppc/gen-semantics.h
index 8d1804b..c6b83de 100644
--- a/sim/ppc/gen-semantics.h
+++ b/sim/ppc/gen-semantics.h
@@ -32,9 +32,9 @@
o cached - separate cracker and semantic
- Two independant functions are created. Firstly the
+ Two independent functions are created. Firstly the
function that cracks an instruction entering it into a
- cache and secondly the semantic function propper that
+ cache and secondly the semantic function proper that
uses the cache.
o cached - semantic + cracking semantic
@@ -45,7 +45,7 @@
cracker and the semantic function when there is a
cache miss).
- For each of these general forms, several refinements can occure:
+ For each of these general forms, several refinements can occur:
o do/don't duplicate/expand semantic functions
diff --git a/sim/ppc/hw_cpu.c b/sim/ppc/hw_cpu.c
index df807c1..8857fed 100644
--- a/sim/ppc/hw_cpu.c
+++ b/sim/ppc/hw_cpu.c
@@ -118,7 +118,7 @@ hw_cpu_init_address(device *me)
/* Take the interrupt and synchronize its delivery with the clock. If
we've not yet scheduled an interrupt for the next clock tick, take
- the oportunity to do it now */
+ the opportunity to do it now */
static void
hw_cpu_interrupt_event(device *me,
diff --git a/sim/ppc/hw_eeprom.c b/sim/ppc/hw_eeprom.c
index 3406be9..e9c33fe 100644
--- a/sim/ppc/hw_eeprom.c
+++ b/sim/ppc/hw_eeprom.c
@@ -35,7 +35,7 @@
/* DEVICE
- eeprom - JEDEC? compatible electricaly erasable programable device
+ eeprom - JEDEC? compatible electricaly erasable programmable device
DESCRIPTION
@@ -43,7 +43,7 @@
This device implements a small byte addressable EEPROM.
Programming is performed using the same write sequences as used by
- standard modern EEPROM components. Writes occure in real time, the
+ standard modern EEPROM components. Writes occur in real time, the
device returning a progress value until the programing has been
completed.
diff --git a/sim/ppc/hw_glue.c b/sim/ppc/hw_glue.c
index c824773..b895638 100644
--- a/sim/ppc/hw_glue.c
+++ b/sim/ppc/hw_glue.c
@@ -55,10 +55,10 @@
<<glue>>: In addition to driving its output interrupt port with any
value written to an interrupt input port is stored in the
corresponding <<output>> register. Such input interrupts, however,
- are not propogated to an output interrupt port.
+ are not propagated to an output interrupt port.
<<glue-and>>: The bit-wise AND of the interrupt inputs is computed
- and then both stored in <<output>> register zero and propogated to
+ and then both stored in <<output>> register zero and propagated to
output interrupt output port zero.
diff --git a/sim/ppc/hw_ide.c b/sim/ppc/hw_ide.c
index 9d3a711..c849005 100644
--- a/sim/ppc/hw_ide.c
+++ b/sim/ppc/hw_ide.c
@@ -37,7 +37,7 @@
This device models the primary/secondary <<ide>> controller
described in the [CHRPIO] document.
- The controller has separate independant interrupt outputs for each
+ The controller has separate independent interrupt outputs for each
<<ide>> bus.
@@ -91,7 +91,7 @@
| i0,0,1c,6 1 \
| i0,0,20,0 8' \
- Note: the fouth and fifth reg entries specify that the register is
+ Note: the fourth and fifth reg entries specify that the register is
at an offset into the address specified by the base register
(<<assigned-addresses>>); Apart from restrictions placed by the
<<pci>> specification, no restrictions are placed on the number of
@@ -508,7 +508,7 @@ get_status(device *me,
}
-/* The address presented to the IDE controler is decoded and then
+/* The address presented to the IDE controller is decoded and then
mapped onto a controller:reg pair */
enum {
diff --git a/sim/ppc/hw_init.c b/sim/ppc/hw_init.c
index 0e7403b..327ff14 100644
--- a/sim/ppc/hw_init.c
+++ b/sim/ppc/hw_init.c
@@ -182,7 +182,7 @@ static device_callbacks const hw_file_callbacks = {
eeprom requires a complex sequence of accesses). The
<<real-address>> is specified as <<0x0c00>> which is the offset
into the eeprom. For brevity, most of the eeprom properties have
- been omited.
+ been omitted.
| /iobus/eeprom@0xfff00000/reg 0xfff00000 0x80000
| /openprom/init/data@0xfff00c00/real-address 0x0c00
@@ -576,7 +576,7 @@ create_ppc_elf_stack_frame(device *me,
const unsigned sizeof_argv = sizeof_arguments(argv);
const unsigned_word start_argv = start_envp - sizeof_argv;
- /* link register save address - alligned to a 16byte boundary */
+ /* link register save address - aligned to a 16byte boundary */
const unsigned_word top_of_stack = ((start_argv
- 2 * sizeof(unsigned_word))
& ~0xf);
diff --git a/sim/ppc/hw_opic.c b/sim/ppc/hw_opic.c
index 69d956b..5df02fc 100644
--- a/sim/ppc/hw_opic.c
+++ b/sim/ppc/hw_opic.c
@@ -883,7 +883,7 @@ do_end_of_interrupt_register_N_write(device *me,
DTRACE(opic, ("eoi %d - ignoring nonzero value\n", dest->nr));
}
- /* user doing wierd things? */
+ /* user doing weird things? */
if (dest->current_in_service == NULL) {
DTRACE(opic, ("eoi %d - strange, no current interrupt\n", dest->nr));
return;
diff --git a/sim/ppc/hw_pal.c b/sim/ppc/hw_pal.c
index 0789929..c91f239 100644
--- a/sim/ppc/hw_pal.c
+++ b/sim/ppc/hw_pal.c
@@ -54,7 +54,7 @@
DESCRIPTION
- Typical hardware dependant hack. This device allows the firmware
+ Typical hardware dependent hack. This device allows the firmware
to gain access to all the things the firmware needs (but the OS
doesn't).
diff --git a/sim/ppc/hw_phb.c b/sim/ppc/hw_phb.c
index 8e3fb17..e8f3ac4 100644
--- a/sim/ppc/hw_phb.c
+++ b/sim/ppc/hw_phb.c
@@ -65,7 +65,7 @@
Define a number of mappings from the parent bus to one of this
devices PCI busses. The exact format of the <<parent-phys-addr>>
- is parent bus dependant. The format of <<my-phys-addr>> is
+ is parent bus dependent. The format of <<my-phys-addr>> is
described in the Open Firmware PCI bindings document (note that the
address must be non-relocatable).
@@ -93,7 +93,7 @@
Since device tree entries that are specified on the command line
are added before most of the device tree has been built it is often
- necessary to explictly add certain device properties and thus
+ necessary to explicitly add certain device properties and thus
ensure they are already present in the device tree. For the
<<phb>> one such property is parent busses <<#address-cells>>.
@@ -157,7 +157,7 @@
The Open Firmware PCI bus bindings document (rev 1.6) suggests that
the register field of non-relocatable PCI address should be zero.
- Unfortunatly, PCI addresses specified in the <<assigned-addresses>>
+ Unfortunately, PCI addresses specified in the <<assigned-addresses>>
property must be both non-relocatable and have non-zero register
fields.
@@ -319,7 +319,7 @@ hw_phb_attach_address(device *me,
&& type != hw_phb_subtractive_decode)
device_error(me, "attach type (%d) specified by %s invalid",
type, device_path(client));
- /* attach it to the relevent bus */
+ /* attach it to the relevant bus */
DTRACE(phb, ("attach %s - %s %s:0x%lx (0x%lx bytes)\n",
device_path(client),
hw_phb_decode_name(type),
diff --git a/sim/ppc/hw_trace.c b/sim/ppc/hw_trace.c
index 9490bfb..f7c72fd 100644
--- a/sim/ppc/hw_trace.c
+++ b/sim/ppc/hw_trace.c
@@ -32,7 +32,7 @@
The properties of this device are used, during initialization, to
specify the value various simulation trace options. The
- initialization can occure implicitly (during device tree init) or
+ initialization can occur implicitly (during device tree init) or
explicitly using this devices ioctl method.
The actual options and their default values (for a given target)
diff --git a/sim/ppc/idecode_expression.h b/sim/ppc/idecode_expression.h
index 13f6020..88a55ba 100644
--- a/sim/ppc/idecode_expression.h
+++ b/sim/ppc/idecode_expression.h
@@ -46,7 +46,7 @@
/* 64bit target expressions:
- Unfortunatly 128bit arrithemetic isn't that common. Consequently
+ Unfortunately, 128bit arithmetics isn't that common. Consequently
the 32/64 bit trick can not be used. Instead all calculations are
required to retain carry/overflow information in separate
variables. Even with this restriction it is still possible for the
diff --git a/sim/ppc/igen.h b/sim/ppc/igen.h
index 052806a..813632c 100644
--- a/sim/ppc/igen.h
+++ b/sim/ppc/igen.h
@@ -41,7 +41,7 @@ typedef enum {
generate_calls = 0x100,
- /* In addition, when refering to fields access them directly instead
+ /* In addition, when referring to fields access them directly instead
of via variables */
generate_calls_with_direct_access
@@ -116,7 +116,7 @@ extern int icache_size;
/* Instruction expansion?
- Should the semantic code for each instruction, when the oportunity
+ Should the semantic code for each instruction, when the opportunity
arrises, be expanded according to the variable opcode files that
the instruction decode process renders constant */
diff --git a/sim/ppc/interrupts.h b/sim/ppc/interrupts.h
index 7171129..ee1f908 100644
--- a/sim/ppc/interrupts.h
+++ b/sim/ppc/interrupts.h
@@ -31,9 +31,9 @@
Interrupts that must immediately force either an abort or restart
of a current instruction are implemented by forcing an instruction
restart. (or to put it another way, long jump). In looking at the
- code it may occure to you that, for some interrupts, they could
+ code it may occur to you that, for some interrupts, they could
return instead of restarting the cpu (eg system_call). While true
- (it once was like that) I've decided to make the behavour of all
+ (it once was like that) I've decided to make the behavior of all
interrupt routines roughly identical.
Because, a cpu's recorded state (ie what is in the cpu structure)
diff --git a/sim/ppc/ld-decode.h b/sim/ppc/ld-decode.h
index 3e64477..9833393 100644
--- a/sim/ppc/ld-decode.h
+++ b/sim/ppc/ld-decode.h
@@ -52,7 +52,7 @@
If an instruction field was found, enlarge the field size so that
it is forced to at least include bits starting from <force_first>
- (<force_last>). To stop this occuring, use <force_first> = <last>
+ (<force_last>). To stop this occurring, use <force_first> = <last>
+ 1 and <force_last> = <first> - 1.
<force_slash>
@@ -64,7 +64,7 @@
Treat any contained register (string) fields as constant when
determining the instruction field. For the instruction decode (and
- controled by IDECODE_EXPAND_SEMANTICS) this forces the expansion of
+ controlled by IDECODE_EXPAND_SEMANTICS) this forces the expansion of
what would otherwize be non constant bits of an instruction.
<use_switch>
diff --git a/sim/ppc/main.c b/sim/ppc/main.c
index 667c02f..9ca371d 100644
--- a/sim/ppc/main.c
+++ b/sim/ppc/main.c
@@ -252,7 +252,7 @@ zalloc(long size)
return memory;
}
-/* When a CNTRL-C occures, queue an event to shut down the simulation */
+/* When a CNTRL-C occurs, queue an event to shut down the simulation */
static RETSIGTYPE
cntrl_c(int sig)
diff --git a/sim/ppc/os_emul.h b/sim/ppc/os_emul.h
index fdc2579..256b6aa 100644
--- a/sim/ppc/os_emul.h
+++ b/sim/ppc/os_emul.h
@@ -35,7 +35,7 @@ INLINE_OS_EMUL\
/* System-call emulation - for user code. Instead of trapping system
- calls to kernel mode, the simulator emulates the kernels behavour */
+ calls to kernel mode, the simulator emulates the kernels behavior */
INLINE_OS_EMUL\
(void) os_emul_system_call
@@ -47,7 +47,7 @@ INLINE_OS_EMUL\
instructions are added to the instruction table that when executed
call this emulation function. The instruction call emulator should
verify the address that the instruction appears before emulating
- the required behavour. If the verification fails, a zero value
+ the required behavior. If the verification fails, a zero value
should be returned (indicating instruction illegal). */
INLINE_OS_EMUL\
diff --git a/sim/ppc/psim.c b/sim/ppc/psim.c
index 3e322e3..78ccfed 100644
--- a/sim/ppc/psim.c
+++ b/sim/ppc/psim.c
@@ -390,7 +390,7 @@ psim_options(device *root,
argp += 1;
}
/* force the trace node to process its options now *before* the tree
- initialization occures */
+ initialization occurs */
device_ioctl(tree_find_device(root, "/openprom/trace"),
NULL, 0,
device_ioctl_set_trace);
@@ -990,7 +990,7 @@ psim_write_register(psim *system,
processor = system->processors[which_cpu];
- /* If the data is comming in raw (target order), need to cook it
+ /* If the data is coming in raw (target order), need to cook it
into host order before putting it into PSIM's internal structures */
if (mode == raw_transfer) {
switch (description.size) {
diff --git a/sim/ppc/sim-endian.h b/sim/ppc/sim-endian.h
index 9a87333..8d7a893 100644
--- a/sim/ppc/sim-endian.h
+++ b/sim/ppc/sim-endian.h
@@ -60,7 +60,7 @@ INLINE_PSIM_ENDIAN(unsigned_4) endian_le2h_4(unsigned_4 x);
INLINE_PSIM_ENDIAN(unsigned_8) endian_le2h_8(unsigned_8 x);
-/* Host dependant:
+/* Host dependent:
The CPP below defines information about the compilation host. In
particular it defines the macro's:
diff --git a/sim/ppc/sim_calls.c b/sim/ppc/sim_calls.c
index 470c958..25f5f04 100644
--- a/sim/ppc/sim_calls.c
+++ b/sim/ppc/sim_calls.c
@@ -18,7 +18,7 @@
*/
-#include <signal.h> /* FIXME - should be machine dependant version */
+#include <signal.h> /* FIXME - should be machine dependent version */
#include <stdarg.h>
#include <ctype.h>
diff --git a/sim/ppc/std-config.h b/sim/ppc/std-config.h
index 7e6b8c2..2c2e751 100644
--- a/sim/ppc/std-config.h
+++ b/sim/ppc/std-config.h
@@ -102,7 +102,7 @@ extern int current_target_byte_order;
expect to see (VEA includes things like coherency and the time
base) while OEA is what an operating system expects to see. By
setting these to specific values, the build process is able to
- eliminate non relevent environment code
+ eliminate non relevant environment code
CURRENT_ENVIRONMENT specifies which of vea or oea is required for
the current runtime. */
@@ -126,7 +126,7 @@ extern int current_environment;
/* Events. Devices modeling real H/W need to be able to efficiently
schedule things to do at known times in the future. The event
- queue implements this. Unfortunatly this adds the need to check
+ queue implements this. Unfortunately this adds the need to check
for any events once each full instruction cycle. */
#define WITH_EVENTS (WITH_ENVIRONMENT != USER_ENVIRONMENT)
@@ -182,7 +182,7 @@ extern int current_environment;
This model. Instead allows both little and big endian modes to
either take exceptions or handle miss aligned transfers.
- If 0 is specified then for big-endian mode miss alligned accesses
+ If 0 is specified then for big-endian mode miss aligned accesses
are permitted (NONSTRICT_ALIGNMENT) while in little-endian mode the
processor will fault on them (STRICT_ALIGNMENT). */
@@ -285,7 +285,7 @@ extern int current_stdio;
speed improvement (x3-x5). In the case of RISC (sparc) while the
performance gain isn't as great it is still significant.
- Each module is controled by the macro <module>_INLINE which can
+ Each module is controlled by the macro <module>_INLINE which can
have the values described below
0 Do not inline any thing for the given module
@@ -385,7 +385,7 @@ extern int current_stdio;
Prefix to any declaration of a global object (function or
variable) that should not be inlined and should have only one
definition. The #ifndef wrapper goes around the definition
- propper to ensure that only one copy is generated.
+ proper to ensure that only one copy is generated.
nb: this will not work when a module is being inlined for every
use.
@@ -494,7 +494,7 @@ extern int current_stdio;
#define MON_INLINE (DEFAULT_INLINE ? ALL_INLINE : 0)
#endif
-/* Code called on the rare occasions that an interrupt occures. */
+/* Code called on the rare occasions that an interrupt occurs. */
#ifndef INTERRUPTS_INLINE
#define INTERRUPTS_INLINE DEFAULT_INLINE
diff --git a/sim/ppc/tree.c b/sim/ppc/tree.c
index 5d20bf4..45fdc93 100644
--- a/sim/ppc/tree.c
+++ b/sim/ppc/tree.c
@@ -454,7 +454,7 @@ count_entries(device *current,
-/* parse: <address> ::= <token> ; device dependant */
+/* parse: <address> ::= <token> ; device dependent */
STATIC_INLINE_TREE\
(const char *)
@@ -1230,7 +1230,7 @@ tree_find_device(device *root,
/* parse the path */
split_device_specifier(root, path_to_device, &spec);
if (spec.value != NULL)
- return NULL; /* something wierd */
+ return NULL; /* something weird */
/* now find it */
node = split_find_device(root, &spec);
diff --git a/sim/ppc/tree.h b/sim/ppc/tree.h
index 165612c..6f2eed2 100644
--- a/sim/ppc/tree.h
+++ b/sim/ppc/tree.h
@@ -35,7 +35,7 @@
This function accepts a printf style formatted string as the
argument that describes the entry. Any properties or interrupt
connections added to a device tree using this function are marked
- as having a permenant disposition. When the tree is (re)
+ as having a permanent disposition. When the tree is (re)
initialized they will be restored to their initial value.
*/
@@ -129,7 +129,7 @@ INLINE_TREE\
Once a device tree has been created the <<device_tree_init()>>
function is used to initialize it. The exact sequence of events
- that occure during initialization are described separatly.
+ that occur during initialization is described separately.
*/
diff --git a/sim/ppc/vm.c b/sim/ppc/vm.c
index 8cf4e8f..71e2c73 100644
--- a/sim/ppc/vm.c
+++ b/sim/ppc/vm.c
@@ -444,7 +444,7 @@ om_write_word(om_map *map,
}
-/* Bring things into existance */
+/* Bring things into existence */
INLINE_VM\
(vm *)
diff --git a/sim/ppc/vm.h b/sim/ppc/vm.h
index 63dc23c..f010664 100644
--- a/sim/ppc/vm.h
+++ b/sim/ppc/vm.h
@@ -59,8 +59,8 @@ INLINE_VM\
unsigned_word cia);
-/* generic block transfers. Dependant on the presence of the
- PROCESSOR arg, either returns the number of bytes transfered or (if
+/* generic block transfers. Dependent on the presence of the
+ PROCESSOR arg, either returns the number of bytes transferred or (if
PROCESSOR is non NULL) aborts the simulation */
INLINE_VM\
diff --git a/sim/sh/interp.c b/sim/sh/interp.c
index 32618ba..6793997 100644
--- a/sim/sh/interp.c
+++ b/sim/sh/interp.c
@@ -158,7 +158,7 @@ static int maskl = 0;
/* Alternate bank of registers r0-r7 */
-/* Note: code controling SR handles flips between BANK0 and BANK1 */
+/* Note: code controlling SR handles flips between BANK0 and BANK1 */
#define Rn_BANK(n) (saved_state.asregs.cregs.named.bank[(n)])
#define SET_Rn_BANK(n, EXP) do { saved_state.asregs.cregs.named.bank[(n)] = (EXP); } while (0)
@@ -738,7 +738,7 @@ static int nsamples;
#define SSR1 (0x05FFFECC) /* Channel 1 serial status register */
#define RDR1 (0x05FFFECD) /* Channel 1 receive data register */
-#define SCI_RDRF 0x40 /* Recieve data register full */
+#define SCI_RDRF 0x40 /* Receive data register full */
#define SCI_TDRE 0x80 /* Transmit data register empty */
static int
@@ -1269,7 +1269,7 @@ macl (int *regs, unsigned char *memory, int n, int m)
mach |= 0xffff8000; /* Sign extend higher 16 bits */
}
else
- mach = mach & 0x00007fff; /* Postive Result */
+ mach = mach & 0x00007fff; /* Positive Result */
}
MACL = macl;
diff --git a/sim/sh/sim-main.h b/sim/sh/sim-main.h
index 4af7b03..b07a029 100644
--- a/sim/sh/sim-main.h
+++ b/sim/sh/sim-main.h
@@ -40,7 +40,7 @@ typedef union
out-of-bounds accesses of sregs.i . This wart of the code could be
fixed by making fregs part of sregs, and including pc too - to avoid
alignment repercussions - but this would cause very onerous union /
- structure nesting, which would only be managable with anonymous
+ structure nesting, which would only be manageable with anonymous
unions and structs. */
union
{
diff --git a/sim/v850/sim-main.h b/sim/v850/sim-main.h
index e7276a6..41bb2eb 100644
--- a/sim/v850/sim-main.h
+++ b/sim/v850/sim-main.h
@@ -35,7 +35,7 @@ typedef struct _v850_regs {
reg_t mpu0_sregs[28]; /* mpu0 system registers */
reg_t mpu1_sregs[28]; /* mpu1 system registers */
reg_t fpu_sregs[28]; /* fpu system registers */
- reg_t selID_sregs[7][32]; /* system registers, selID 1 thru selID 7 */
+ reg_t selID_sregs[7][32]; /* system registers, selID 1 through selID 7 */
reg64_t vregs[32]; /* vector registers. */
} v850_regs;
diff --git a/sim/v850/simops.c b/sim/v850/simops.c
index 40d578e..7714dd9 100644
--- a/sim/v850/simops.c
+++ b/sim/v850/simops.c
@@ -360,7 +360,7 @@ Multiply64 (int sign, unsigned long op0)
hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
/* We now need to add all of these results together, taking care
- to propogate the carries from the additions: */
+ to propagate the carries from the additions: */
RdLo = Add32 (lo, (mid1 << 16), & carry);
RdHi = carry;
RdLo = Add32 (RdLo, (mid2 << 16), & carry);
--
2.7.4
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH 2/5] Fix spelling in comments in Assembler files (sim)
2016-11-25 19:46 [PATCH 0/5] Fix spelling mistakes in comments - SIM Ambrogino Modigliani
` (3 preceding siblings ...)
2016-11-25 19:47 ` [PATCH 5/5] Fix spelling in comments in .inc " Ambrogino Modigliani
@ 2016-11-25 19:47 ` Ambrogino Modigliani
2016-11-25 20:41 ` [PATCH 0/5] Fix spelling mistakes in comments - SIM Mike Frysinger
5 siblings, 0 replies; 7+ messages in thread
From: Ambrogino Modigliani @ 2016-11-25 19:47 UTC (permalink / raw)
To: gdb-patches, pedro_alves, ambrogino.modigliani, ambrogino.modigliani
sim/testsuite/ChangeLog:
* d10v-elf/t-macros.i: Fix spelling in comments.
* sim/bfin/divq.s: Fix spelling in comments.
* sim/bfin/se_illegalcombination.S: Fix spelling in comments.
* sim/bfin/se_undefinedinstruction1.S: Fix spelling in comments.
* sim/bfin/se_undefinedinstruction2.S: Fix spelling in comments.
* sim/fr30/addsp.cgs: Fix spelling in comments.
* sim/fr30/bc.cgs: Fix spelling in comments.
* sim/fr30/beq.cgs: Fix spelling in comments.
* sim/fr30/bge.cgs: Fix spelling in comments.
* sim/fr30/bgt.cgs: Fix spelling in comments.
* sim/fr30/bhi.cgs: Fix spelling in comments.
* sim/fr30/ble.cgs: Fix spelling in comments.
* sim/fr30/bls.cgs: Fix spelling in comments.
* sim/fr30/blt.cgs: Fix spelling in comments.
* sim/fr30/bn.cgs: Fix spelling in comments.
* sim/fr30/bnc.cgs: Fix spelling in comments.
* sim/fr30/bne.cgs: Fix spelling in comments.
* sim/fr30/bno.cgs: Fix spelling in comments.
* sim/fr30/bnv.cgs: Fix spelling in comments.
* sim/fr30/bp.cgs: Fix spelling in comments.
* sim/fr30/bra.cgs: Fix spelling in comments.
* sim/fr30/bv.cgs: Fix spelling in comments.
* sim/fr30/copld.cgs: Fix spelling in comments.
* sim/fr30/copop.cgs: Fix spelling in comments.
* sim/fr30/copst.cgs: Fix spelling in comments.
* sim/fr30/copsv.cgs: Fix spelling in comments.
* sim/fr30/enter.cgs: Fix spelling in comments.
* sim/fr30/extsb.cgs: Fix spelling in comments.
* sim/fr30/extsh.cgs: Fix spelling in comments.
* sim/fr30/extub.cgs: Fix spelling in comments.
* sim/fr30/extuh.cgs: Fix spelling in comments.
* sim/fr30/ldres.cgs: Fix spelling in comments.
* sim/fr30/leave.cgs: Fix spelling in comments.
* sim/fr30/nop.cgs: Fix spelling in comments.
* sim/fr30/stres.cgs: Fix spelling in comments.
* sim/fr30/xchb.cgs: Fix spelling in comments.
* sim/h8300/ldc.s: Fix spelling in comments.
* sim/h8300/stc.s: Fix spelling in comments.
* sim/mips/hilo-hazard-3.s: Fix spelling in comments.
* sim/mips/hilo-hazard-4.s: Fix spelling in comments.
* sim/sh/fipr.s: Fix spelling in comments.
---
sim/testsuite/d10v-elf/t-macros.i | 2 +-
sim/testsuite/sim/bfin/divq.s | 2 +-
sim/testsuite/sim/bfin/se_illegalcombination.S | 2 +-
sim/testsuite/sim/bfin/se_undefinedinstruction1.S | 2 +-
sim/testsuite/sim/bfin/se_undefinedinstruction2.S | 4 +-
sim/testsuite/sim/fr30/addsp.cgs | 6 +--
sim/testsuite/sim/fr30/bc.cgs | 64 +++++++++++------------
sim/testsuite/sim/fr30/beq.cgs | 64 +++++++++++------------
sim/testsuite/sim/fr30/bge.cgs | 64 +++++++++++------------
sim/testsuite/sim/fr30/bgt.cgs | 64 +++++++++++------------
sim/testsuite/sim/fr30/bhi.cgs | 64 +++++++++++------------
sim/testsuite/sim/fr30/ble.cgs | 64 +++++++++++------------
sim/testsuite/sim/fr30/bls.cgs | 64 +++++++++++------------
sim/testsuite/sim/fr30/blt.cgs | 64 +++++++++++------------
sim/testsuite/sim/fr30/bn.cgs | 64 +++++++++++------------
sim/testsuite/sim/fr30/bnc.cgs | 64 +++++++++++------------
sim/testsuite/sim/fr30/bne.cgs | 64 +++++++++++------------
sim/testsuite/sim/fr30/bno.cgs | 64 +++++++++++------------
sim/testsuite/sim/fr30/bnv.cgs | 64 +++++++++++------------
sim/testsuite/sim/fr30/bp.cgs | 64 +++++++++++------------
sim/testsuite/sim/fr30/bra.cgs | 64 +++++++++++------------
sim/testsuite/sim/fr30/bv.cgs | 64 +++++++++++------------
sim/testsuite/sim/fr30/copld.cgs | 4 +-
sim/testsuite/sim/fr30/copop.cgs | 4 +-
sim/testsuite/sim/fr30/copst.cgs | 4 +-
sim/testsuite/sim/fr30/copsv.cgs | 4 +-
sim/testsuite/sim/fr30/enter.cgs | 4 +-
sim/testsuite/sim/fr30/extsb.cgs | 8 +--
sim/testsuite/sim/fr30/extsh.cgs | 12 ++---
sim/testsuite/sim/fr30/extub.cgs | 10 ++--
sim/testsuite/sim/fr30/extuh.cgs | 14 ++---
sim/testsuite/sim/fr30/ldres.cgs | 4 +-
sim/testsuite/sim/fr30/leave.cgs | 2 +-
sim/testsuite/sim/fr30/nop.cgs | 2 +-
sim/testsuite/sim/fr30/stres.cgs | 4 +-
sim/testsuite/sim/fr30/xchb.cgs | 2 +-
sim/testsuite/sim/h8300/ldc.s | 4 +-
sim/testsuite/sim/h8300/stc.s | 4 +-
sim/testsuite/sim/mips/hilo-hazard-3.s | 2 +-
sim/testsuite/sim/mips/hilo-hazard-4.s | 2 +-
sim/testsuite/sim/sh/fipr.s | 2 +-
41 files changed, 567 insertions(+), 567 deletions(-)
diff --git a/sim/testsuite/d10v-elf/t-macros.i b/sim/testsuite/d10v-elf/t-macros.i
index f424acf..0de38d4 100644
--- a/sim/testsuite/d10v-elf/t-macros.i
+++ b/sim/testsuite/d10v-elf/t-macros.i
@@ -170,7 +170,7 @@ _start:
.data
1: ldi r1, 2f@word
jmp r1
-;;; Successfull trap jumps back to here
+;;; Successful trap jumps back to here
.text
;;; Verify the PSW
2: mvfc r2, cr0
diff --git a/sim/testsuite/sim/bfin/divq.s b/sim/testsuite/sim/bfin/divq.s
index 6cb881b..61880c7 100644
--- a/sim/testsuite/sim/bfin/divq.s
+++ b/sim/testsuite/sim/bfin/divq.s
@@ -7,7 +7,7 @@
start
/*
- * Evaluate given a signed integer dividend and signed interger divisor
+ * Evaluate given a signed integer dividend and signed integer divisor
* input is:
* r0 = dividend, or numerator
* r1 = divisor, or denominator
diff --git a/sim/testsuite/sim/bfin/se_illegalcombination.S b/sim/testsuite/sim/bfin/se_illegalcombination.S
index 0fe5f27..bd8f333 100644
--- a/sim/testsuite/sim/bfin/se_illegalcombination.S
+++ b/sim/testsuite/sim/bfin/se_illegalcombination.S
@@ -2,7 +2,7 @@
// Description: Multi-issue Illegal Combinations
# mach: bfin
# sim: --environment operating
-# xfail: "missing a few checks; hardware doesnt seem to match PRM?" bfin-*
+# xfail: "missing a few checks; hardware doesn't seem to match PRM?" bfin-*
#include "test.h"
.include "testutils.inc"
diff --git a/sim/testsuite/sim/bfin/se_undefinedinstruction1.S b/sim/testsuite/sim/bfin/se_undefinedinstruction1.S
index 5337a74..fa1ab72 100644
--- a/sim/testsuite/sim/bfin/se_undefinedinstruction1.S
+++ b/sim/testsuite/sim/bfin/se_undefinedinstruction1.S
@@ -200,7 +200,7 @@ BEGIN:
.dw 0x21 ;
.dw 0x22 ;
.dw 0x26 ;
- .dw 0x27 ; // XXX: hardware doesnt trigger illegal exception ?
+ .dw 0x27 ; // XXX: hardware doesn't trigger illegal exception ?
.dw 0x28 ;
.dw 0x29 ;
.dw 0x2A ;
diff --git a/sim/testsuite/sim/bfin/se_undefinedinstruction2.S b/sim/testsuite/sim/bfin/se_undefinedinstruction2.S
index d21e375..9d68ccb 100644
--- a/sim/testsuite/sim/bfin/se_undefinedinstruction2.S
+++ b/sim/testsuite/sim/bfin/se_undefinedinstruction2.S
@@ -175,12 +175,12 @@ BEGIN:
.dw 0x10E ;
.dw 0x124 ;
.ifndef BFIN_HW
- // XXX: hardware doesnt trigger illegal exception ?
+ // XXX: hardware doesn't trigger illegal exception ?
.dw 0x125 ;
.endif
.dw 0x164 ;
.ifndef BFIN_HW
- // XXX: hardware doesnt trigger illegal exception ?
+ // XXX: hardware doesn't trigger illegal exception ?
.dw 0x165 ;
.endif
.dw 0x128 ;
diff --git a/sim/testsuite/sim/fr30/addsp.cgs b/sim/testsuite/sim/fr30/addsp.cgs
index da5bc36..d12eefd 100644
--- a/sim/testsuite/sim/fr30/addsp.cgs
+++ b/sim/testsuite/sim/fr30/addsp.cgs
@@ -11,18 +11,18 @@ addsp:
; Test addsp $s10
mvr_h_gr sp,r7 ; save stack pointer permanently
mvr_h_gr sp,r8 ; Shadow updated sp
- set_cc 0x0f ; Condition codes are irrelevent
+ set_cc 0x0f ; Condition codes are irrelevant
addsp 508
test_cc 1 1 1 1
inci_h_gr 508,r8
testr_h_gr r8,sp
- set_cc 0x0e ; Condition codes are irrelevent
+ set_cc 0x0e ; Condition codes are irrelevant
addsp 0
test_cc 1 1 1 0
testr_h_gr r8,sp
- set_cc 0x0d ; Condition codes are irrelevent
+ set_cc 0x0d ; Condition codes are irrelevant
addsp -512
test_cc 1 1 0 1
inci_h_gr -512,r8
diff --git a/sim/testsuite/sim/fr30/bc.cgs b/sim/testsuite/sim/fr30/bc.cgs
index 0502625..e2233a1 100644
--- a/sim/testsuite/sim/fr30/bc.cgs
+++ b/sim/testsuite/sim/fr30/bc.cgs
@@ -9,101 +9,101 @@
.global bc
bc:
; Test bc $label9
- set_cc 0x0f ; condition codes are irrelevent
+ set_cc 0x0f ; condition codes are irrelevant
take_branch bc
- set_cc 0x0e ; condition codes are irrelevent
+ set_cc 0x0e ; condition codes are irrelevant
no_branch bc
- set_cc 0x0d ; condition codes are irrelevent
+ set_cc 0x0d ; condition codes are irrelevant
take_branch bc
- set_cc 0x0c ; condition codes are irrelevent
+ set_cc 0x0c ; condition codes are irrelevant
no_branch bc
- set_cc 0x0b ; condition codes are irrelevent
+ set_cc 0x0b ; condition codes are irrelevant
take_branch bc
- set_cc 0x0a ; condition codes are irrelevent
+ set_cc 0x0a ; condition codes are irrelevant
no_branch bc
- set_cc 0x09 ; condition codes are irrelevent
+ set_cc 0x09 ; condition codes are irrelevant
take_branch bc
- set_cc 0x08 ; condition codes are irrelevent
+ set_cc 0x08 ; condition codes are irrelevant
no_branch bc
- set_cc 0x07 ; condition codes are irrelevent
+ set_cc 0x07 ; condition codes are irrelevant
take_branch bc
- set_cc 0x06 ; condition codes are irrelevent
+ set_cc 0x06 ; condition codes are irrelevant
no_branch bc
- set_cc 0x05 ; condition codes are irrelevent
+ set_cc 0x05 ; condition codes are irrelevant
take_branch bc
- set_cc 0x04 ; condition codes are irrelevent
+ set_cc 0x04 ; condition codes are irrelevant
no_branch bc
- set_cc 0x03 ; condition codes are irrelevent
+ set_cc 0x03 ; condition codes are irrelevant
take_branch bc
- set_cc 0x02 ; condition codes are irrelevent
+ set_cc 0x02 ; condition codes are irrelevant
no_branch bc
- set_cc 0x01 ; condition codes are irrelevent
+ set_cc 0x01 ; condition codes are irrelevant
take_branch bc
- set_cc 0x00 ; condition codes are irrelevent
+ set_cc 0x00 ; condition codes are irrelevant
no_branch bc
; Test bc:d label9
- set_cc 0x0f ; condition codes are irrelevent
+ set_cc 0x0f ; condition codes are irrelevant
take_branch_d bc:d 0xf
- set_cc 0x0e ; condition codes are irrelevent
+ set_cc 0x0e ; condition codes are irrelevant
no_branch_d bc:d 0xe
- set_cc 0x0d ; condition codes are irrelevent
+ set_cc 0x0d ; condition codes are irrelevant
take_branch_d bc:d 0xd
- set_cc 0x0c ; condition codes are irrelevent
+ set_cc 0x0c ; condition codes are irrelevant
no_branch_d bc:d 0xc
- set_cc 0x0b ; condition codes are irrelevent
+ set_cc 0x0b ; condition codes are irrelevant
take_branch_d bc:d 0xb
- set_cc 0x0a ; condition codes are irrelevent
+ set_cc 0x0a ; condition codes are irrelevant
no_branch_d bc:d 0xa
- set_cc 0x09 ; condition codes are irrelevent
+ set_cc 0x09 ; condition codes are irrelevant
take_branch_d bc:d 0x9
- set_cc 0x08 ; condition codes are irrelevent
+ set_cc 0x08 ; condition codes are irrelevant
no_branch_d bc:d 0x8
- set_cc 0x07 ; condition codes are irrelevent
+ set_cc 0x07 ; condition codes are irrelevant
take_branch_d bc:d 0x7
- set_cc 0x06 ; condition codes are irrelevent
+ set_cc 0x06 ; condition codes are irrelevant
no_branch_d bc:d 0x6
- set_cc 0x05 ; condition codes are irrelevent
+ set_cc 0x05 ; condition codes are irrelevant
take_branch_d bc:d 0x5
- set_cc 0x04 ; condition codes are irrelevent
+ set_cc 0x04 ; condition codes are irrelevant
no_branch_d bc:d 0x4
- set_cc 0x03 ; condition codes are irrelevent
+ set_cc 0x03 ; condition codes are irrelevant
take_branch_d bc:d 0x3
- set_cc 0x02 ; condition codes are irrelevent
+ set_cc 0x02 ; condition codes are irrelevant
no_branch_d bc:d 0x2
- set_cc 0x01 ; condition codes are irrelevent
+ set_cc 0x01 ; condition codes are irrelevant
take_branch_d bc:d 0x1
- set_cc 0x00 ; condition codes are irrelevent
+ set_cc 0x00 ; condition codes are irrelevant
no_branch_d bc:d 0x0
pass
diff --git a/sim/testsuite/sim/fr30/beq.cgs b/sim/testsuite/sim/fr30/beq.cgs
index edd797e..443ebbe 100644
--- a/sim/testsuite/sim/fr30/beq.cgs
+++ b/sim/testsuite/sim/fr30/beq.cgs
@@ -9,101 +9,101 @@
.global beq
beq:
; Test beq $label9
- set_cc 0x0f ; condition codes are irrelevent
+ set_cc 0x0f ; condition codes are irrelevant
take_branch beq
- set_cc 0x0e ; condition codes are irrelevent
+ set_cc 0x0e ; condition codes are irrelevant
take_branch beq
- set_cc 0x0d ; condition codes are irrelevent
+ set_cc 0x0d ; condition codes are irrelevant
take_branch beq
- set_cc 0x0c ; condition codes are irrelevent
+ set_cc 0x0c ; condition codes are irrelevant
take_branch beq
- set_cc 0x0b ; condition codes are irrelevent
+ set_cc 0x0b ; condition codes are irrelevant
no_branch beq
- set_cc 0x0a ; condition codes are irrelevent
+ set_cc 0x0a ; condition codes are irrelevant
no_branch beq
- set_cc 0x09 ; condition codes are irrelevent
+ set_cc 0x09 ; condition codes are irrelevant
no_branch beq
- set_cc 0x08 ; condition codes are irrelevent
+ set_cc 0x08 ; condition codes are irrelevant
no_branch beq
- set_cc 0x07 ; condition codes are irrelevent
+ set_cc 0x07 ; condition codes are irrelevant
take_branch beq
- set_cc 0x06 ; condition codes are irrelevent
+ set_cc 0x06 ; condition codes are irrelevant
take_branch beq
- set_cc 0x05 ; condition codes are irrelevent
+ set_cc 0x05 ; condition codes are irrelevant
take_branch beq
- set_cc 0x04 ; condition codes are irrelevent
+ set_cc 0x04 ; condition codes are irrelevant
take_branch beq
- set_cc 0x03 ; condition codes are irrelevent
+ set_cc 0x03 ; condition codes are irrelevant
no_branch beq
- set_cc 0x02 ; condition codes are irrelevent
+ set_cc 0x02 ; condition codes are irrelevant
no_branch beq
- set_cc 0x01 ; condition codes are irrelevent
+ set_cc 0x01 ; condition codes are irrelevant
no_branch beq
- set_cc 0x00 ; condition codes are irrelevent
+ set_cc 0x00 ; condition codes are irrelevant
no_branch beq
; Test beq:d label9
- set_cc 0x0f ; condition codes are irrelevent
+ set_cc 0x0f ; condition codes are irrelevant
take_branch_d beq:d 0xf
- set_cc 0x0e ; condition codes are irrelevent
+ set_cc 0x0e ; condition codes are irrelevant
take_branch_d beq:d 0xe
- set_cc 0x0d ; condition codes are irrelevent
+ set_cc 0x0d ; condition codes are irrelevant
take_branch_d beq:d 0xd
- set_cc 0x0c ; condition codes are irrelevent
+ set_cc 0x0c ; condition codes are irrelevant
take_branch_d beq:d 0xc
- set_cc 0x0b ; condition codes are irrelevent
+ set_cc 0x0b ; condition codes are irrelevant
no_branch_d beq:d 0xb
- set_cc 0x0a ; condition codes are irrelevent
+ set_cc 0x0a ; condition codes are irrelevant
no_branch_d beq:d 0xa
- set_cc 0x09 ; condition codes are irrelevent
+ set_cc 0x09 ; condition codes are irrelevant
no_branch_d beq:d 0x9
- set_cc 0x08 ; condition codes are irrelevent
+ set_cc 0x08 ; condition codes are irrelevant
no_branch_d beq:d 0x8
- set_cc 0x07 ; condition codes are irrelevent
+ set_cc 0x07 ; condition codes are irrelevant
take_branch_d beq:d 0x7
- set_cc 0x06 ; condition codes are irrelevent
+ set_cc 0x06 ; condition codes are irrelevant
take_branch_d beq:d 0x6
- set_cc 0x05 ; condition codes are irrelevent
+ set_cc 0x05 ; condition codes are irrelevant
take_branch_d beq:d 0x5
- set_cc 0x04 ; condition codes are irrelevent
+ set_cc 0x04 ; condition codes are irrelevant
take_branch_d beq:d 0x4
- set_cc 0x03 ; condition codes are irrelevent
+ set_cc 0x03 ; condition codes are irrelevant
no_branch_d beq:d 0x3
- set_cc 0x02 ; condition codes are irrelevent
+ set_cc 0x02 ; condition codes are irrelevant
no_branch_d beq:d 0x2
- set_cc 0x01 ; condition codes are irrelevent
+ set_cc 0x01 ; condition codes are irrelevant
no_branch_d beq:d 0x1
- set_cc 0x00 ; condition codes are irrelevent
+ set_cc 0x00 ; condition codes are irrelevant
no_branch_d beq:d 0x0
pass
diff --git a/sim/testsuite/sim/fr30/bge.cgs b/sim/testsuite/sim/fr30/bge.cgs
index dd7796c..6db3f3e 100644
--- a/sim/testsuite/sim/fr30/bge.cgs
+++ b/sim/testsuite/sim/fr30/bge.cgs
@@ -9,101 +9,101 @@
.global bge
bge:
; Test bge $label9
- set_cc 0x0f ; condition codes are irrelevent
+ set_cc 0x0f ; condition codes are irrelevant
take_branch bge
- set_cc 0x0e ; condition codes are irrelevent
+ set_cc 0x0e ; condition codes are irrelevant
take_branch bge
- set_cc 0x0d ; condition codes are irrelevent
+ set_cc 0x0d ; condition codes are irrelevant
no_branch bge
- set_cc 0x0c ; condition codes are irrelevent
+ set_cc 0x0c ; condition codes are irrelevant
no_branch bge
- set_cc 0x0b ; condition codes are irrelevent
+ set_cc 0x0b ; condition codes are irrelevant
take_branch bge
- set_cc 0x0a ; condition codes are irrelevent
+ set_cc 0x0a ; condition codes are irrelevant
take_branch bge
- set_cc 0x09 ; condition codes are irrelevent
+ set_cc 0x09 ; condition codes are irrelevant
no_branch bge
- set_cc 0x08 ; condition codes are irrelevent
+ set_cc 0x08 ; condition codes are irrelevant
no_branch bge
- set_cc 0x07 ; condition codes are irrelevent
+ set_cc 0x07 ; condition codes are irrelevant
no_branch bge
- set_cc 0x06 ; condition codes are irrelevent
+ set_cc 0x06 ; condition codes are irrelevant
no_branch bge
- set_cc 0x05 ; condition codes are irrelevent
+ set_cc 0x05 ; condition codes are irrelevant
take_branch bge
- set_cc 0x04 ; condition codes are irrelevent
+ set_cc 0x04 ; condition codes are irrelevant
take_branch bge
- set_cc 0x03 ; condition codes are irrelevent
+ set_cc 0x03 ; condition codes are irrelevant
no_branch bge
- set_cc 0x02 ; condition codes are irrelevent
+ set_cc 0x02 ; condition codes are irrelevant
no_branch bge
- set_cc 0x01 ; condition codes are irrelevent
+ set_cc 0x01 ; condition codes are irrelevant
take_branch bge
- set_cc 0x00 ; condition codes are irrelevent
+ set_cc 0x00 ; condition codes are irrelevant
take_branch bge
; Test bge:d label9
- set_cc 0x0f ; condition codes are irrelevent
+ set_cc 0x0f ; condition codes are irrelevant
take_branch_d bge:d 0xf
- set_cc 0x0e ; condition codes are irrelevent
+ set_cc 0x0e ; condition codes are irrelevant
take_branch_d bge:d 0xe
- set_cc 0x0d ; condition codes are irrelevent
+ set_cc 0x0d ; condition codes are irrelevant
no_branch_d bge:d 0xd
- set_cc 0x0c ; condition codes are irrelevent
+ set_cc 0x0c ; condition codes are irrelevant
no_branch_d bge:d 0xc
- set_cc 0x0b ; condition codes are irrelevent
+ set_cc 0x0b ; condition codes are irrelevant
take_branch_d bge:d 0xb
- set_cc 0x0a ; condition codes are irrelevent
+ set_cc 0x0a ; condition codes are irrelevant
take_branch_d bge:d 0xa
- set_cc 0x09 ; condition codes are irrelevent
+ set_cc 0x09 ; condition codes are irrelevant
no_branch_d bge:d 0x9
- set_cc 0x08 ; condition codes are irrelevent
+ set_cc 0x08 ; condition codes are irrelevant
no_branch_d bge:d 0x8
- set_cc 0x07 ; condition codes are irrelevent
+ set_cc 0x07 ; condition codes are irrelevant
no_branch_d bge:d 0x7
- set_cc 0x06 ; condition codes are irrelevent
+ set_cc 0x06 ; condition codes are irrelevant
no_branch_d bge:d 0x6
- set_cc 0x05 ; condition codes are irrelevent
+ set_cc 0x05 ; condition codes are irrelevant
take_branch_d bge:d 0x5
- set_cc 0x04 ; condition codes are irrelevent
+ set_cc 0x04 ; condition codes are irrelevant
take_branch_d bge:d 0x4
- set_cc 0x03 ; condition codes are irrelevent
+ set_cc 0x03 ; condition codes are irrelevant
no_branch_d bge:d 0x3
- set_cc 0x02 ; condition codes are irrelevent
+ set_cc 0x02 ; condition codes are irrelevant
no_branch_d bge:d 0x2
- set_cc 0x01 ; condition codes are irrelevent
+ set_cc 0x01 ; condition codes are irrelevant
take_branch_d bge:d 0x1
- set_cc 0x00 ; condition codes are irrelevent
+ set_cc 0x00 ; condition codes are irrelevant
take_branch_d bge:d 0x0
pass
diff --git a/sim/testsuite/sim/fr30/bgt.cgs b/sim/testsuite/sim/fr30/bgt.cgs
index 525ac2e..f4924eb 100644
--- a/sim/testsuite/sim/fr30/bgt.cgs
+++ b/sim/testsuite/sim/fr30/bgt.cgs
@@ -9,101 +9,101 @@
.global bgt
bgt:
; Test bgt $label9
- set_cc 0x0f ; condition codes are irrelevent
+ set_cc 0x0f ; condition codes are irrelevant
no_branch bgt
- set_cc 0x0e ; condition codes are irrelevent
+ set_cc 0x0e ; condition codes are irrelevant
no_branch bgt
- set_cc 0x0d ; condition codes are irrelevent
+ set_cc 0x0d ; condition codes are irrelevant
no_branch bgt
- set_cc 0x0c ; condition codes are irrelevent
+ set_cc 0x0c ; condition codes are irrelevant
no_branch bgt
- set_cc 0x0b ; condition codes are irrelevent
+ set_cc 0x0b ; condition codes are irrelevant
take_branch bgt
- set_cc 0x0a ; condition codes are irrelevent
+ set_cc 0x0a ; condition codes are irrelevant
take_branch bgt
- set_cc 0x09 ; condition codes are irrelevent
+ set_cc 0x09 ; condition codes are irrelevant
no_branch bgt
- set_cc 0x08 ; condition codes are irrelevent
+ set_cc 0x08 ; condition codes are irrelevant
no_branch bgt
- set_cc 0x07 ; condition codes are irrelevent
+ set_cc 0x07 ; condition codes are irrelevant
no_branch bgt
- set_cc 0x06 ; condition codes are irrelevent
+ set_cc 0x06 ; condition codes are irrelevant
no_branch bgt
- set_cc 0x05 ; condition codes are irrelevent
+ set_cc 0x05 ; condition codes are irrelevant
no_branch bgt
- set_cc 0x04 ; condition codes are irrelevent
+ set_cc 0x04 ; condition codes are irrelevant
no_branch bgt
- set_cc 0x03 ; condition codes are irrelevent
+ set_cc 0x03 ; condition codes are irrelevant
no_branch bgt
- set_cc 0x02 ; condition codes are irrelevent
+ set_cc 0x02 ; condition codes are irrelevant
no_branch bgt
- set_cc 0x01 ; condition codes are irrelevent
+ set_cc 0x01 ; condition codes are irrelevant
take_branch bgt
- set_cc 0x00 ; condition codes are irrelevent
+ set_cc 0x00 ; condition codes are irrelevant
take_branch bgt
; Test bgt:d label9
- set_cc 0x0f ; condition codes are irrelevent
+ set_cc 0x0f ; condition codes are irrelevant
no_branch_d bgt:d 0xf
- set_cc 0x0e ; condition codes are irrelevent
+ set_cc 0x0e ; condition codes are irrelevant
no_branch_d bgt:d 0xe
- set_cc 0x0d ; condition codes are irrelevent
+ set_cc 0x0d ; condition codes are irrelevant
no_branch_d bgt:d 0xd
- set_cc 0x0c ; condition codes are irrelevent
+ set_cc 0x0c ; condition codes are irrelevant
no_branch_d bgt:d 0xc
- set_cc 0x0b ; condition codes are irrelevent
+ set_cc 0x0b ; condition codes are irrelevant
take_branch_d bgt:d 0xb
- set_cc 0x0a ; condition codes are irrelevent
+ set_cc 0x0a ; condition codes are irrelevant
take_branch_d bgt:d 0xa
- set_cc 0x09 ; condition codes are irrelevent
+ set_cc 0x09 ; condition codes are irrelevant
no_branch_d bgt:d 0x9
- set_cc 0x08 ; condition codes are irrelevent
+ set_cc 0x08 ; condition codes are irrelevant
no_branch_d bgt:d 0x8
- set_cc 0x07 ; condition codes are irrelevent
+ set_cc 0x07 ; condition codes are irrelevant
no_branch_d bgt:d 0x7
- set_cc 0x06 ; condition codes are irrelevent
+ set_cc 0x06 ; condition codes are irrelevant
no_branch_d bgt:d 0x6
- set_cc 0x05 ; condition codes are irrelevent
+ set_cc 0x05 ; condition codes are irrelevant
no_branch_d bgt:d 0x5
- set_cc 0x04 ; condition codes are irrelevent
+ set_cc 0x04 ; condition codes are irrelevant
no_branch_d bgt:d 0x4
- set_cc 0x03 ; condition codes are irrelevent
+ set_cc 0x03 ; condition codes are irrelevant
no_branch_d bgt:d 0x3
- set_cc 0x02 ; condition codes are irrelevent
+ set_cc 0x02 ; condition codes are irrelevant
no_branch_d bgt:d 0x2
- set_cc 0x01 ; condition codes are irrelevent
+ set_cc 0x01 ; condition codes are irrelevant
take_branch_d bgt:d 0x1
- set_cc 0x00 ; condition codes are irrelevent
+ set_cc 0x00 ; condition codes are irrelevant
take_branch_d bgt:d 0x0
pass
diff --git a/sim/testsuite/sim/fr30/bhi.cgs b/sim/testsuite/sim/fr30/bhi.cgs
index f5a1549..fb2bebf 100644
--- a/sim/testsuite/sim/fr30/bhi.cgs
+++ b/sim/testsuite/sim/fr30/bhi.cgs
@@ -9,101 +9,101 @@
.global bhi
bhi:
; Test bhi $label9
- set_cc 0x0f ; condition codes are irrelevent
+ set_cc 0x0f ; condition codes are irrelevant
no_branch bhi
- set_cc 0x0e ; condition codes are irrelevent
+ set_cc 0x0e ; condition codes are irrelevant
no_branch bhi
- set_cc 0x0d ; condition codes are irrelevent
+ set_cc 0x0d ; condition codes are irrelevant
no_branch bhi
- set_cc 0x0c ; condition codes are irrelevent
+ set_cc 0x0c ; condition codes are irrelevant
no_branch bhi
- set_cc 0x0b ; condition codes are irrelevent
+ set_cc 0x0b ; condition codes are irrelevant
no_branch bhi
- set_cc 0x0a ; condition codes are irrelevent
+ set_cc 0x0a ; condition codes are irrelevant
take_branch bhi
- set_cc 0x09 ; condition codes are irrelevent
+ set_cc 0x09 ; condition codes are irrelevant
no_branch bhi
- set_cc 0x08 ; condition codes are irrelevent
+ set_cc 0x08 ; condition codes are irrelevant
take_branch bhi
- set_cc 0x07 ; condition codes are irrelevent
+ set_cc 0x07 ; condition codes are irrelevant
no_branch bhi
- set_cc 0x06 ; condition codes are irrelevent
+ set_cc 0x06 ; condition codes are irrelevant
no_branch bhi
- set_cc 0x05 ; condition codes are irrelevent
+ set_cc 0x05 ; condition codes are irrelevant
no_branch bhi
- set_cc 0x04 ; condition codes are irrelevent
+ set_cc 0x04 ; condition codes are irrelevant
no_branch bhi
- set_cc 0x03 ; condition codes are irrelevent
+ set_cc 0x03 ; condition codes are irrelevant
no_branch bhi
- set_cc 0x02 ; condition codes are irrelevent
+ set_cc 0x02 ; condition codes are irrelevant
take_branch bhi
- set_cc 0x01 ; condition codes are irrelevent
+ set_cc 0x01 ; condition codes are irrelevant
no_branch bhi
- set_cc 0x00 ; condition codes are irrelevent
+ set_cc 0x00 ; condition codes are irrelevant
take_branch bhi
; Test bhi:d label9
- set_cc 0x0f ; condition codes are irrelevent
+ set_cc 0x0f ; condition codes are irrelevant
no_branch_d bhi:d 0xf
- set_cc 0x0e ; condition codes are irrelevent
+ set_cc 0x0e ; condition codes are irrelevant
no_branch_d bhi:d 0xe
- set_cc 0x0d ; condition codes are irrelevent
+ set_cc 0x0d ; condition codes are irrelevant
no_branch_d bhi:d 0xd
- set_cc 0x0c ; condition codes are irrelevent
+ set_cc 0x0c ; condition codes are irrelevant
no_branch_d bhi:d 0xc
- set_cc 0x0b ; condition codes are irrelevent
+ set_cc 0x0b ; condition codes are irrelevant
no_branch_d bhi:d 0xb
- set_cc 0x0a ; condition codes are irrelevent
+ set_cc 0x0a ; condition codes are irrelevant
take_branch_d bhi:d 0xa
- set_cc 0x09 ; condition codes are irrelevent
+ set_cc 0x09 ; condition codes are irrelevant
no_branch_d bhi:d 0x9
- set_cc 0x08 ; condition codes are irrelevent
+ set_cc 0x08 ; condition codes are irrelevant
take_branch_d bhi:d 0x8
- set_cc 0x07 ; condition codes are irrelevent
+ set_cc 0x07 ; condition codes are irrelevant
no_branch_d bhi:d 0x7
- set_cc 0x06 ; condition codes are irrelevent
+ set_cc 0x06 ; condition codes are irrelevant
no_branch_d bhi:d 0x6
- set_cc 0x05 ; condition codes are irrelevent
+ set_cc 0x05 ; condition codes are irrelevant
no_branch_d bhi:d 0x5
- set_cc 0x04 ; condition codes are irrelevent
+ set_cc 0x04 ; condition codes are irrelevant
no_branch_d bhi:d 0x4
- set_cc 0x03 ; condition codes are irrelevent
+ set_cc 0x03 ; condition codes are irrelevant
no_branch_d bhi:d 0x3
- set_cc 0x02 ; condition codes are irrelevent
+ set_cc 0x02 ; condition codes are irrelevant
take_branch_d bhi:d 0x2
- set_cc 0x01 ; condition codes are irrelevent
+ set_cc 0x01 ; condition codes are irrelevant
no_branch_d bhi:d 0x1
- set_cc 0x00 ; condition codes are irrelevent
+ set_cc 0x00 ; condition codes are irrelevant
take_branch_d bhi:d 0x0
pass
diff --git a/sim/testsuite/sim/fr30/ble.cgs b/sim/testsuite/sim/fr30/ble.cgs
index 1a33f78..ae361bb 100644
--- a/sim/testsuite/sim/fr30/ble.cgs
+++ b/sim/testsuite/sim/fr30/ble.cgs
@@ -9,101 +9,101 @@
.global ble
ble:
; Test ble $label9
- set_cc 0x0f ; condition codes are irrelevent
+ set_cc 0x0f ; condition codes are irrelevant
take_branch ble
- set_cc 0x0e ; condition codes are irrelevent
+ set_cc 0x0e ; condition codes are irrelevant
take_branch ble
- set_cc 0x0d ; condition codes are irrelevent
+ set_cc 0x0d ; condition codes are irrelevant
take_branch ble
- set_cc 0x0c ; condition codes are irrelevent
+ set_cc 0x0c ; condition codes are irrelevant
take_branch ble
- set_cc 0x0b ; condition codes are irrelevent
+ set_cc 0x0b ; condition codes are irrelevant
no_branch ble
- set_cc 0x0a ; condition codes are irrelevent
+ set_cc 0x0a ; condition codes are irrelevant
no_branch ble
- set_cc 0x09 ; condition codes are irrelevent
+ set_cc 0x09 ; condition codes are irrelevant
take_branch ble
- set_cc 0x08 ; condition codes are irrelevent
+ set_cc 0x08 ; condition codes are irrelevant
take_branch ble
- set_cc 0x07 ; condition codes are irrelevent
+ set_cc 0x07 ; condition codes are irrelevant
take_branch ble
- set_cc 0x06 ; condition codes are irrelevent
+ set_cc 0x06 ; condition codes are irrelevant
take_branch ble
- set_cc 0x05 ; condition codes are irrelevent
+ set_cc 0x05 ; condition codes are irrelevant
take_branch ble
- set_cc 0x04 ; condition codes are irrelevent
+ set_cc 0x04 ; condition codes are irrelevant
take_branch ble
- set_cc 0x03 ; condition codes are irrelevent
+ set_cc 0x03 ; condition codes are irrelevant
take_branch ble
- set_cc 0x02 ; condition codes are irrelevent
+ set_cc 0x02 ; condition codes are irrelevant
take_branch ble
- set_cc 0x01 ; condition codes are irrelevent
+ set_cc 0x01 ; condition codes are irrelevant
no_branch ble
- set_cc 0x00 ; condition codes are irrelevent
+ set_cc 0x00 ; condition codes are irrelevant
no_branch ble
; Test ble:d label9
- set_cc 0x0f ; condition codes are irrelevent
+ set_cc 0x0f ; condition codes are irrelevant
take_branch_d ble:d 0xf
- set_cc 0x0e ; condition codes are irrelevent
+ set_cc 0x0e ; condition codes are irrelevant
take_branch_d ble:d 0xe
- set_cc 0x0d ; condition codes are irrelevent
+ set_cc 0x0d ; condition codes are irrelevant
take_branch_d ble:d 0xd
- set_cc 0x0c ; condition codes are irrelevent
+ set_cc 0x0c ; condition codes are irrelevant
take_branch_d ble:d 0xc
- set_cc 0x0b ; condition codes are irrelevent
+ set_cc 0x0b ; condition codes are irrelevant
no_branch_d ble:d 0xb
- set_cc 0x0a ; condition codes are irrelevent
+ set_cc 0x0a ; condition codes are irrelevant
no_branch_d ble:d 0xa
- set_cc 0x09 ; condition codes are irrelevent
+ set_cc 0x09 ; condition codes are irrelevant
take_branch_d ble:d 0x9
- set_cc 0x08 ; condition codes are irrelevent
+ set_cc 0x08 ; condition codes are irrelevant
take_branch_d ble:d 0x8
- set_cc 0x07 ; condition codes are irrelevent
+ set_cc 0x07 ; condition codes are irrelevant
take_branch_d ble:d 0x7
- set_cc 0x06 ; condition codes are irrelevent
+ set_cc 0x06 ; condition codes are irrelevant
take_branch_d ble:d 0x6
- set_cc 0x05 ; condition codes are irrelevent
+ set_cc 0x05 ; condition codes are irrelevant
take_branch_d ble:d 0x5
- set_cc 0x04 ; condition codes are irrelevent
+ set_cc 0x04 ; condition codes are irrelevant
take_branch_d ble:d 0x4
- set_cc 0x03 ; condition codes are irrelevent
+ set_cc 0x03 ; condition codes are irrelevant
take_branch_d ble:d 0x3
- set_cc 0x02 ; condition codes are irrelevent
+ set_cc 0x02 ; condition codes are irrelevant
take_branch_d ble:d 0x2
- set_cc 0x01 ; condition codes are irrelevent
+ set_cc 0x01 ; condition codes are irrelevant
no_branch_d ble:d 0x1
- set_cc 0x00 ; condition codes are irrelevent
+ set_cc 0x00 ; condition codes are irrelevant
no_branch_d ble:d 0x0
pass
diff --git a/sim/testsuite/sim/fr30/bls.cgs b/sim/testsuite/sim/fr30/bls.cgs
index c0148b7..bd13fd5 100644
--- a/sim/testsuite/sim/fr30/bls.cgs
+++ b/sim/testsuite/sim/fr30/bls.cgs
@@ -9,101 +9,101 @@
.global bls
bls:
; Test bls $label9
- set_cc 0x0f ; condition codes are irrelevent
+ set_cc 0x0f ; condition codes are irrelevant
take_branch bls
- set_cc 0x0e ; condition codes are irrelevent
+ set_cc 0x0e ; condition codes are irrelevant
take_branch bls
- set_cc 0x0d ; condition codes are irrelevent
+ set_cc 0x0d ; condition codes are irrelevant
take_branch bls
- set_cc 0x0c ; condition codes are irrelevent
+ set_cc 0x0c ; condition codes are irrelevant
take_branch bls
- set_cc 0x0b ; condition codes are irrelevent
+ set_cc 0x0b ; condition codes are irrelevant
take_branch bls
- set_cc 0x0a ; condition codes are irrelevent
+ set_cc 0x0a ; condition codes are irrelevant
no_branch bls
- set_cc 0x09 ; condition codes are irrelevent
+ set_cc 0x09 ; condition codes are irrelevant
take_branch bls
- set_cc 0x08 ; condition codes are irrelevent
+ set_cc 0x08 ; condition codes are irrelevant
no_branch bls
- set_cc 0x07 ; condition codes are irrelevent
+ set_cc 0x07 ; condition codes are irrelevant
take_branch bls
- set_cc 0x06 ; condition codes are irrelevent
+ set_cc 0x06 ; condition codes are irrelevant
take_branch bls
- set_cc 0x05 ; condition codes are irrelevent
+ set_cc 0x05 ; condition codes are irrelevant
take_branch bls
- set_cc 0x04 ; condition codes are irrelevent
+ set_cc 0x04 ; condition codes are irrelevant
take_branch bls
- set_cc 0x03 ; condition codes are irrelevent
+ set_cc 0x03 ; condition codes are irrelevant
take_branch bls
- set_cc 0x02 ; condition codes are irrelevent
+ set_cc 0x02 ; condition codes are irrelevant
no_branch bls
- set_cc 0x01 ; condition codes are irrelevent
+ set_cc 0x01 ; condition codes are irrelevant
take_branch bls
- set_cc 0x00 ; condition codes are irrelevent
+ set_cc 0x00 ; condition codes are irrelevant
no_branch bls
; Test bls:d label9
- set_cc 0x0f ; condition codes are irrelevent
+ set_cc 0x0f ; condition codes are irrelevant
take_branch_d bls:d 0xf
- set_cc 0x0e ; condition codes are irrelevent
+ set_cc 0x0e ; condition codes are irrelevant
take_branch_d bls:d 0xe
- set_cc 0x0d ; condition codes are irrelevent
+ set_cc 0x0d ; condition codes are irrelevant
take_branch_d bls:d 0xd
- set_cc 0x0c ; condition codes are irrelevent
+ set_cc 0x0c ; condition codes are irrelevant
take_branch_d bls:d 0xc
- set_cc 0x0b ; condition codes are irrelevent
+ set_cc 0x0b ; condition codes are irrelevant
take_branch_d bls:d 0xb
- set_cc 0x0a ; condition codes are irrelevent
+ set_cc 0x0a ; condition codes are irrelevant
no_branch_d bls:d 0xa
- set_cc 0x09 ; condition codes are irrelevent
+ set_cc 0x09 ; condition codes are irrelevant
take_branch_d bls:d 0x9
- set_cc 0x08 ; condition codes are irrelevent
+ set_cc 0x08 ; condition codes are irrelevant
no_branch_d bls:d 0x8
- set_cc 0x07 ; condition codes are irrelevent
+ set_cc 0x07 ; condition codes are irrelevant
take_branch_d bls:d 0x7
- set_cc 0x06 ; condition codes are irrelevent
+ set_cc 0x06 ; condition codes are irrelevant
take_branch_d bls:d 0x6
- set_cc 0x05 ; condition codes are irrelevent
+ set_cc 0x05 ; condition codes are irrelevant
take_branch_d bls:d 0x5
- set_cc 0x04 ; condition codes are irrelevent
+ set_cc 0x04 ; condition codes are irrelevant
take_branch_d bls:d 0x4
- set_cc 0x03 ; condition codes are irrelevent
+ set_cc 0x03 ; condition codes are irrelevant
take_branch_d bls:d 0x3
- set_cc 0x02 ; condition codes are irrelevent
+ set_cc 0x02 ; condition codes are irrelevant
no_branch_d bls:d 0x2
- set_cc 0x01 ; condition codes are irrelevent
+ set_cc 0x01 ; condition codes are irrelevant
take_branch_d bls:d 0x1
- set_cc 0x00 ; condition codes are irrelevent
+ set_cc 0x00 ; condition codes are irrelevant
no_branch_d bls:d 0x0
pass
diff --git a/sim/testsuite/sim/fr30/blt.cgs b/sim/testsuite/sim/fr30/blt.cgs
index f7b6ff1..3b1222b 100644
--- a/sim/testsuite/sim/fr30/blt.cgs
+++ b/sim/testsuite/sim/fr30/blt.cgs
@@ -9,101 +9,101 @@
.global blt
blt:
; Test blt $label9
- set_cc 0x0f ; condition codes are irrelevent
+ set_cc 0x0f ; condition codes are irrelevant
no_branch blt
- set_cc 0x0e ; condition codes are irrelevent
+ set_cc 0x0e ; condition codes are irrelevant
no_branch blt
- set_cc 0x0d ; condition codes are irrelevent
+ set_cc 0x0d ; condition codes are irrelevant
take_branch blt
- set_cc 0x0c ; condition codes are irrelevent
+ set_cc 0x0c ; condition codes are irrelevant
take_branch blt
- set_cc 0x0b ; condition codes are irrelevent
+ set_cc 0x0b ; condition codes are irrelevant
no_branch blt
- set_cc 0x0a ; condition codes are irrelevent
+ set_cc 0x0a ; condition codes are irrelevant
no_branch blt
- set_cc 0x09 ; condition codes are irrelevent
+ set_cc 0x09 ; condition codes are irrelevant
take_branch blt
- set_cc 0x08 ; condition codes are irrelevent
+ set_cc 0x08 ; condition codes are irrelevant
take_branch blt
- set_cc 0x07 ; condition codes are irrelevent
+ set_cc 0x07 ; condition codes are irrelevant
take_branch blt
- set_cc 0x06 ; condition codes are irrelevent
+ set_cc 0x06 ; condition codes are irrelevant
take_branch blt
- set_cc 0x05 ; condition codes are irrelevent
+ set_cc 0x05 ; condition codes are irrelevant
no_branch blt
- set_cc 0x04 ; condition codes are irrelevent
+ set_cc 0x04 ; condition codes are irrelevant
no_branch blt
- set_cc 0x03 ; condition codes are irrelevent
+ set_cc 0x03 ; condition codes are irrelevant
take_branch blt
- set_cc 0x02 ; condition codes are irrelevent
+ set_cc 0x02 ; condition codes are irrelevant
take_branch blt
- set_cc 0x01 ; condition codes are irrelevent
+ set_cc 0x01 ; condition codes are irrelevant
no_branch blt
- set_cc 0x00 ; condition codes are irrelevent
+ set_cc 0x00 ; condition codes are irrelevant
no_branch blt
; Test blt:d label9
- set_cc 0x0f ; condition codes are irrelevent
+ set_cc 0x0f ; condition codes are irrelevant
no_branch_d blt:d 0xf
- set_cc 0x0e ; condition codes are irrelevent
+ set_cc 0x0e ; condition codes are irrelevant
no_branch_d blt:d 0xe
- set_cc 0x0d ; condition codes are irrelevent
+ set_cc 0x0d ; condition codes are irrelevant
take_branch_d blt:d 0xd
- set_cc 0x0c ; condition codes are irrelevent
+ set_cc 0x0c ; condition codes are irrelevant
take_branch_d blt:d 0xc
- set_cc 0x0b ; condition codes are irrelevent
+ set_cc 0x0b ; condition codes are irrelevant
no_branch_d blt:d 0xb
- set_cc 0x0a ; condition codes are irrelevent
+ set_cc 0x0a ; condition codes are irrelevant
no_branch_d blt:d 0xa
- set_cc 0x09 ; condition codes are irrelevent
+ set_cc 0x09 ; condition codes are irrelevant
take_branch_d blt:d 0x9
- set_cc 0x08 ; condition codes are irrelevent
+ set_cc 0x08 ; condition codes are irrelevant
take_branch_d blt:d 0x8
- set_cc 0x07 ; condition codes are irrelevent
+ set_cc 0x07 ; condition codes are irrelevant
take_branch_d blt:d 0x7
- set_cc 0x06 ; condition codes are irrelevent
+ set_cc 0x06 ; condition codes are irrelevant
take_branch_d blt:d 0x6
- set_cc 0x05 ; condition codes are irrelevent
+ set_cc 0x05 ; condition codes are irrelevant
no_branch_d blt:d 0x5
- set_cc 0x04 ; condition codes are irrelevent
+ set_cc 0x04 ; condition codes are irrelevant
no_branch_d blt:d 0x4
- set_cc 0x03 ; condition codes are irrelevent
+ set_cc 0x03 ; condition codes are irrelevant
take_branch_d blt:d 0x3
- set_cc 0x02 ; condition codes are irrelevent
+ set_cc 0x02 ; condition codes are irrelevant
take_branch_d blt:d 0x2
- set_cc 0x01 ; condition codes are irrelevent
+ set_cc 0x01 ; condition codes are irrelevant
no_branch_d blt:d 0x1
- set_cc 0x00 ; condition codes are irrelevent
+ set_cc 0x00 ; condition codes are irrelevant
no_branch_d blt:d 0x0
pass
diff --git a/sim/testsuite/sim/fr30/bn.cgs b/sim/testsuite/sim/fr30/bn.cgs
index 45858fc..10e57ad 100644
--- a/sim/testsuite/sim/fr30/bn.cgs
+++ b/sim/testsuite/sim/fr30/bn.cgs
@@ -9,101 +9,101 @@
.global bn
bn:
; Test bn $label9
- set_cc 0x0f ; condition codes are irrelevent
+ set_cc 0x0f ; condition codes are irrelevant
take_branch bn
- set_cc 0x0e ; condition codes are irrelevent
+ set_cc 0x0e ; condition codes are irrelevant
take_branch bn
- set_cc 0x0d ; condition codes are irrelevent
+ set_cc 0x0d ; condition codes are irrelevant
take_branch bn
- set_cc 0x0c ; condition codes are irrelevent
+ set_cc 0x0c ; condition codes are irrelevant
take_branch bn
- set_cc 0x0b ; condition codes are irrelevent
+ set_cc 0x0b ; condition codes are irrelevant
take_branch bn
- set_cc 0x0a ; condition codes are irrelevent
+ set_cc 0x0a ; condition codes are irrelevant
take_branch bn
- set_cc 0x09 ; condition codes are irrelevent
+ set_cc 0x09 ; condition codes are irrelevant
take_branch bn
- set_cc 0x08 ; condition codes are irrelevent
+ set_cc 0x08 ; condition codes are irrelevant
take_branch bn
- set_cc 0x07 ; condition codes are irrelevent
+ set_cc 0x07 ; condition codes are irrelevant
no_branch bn
- set_cc 0x06 ; condition codes are irrelevent
+ set_cc 0x06 ; condition codes are irrelevant
no_branch bn
- set_cc 0x05 ; condition codes are irrelevent
+ set_cc 0x05 ; condition codes are irrelevant
no_branch bn
- set_cc 0x04 ; condition codes are irrelevent
+ set_cc 0x04 ; condition codes are irrelevant
no_branch bn
- set_cc 0x03 ; condition codes are irrelevent
+ set_cc 0x03 ; condition codes are irrelevant
no_branch bn
- set_cc 0x02 ; condition codes are irrelevent
+ set_cc 0x02 ; condition codes are irrelevant
no_branch bn
- set_cc 0x01 ; condition codes are irrelevent
+ set_cc 0x01 ; condition codes are irrelevant
no_branch bn
- set_cc 0x00 ; condition codes are irrelevent
+ set_cc 0x00 ; condition codes are irrelevant
no_branch bn
; Test bn:d label9
- set_cc 0x0f ; condition codes are irrelevent
+ set_cc 0x0f ; condition codes are irrelevant
take_branch_d bn:d 0xf
- set_cc 0x0e ; condition codes are irrelevent
+ set_cc 0x0e ; condition codes are irrelevant
take_branch_d bn:d 0xe
- set_cc 0x0d ; condition codes are irrelevent
+ set_cc 0x0d ; condition codes are irrelevant
take_branch_d bn:d 0xd
- set_cc 0x0c ; condition codes are irrelevent
+ set_cc 0x0c ; condition codes are irrelevant
take_branch_d bn:d 0xc
- set_cc 0x0b ; condition codes are irrelevent
+ set_cc 0x0b ; condition codes are irrelevant
take_branch_d bn:d 0xb
- set_cc 0x0a ; condition codes are irrelevent
+ set_cc 0x0a ; condition codes are irrelevant
take_branch_d bn:d 0xa
- set_cc 0x09 ; condition codes are irrelevent
+ set_cc 0x09 ; condition codes are irrelevant
take_branch_d bn:d 0x9
- set_cc 0x08 ; condition codes are irrelevent
+ set_cc 0x08 ; condition codes are irrelevant
take_branch_d bn:d 0x8
- set_cc 0x07 ; condition codes are irrelevent
+ set_cc 0x07 ; condition codes are irrelevant
no_branch_d bn:d 0x7
- set_cc 0x06 ; condition codes are irrelevent
+ set_cc 0x06 ; condition codes are irrelevant
no_branch_d bn:d 0x6
- set_cc 0x05 ; condition codes are irrelevent
+ set_cc 0x05 ; condition codes are irrelevant
no_branch_d bn:d 0x5
- set_cc 0x04 ; condition codes are irrelevent
+ set_cc 0x04 ; condition codes are irrelevant
no_branch_d bn:d 0x4
- set_cc 0x03 ; condition codes are irrelevent
+ set_cc 0x03 ; condition codes are irrelevant
no_branch_d bn:d 0x3
- set_cc 0x02 ; condition codes are irrelevent
+ set_cc 0x02 ; condition codes are irrelevant
no_branch_d bn:d 0x2
- set_cc 0x01 ; condition codes are irrelevent
+ set_cc 0x01 ; condition codes are irrelevant
no_branch_d bn:d 0x1
- set_cc 0x00 ; condition codes are irrelevent
+ set_cc 0x00 ; condition codes are irrelevant
no_branch_d bn:d 0x0
pass
diff --git a/sim/testsuite/sim/fr30/bnc.cgs b/sim/testsuite/sim/fr30/bnc.cgs
index 9968c43..5d86cee 100644
--- a/sim/testsuite/sim/fr30/bnc.cgs
+++ b/sim/testsuite/sim/fr30/bnc.cgs
@@ -9,101 +9,101 @@
.global bnc
bc:
; Test bnc $label9
- set_cc 0x0f ; condition codes are irrelevent
+ set_cc 0x0f ; condition codes are irrelevant
no_branch bnc
- set_cc 0x0e ; condition codes are irrelevent
+ set_cc 0x0e ; condition codes are irrelevant
take_branch bnc
- set_cc 0x0d ; condition codes are irrelevent
+ set_cc 0x0d ; condition codes are irrelevant
no_branch bnc
- set_cc 0x0c ; condition codes are irrelevent
+ set_cc 0x0c ; condition codes are irrelevant
take_branch bnc
- set_cc 0x0b ; condition codes are irrelevent
+ set_cc 0x0b ; condition codes are irrelevant
no_branch bnc
- set_cc 0x0a ; condition codes are irrelevent
+ set_cc 0x0a ; condition codes are irrelevant
take_branch bnc
- set_cc 0x09 ; condition codes are irrelevent
+ set_cc 0x09 ; condition codes are irrelevant
no_branch bnc
- set_cc 0x08 ; condition codes are irrelevent
+ set_cc 0x08 ; condition codes are irrelevant
take_branch bnc
- set_cc 0x07 ; condition codes are irrelevent
+ set_cc 0x07 ; condition codes are irrelevant
no_branch bnc
- set_cc 0x06 ; condition codes are irrelevent
+ set_cc 0x06 ; condition codes are irrelevant
take_branch bnc
- set_cc 0x05 ; condition codes are irrelevent
+ set_cc 0x05 ; condition codes are irrelevant
no_branch bnc
- set_cc 0x04 ; condition codes are irrelevent
+ set_cc 0x04 ; condition codes are irrelevant
take_branch bnc
- set_cc 0x03 ; condition codes are irrelevent
+ set_cc 0x03 ; condition codes are irrelevant
no_branch bnc
- set_cc 0x02 ; condition codes are irrelevent
+ set_cc 0x02 ; condition codes are irrelevant
take_branch bnc
- set_cc 0x01 ; condition codes are irrelevent
+ set_cc 0x01 ; condition codes are irrelevant
no_branch bnc
- set_cc 0x00 ; condition codes are irrelevent
+ set_cc 0x00 ; condition codes are irrelevant
take_branch bnc
; Test bnc:d label9
- set_cc 0x0f ; condition codes are irrelevent
+ set_cc 0x0f ; condition codes are irrelevant
no_branch_d bnc:d 0xf
- set_cc 0x0e ; condition codes are irrelevent
+ set_cc 0x0e ; condition codes are irrelevant
take_branch_d bnc:d 0xe
- set_cc 0x0d ; condition codes are irrelevent
+ set_cc 0x0d ; condition codes are irrelevant
no_branch_d bnc:d 0xd
- set_cc 0x0c ; condition codes are irrelevent
+ set_cc 0x0c ; condition codes are irrelevant
take_branch_d bnc:d 0xc
- set_cc 0x0b ; condition codes are irrelevent
+ set_cc 0x0b ; condition codes are irrelevant
no_branch_d bnc:d 0xb
- set_cc 0x0a ; condition codes are irrelevent
+ set_cc 0x0a ; condition codes are irrelevant
take_branch_d bnc:d 0xa
- set_cc 0x09 ; condition codes are irrelevent
+ set_cc 0x09 ; condition codes are irrelevant
no_branch_d bnc:d 0x9
- set_cc 0x08 ; condition codes are irrelevent
+ set_cc 0x08 ; condition codes are irrelevant
take_branch_d bnc:d 0x8
- set_cc 0x07 ; condition codes are irrelevent
+ set_cc 0x07 ; condition codes are irrelevant
no_branch_d bnc:d 0x7
- set_cc 0x06 ; condition codes are irrelevent
+ set_cc 0x06 ; condition codes are irrelevant
take_branch_d bnc:d 0x6
- set_cc 0x05 ; condition codes are irrelevent
+ set_cc 0x05 ; condition codes are irrelevant
no_branch_d bnc:d 0x5
- set_cc 0x04 ; condition codes are irrelevent
+ set_cc 0x04 ; condition codes are irrelevant
take_branch_d bnc:d 0x4
- set_cc 0x03 ; condition codes are irrelevent
+ set_cc 0x03 ; condition codes are irrelevant
no_branch_d bnc:d 0x3
- set_cc 0x02 ; condition codes are irrelevent
+ set_cc 0x02 ; condition codes are irrelevant
take_branch_d bnc:d 0x2
- set_cc 0x01 ; condition codes are irrelevent
+ set_cc 0x01 ; condition codes are irrelevant
no_branch_d bnc:d 0x1
- set_cc 0x00 ; condition codes are irrelevent
+ set_cc 0x00 ; condition codes are irrelevant
take_branch_d bnc:d 0x0
pass
diff --git a/sim/testsuite/sim/fr30/bne.cgs b/sim/testsuite/sim/fr30/bne.cgs
index 58971de..6ada810 100644
--- a/sim/testsuite/sim/fr30/bne.cgs
+++ b/sim/testsuite/sim/fr30/bne.cgs
@@ -9,101 +9,101 @@
.global bne
bne:
; Test bne $label9
- set_cc 0x0f ; condition codes are irrelevent
+ set_cc 0x0f ; condition codes are irrelevant
no_branch bne
- set_cc 0x0e ; condition codes are irrelevent
+ set_cc 0x0e ; condition codes are irrelevant
no_branch bne
- set_cc 0x0d ; condition codes are irrelevent
+ set_cc 0x0d ; condition codes are irrelevant
no_branch bne
- set_cc 0x0c ; condition codes are irrelevent
+ set_cc 0x0c ; condition codes are irrelevant
no_branch bne
- set_cc 0x0b ; condition codes are irrelevent
+ set_cc 0x0b ; condition codes are irrelevant
take_branch bne
- set_cc 0x0a ; condition codes are irrelevent
+ set_cc 0x0a ; condition codes are irrelevant
take_branch bne
- set_cc 0x09 ; condition codes are irrelevent
+ set_cc 0x09 ; condition codes are irrelevant
take_branch bne
- set_cc 0x08 ; condition codes are irrelevent
+ set_cc 0x08 ; condition codes are irrelevant
take_branch bne
- set_cc 0x07 ; condition codes are irrelevent
+ set_cc 0x07 ; condition codes are irrelevant
no_branch bne
- set_cc 0x06 ; condition codes are irrelevent
+ set_cc 0x06 ; condition codes are irrelevant
no_branch bne
- set_cc 0x05 ; condition codes are irrelevent
+ set_cc 0x05 ; condition codes are irrelevant
no_branch bne
- set_cc 0x04 ; condition codes are irrelevent
+ set_cc 0x04 ; condition codes are irrelevant
no_branch bne
- set_cc 0x03 ; condition codes are irrelevent
+ set_cc 0x03 ; condition codes are irrelevant
take_branch bne
- set_cc 0x02 ; condition codes are irrelevent
+ set_cc 0x02 ; condition codes are irrelevant
take_branch bne
- set_cc 0x01 ; condition codes are irrelevent
+ set_cc 0x01 ; condition codes are irrelevant
take_branch bne
- set_cc 0x00 ; condition codes are irrelevent
+ set_cc 0x00 ; condition codes are irrelevant
take_branch bne
; Test bne:d label9
- set_cc 0x0f ; condition codes are irrelevent
+ set_cc 0x0f ; condition codes are irrelevant
no_branch_d bne:d 0xf
- set_cc 0x0e ; condition codes are irrelevent
+ set_cc 0x0e ; condition codes are irrelevant
no_branch_d bne:d 0xe
- set_cc 0x0d ; condition codes are irrelevent
+ set_cc 0x0d ; condition codes are irrelevant
no_branch_d bne:d 0xd
- set_cc 0x0c ; condition codes are irrelevent
+ set_cc 0x0c ; condition codes are irrelevant
no_branch_d bne:d 0xc
- set_cc 0x0b ; condition codes are irrelevent
+ set_cc 0x0b ; condition codes are irrelevant
take_branch_d bne:d 0xb
- set_cc 0x0a ; condition codes are irrelevent
+ set_cc 0x0a ; condition codes are irrelevant
take_branch_d bne:d 0xa
- set_cc 0x09 ; condition codes are irrelevent
+ set_cc 0x09 ; condition codes are irrelevant
take_branch_d bne:d 0x9
- set_cc 0x08 ; condition codes are irrelevent
+ set_cc 0x08 ; condition codes are irrelevant
take_branch_d bne:d 0x8
- set_cc 0x07 ; condition codes are irrelevent
+ set_cc 0x07 ; condition codes are irrelevant
no_branch_d bne:d 0x7
- set_cc 0x06 ; condition codes are irrelevent
+ set_cc 0x06 ; condition codes are irrelevant
no_branch_d bne:d 0x6
- set_cc 0x05 ; condition codes are irrelevent
+ set_cc 0x05 ; condition codes are irrelevant
no_branch_d bne:d 0x5
- set_cc 0x04 ; condition codes are irrelevent
+ set_cc 0x04 ; condition codes are irrelevant
no_branch_d bne:d 0x4
- set_cc 0x03 ; condition codes are irrelevent
+ set_cc 0x03 ; condition codes are irrelevant
take_branch_d bne:d 0x3
- set_cc 0x02 ; condition codes are irrelevent
+ set_cc 0x02 ; condition codes are irrelevant
take_branch_d bne:d 0x2
- set_cc 0x01 ; condition codes are irrelevent
+ set_cc 0x01 ; condition codes are irrelevant
take_branch_d bne:d 0x1
- set_cc 0x00 ; condition codes are irrelevent
+ set_cc 0x00 ; condition codes are irrelevant
take_branch_d bne:d 0x0
pass
diff --git a/sim/testsuite/sim/fr30/bno.cgs b/sim/testsuite/sim/fr30/bno.cgs
index faef9ba..17f1356 100644
--- a/sim/testsuite/sim/fr30/bno.cgs
+++ b/sim/testsuite/sim/fr30/bno.cgs
@@ -9,101 +9,101 @@
.global bno
bno:
; Test bno $label9
- set_cc 0x0f ; condition codes are irrelevent
+ set_cc 0x0f ; condition codes are irrelevant
no_branch bno
- set_cc 0x0e ; condition codes are irrelevent
+ set_cc 0x0e ; condition codes are irrelevant
no_branch bno
- set_cc 0x0d ; condition codes are irrelevent
+ set_cc 0x0d ; condition codes are irrelevant
no_branch bno
- set_cc 0x0c ; condition codes are irrelevent
+ set_cc 0x0c ; condition codes are irrelevant
no_branch bno
- set_cc 0x0b ; condition codes are irrelevent
+ set_cc 0x0b ; condition codes are irrelevant
no_branch bno
- set_cc 0x0a ; condition codes are irrelevent
+ set_cc 0x0a ; condition codes are irrelevant
no_branch bno
- set_cc 0x09 ; condition codes are irrelevent
+ set_cc 0x09 ; condition codes are irrelevant
no_branch bno
- set_cc 0x08 ; condition codes are irrelevent
+ set_cc 0x08 ; condition codes are irrelevant
no_branch bno
- set_cc 0x07 ; condition codes are irrelevent
+ set_cc 0x07 ; condition codes are irrelevant
no_branch bno
- set_cc 0x06 ; condition codes are irrelevent
+ set_cc 0x06 ; condition codes are irrelevant
no_branch bno
- set_cc 0x05 ; condition codes are irrelevent
+ set_cc 0x05 ; condition codes are irrelevant
no_branch bno
- set_cc 0x04 ; condition codes are irrelevent
+ set_cc 0x04 ; condition codes are irrelevant
no_branch bno
- set_cc 0x03 ; condition codes are irrelevent
+ set_cc 0x03 ; condition codes are irrelevant
no_branch bno
- set_cc 0x02 ; condition codes are irrelevent
+ set_cc 0x02 ; condition codes are irrelevant
no_branch bno
- set_cc 0x01 ; condition codes are irrelevent
+ set_cc 0x01 ; condition codes are irrelevant
no_branch bno
- set_cc 0x00 ; condition codes are irrelevent
+ set_cc 0x00 ; condition codes are irrelevant
no_branch bno
; Test bno:d label9
- set_cc 0x0f ; condition codes are irrelevent
+ set_cc 0x0f ; condition codes are irrelevant
no_branch_d bno:d 0xf
- set_cc 0x0e ; condition codes are irrelevent
+ set_cc 0x0e ; condition codes are irrelevant
no_branch_d bno:d 0xe
- set_cc 0x0d ; condition codes are irrelevent
+ set_cc 0x0d ; condition codes are irrelevant
no_branch_d bno:d 0xd
- set_cc 0x0c ; condition codes are irrelevent
+ set_cc 0x0c ; condition codes are irrelevant
no_branch_d bno:d 0xc
- set_cc 0x0b ; condition codes are irrelevent
+ set_cc 0x0b ; condition codes are irrelevant
no_branch_d bno:d 0xb
- set_cc 0x0a ; condition codes are irrelevent
+ set_cc 0x0a ; condition codes are irrelevant
no_branch_d bno:d 0xa
- set_cc 0x09 ; condition codes are irrelevent
+ set_cc 0x09 ; condition codes are irrelevant
no_branch_d bno:d 0x9
- set_cc 0x08 ; condition codes are irrelevent
+ set_cc 0x08 ; condition codes are irrelevant
no_branch_d bno:d 0x8
- set_cc 0x07 ; condition codes are irrelevent
+ set_cc 0x07 ; condition codes are irrelevant
no_branch_d bno:d 0x7
- set_cc 0x06 ; condition codes are irrelevent
+ set_cc 0x06 ; condition codes are irrelevant
no_branch_d bno:d 0x6
- set_cc 0x05 ; condition codes are irrelevent
+ set_cc 0x05 ; condition codes are irrelevant
no_branch_d bno:d 0x5
- set_cc 0x04 ; condition codes are irrelevent
+ set_cc 0x04 ; condition codes are irrelevant
no_branch_d bno:d 0x4
- set_cc 0x03 ; condition codes are irrelevent
+ set_cc 0x03 ; condition codes are irrelevant
no_branch_d bno:d 0x3
- set_cc 0x02 ; condition codes are irrelevent
+ set_cc 0x02 ; condition codes are irrelevant
no_branch_d bno:d 0x2
- set_cc 0x01 ; condition codes are irrelevent
+ set_cc 0x01 ; condition codes are irrelevant
no_branch_d bno:d 0x1
- set_cc 0x00 ; condition codes are irrelevent
+ set_cc 0x00 ; condition codes are irrelevant
no_branch_d bno:d 0x0
pass
diff --git a/sim/testsuite/sim/fr30/bnv.cgs b/sim/testsuite/sim/fr30/bnv.cgs
index 7615abd..995dbb4 100644
--- a/sim/testsuite/sim/fr30/bnv.cgs
+++ b/sim/testsuite/sim/fr30/bnv.cgs
@@ -9,101 +9,101 @@
.global bnv
bnv:
; Test bnv $label9
- set_cc 0x0f ; condition codes are irrelevent
+ set_cc 0x0f ; condition codes are irrelevant
no_branch bnv
- set_cc 0x0e ; condition codes are irrelevent
+ set_cc 0x0e ; condition codes are irrelevant
no_branch bnv
- set_cc 0x0d ; condition codes are irrelevent
+ set_cc 0x0d ; condition codes are irrelevant
take_branch bnv
- set_cc 0x0c ; condition codes are irrelevent
+ set_cc 0x0c ; condition codes are irrelevant
take_branch bnv
- set_cc 0x0b ; condition codes are irrelevent
+ set_cc 0x0b ; condition codes are irrelevant
no_branch bnv
- set_cc 0x0a ; condition codes are irrelevent
+ set_cc 0x0a ; condition codes are irrelevant
no_branch bnv
- set_cc 0x09 ; condition codes are irrelevent
+ set_cc 0x09 ; condition codes are irrelevant
take_branch bnv
- set_cc 0x08 ; condition codes are irrelevent
+ set_cc 0x08 ; condition codes are irrelevant
take_branch bnv
- set_cc 0x07 ; condition codes are irrelevent
+ set_cc 0x07 ; condition codes are irrelevant
no_branch bnv
- set_cc 0x06 ; condition codes are irrelevent
+ set_cc 0x06 ; condition codes are irrelevant
no_branch bnv
- set_cc 0x05 ; condition codes are irrelevent
+ set_cc 0x05 ; condition codes are irrelevant
take_branch bnv
- set_cc 0x04 ; condition codes are irrelevent
+ set_cc 0x04 ; condition codes are irrelevant
take_branch bnv
- set_cc 0x03 ; condition codes are irrelevent
+ set_cc 0x03 ; condition codes are irrelevant
no_branch bnv
- set_cc 0x02 ; condition codes are irrelevent
+ set_cc 0x02 ; condition codes are irrelevant
no_branch bnv
- set_cc 0x01 ; condition codes are irrelevent
+ set_cc 0x01 ; condition codes are irrelevant
take_branch bnv
- set_cc 0x00 ; condition codes are irrelevent
+ set_cc 0x00 ; condition codes are irrelevant
take_branch bnv
; Test bnv:d label9
- set_cc 0x0f ; condition codes are irrelevent
+ set_cc 0x0f ; condition codes are irrelevant
no_branch_d bnv:d 0xf
- set_cc 0x0e ; condition codes are irrelevent
+ set_cc 0x0e ; condition codes are irrelevant
no_branch_d bnv:d 0xe
- set_cc 0x0d ; condition codes are irrelevent
+ set_cc 0x0d ; condition codes are irrelevant
take_branch_d bnv:d 0xd
- set_cc 0x0c ; condition codes are irrelevent
+ set_cc 0x0c ; condition codes are irrelevant
take_branch_d bnv:d 0xc
- set_cc 0x0b ; condition codes are irrelevent
+ set_cc 0x0b ; condition codes are irrelevant
no_branch_d bnv:d 0xb
- set_cc 0x0a ; condition codes are irrelevent
+ set_cc 0x0a ; condition codes are irrelevant
no_branch_d bnv:d 0xa
- set_cc 0x09 ; condition codes are irrelevent
+ set_cc 0x09 ; condition codes are irrelevant
take_branch_d bnv:d 0x9
- set_cc 0x08 ; condition codes are irrelevent
+ set_cc 0x08 ; condition codes are irrelevant
take_branch_d bnv:d 0x8
- set_cc 0x07 ; condition codes are irrelevent
+ set_cc 0x07 ; condition codes are irrelevant
no_branch_d bnv:d 0x7
- set_cc 0x06 ; condition codes are irrelevent
+ set_cc 0x06 ; condition codes are irrelevant
no_branch_d bnv:d 0x6
- set_cc 0x05 ; condition codes are irrelevent
+ set_cc 0x05 ; condition codes are irrelevant
take_branch_d bnv:d 0x5
- set_cc 0x04 ; condition codes are irrelevent
+ set_cc 0x04 ; condition codes are irrelevant
take_branch_d bnv:d 0x4
- set_cc 0x03 ; condition codes are irrelevent
+ set_cc 0x03 ; condition codes are irrelevant
no_branch_d bnv:d 0x3
- set_cc 0x02 ; condition codes are irrelevent
+ set_cc 0x02 ; condition codes are irrelevant
no_branch_d bnv:d 0x2
- set_cc 0x01 ; condition codes are irrelevent
+ set_cc 0x01 ; condition codes are irrelevant
take_branch_d bnv:d 0x1
- set_cc 0x00 ; condition codes are irrelevent
+ set_cc 0x00 ; condition codes are irrelevant
take_branch_d bnv:d 0x0
pass
diff --git a/sim/testsuite/sim/fr30/bp.cgs b/sim/testsuite/sim/fr30/bp.cgs
index 3753283..e89426a 100644
--- a/sim/testsuite/sim/fr30/bp.cgs
+++ b/sim/testsuite/sim/fr30/bp.cgs
@@ -9,101 +9,101 @@
.global bp
bp:
; Test bp $label9
- set_cc 0x0f ; condition codes are irrelevent
+ set_cc 0x0f ; condition codes are irrelevant
no_branch bp
- set_cc 0x0e ; condition codes are irrelevent
+ set_cc 0x0e ; condition codes are irrelevant
no_branch bp
- set_cc 0x0d ; condition codes are irrelevent
+ set_cc 0x0d ; condition codes are irrelevant
no_branch bp
- set_cc 0x0c ; condition codes are irrelevent
+ set_cc 0x0c ; condition codes are irrelevant
no_branch bp
- set_cc 0x0b ; condition codes are irrelevent
+ set_cc 0x0b ; condition codes are irrelevant
no_branch bp
- set_cc 0x0a ; condition codes are irrelevent
+ set_cc 0x0a ; condition codes are irrelevant
no_branch bp
- set_cc 0x09 ; condition codes are irrelevent
+ set_cc 0x09 ; condition codes are irrelevant
no_branch bp
- set_cc 0x08 ; condition codes are irrelevent
+ set_cc 0x08 ; condition codes are irrelevant
no_branch bp
- set_cc 0x07 ; condition codes are irrelevent
+ set_cc 0x07 ; condition codes are irrelevant
take_branch bp
- set_cc 0x06 ; condition codes are irrelevent
+ set_cc 0x06 ; condition codes are irrelevant
take_branch bp
- set_cc 0x05 ; condition codes are irrelevent
+ set_cc 0x05 ; condition codes are irrelevant
take_branch bp
- set_cc 0x04 ; condition codes are irrelevent
+ set_cc 0x04 ; condition codes are irrelevant
take_branch bp
- set_cc 0x03 ; condition codes are irrelevent
+ set_cc 0x03 ; condition codes are irrelevant
take_branch bp
- set_cc 0x02 ; condition codes are irrelevent
+ set_cc 0x02 ; condition codes are irrelevant
take_branch bp
- set_cc 0x01 ; condition codes are irrelevent
+ set_cc 0x01 ; condition codes are irrelevant
take_branch bp
- set_cc 0x00 ; condition codes are irrelevent
+ set_cc 0x00 ; condition codes are irrelevant
take_branch bp
; Test bp:d label9
- set_cc 0x0f ; condition codes are irrelevent
+ set_cc 0x0f ; condition codes are irrelevant
no_branch_d bp:d 0xf
- set_cc 0x0e ; condition codes are irrelevent
+ set_cc 0x0e ; condition codes are irrelevant
no_branch_d bp:d 0xe
- set_cc 0x0d ; condition codes are irrelevent
+ set_cc 0x0d ; condition codes are irrelevant
no_branch_d bp:d 0xd
- set_cc 0x0c ; condition codes are irrelevent
+ set_cc 0x0c ; condition codes are irrelevant
no_branch_d bp:d 0xc
- set_cc 0x0b ; condition codes are irrelevent
+ set_cc 0x0b ; condition codes are irrelevant
no_branch_d bp:d 0xb
- set_cc 0x0a ; condition codes are irrelevent
+ set_cc 0x0a ; condition codes are irrelevant
no_branch_d bp:d 0xa
- set_cc 0x09 ; condition codes are irrelevent
+ set_cc 0x09 ; condition codes are irrelevant
no_branch_d bp:d 0x9
- set_cc 0x08 ; condition codes are irrelevent
+ set_cc 0x08 ; condition codes are irrelevant
no_branch_d bp:d 0x8
- set_cc 0x07 ; condition codes are irrelevent
+ set_cc 0x07 ; condition codes are irrelevant
take_branch_d bp:d 0x7
- set_cc 0x06 ; condition codes are irrelevent
+ set_cc 0x06 ; condition codes are irrelevant
take_branch_d bp:d 0x6
- set_cc 0x05 ; condition codes are irrelevent
+ set_cc 0x05 ; condition codes are irrelevant
take_branch_d bp:d 0x5
- set_cc 0x04 ; condition codes are irrelevent
+ set_cc 0x04 ; condition codes are irrelevant
take_branch_d bp:d 0x4
- set_cc 0x03 ; condition codes are irrelevent
+ set_cc 0x03 ; condition codes are irrelevant
take_branch_d bp:d 0x3
- set_cc 0x02 ; condition codes are irrelevent
+ set_cc 0x02 ; condition codes are irrelevant
take_branch_d bp:d 0x2
- set_cc 0x01 ; condition codes are irrelevent
+ set_cc 0x01 ; condition codes are irrelevant
take_branch_d bp:d 0x1
- set_cc 0x00 ; condition codes are irrelevent
+ set_cc 0x00 ; condition codes are irrelevant
take_branch_d bp:d 0x0
pass
diff --git a/sim/testsuite/sim/fr30/bra.cgs b/sim/testsuite/sim/fr30/bra.cgs
index 3732f74..4afc585 100644
--- a/sim/testsuite/sim/fr30/bra.cgs
+++ b/sim/testsuite/sim/fr30/bra.cgs
@@ -9,101 +9,101 @@
.global bra
bra:
; Test bra $label9
- set_cc 0x0f ; condition codes are irrelevent
+ set_cc 0x0f ; condition codes are irrelevant
take_branch bra
- set_cc 0x0e ; condition codes are irrelevent
+ set_cc 0x0e ; condition codes are irrelevant
take_branch bra
- set_cc 0x0d ; condition codes are irrelevent
+ set_cc 0x0d ; condition codes are irrelevant
take_branch bra
- set_cc 0x0c ; condition codes are irrelevent
+ set_cc 0x0c ; condition codes are irrelevant
take_branch bra
- set_cc 0x0b ; condition codes are irrelevent
+ set_cc 0x0b ; condition codes are irrelevant
take_branch bra
- set_cc 0x0a ; condition codes are irrelevent
+ set_cc 0x0a ; condition codes are irrelevant
take_branch bra
- set_cc 0x09 ; condition codes are irrelevent
+ set_cc 0x09 ; condition codes are irrelevant
take_branch bra
- set_cc 0x08 ; condition codes are irrelevent
+ set_cc 0x08 ; condition codes are irrelevant
take_branch bra
- set_cc 0x07 ; condition codes are irrelevent
+ set_cc 0x07 ; condition codes are irrelevant
take_branch bra
- set_cc 0x06 ; condition codes are irrelevent
+ set_cc 0x06 ; condition codes are irrelevant
take_branch bra
- set_cc 0x05 ; condition codes are irrelevent
+ set_cc 0x05 ; condition codes are irrelevant
take_branch bra
- set_cc 0x04 ; condition codes are irrelevent
+ set_cc 0x04 ; condition codes are irrelevant
take_branch bra
- set_cc 0x03 ; condition codes are irrelevent
+ set_cc 0x03 ; condition codes are irrelevant
take_branch bra
- set_cc 0x02 ; condition codes are irrelevent
+ set_cc 0x02 ; condition codes are irrelevant
take_branch bra
- set_cc 0x01 ; condition codes are irrelevent
+ set_cc 0x01 ; condition codes are irrelevant
take_branch bra
- set_cc 0x00 ; condition codes are irrelevent
+ set_cc 0x00 ; condition codes are irrelevant
take_branch bra
; Test bra:d label9
- set_cc 0x0f ; condition codes are irrelevent
+ set_cc 0x0f ; condition codes are irrelevant
take_branch_d bra:d 0xf
- set_cc 0x0e ; condition codes are irrelevent
+ set_cc 0x0e ; condition codes are irrelevant
take_branch_d bra:d 0xe
- set_cc 0x0d ; condition codes are irrelevent
+ set_cc 0x0d ; condition codes are irrelevant
take_branch_d bra:d 0xd
- set_cc 0x0c ; condition codes are irrelevent
+ set_cc 0x0c ; condition codes are irrelevant
take_branch_d bra:d 0xc
- set_cc 0x0b ; condition codes are irrelevent
+ set_cc 0x0b ; condition codes are irrelevant
take_branch_d bra:d 0xb
- set_cc 0x0a ; condition codes are irrelevent
+ set_cc 0x0a ; condition codes are irrelevant
take_branch_d bra:d 0xa
- set_cc 0x09 ; condition codes are irrelevent
+ set_cc 0x09 ; condition codes are irrelevant
take_branch_d bra:d 0x9
- set_cc 0x08 ; condition codes are irrelevent
+ set_cc 0x08 ; condition codes are irrelevant
take_branch_d bra:d 0x8
- set_cc 0x07 ; condition codes are irrelevent
+ set_cc 0x07 ; condition codes are irrelevant
take_branch_d bra:d 0x7
- set_cc 0x06 ; condition codes are irrelevent
+ set_cc 0x06 ; condition codes are irrelevant
take_branch_d bra:d 0x6
- set_cc 0x05 ; condition codes are irrelevent
+ set_cc 0x05 ; condition codes are irrelevant
take_branch_d bra:d 0x5
- set_cc 0x04 ; condition codes are irrelevent
+ set_cc 0x04 ; condition codes are irrelevant
take_branch_d bra:d 0x4
- set_cc 0x03 ; condition codes are irrelevent
+ set_cc 0x03 ; condition codes are irrelevant
take_branch_d bra:d 0x3
- set_cc 0x02 ; condition codes are irrelevent
+ set_cc 0x02 ; condition codes are irrelevant
take_branch_d bra:d 0x2
- set_cc 0x01 ; condition codes are irrelevent
+ set_cc 0x01 ; condition codes are irrelevant
take_branch_d bra:d 0x1
- set_cc 0x00 ; condition codes are irrelevent
+ set_cc 0x00 ; condition codes are irrelevant
take_branch_d bra:d 0x0
pass
diff --git a/sim/testsuite/sim/fr30/bv.cgs b/sim/testsuite/sim/fr30/bv.cgs
index 68cb9acf..0a421e5 100644
--- a/sim/testsuite/sim/fr30/bv.cgs
+++ b/sim/testsuite/sim/fr30/bv.cgs
@@ -9,101 +9,101 @@
.global bv
bv:
; Test bv $label9
- set_cc 0x0f ; condition codes are irrelevent
+ set_cc 0x0f ; condition codes are irrelevant
take_branch bv
- set_cc 0x0e ; condition codes are irrelevent
+ set_cc 0x0e ; condition codes are irrelevant
take_branch bv
- set_cc 0x0d ; condition codes are irrelevent
+ set_cc 0x0d ; condition codes are irrelevant
no_branch bv
- set_cc 0x0c ; condition codes are irrelevent
+ set_cc 0x0c ; condition codes are irrelevant
no_branch bv
- set_cc 0x0b ; condition codes are irrelevent
+ set_cc 0x0b ; condition codes are irrelevant
take_branch bv
- set_cc 0x0a ; condition codes are irrelevent
+ set_cc 0x0a ; condition codes are irrelevant
take_branch bv
- set_cc 0x09 ; condition codes are irrelevent
+ set_cc 0x09 ; condition codes are irrelevant
no_branch bv
- set_cc 0x08 ; condition codes are irrelevent
+ set_cc 0x08 ; condition codes are irrelevant
no_branch bv
- set_cc 0x07 ; condition codes are irrelevent
+ set_cc 0x07 ; condition codes are irrelevant
take_branch bv
- set_cc 0x06 ; condition codes are irrelevent
+ set_cc 0x06 ; condition codes are irrelevant
take_branch bv
- set_cc 0x05 ; condition codes are irrelevent
+ set_cc 0x05 ; condition codes are irrelevant
no_branch bv
- set_cc 0x04 ; condition codes are irrelevent
+ set_cc 0x04 ; condition codes are irrelevant
no_branch bv
- set_cc 0x03 ; condition codes are irrelevent
+ set_cc 0x03 ; condition codes are irrelevant
take_branch bv
- set_cc 0x02 ; condition codes are irrelevent
+ set_cc 0x02 ; condition codes are irrelevant
take_branch bv
- set_cc 0x01 ; condition codes are irrelevent
+ set_cc 0x01 ; condition codes are irrelevant
no_branch bv
- set_cc 0x00 ; condition codes are irrelevent
+ set_cc 0x00 ; condition codes are irrelevant
no_branch bv
; Test bv:d label9
- set_cc 0x0f ; condition codes are irrelevent
+ set_cc 0x0f ; condition codes are irrelevant
take_branch_d bv:d 0xf
- set_cc 0x0e ; condition codes are irrelevent
+ set_cc 0x0e ; condition codes are irrelevant
take_branch_d bv:d 0xe
- set_cc 0x0d ; condition codes are irrelevent
+ set_cc 0x0d ; condition codes are irrelevant
no_branch_d bv:d 0xd
- set_cc 0x0c ; condition codes are irrelevent
+ set_cc 0x0c ; condition codes are irrelevant
no_branch_d bv:d 0xc
- set_cc 0x0b ; condition codes are irrelevent
+ set_cc 0x0b ; condition codes are irrelevant
take_branch_d bv:d 0xb
- set_cc 0x0a ; condition codes are irrelevent
+ set_cc 0x0a ; condition codes are irrelevant
take_branch_d bv:d 0xa
- set_cc 0x09 ; condition codes are irrelevent
+ set_cc 0x09 ; condition codes are irrelevant
no_branch_d bv:d 0x9
- set_cc 0x08 ; condition codes are irrelevent
+ set_cc 0x08 ; condition codes are irrelevant
no_branch_d bv:d 0x8
- set_cc 0x07 ; condition codes are irrelevent
+ set_cc 0x07 ; condition codes are irrelevant
take_branch_d bv:d 0x7
- set_cc 0x06 ; condition codes are irrelevent
+ set_cc 0x06 ; condition codes are irrelevant
take_branch_d bv:d 0x6
- set_cc 0x05 ; condition codes are irrelevent
+ set_cc 0x05 ; condition codes are irrelevant
no_branch_d bv:d 0x5
- set_cc 0x04 ; condition codes are irrelevent
+ set_cc 0x04 ; condition codes are irrelevant
no_branch_d bv:d 0x4
- set_cc 0x03 ; condition codes are irrelevent
+ set_cc 0x03 ; condition codes are irrelevant
take_branch_d bv:d 0x3
- set_cc 0x02 ; condition codes are irrelevent
+ set_cc 0x02 ; condition codes are irrelevant
take_branch_d bv:d 0x2
- set_cc 0x01 ; condition codes are irrelevent
+ set_cc 0x01 ; condition codes are irrelevant
no_branch_d bv:d 0x1
- set_cc 0x00 ; condition codes are irrelevent
+ set_cc 0x00 ; condition codes are irrelevant
no_branch_d bv:d 0x0
pass
diff --git a/sim/testsuite/sim/fr30/copld.cgs b/sim/testsuite/sim/fr30/copld.cgs
index e0ababb..2273243 100644
--- a/sim/testsuite/sim/fr30/copld.cgs
+++ b/sim/testsuite/sim/fr30/copld.cgs
@@ -10,11 +10,11 @@
copld:
; Test copld copld $u4,$cc,$Rj,CRi
; The current implementation is a noop
- set_cc 0x0f ; Condition codes are irrelevent
+ set_cc 0x0f ; Condition codes are irrelevant
copld 0,0,r0,cr15
test_cc 1 1 1 1
- set_cc 0x0e ; Condition codes are irrelevent
+ set_cc 0x0e ; Condition codes are irrelevant
copld 15,255,r15,cr0
test_cc 1 1 1 0
diff --git a/sim/testsuite/sim/fr30/copop.cgs b/sim/testsuite/sim/fr30/copop.cgs
index b0afd77..3fe785a 100644
--- a/sim/testsuite/sim/fr30/copop.cgs
+++ b/sim/testsuite/sim/fr30/copop.cgs
@@ -10,11 +10,11 @@
copop:
; Test copop copop $u4,$cc,$CRj,CRi
; The current implementation is a noop
- set_cc 0x0f ; Condition codes are irrelevent
+ set_cc 0x0f ; Condition codes are irrelevant
copop 0,0,cr0,cr15
test_cc 1 1 1 1
- set_cc 0x0e ; Condition codes are irrelevent
+ set_cc 0x0e ; Condition codes are irrelevant
copop 15,255,cr0,cr15
test_cc 1 1 1 0
diff --git a/sim/testsuite/sim/fr30/copst.cgs b/sim/testsuite/sim/fr30/copst.cgs
index 00120b2..034b920 100644
--- a/sim/testsuite/sim/fr30/copst.cgs
+++ b/sim/testsuite/sim/fr30/copst.cgs
@@ -10,11 +10,11 @@
copst:
; Test copst copst $u4,$cc,$CRj,Ri
; The current implementation is a noop
- set_cc 0x0f ; Condition codes are irrelevent
+ set_cc 0x0f ; Condition codes are irrelevant
copst 0,0,cr0,r15
test_cc 1 1 1 1
- set_cc 0x0e ; Condition codes are irrelevent
+ set_cc 0x0e ; Condition codes are irrelevant
copst 15,255,cr15,r0
test_cc 1 1 1 0
diff --git a/sim/testsuite/sim/fr30/copsv.cgs b/sim/testsuite/sim/fr30/copsv.cgs
index e00a4f5..45b3e98 100644
--- a/sim/testsuite/sim/fr30/copsv.cgs
+++ b/sim/testsuite/sim/fr30/copsv.cgs
@@ -10,11 +10,11 @@
copsv:
; Test copsv copsv $u4,$cc,$CRj,Ri
; The current implementation is a noop
- set_cc 0x0f ; Condition codes are irrelevent
+ set_cc 0x0f ; Condition codes are irrelevant
copsv 0,0,cr0,r15
test_cc 1 1 1 1
- set_cc 0x0e ; Condition codes are irrelevent
+ set_cc 0x0e ; Condition codes are irrelevant
copsv 15,255,cr15,r0
test_cc 1 1 1 0
diff --git a/sim/testsuite/sim/fr30/enter.cgs b/sim/testsuite/sim/fr30/enter.cgs
index ae75e16..7d20845 100644
--- a/sim/testsuite/sim/fr30/enter.cgs
+++ b/sim/testsuite/sim/fr30/enter.cgs
@@ -12,7 +12,7 @@ enter:
mvr_h_gr sp,r7 ; save stack pointer
mvr_h_gr sp,r8 ; shadow stack pointer
mvr_h_gr sp,r14 ; Initialize
- set_cc 0x0f ; Condition codes are irrelevent
+ set_cc 0x0f ; Condition codes are irrelevant
enter 0
test_cc 1 1 1 1
testr_h_gr r8,sp
@@ -22,7 +22,7 @@ enter:
mvr_h_gr sp,r8 ; shadow stack pointer
mvr_h_gr r14,r9 ; save
- set_cc 0x0e ; Condition codes are irrelevent
+ set_cc 0x0e ; Condition codes are irrelevant
enter 0x3fc
test_cc 1 1 1 0
inci_h_gr -4,r8
diff --git a/sim/testsuite/sim/fr30/extsb.cgs b/sim/testsuite/sim/fr30/extsb.cgs
index 6a18d7e..8d4158a 100644
--- a/sim/testsuite/sim/fr30/extsb.cgs
+++ b/sim/testsuite/sim/fr30/extsb.cgs
@@ -10,25 +10,25 @@
extsb:
; Test extsb $Ri
mvi_h_gr 0,r7
- set_cc 0x0f ; Condition codes are irrelevent
+ set_cc 0x0f ; Condition codes are irrelevant
extsb r7
test_cc 1 1 1 1
test_h_gr 0,r7
mvi_h_gr 0x7f,r7
- set_cc 0x0e ; Condition codes are irrelevent
+ set_cc 0x0e ; Condition codes are irrelevant
extsb r7
test_cc 1 1 1 0
test_h_gr 0x7f,r7
mvi_h_gr 0x80,r7
- set_cc 0x0d ; Condition codes are irrelevent
+ set_cc 0x0d ; Condition codes are irrelevant
extsb r7
test_cc 1 1 0 1
test_h_gr 0xffffff80,r7
mvi_h_gr 0xffffff7f,r7
- set_cc 0x0c ; Condition codes are irrelevent
+ set_cc 0x0c ; Condition codes are irrelevant
extsb r7
test_cc 1 1 0 0
test_h_gr 0x7f,r7
diff --git a/sim/testsuite/sim/fr30/extsh.cgs b/sim/testsuite/sim/fr30/extsh.cgs
index eb12fd0..1e575ee 100644
--- a/sim/testsuite/sim/fr30/extsh.cgs
+++ b/sim/testsuite/sim/fr30/extsh.cgs
@@ -10,37 +10,37 @@
extsh:
; Test extsh $Ri
mvi_h_gr 0,r7
- set_cc 0x0f ; Condition codes are irrelevent
+ set_cc 0x0f ; Condition codes are irrelevant
extsh r7
test_cc 1 1 1 1
test_h_gr 0,r7
mvi_h_gr 0x7f,r7
- set_cc 0x0e ; Condition codes are irrelevent
+ set_cc 0x0e ; Condition codes are irrelevant
extsh r7
test_cc 1 1 1 0
test_h_gr 0x7f,r7
mvi_h_gr 0x80,r7
- set_cc 0x0d ; Condition codes are irrelevent
+ set_cc 0x0d ; Condition codes are irrelevant
extsh r7
test_cc 1 1 0 1
test_h_gr 0x80,r7
mvi_h_gr 0x7fff,r7
- set_cc 0x0c ; Condition codes are irrelevent
+ set_cc 0x0c ; Condition codes are irrelevant
extsh r7
test_cc 1 1 0 0
test_h_gr 0x7fff,r7
mvi_h_gr 0x8000,r7
- set_cc 0x0b ; Condition codes are irrelevent
+ set_cc 0x0b ; Condition codes are irrelevant
extsh r7
test_cc 1 0 1 1
test_h_gr 0xffff8000,r7
mvi_h_gr 0xffff7fff,r7
- set_cc 0x0a ; Condition codes are irrelevent
+ set_cc 0x0a ; Condition codes are irrelevant
extsh r7
test_cc 1 0 1 0
test_h_gr 0x7fff,r7
diff --git a/sim/testsuite/sim/fr30/extub.cgs b/sim/testsuite/sim/fr30/extub.cgs
index ddcc683..846f95f 100644
--- a/sim/testsuite/sim/fr30/extub.cgs
+++ b/sim/testsuite/sim/fr30/extub.cgs
@@ -10,31 +10,31 @@
extub:
; Test extub $Ri
mvi_h_gr 0,r7
- set_cc 0x0f ; Condition codes are irrelevent
+ set_cc 0x0f ; Condition codes are irrelevant
extub r7
test_cc 1 1 1 1
test_h_gr 0,r7
mvi_h_gr 0x7f,r7
- set_cc 0x0e ; Condition codes are irrelevent
+ set_cc 0x0e ; Condition codes are irrelevant
extub r7
test_cc 1 1 1 0
test_h_gr 0x7f,r7
mvi_h_gr 0x80,r7
- set_cc 0x0d ; Condition codes are irrelevent
+ set_cc 0x0d ; Condition codes are irrelevant
extub r7
test_cc 1 1 0 1
test_h_gr 0x80,r7
mvi_h_gr 0xffffff7f,r7
- set_cc 0x0c ; Condition codes are irrelevent
+ set_cc 0x0c ; Condition codes are irrelevant
extub r7
test_cc 1 1 0 0
test_h_gr 0x7f,r7
mvi_h_gr 0xffffff80,r7
- set_cc 0x0b ; Condition codes are irrelevent
+ set_cc 0x0b ; Condition codes are irrelevant
extub r7
test_cc 1 0 1 1
test_h_gr 0x80,r7
diff --git a/sim/testsuite/sim/fr30/extuh.cgs b/sim/testsuite/sim/fr30/extuh.cgs
index fa2579e..c4ed4ad 100644
--- a/sim/testsuite/sim/fr30/extuh.cgs
+++ b/sim/testsuite/sim/fr30/extuh.cgs
@@ -10,43 +10,43 @@
extuh:
; Test extuh $Ri
mvi_h_gr 0,r7
- set_cc 0x0f ; Condition codes are irrelevent
+ set_cc 0x0f ; Condition codes are irrelevant
extuh r7
test_cc 1 1 1 1
test_h_gr 0,r7
mvi_h_gr 0x7f,r7
- set_cc 0x0e ; Condition codes are irrelevent
+ set_cc 0x0e ; Condition codes are irrelevant
extuh r7
test_cc 1 1 1 0
test_h_gr 0x7f,r7
mvi_h_gr 0x80,r7
- set_cc 0x0d ; Condition codes are irrelevent
+ set_cc 0x0d ; Condition codes are irrelevant
extuh r7
test_cc 1 1 0 1
test_h_gr 0x80,r7
mvi_h_gr 0x7fff,r7
- set_cc 0x0e ; Condition codes are irrelevent
+ set_cc 0x0e ; Condition codes are irrelevant
extuh r7
test_cc 1 1 1 0
test_h_gr 0x7fff,r7
mvi_h_gr 0x8000,r7
- set_cc 0x0d ; Condition codes are irrelevent
+ set_cc 0x0d ; Condition codes are irrelevant
extuh r7
test_cc 1 1 0 1
test_h_gr 0x8000,r7
mvi_h_gr 0xffff7fff,r7
- set_cc 0x0c ; Condition codes are irrelevent
+ set_cc 0x0c ; Condition codes are irrelevant
extuh r7
test_cc 1 1 0 0
test_h_gr 0x7fff,r7
mvi_h_gr 0xffff8000,r7
- set_cc 0x0b ; Condition codes are irrelevent
+ set_cc 0x0b ; Condition codes are irrelevant
extuh r7
test_cc 1 0 1 1
test_h_gr 0x8000,r7
diff --git a/sim/testsuite/sim/fr30/ldres.cgs b/sim/testsuite/sim/fr30/ldres.cgs
index 0083489..c03e341 100644
--- a/sim/testsuite/sim/fr30/ldres.cgs
+++ b/sim/testsuite/sim/fr30/ldres.cgs
@@ -11,13 +11,13 @@ ldres:
; Test ldres $@Ri+,$u4
; The current implementation simply increments Ri
mvi_h_gr 0x1000,r7
- set_cc 0x0f ; Condition codes are irrelevent
+ set_cc 0x0f ; Condition codes are irrelevant
ldres @r7+,0
test_cc 1 1 1 1
test_h_gr 0x1004,r7
mvi_h_gr 0x1000,r7
- set_cc 0x0f ; Condition codes are irrelevent
+ set_cc 0x0f ; Condition codes are irrelevant
ldres @r7+,0xf
test_cc 1 1 1 1
test_h_gr 0x1004,r7
diff --git a/sim/testsuite/sim/fr30/leave.cgs b/sim/testsuite/sim/fr30/leave.cgs
index 4d3dd70..225d3ed 100644
--- a/sim/testsuite/sim/fr30/leave.cgs
+++ b/sim/testsuite/sim/fr30/leave.cgs
@@ -14,7 +14,7 @@ leave:
inci_h_gr -4,r14
mvi_h_mem 0xdeadbeef,r14
mvi_h_gr 0xbeefdead,r15
- set_cc 0x0f ; Condition codes are irrelevent
+ set_cc 0x0f ; Condition codes are irrelevant
leave
test_cc 1 1 1 1
testr_h_gr sp,r7
diff --git a/sim/testsuite/sim/fr30/nop.cgs b/sim/testsuite/sim/fr30/nop.cgs
index 885c55c..10848ae 100644
--- a/sim/testsuite/sim/fr30/nop.cgs
+++ b/sim/testsuite/sim/fr30/nop.cgs
@@ -9,7 +9,7 @@
.global nop
nop:
; Test nop
- set_cc 0x0f ; Condition codes are irrelevent
+ set_cc 0x0f ; Condition codes are irrelevant
nop
test_cc 1 1 1 1
diff --git a/sim/testsuite/sim/fr30/stres.cgs b/sim/testsuite/sim/fr30/stres.cgs
index a85fdf3..fd9c07e 100644
--- a/sim/testsuite/sim/fr30/stres.cgs
+++ b/sim/testsuite/sim/fr30/stres.cgs
@@ -11,13 +11,13 @@ stres:
; Test stres $@Ri+,$u4
; The current implementation simply increments Ri
mvi_h_gr 0x1000,r7
- set_cc 0x0f ; Condition codes are irrelevent
+ set_cc 0x0f ; Condition codes are irrelevant
stres 0,@r7+
test_cc 1 1 1 1
test_h_gr 0x1004,r7
mvi_h_gr 0x1000,r7
- set_cc 0x0f ; Condition codes are irrelevent
+ set_cc 0x0f ; Condition codes are irrelevant
stres 0xf,@r7+
test_cc 1 1 1 1
test_h_gr 0x1004,r7
diff --git a/sim/testsuite/sim/fr30/xchb.cgs b/sim/testsuite/sim/fr30/xchb.cgs
index 3450a2e..08b8fb5 100644
--- a/sim/testsuite/sim/fr30/xchb.cgs
+++ b/sim/testsuite/sim/fr30/xchb.cgs
@@ -11,7 +11,7 @@ xchb:
; Test xchb @$Rj,Ri
mvi_h_mem 0xdeadbeef,sp
mvi_h_gr 0xbeefdead,r0
- set_cc 0x0f ; Condition codes are irrelevent
+ set_cc 0x0f ; Condition codes are irrelevant
xchb @sp,r0
test_cc 1 1 1 1
test_h_gr 0xde,r0
diff --git a/sim/testsuite/sim/h8300/ldc.s b/sim/testsuite/sim/h8300/ldc.s
index 3712a6c..56eb949 100644
--- a/sim/testsuite/sim/h8300/ldc.s
+++ b/sim/testsuite/sim/h8300/ldc.s
@@ -341,7 +341,7 @@ ldc_reg_sbr:
mov #0xaaaaaaaa, er0
ldc er0, sbr ; set sbr to 0xaaaaaaaa
- stc sbr, er1 ; retreive and check sbr value
+ stc sbr, er1 ; retrieve and check sbr value
test_h_gr32 0xaaaaaaaa er1
test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
@@ -358,7 +358,7 @@ ldc_reg_vbr:
mov #0xaaaaaaaa, er0
ldc er0, vbr ; set sbr to 0xaaaaaaaa
- stc vbr, er1 ; retreive and check sbr value
+ stc vbr, er1 ; retrieve and check sbr value
test_h_gr32 0xaaaaaaaa er1
test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
diff --git a/sim/testsuite/sim/h8300/stc.s b/sim/testsuite/sim/h8300/stc.s
index 232bd5a..4b86ff3 100644
--- a/sim/testsuite/sim/h8300/stc.s
+++ b/sim/testsuite/sim/h8300/stc.s
@@ -304,7 +304,7 @@ stc_sbr_reg:
mov #0xaaaaaaaa, er0
ldc er0, sbr ; set sbr to 0xaaaaaaaa
- stc sbr, er1 ; retreive and check sbr value
+ stc sbr, er1 ; retrieve and check sbr value
test_h_gr32 0xaaaaaaaa er1
test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
@@ -321,7 +321,7 @@ stc_vbr_reg:
mov #0xaaaaaaaa, er0
ldc er0, vbr ; set sbr to 0xaaaaaaaa
- stc vbr, er1 ; retreive and check sbr value
+ stc vbr, er1 ; retrieve and check sbr value
test_h_gr32 0xaaaaaaaa er1
test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
diff --git a/sim/testsuite/sim/mips/hilo-hazard-3.s b/sim/testsuite/sim/mips/hilo-hazard-3.s
index 1a0949d..e9a1595 100644
--- a/sim/testsuite/sim/mips/hilo-hazard-3.s
+++ b/sim/testsuite/sim/mips/hilo-hazard-3.s
@@ -1,4 +1,4 @@
-# Test for mf{hi,lo} -> mult/div/mt{hi,lo} with 2 nops inbetween.
+# Test for mf{hi,lo} -> mult/div/mt{hi,lo} with 2 nops in between.
#
# mach: all
# as: -mabi=eabi
diff --git a/sim/testsuite/sim/mips/hilo-hazard-4.s b/sim/testsuite/sim/mips/hilo-hazard-4.s
index 8a4c888..ba298b4 100644
--- a/sim/testsuite/sim/mips/hilo-hazard-4.s
+++ b/sim/testsuite/sim/mips/hilo-hazard-4.s
@@ -1,4 +1,4 @@
-# Test for mf{hi,lo} -> mult/div/mt{hi,lo} with 2 nops inbetween.
+# Test for mf{hi,lo} -> mult/div/mt{hi,lo} with 2 nops in between.
#
# mach: all
# as: -mabi=eabi -mmicromips
diff --git a/sim/testsuite/sim/sh/fipr.s b/sim/testsuite/sim/sh/fipr.s
index 6a949aa..50bbc5c 100644
--- a/sim/testsuite/sim/sh/fipr.s
+++ b/sim/testsuite/sim/sh/fipr.s
@@ -58,7 +58,7 @@ test_infp:
# fr11 should be plus infinity
assert_fpreg_x 0x7f800000, fr11
test_infm:
- # Test negitive infinity
+ # Test negative infinity
fldi0 fr11
mov.l infm, r0
lds r0, fpul
--
2.7.4
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