* [PATCH v2 1/9] RISC-V: Remove the redundant gas test file.
2020-05-06 2:55 [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR Nelson Chu
@ 2020-05-06 2:55 ` Nelson Chu
2020-05-19 9:07 ` Nelson Chu
2020-05-06 2:55 ` [PATCH v2 2/9] RISC-V: Forgot to update the priv-reg-fail-read-only-01 test case Nelson Chu
` (8 subsequent siblings)
9 siblings, 1 reply; 25+ messages in thread
From: Nelson Chu @ 2020-05-06 2:55 UTC (permalink / raw)
To: binutils, gdb-patches
Cc: palmer, kito.cheng, jimw, andrew, andrew.burgess, asb,
maxim.blinov, nelson.chu
gas/
* testsuite/gas/riscv/march-fail-s-with-version: Removed.
---
gas/testsuite/gas/riscv/march-fail-s-with-version | 2 --
1 file changed, 2 deletions(-)
delete mode 100644 gas/testsuite/gas/riscv/march-fail-s-with-version
diff --git a/gas/testsuite/gas/riscv/march-fail-s-with-version b/gas/testsuite/gas/riscv/march-fail-s-with-version
deleted file mode 100644
index a514d4a..0000000
--- a/gas/testsuite/gas/riscv/march-fail-s-with-version
+++ /dev/null
@@ -1,2 +0,0 @@
-Assembler messages:
-.*: Invalid or unknown s ISA extension: 'sfoo'
\ No newline at end of file
--
2.7.4
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [PATCH v2 1/9] RISC-V: Remove the redundant gas test file.
2020-05-06 2:55 ` [PATCH v2 1/9] RISC-V: Remove the redundant gas test file Nelson Chu
@ 2020-05-19 9:07 ` Nelson Chu
0 siblings, 0 replies; 25+ messages in thread
From: Nelson Chu @ 2020-05-19 9:07 UTC (permalink / raw)
To: Binutils, gdb-patches
Cc: Palmer Dabbelt, Kito Cheng, Jim Wilson, Andrew Waterman,
Andrew Burgess, Alex Bradbury, Maxim Blinov
PING :)
On Wed, May 6, 2020 at 10:55 AM Nelson Chu <nelson.chu@sifive.com> wrote:
>
> gas/
> * testsuite/gas/riscv/march-fail-s-with-version: Removed.
> ---
> gas/testsuite/gas/riscv/march-fail-s-with-version | 2 --
> 1 file changed, 2 deletions(-)
> delete mode 100644 gas/testsuite/gas/riscv/march-fail-s-with-version
>
> diff --git a/gas/testsuite/gas/riscv/march-fail-s-with-version b/gas/testsuite/gas/riscv/march-fail-s-with-version
> deleted file mode 100644
> index a514d4a..0000000
> --- a/gas/testsuite/gas/riscv/march-fail-s-with-version
> +++ /dev/null
> @@ -1,2 +0,0 @@
> -Assembler messages:
> -.*: Invalid or unknown s ISA extension: 'sfoo'
> \ No newline at end of file
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 2/9] RISC-V: Forgot to update the priv-reg-fail-read-only-01 test case.
2020-05-06 2:55 [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR Nelson Chu
2020-05-06 2:55 ` [PATCH v2 1/9] RISC-V: Remove the redundant gas test file Nelson Chu
@ 2020-05-06 2:55 ` Nelson Chu
2020-05-19 9:07 ` Nelson Chu
2020-05-06 2:55 ` [PATCH v2 3/9] RISC-V: Support GAS option -misa-spec to set ISA versions Nelson Chu
` (7 subsequent siblings)
9 siblings, 1 reply; 25+ messages in thread
From: Nelson Chu @ 2020-05-06 2:55 UTC (permalink / raw)
To: binutils, gdb-patches
Cc: palmer, kito.cheng, jimw, andrew, andrew.burgess, asb,
maxim.blinov, nelson.chu
priv-reg and priv-reg-fail-read-only-01 should be updated at the same time.
The fromer checks all CSR by csrr instructions, and the later uses csrw to
check whether the CSR is read only or not.
gas/
* testsuite/gas/riscv/priv-reg-fail-read-only-01.s: Updated.
---
.../gas/riscv/priv-reg-fail-read-only-01.s | 114 ++++++++++-----------
1 file changed, 57 insertions(+), 57 deletions(-)
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.s b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.s
index 501a52e..3646c80 100644
--- a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.s
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.s
@@ -1,7 +1,8 @@
.macro csr val
csrw \val, a1
.endm
-# 1.9.1 registers
+
+ # Supported the current priv spec 1.11.
csr ustatus
csr uie
csr utvec
@@ -9,7 +10,7 @@
csr uscratch
csr uepc
csr ucause
- csr ubadaddr
+ csr utval # Added in 1.10
csr uip
csr fflags
@@ -86,26 +87,15 @@
csr sideleg
csr sie
csr stvec
+ csr scounteren # Added in 1.10
csr sscratch
csr sepc
csr scause
- csr sbadaddr
+ csr stval # Added in 1.10
csr sip
- csr sptbr
-
- csr hstatus
- csr hedeleg
- csr hideleg
- csr hie
- csr htvec
-
- csr hscratch
- csr hepc
- csr hcause
- csr hbadaddr
- csr hip
+ csr satp # Added in 1.10
csr mvendorid
csr marchid
@@ -113,24 +103,39 @@
csr mhartid
csr mstatus
- csr misa
+ csr misa # 0xf10 in 1.9, but changed to 0x301 since 1.9.1.
csr medeleg
csr mideleg
csr mie
csr mtvec
+ csr mcounteren # Added in 1.10
csr mscratch
csr mepc
csr mcause
- csr mbadaddr
+ csr mtval # Added in 1.10
csr mip
- csr mbase
- csr mbound
- csr mibase
- csr mibound
- csr mdbase
- csr mdbound
+ csr pmpcfg0 # Added in 1.10
+ csr pmpcfg1 # Added in 1.10
+ csr pmpcfg2 # Added in 1.10
+ csr pmpcfg3 # Added in 1.10
+ csr pmpaddr0 # Added in 1.10
+ csr pmpaddr1 # Added in 1.10
+ csr pmpaddr2 # Added in 1.10
+ csr pmpaddr3 # Added in 1.10
+ csr pmpaddr4 # Added in 1.10
+ csr pmpaddr5 # Added in 1.10
+ csr pmpaddr6 # Added in 1.10
+ csr pmpaddr7 # Added in 1.10
+ csr pmpaddr8 # Added in 1.10
+ csr pmpaddr9 # Added in 1.10
+ csr pmpaddr10 # Added in 1.10
+ csr pmpaddr11 # Added in 1.10
+ csr pmpaddr12 # Added in 1.10
+ csr pmpaddr13 # Added in 1.10
+ csr pmpaddr14 # Added in 1.10
+ csr pmpaddr15 # Added in 1.10
csr mcycle
csr minstret
@@ -195,10 +200,7 @@
csr mhpmcounter30h
csr mhpmcounter31h
- csr mucounteren
- csr mscounteren
- csr mhcounteren
-
+ csr mcountinhibit # Added in 1.11
csr mhpmevent3
csr mhpmevent4
csr mhpmevent5
@@ -236,34 +238,32 @@
csr dcsr
csr dpc
- csr dscratch
-# 1.10 registers
- csr utval
-
- csr scounteren
- csr stval
- csr satp
+ csr dscratch0 # Added in 1.11
+ csr dscratch1 # Added in 1.11
- csr mcounteren
- csr mtval
+ # Supported in previous priv spec, but dropped now.
+ csr ubadaddr # 0x043 in 1.9.1, but the value is utval since 1.10
+ csr sbadaddr # 0x143 in 1.9.1, but the value is stval since 1.10
+ csr sptbr # 0x180 in 1.9.1, but the value is satp since 1.10
+ csr mbadaddr # 0x343 in 1.9.1, but the value is mtval since 1.10
+ csr mucounteren # 0x320 in 1.9.1, dropped in 1.10, but the value is mcountinhibit since 1.11
+ csr dscratch # 0x7b2 in 1.10, but the value is dscratch0 since 1.11
- csr pmpcfg0
- csr pmpcfg1
- csr pmpcfg2
- csr pmpcfg3
- csr pmpaddr0
- csr pmpaddr1
- csr pmpaddr2
- csr pmpaddr3
- csr pmpaddr4
- csr pmpaddr5
- csr pmpaddr6
- csr pmpaddr7
- csr pmpaddr8
- csr pmpaddr9
- csr pmpaddr10
- csr pmpaddr11
- csr pmpaddr12
- csr pmpaddr13
- csr pmpaddr14
- csr pmpaddr15
+ csr hstatus # 0x200, dropped in 1.10
+ csr hedeleg # 0x202, dropped in 1.10
+ csr hideleg # 0x203, dropped in 1.10
+ csr hie # 0x204, dropped in 1.10
+ csr htvec # 0x205, dropped in 1.10
+ csr hscratch # 0x240, dropped in 1.10
+ csr hepc # 0x241, dropped in 1.10
+ csr hcause # 0x242, dropped in 1.10
+ csr hbadaddr # 0x243, dropped in 1.10
+ csr hip # 0x244, dropped in 1.10
+ csr mbase # 0x380, dropped in 1.10
+ csr mbound # 0x381, dropped in 1.10
+ csr mibase # 0x382, dropped in 1.10
+ csr mibound # 0x383, dropped in 1.10
+ csr mdbase # 0x384, dropped in 1.10
+ csr mdbound # 0x385, dropped in 1.10
+ csr mscounteren # 0x321, dropped in 1.10
+ csr mhcounteren # 0x322, dropped in 1.10
--
2.7.4
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [PATCH v2 2/9] RISC-V: Forgot to update the priv-reg-fail-read-only-01 test case.
2020-05-06 2:55 ` [PATCH v2 2/9] RISC-V: Forgot to update the priv-reg-fail-read-only-01 test case Nelson Chu
@ 2020-05-19 9:07 ` Nelson Chu
0 siblings, 0 replies; 25+ messages in thread
From: Nelson Chu @ 2020-05-19 9:07 UTC (permalink / raw)
To: Binutils, gdb-patches
Cc: Palmer Dabbelt, Kito Cheng, Jim Wilson, Andrew Waterman,
Andrew Burgess, Alex Bradbury, Maxim Blinov
PING :)
On Wed, May 6, 2020 at 10:55 AM Nelson Chu <nelson.chu@sifive.com> wrote:
>
> priv-reg and priv-reg-fail-read-only-01 should be updated at the same time.
> The fromer checks all CSR by csrr instructions, and the later uses csrw to
> check whether the CSR is read only or not.
>
> gas/
> * testsuite/gas/riscv/priv-reg-fail-read-only-01.s: Updated.
> ---
> .../gas/riscv/priv-reg-fail-read-only-01.s | 114 ++++++++++-----------
> 1 file changed, 57 insertions(+), 57 deletions(-)
>
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.s b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.s
> index 501a52e..3646c80 100644
> --- a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.s
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.s
> @@ -1,7 +1,8 @@
> .macro csr val
> csrw \val, a1
> .endm
> -# 1.9.1 registers
> +
> + # Supported the current priv spec 1.11.
> csr ustatus
> csr uie
> csr utvec
> @@ -9,7 +10,7 @@
> csr uscratch
> csr uepc
> csr ucause
> - csr ubadaddr
> + csr utval # Added in 1.10
> csr uip
>
> csr fflags
> @@ -86,26 +87,15 @@
> csr sideleg
> csr sie
> csr stvec
> + csr scounteren # Added in 1.10
>
> csr sscratch
> csr sepc
> csr scause
> - csr sbadaddr
> + csr stval # Added in 1.10
> csr sip
>
> - csr sptbr
> -
> - csr hstatus
> - csr hedeleg
> - csr hideleg
> - csr hie
> - csr htvec
> -
> - csr hscratch
> - csr hepc
> - csr hcause
> - csr hbadaddr
> - csr hip
> + csr satp # Added in 1.10
>
> csr mvendorid
> csr marchid
> @@ -113,24 +103,39 @@
> csr mhartid
>
> csr mstatus
> - csr misa
> + csr misa # 0xf10 in 1.9, but changed to 0x301 since 1.9.1.
> csr medeleg
> csr mideleg
> csr mie
> csr mtvec
> + csr mcounteren # Added in 1.10
>
> csr mscratch
> csr mepc
> csr mcause
> - csr mbadaddr
> + csr mtval # Added in 1.10
> csr mip
>
> - csr mbase
> - csr mbound
> - csr mibase
> - csr mibound
> - csr mdbase
> - csr mdbound
> + csr pmpcfg0 # Added in 1.10
> + csr pmpcfg1 # Added in 1.10
> + csr pmpcfg2 # Added in 1.10
> + csr pmpcfg3 # Added in 1.10
> + csr pmpaddr0 # Added in 1.10
> + csr pmpaddr1 # Added in 1.10
> + csr pmpaddr2 # Added in 1.10
> + csr pmpaddr3 # Added in 1.10
> + csr pmpaddr4 # Added in 1.10
> + csr pmpaddr5 # Added in 1.10
> + csr pmpaddr6 # Added in 1.10
> + csr pmpaddr7 # Added in 1.10
> + csr pmpaddr8 # Added in 1.10
> + csr pmpaddr9 # Added in 1.10
> + csr pmpaddr10 # Added in 1.10
> + csr pmpaddr11 # Added in 1.10
> + csr pmpaddr12 # Added in 1.10
> + csr pmpaddr13 # Added in 1.10
> + csr pmpaddr14 # Added in 1.10
> + csr pmpaddr15 # Added in 1.10
>
> csr mcycle
> csr minstret
> @@ -195,10 +200,7 @@
> csr mhpmcounter30h
> csr mhpmcounter31h
>
> - csr mucounteren
> - csr mscounteren
> - csr mhcounteren
> -
> + csr mcountinhibit # Added in 1.11
> csr mhpmevent3
> csr mhpmevent4
> csr mhpmevent5
> @@ -236,34 +238,32 @@
>
> csr dcsr
> csr dpc
> - csr dscratch
> -# 1.10 registers
> - csr utval
> -
> - csr scounteren
> - csr stval
> - csr satp
> + csr dscratch0 # Added in 1.11
> + csr dscratch1 # Added in 1.11
>
> - csr mcounteren
> - csr mtval
> + # Supported in previous priv spec, but dropped now.
> + csr ubadaddr # 0x043 in 1.9.1, but the value is utval since 1.10
> + csr sbadaddr # 0x143 in 1.9.1, but the value is stval since 1.10
> + csr sptbr # 0x180 in 1.9.1, but the value is satp since 1.10
> + csr mbadaddr # 0x343 in 1.9.1, but the value is mtval since 1.10
> + csr mucounteren # 0x320 in 1.9.1, dropped in 1.10, but the value is mcountinhibit since 1.11
> + csr dscratch # 0x7b2 in 1.10, but the value is dscratch0 since 1.11
>
> - csr pmpcfg0
> - csr pmpcfg1
> - csr pmpcfg2
> - csr pmpcfg3
> - csr pmpaddr0
> - csr pmpaddr1
> - csr pmpaddr2
> - csr pmpaddr3
> - csr pmpaddr4
> - csr pmpaddr5
> - csr pmpaddr6
> - csr pmpaddr7
> - csr pmpaddr8
> - csr pmpaddr9
> - csr pmpaddr10
> - csr pmpaddr11
> - csr pmpaddr12
> - csr pmpaddr13
> - csr pmpaddr14
> - csr pmpaddr15
> + csr hstatus # 0x200, dropped in 1.10
> + csr hedeleg # 0x202, dropped in 1.10
> + csr hideleg # 0x203, dropped in 1.10
> + csr hie # 0x204, dropped in 1.10
> + csr htvec # 0x205, dropped in 1.10
> + csr hscratch # 0x240, dropped in 1.10
> + csr hepc # 0x241, dropped in 1.10
> + csr hcause # 0x242, dropped in 1.10
> + csr hbadaddr # 0x243, dropped in 1.10
> + csr hip # 0x244, dropped in 1.10
> + csr mbase # 0x380, dropped in 1.10
> + csr mbound # 0x381, dropped in 1.10
> + csr mibase # 0x382, dropped in 1.10
> + csr mibound # 0x383, dropped in 1.10
> + csr mdbase # 0x384, dropped in 1.10
> + csr mdbound # 0x385, dropped in 1.10
> + csr mscounteren # 0x321, dropped in 1.10
> + csr mhcounteren # 0x322, dropped in 1.10
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 3/9] RISC-V: Support GAS option -misa-spec to set ISA versions.
2020-05-06 2:55 [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR Nelson Chu
2020-05-06 2:55 ` [PATCH v2 1/9] RISC-V: Remove the redundant gas test file Nelson Chu
2020-05-06 2:55 ` [PATCH v2 2/9] RISC-V: Forgot to update the priv-reg-fail-read-only-01 test case Nelson Chu
@ 2020-05-06 2:55 ` Nelson Chu
2020-05-19 9:07 ` Nelson Chu
2020-05-06 2:55 ` [PATCH v2 4/9] RISC-V: Support configure options to set ISA versions by default Nelson Chu
` (6 subsequent siblings)
9 siblings, 1 reply; 25+ messages in thread
From: Nelson Chu @ 2020-05-06 2:55 UTC (permalink / raw)
To: binutils, gdb-patches
Cc: palmer, kito.cheng, jimw, andrew, andrew.burgess, asb,
maxim.blinov, nelson.chu
For now, we can only use the GAS option -march and ELF arch attribute
to set the versions for ISA extensions. It seems not so friendly for
user. Therefore, we support new GAS option to make it easiler.
* -misa-spec = [2.2|20190608|20191213]
You can simply choose the ISA spec by this option, and then assembler
will set the version for the standard extensions if you do not set in
the ELF arch attributes or -march option.
The default ISA spec is set to 2.2 rather than the lastest version, if
the -misa-spec is not set. The reason is that compiler generates the ISA
string with fixed 2p0 verisons only for the RISCV ELF architecture attributes,
but not for the -march option. We should resolve this in the future patches.
gas/
* config/tc-riscv.c (default_arch_with_ext, default_isa_spec):
Static variables which are used to set the ISA extensions. You can
use -march (or ELF build attributes) and -misa-spec to set them,
respectively.
(ext_version_hash): The hash table used to handle the extensions
with versions.
(init_ext_version_hash): Initialize the ext_version_hash according
to riscv_ext_version_table.
(riscv_get_default_ext_version): The callback function of
riscv_parse_subset_t. According to the choosed ISA spec,
get the default version for the specific extension.
(riscv_set_arch): Set the callback function.
(enum options, struct option md_longopts): Add new option -misa-spec.
(md_parse_option): Do not call riscv_set_arch for -march. We will
call it later in riscv_after_parse_args. Call riscv_get_isa_spec_class
to set default_isa_spec class.
(riscv_after_parse_args): Call init_ext_version_hash to initialize the
ext_version_hash, and then call riscv_set_arch to set the architecture
with versions according to default_arch_with_ext.
* testsuite/gas/riscv/attribute-02.d: Set 0p0 as default version for
x extensions.
* testsuite/gas/riscv/attribute-03.d: Likewise.
* testsuite/gas/riscv/attribute-09.d: New testcase. For i-ext, we
already set it's version to 2p1 by march, so no need to use the default
2p2 version. For m-ext, we do not set the version by -march and ELF arch
attribute, so set the default 2p0 to it. For zicsr, it is not defined in
ISA spec 2p2, so set 0p0 to it.
* testsuite/gas/riscv/attribute-10.d: New testcase. The version of
zicsr is 2p0 according to ISA spec 20191213.
bfd/
* elfxx-riscv.h (riscv_parse_subset_t): Add new callback function
get_default_version. It is used to find the default version for
the specific extension.
* elfxx-riscv.c (riscv_parsing_subset_version): Remove the parameters
default_major_version and default_minor_version. Add new bfd_boolean
parameter *use_default_version. Set it to TRUE if we need to call
the callback rps->get_default_version to find the default version.
(riscv_parse_std_ext): Call rps->get_default_version if we fail to find
the default version in riscv_parsing_subset_version, and then call
riscv_add_subset to add the subset into subset list.
(riscv_parse_prefixed_ext): Likewise.
(riscv_std_z_ext_strtab): Support Zicsr extensions.
* elfnn-riscv.c (riscv_merge_std_ext): Use strcasecmp to compare the
strings rather than characters.
riscv_merge_arch_attr_info): The callback function get_default_version
is only needed for assembler, so set it to NULL int the linker.
include/
* opcode/riscv.h: Include "bfd.h" to support bfd_boolean.
(enum riscv_isa_spec_class): New enum class. All supported ISA spec
belong to one of the class
(struct riscv_ext_version): New structure holds version information
for the specific ISA.
opcodes/
* riscv-opc.c (riscv_ext_version_table): The table used to store
all information about the supported spec and the corresponding ISA
versions. Currently, only Zicsr is supported to verify the
correctness of Z sub extension settings. Others will be supported
in the future patches.
(struct isa_spec_t, isa_specs): List for all supported ISA spec
classes and the corresponding strings.
(riscv_get_isa_spec_class): New function. Get the corresponding ISA
spec class by giving a ISA spec string.
---
bfd/elfnn-riscv.c | 6 +-
bfd/elfxx-riscv.c | 203 +++++++++++++++++++--------------
bfd/elfxx-riscv.h | 3 +
gas/config/tc-riscv.c | 100 +++++++++++++++-
gas/testsuite/gas/riscv/attribute-02.d | 2 +-
gas/testsuite/gas/riscv/attribute-03.d | 2 +-
gas/testsuite/gas/riscv/attribute-09.d | 6 +
gas/testsuite/gas/riscv/attribute-10.d | 6 +
include/opcode/riscv.h | 26 +++++
opcodes/riscv-opc.c | 93 +++++++++++++++
10 files changed, 355 insertions(+), 92 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/attribute-09.d
create mode 100644 gas/testsuite/gas/riscv/attribute-10.d
diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
index 473bf50..2b5e713 100644
--- a/bfd/elfnn-riscv.c
+++ b/bfd/elfnn-riscv.c
@@ -2802,7 +2802,7 @@ riscv_merge_std_ext (bfd *ibfd,
if (!riscv_i_or_e_p (ibfd, out_arch, out))
return FALSE;
- if (in->name[0] != out->name[0])
+ if (strcasecmp (in->name, out->name) != 0)
{
/* TODO: We might allow merge 'i' with 'e'. */
_bfd_error_handler
@@ -2975,13 +2975,17 @@ riscv_merge_arch_attr_info (bfd *ibfd, char *in_arch, char *out_arch)
riscv_parse_subset_t rpe_in;
riscv_parse_subset_t rpe_out;
+ /* Only assembler needs to check the default version of ISA, so just set
+ the rpe_in.get_default_version and rpe_out.get_default_version to NULL. */
rpe_in.subset_list = &in_subsets;
rpe_in.error_handler = _bfd_error_handler;
rpe_in.xlen = &xlen_in;
+ rpe_in.get_default_version = NULL;
rpe_out.subset_list = &out_subsets;
rpe_out.error_handler = _bfd_error_handler;
rpe_out.xlen = &xlen_out;
+ rpe_out.get_default_version = NULL;
if (in_arch == NULL && out_arch == NULL)
return NULL;
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index b15fdee..e025689 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1025,9 +1025,8 @@ riscv_elf_add_sub_reloc (bfd *abfd,
`minor_version`: Parsing result of minor version, set to 0 if version is
not present in arch string, but set to `default_minor_version` if
`major_version` using default_major_version.
- `default_major_version`: Default major version.
- `default_minor_version`: Default minor version.
- `std_ext_p`: True if parsing std extension. */
+ `std_ext_p`: True if parsing std extension.
+ `use_default_version`: Set it to True if we need the default version. */
static const char *
riscv_parsing_subset_version (riscv_parse_subset_t *rps,
@@ -1035,17 +1034,16 @@ riscv_parsing_subset_version (riscv_parse_subset_t *rps,
const char *p,
unsigned *major_version,
unsigned *minor_version,
- unsigned default_major_version,
- unsigned default_minor_version,
- bfd_boolean std_ext_p)
+ bfd_boolean std_ext_p,
+ bfd_boolean *use_default_version)
{
bfd_boolean major_p = TRUE;
unsigned version = 0;
- unsigned major = 0;
- unsigned minor = 0;
char np;
- for (;*p; ++p)
+ *major_version = 0;
+ *minor_version = 0;
+ for (; *p; ++p)
{
if (*p == 'p')
{
@@ -1057,7 +1055,6 @@ riscv_parsing_subset_version (riscv_parse_subset_t *rps,
if (std_ext_p)
{
*major_version = version;
- *minor_version = 0;
return p;
}
else
@@ -1068,7 +1065,7 @@ riscv_parsing_subset_version (riscv_parse_subset_t *rps,
}
}
- major = version;
+ *major_version = version;
major_p = FALSE;
version = 0;
}
@@ -1079,21 +1076,15 @@ riscv_parsing_subset_version (riscv_parse_subset_t *rps,
}
if (major_p)
- major = version;
+ *major_version = version;
else
- minor = version;
+ *minor_version = version;
- if (major == 0 && minor == 0)
- {
- /* We don't found any version string, use default version. */
- *major_version = default_major_version;
- *minor_version = default_minor_version;
- }
- else
- {
- *major_version = major;
- *minor_version = minor;
- }
+ /* We can not find any version in string, need to parse default version. */
+ if (use_default_version != NULL
+ && *major_version == 0
+ && *minor_version == 0)
+ *use_default_version = TRUE;
return p;
}
@@ -1122,38 +1113,58 @@ riscv_parse_std_ext (riscv_parse_subset_t *rps,
{
const char *all_std_exts = riscv_supported_std_ext ();
const char *std_exts = all_std_exts;
-
unsigned major_version = 0;
unsigned minor_version = 0;
char std_ext = '\0';
+ bfd_boolean use_default_version = FALSE;
/* First letter must start with i, e or g. */
switch (*p)
{
case 'i':
- p++;
- p = riscv_parsing_subset_version (
- rps,
- march,
- p, &major_version, &minor_version,
- /* default_major_version= */ 2,
- /* default_minor_version= */ 0,
- /* std_ext_p= */TRUE);
- riscv_add_subset (rps->subset_list, "i", major_version, minor_version);
+ p = riscv_parsing_subset_version (rps,
+ march,
+ ++p,
+ &major_version,
+ &minor_version,
+ /* std_ext_p= */TRUE,
+ &use_default_version);
+
+ /* Find the default version if needed. */
+ if (use_default_version
+ && rps->get_default_version != NULL)
+ rps->get_default_version ("i",
+ &major_version,
+ &minor_version);
+ riscv_add_subset (rps->subset_list, "i",
+ major_version, minor_version);
break;
case 'e':
- p++;
- p = riscv_parsing_subset_version (
- rps,
- march,
- p, &major_version, &minor_version,
- /* default_major_version= */ 1,
- /* default_minor_version= */ 9,
- /* std_ext_p= */TRUE);
-
- riscv_add_subset (rps->subset_list, "e", major_version, minor_version);
- riscv_add_subset (rps->subset_list, "i", 2, 0);
+ p = riscv_parsing_subset_version (rps,
+ march,
+ ++p,
+ &major_version,
+ &minor_version,
+ /* std_ext_p= */TRUE,
+ &use_default_version);
+
+ /* Find the default version if needed. */
+ if (use_default_version
+ && rps->get_default_version != NULL)
+ rps->get_default_version ("e",
+ &major_version,
+ &minor_version);
+ riscv_add_subset (rps->subset_list, "e",
+ major_version, minor_version);
+
+ /* i-ext must be enabled. */
+ if (rps->get_default_version != NULL)
+ rps->get_default_version ("i",
+ &major_version,
+ &minor_version);
+ riscv_add_subset (rps->subset_list, "i",
+ major_version, minor_version);
if (*rps->xlen > 32)
{
@@ -1161,25 +1172,36 @@ riscv_parse_std_ext (riscv_parse_subset_t *rps,
march, *rps->xlen);
return NULL;
}
-
break;
case 'g':
- p++;
- p = riscv_parsing_subset_version (
- rps,
- march,
- p, &major_version, &minor_version,
- /* default_major_version= */ 2,
- /* default_minor_version= */ 0,
- /* std_ext_p= */TRUE);
- riscv_add_subset (rps->subset_list, "i", major_version, minor_version);
+ /* The g-ext shouldn't has the version, so we just skip the setting if
+ user set a version to it. */
+ p = riscv_parsing_subset_version (rps,
+ march,
+ ++p,
+ &major_version,
+ &minor_version,
+ TRUE,
+ &use_default_version);
+
+ /* i-ext must be enabled. */
+ if (rps->get_default_version != NULL)
+ rps->get_default_version ("i",
+ &major_version,
+ &minor_version);
+ riscv_add_subset (rps->subset_list, "i",
+ major_version, minor_version);
for ( ; *std_exts != 'q'; std_exts++)
{
const char subset[] = {*std_exts, '\0'};
- riscv_add_subset (
- rps->subset_list, subset, major_version, minor_version);
+ if (rps->get_default_version != NULL)
+ rps->get_default_version (subset,
+ &major_version,
+ &minor_version);
+ riscv_add_subset (rps->subset_list, subset,
+ major_version, minor_version);
}
break;
@@ -1189,7 +1211,9 @@ riscv_parse_std_ext (riscv_parse_subset_t *rps,
return NULL;
}
- while (*p)
+ /* The riscv_parsing_subset_version may set `p` to NULL, so I think we should
+ skip parsing the string if `p` is NULL or value of `p` is `\0`. */
+ while (p != NULL && *p != '\0')
{
char subset[2] = {0, 0};
@@ -1218,21 +1242,26 @@ riscv_parse_std_ext (riscv_parse_subset_t *rps,
march, *p);
return NULL;
}
-
std_exts++;
- p++;
- p = riscv_parsing_subset_version (
- rps,
- march,
- p, &major_version, &minor_version,
- /* default_major_version= */ 2,
- /* default_minor_version= */ 0,
- /* std_ext_p= */TRUE);
-
+ use_default_version = FALSE;
subset[0] = std_ext;
-
- riscv_add_subset (rps->subset_list, subset, major_version, minor_version);
+ p = riscv_parsing_subset_version (rps,
+ march,
+ ++p,
+ &major_version,
+ &minor_version,
+ TRUE,
+ &use_default_version);
+
+ /* Find the default version if needed. */
+ if (use_default_version
+ && rps->get_default_version != NULL)
+ rps->get_default_version (subset,
+ &major_version,
+ &minor_version);
+ riscv_add_subset (rps->subset_list, subset,
+ major_version, minor_version);
}
return p;
}
@@ -1272,9 +1301,10 @@ typedef struct riscv_parse_config
} riscv_parse_config_t;
/* Parse a generic prefixed extension.
- march: The full architecture string as passed in by "-march=...".
- p: Point from which to start parsing the -march string.
- config: What class of extensions to parse, predicate funcs,
+ `rps`: Hooks and status for parsing subset.
+ `march`: The full architecture string as passed in by "-march=...".
+ `p`: Point from which to start parsing the -march string.
+ `config`: What class of extensions to parse, predicate funcs,
and strings to use in error reporting. */
static const char *
@@ -1287,6 +1317,7 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
unsigned minor_version = 0;
const char *last_name;
riscv_isa_ext_class_t class;
+ bfd_boolean use_default_version;
while (*p)
{
@@ -1309,15 +1340,11 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
while (*++q != '\0' && *q != '_' && !ISDIGIT (*q))
;
+ use_default_version = FALSE;
end_of_version =
- riscv_parsing_subset_version (
- rps,
- march,
- q, &major_version, &minor_version,
- /* default_major_version= */ 2,
- /* default_minor_version= */ 0,
- /* std_ext_p= */FALSE);
-
+ riscv_parsing_subset_version (rps, march, q, &major_version,
+ &minor_version, FALSE,
+ &use_default_version);
*q = '\0';
/* Check that the name is valid.
@@ -1337,7 +1364,6 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
/* Check that the last item is not the same as this. */
last_name = rps->subset_list->tail->name;
-
if (!strcasecmp (last_name, subset))
{
rps->error_handler ("-march=%s: Duplicate %s ISA extension: \'%s\'",
@@ -1357,7 +1383,15 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
return NULL;
}
- riscv_add_subset (rps->subset_list, subset, major_version, minor_version);
+ /* Find the default version if needed. */
+ if (use_default_version
+ && rps->get_default_version != NULL)
+ rps->get_default_version (subset,
+ &major_version,
+ &minor_version);
+ riscv_add_subset (rps->subset_list, subset,
+ major_version, minor_version);
+
free (subset);
p += end_of_version - subset;
@@ -1384,7 +1418,7 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
static const char * const riscv_std_z_ext_strtab[] =
{
- NULL
+ "zicsr", NULL
};
/* Same as `riscv_std_z_ext_strtab', but for S-class extensions. */
@@ -1490,7 +1524,6 @@ riscv_parse_subset (riscv_parse_subset_t *rps,
return FALSE;
/* Parse the different classes of extensions in the specified order. */
-
for (i = 0; i < ARRAY_SIZE (parse_config); ++i) {
p = riscv_parse_prefixed_ext (rps, arch, p, &parse_config[i]);
diff --git a/bfd/elfxx-riscv.h b/bfd/elfxx-riscv.h
index 76ee274..cbafd28 100644
--- a/bfd/elfxx-riscv.h
+++ b/bfd/elfxx-riscv.h
@@ -72,6 +72,9 @@ typedef struct {
void (*error_handler) (const char *,
...) ATTRIBUTE_PRINTF_1;
unsigned *xlen;
+ void (*get_default_version) (const char *,
+ unsigned int *,
+ unsigned int *);
} riscv_parse_subset_t;
extern bfd_boolean
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 168561e..5ef257e 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -64,6 +64,8 @@ struct riscv_cl_insn
#endif
static const char default_arch[] = DEFAULT_ARCH;
+static const char *default_arch_with_ext = NULL;
+static enum riscv_isa_spec_class default_isa_spec = ISA_SPEC_CLASS_NONE;
static unsigned xlen = 0; /* width of an x-register */
static unsigned abi_xlen = 0; /* width of a pointer in the ABI */
@@ -147,6 +149,67 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
}
}
+/* Handle of the extension with version hash table. */
+static struct hash_control *ext_version_hash = NULL;
+
+static struct hash_control *
+init_ext_version_hash (const struct riscv_ext_version *table)
+{
+ int i = 0;
+ struct hash_control *hash = hash_new ();
+
+ while (table[i].name)
+ {
+ const char *name = table[i].name;
+ const char *hash_error =
+ hash_insert (hash, name, (void *) &table[i]);
+
+ if (hash_error != NULL)
+ {
+ fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
+ table[i].name, hash_error);
+ /* Probably a memory allocation problem? Give up now. */
+ as_fatal (_("Broken assembler. No assembly attempted."));
+ return NULL;
+ }
+
+ i++;
+ while (table[i].name
+ && strcmp (table[i].name, name) == 0)
+ i++;
+ }
+
+ return hash;
+}
+
+static void
+riscv_get_default_ext_version (const char *name,
+ unsigned int *major_version,
+ unsigned int *minor_version)
+{
+ struct riscv_ext_version *ext;
+
+ *major_version = 0;
+ *minor_version = 0;
+
+ if (name == NULL || default_isa_spec == ISA_SPEC_CLASS_NONE)
+ return;
+
+ ext = (struct riscv_ext_version *) hash_find (ext_version_hash, name);
+ while (ext
+ && ext->name
+ && strcmp (ext->name, name) == 0)
+ {
+ if (ext->isa_spec_class == default_isa_spec)
+ {
+ *major_version = ext->major_version;
+ *minor_version = ext->minor_version;
+ return;
+ }
+ ext++;
+ }
+}
+
/* Set which ISA and extensions are available. */
static void
@@ -156,6 +219,10 @@ riscv_set_arch (const char *s)
rps.subset_list = &riscv_subsets;
rps.error_handler = as_fatal;
rps.xlen = &xlen;
+ rps.get_default_version = riscv_get_default_ext_version;
+
+ if (s == NULL)
+ return;
riscv_release_subset_list (&riscv_subsets);
riscv_parse_subset (&rps, s);
@@ -2348,6 +2415,7 @@ enum options
OPTION_NO_ARCH_ATTR,
OPTION_CSR_CHECK,
OPTION_NO_CSR_CHECK,
+ OPTION_MISA_SPEC,
OPTION_END_OF_ENUM
};
@@ -2364,6 +2432,7 @@ struct option md_longopts[] =
{"mno-arch-attr", no_argument, NULL, OPTION_NO_ARCH_ATTR},
{"mcsr-check", no_argument, NULL, OPTION_CSR_CHECK},
{"mno-csr-check", no_argument, NULL, OPTION_NO_CSR_CHECK},
+ {"misa-spec", required_argument, NULL, OPTION_MISA_SPEC},
{NULL, no_argument, NULL, 0}
};
@@ -2392,7 +2461,9 @@ md_parse_option (int c, const char *arg)
switch (c)
{
case OPTION_MARCH:
- riscv_set_arch (arg);
+ /* riscv_after_parse_args will call riscv_set_arch to parse
+ the architecture. */
+ default_arch_with_ext = arg;
break;
case OPTION_NO_PIC:
@@ -2450,6 +2521,14 @@ md_parse_option (int c, const char *arg)
riscv_opts.csr_check = FALSE;
break;
+ case OPTION_MISA_SPEC:
+ if (!riscv_get_isa_spec_class (arg, &default_isa_spec))
+ {
+ as_bad ("Unknown default ISA spec `%s' set by -misa-spec", arg);
+ return 0;
+ }
+ break;
+
default:
return 0;
}
@@ -2469,9 +2548,22 @@ riscv_after_parse_args (void)
else
as_bad ("unknown default architecture `%s'", default_arch);
}
-
- if (riscv_subsets.head == NULL)
- riscv_set_arch (xlen == 64 ? "rv64g" : "rv32g");
+ if (default_arch_with_ext == NULL)
+ default_arch_with_ext = xlen == 64 ? "rv64g" : "rv32g";
+
+ /* Initialize the hash table for extensions with default version. */
+ ext_version_hash = init_ext_version_hash (riscv_ext_version_table);
+
+ /* The default ISA spec is set to 2.2 rather than the lastest version.
+ The reason is that compiler generates the ISA string with fixed 2p0
+ verisons only for the RISCV ELF architecture attributes, but not for
+ the -march option. Therefore, we should update the compiler or linker
+ to resolve this problem. */
+ if (default_isa_spec == ISA_SPEC_CLASS_NONE)
+ default_isa_spec = ISA_SPEC_CLASS_2P2;
+
+ /* Set the architecture according to -march. */
+ riscv_set_arch (default_arch_with_ext);
/* Add the RVC extension, regardless of -march, to support .option rvc. */
riscv_set_rvc (FALSE);
diff --git a/gas/testsuite/gas/riscv/attribute-02.d b/gas/testsuite/gas/riscv/attribute-02.d
index bc3295b..e1e8ce3 100644
--- a/gas/testsuite/gas/riscv/attribute-02.d
+++ b/gas/testsuite/gas/riscv/attribute-02.d
@@ -3,4 +3,4 @@
#source: empty.s
Attribute Section: riscv
File Attributes
- Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_xargle2p0"
+ Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_xargle0p0"
diff --git a/gas/testsuite/gas/riscv/attribute-03.d b/gas/testsuite/gas/riscv/attribute-03.d
index 78b706a..fa38bf3 100644
--- a/gas/testsuite/gas/riscv/attribute-03.d
+++ b/gas/testsuite/gas/riscv/attribute-03.d
@@ -3,4 +3,4 @@
#source: empty.s
Attribute Section: riscv
File Attributes
- Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_xargle2p0_xfoo2p0"
+ Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_xargle0p0_xfoo0p0"
diff --git a/gas/testsuite/gas/riscv/attribute-09.d b/gas/testsuite/gas/riscv/attribute-09.d
new file mode 100644
index 0000000..cad1713
--- /dev/null
+++ b/gas/testsuite/gas/riscv/attribute-09.d
@@ -0,0 +1,6 @@
+#as: -march-attr -march=rv32i2p1m_zicsr -misa-spec=2.2
+#readelf: -A
+#source: empty.s
+Attribute Section: riscv
+File Attributes
+ Tag_RISCV_arch: "rv32i2p1_m2p0_zicsr0p0"
diff --git a/gas/testsuite/gas/riscv/attribute-10.d b/gas/testsuite/gas/riscv/attribute-10.d
new file mode 100644
index 0000000..ba903d1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/attribute-10.d
@@ -0,0 +1,6 @@
+#as: -march-attr -march=rv32gc_zicsr -misa-spec=20191213
+#readelf: -A
+#source: empty.s
+Attribute Section: riscv
+File Attributes
+ Tag_RISCV_arch: "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0"
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index ac6e861..d83e9ca 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -24,6 +24,7 @@
#include "riscv-opc.h"
#include <stdlib.h>
#include <stdint.h>
+#include "bfd.h"
typedef uint64_t insn_t;
@@ -343,6 +344,27 @@ struct riscv_opcode
unsigned long pinfo;
};
+/* The current supported ISA spec versions. */
+
+enum riscv_isa_spec_class
+{
+ ISA_SPEC_CLASS_NONE,
+
+ ISA_SPEC_CLASS_2P2,
+ ISA_SPEC_CLASS_20190608,
+ ISA_SPEC_CLASS_20191213
+};
+
+/* This structure holds version information for specific ISA. */
+
+struct riscv_ext_version
+{
+ const char *name;
+ enum riscv_isa_spec_class isa_spec_class;
+ unsigned int major_version;
+ unsigned int minor_version;
+};
+
/* Instruction is a simple alias (e.g. "mv" for "addi"). */
#define INSN_ALIAS 0x00000001
@@ -420,5 +442,9 @@ extern const char * const riscv_fpr_names_abi[NFPR];
extern const struct riscv_opcode riscv_opcodes[];
extern const struct riscv_opcode riscv_insn_types[];
+extern const struct riscv_ext_version riscv_ext_version_table[];
+
+extern bfd_boolean
+riscv_get_isa_spec_class (const char *, enum riscv_isa_spec_class *);
#endif /* _RISCV_H_ */
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index ceedcaf..f08b15e 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -884,3 +884,96 @@ const struct riscv_opcode riscv_insn_types[] =
/* Terminate the list. */
{0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
};
+
+/* All standard extensions defined in all supported ISA spec. */
+const struct riscv_ext_version riscv_ext_version_table[] =
+{
+/* name, ISA spec, major version, minor_version. */
+{"e", ISA_SPEC_CLASS_20191213, 1, 9},
+{"e", ISA_SPEC_CLASS_20190608, 1, 9},
+{"e", ISA_SPEC_CLASS_2P2, 1, 9},
+
+{"i", ISA_SPEC_CLASS_20191213, 2, 1},
+{"i", ISA_SPEC_CLASS_20190608, 2, 1},
+{"i", ISA_SPEC_CLASS_2P2, 2, 0},
+
+{"m", ISA_SPEC_CLASS_20191213, 2, 0},
+{"m", ISA_SPEC_CLASS_20190608, 2, 0},
+{"m", ISA_SPEC_CLASS_2P2, 2, 0},
+
+{"a", ISA_SPEC_CLASS_20191213, 2, 1},
+{"a", ISA_SPEC_CLASS_20190608, 2, 0},
+{"a", ISA_SPEC_CLASS_2P2, 2, 0},
+
+{"f", ISA_SPEC_CLASS_20191213, 2, 2},
+{"f", ISA_SPEC_CLASS_20190608, 2, 2},
+{"f", ISA_SPEC_CLASS_2P2, 2, 0},
+
+{"d", ISA_SPEC_CLASS_20191213, 2, 2},
+{"d", ISA_SPEC_CLASS_20190608, 2, 2},
+{"d", ISA_SPEC_CLASS_2P2, 2, 0},
+
+{"q", ISA_SPEC_CLASS_20191213, 2, 2},
+{"q", ISA_SPEC_CLASS_20190608, 2, 2},
+{"q", ISA_SPEC_CLASS_2P2, 2, 0},
+
+{"c", ISA_SPEC_CLASS_20191213, 2, 0},
+{"c", ISA_SPEC_CLASS_20190608, 2, 0},
+{"c", ISA_SPEC_CLASS_2P2, 2, 0},
+
+{"p", ISA_SPEC_CLASS_20191213, 0, 2},
+{"p", ISA_SPEC_CLASS_20190608, 0, 2},
+{"p", ISA_SPEC_CLASS_2P2, 0, 1},
+
+{"v", ISA_SPEC_CLASS_20191213, 0, 7},
+{"v", ISA_SPEC_CLASS_20190608, 0, 7},
+{"v", ISA_SPEC_CLASS_2P2, 0, 7},
+
+{"n", ISA_SPEC_CLASS_20190608, 1, 1},
+{"n", ISA_SPEC_CLASS_2P2, 1, 1},
+
+{"zicsr", ISA_SPEC_CLASS_20191213, 2, 0},
+{"zicsr", ISA_SPEC_CLASS_20190608, 2, 0},
+
+/* Terminate the list. */
+{NULL, 0, 0, 0}
+};
+
+struct isa_spec_t
+{
+ const char *name;
+ enum riscv_isa_spec_class class;
+};
+
+/* List for all supported ISA spec versions. */
+static const struct isa_spec_t isa_specs[] =
+{
+ {"2.2", ISA_SPEC_CLASS_2P2},
+ {"20190608", ISA_SPEC_CLASS_20190608},
+ {"20191213", ISA_SPEC_CLASS_20191213},
+
+/* Terminate the list. */
+ {NULL, 0}
+};
+
+/* Get the corresponding ISA spec class by giving a ISA spec string. */
+
+bfd_boolean
+riscv_get_isa_spec_class (const char *s,
+ enum riscv_isa_spec_class *class)
+{
+ const struct isa_spec_t *version;
+
+ if (s == NULL)
+ return FALSE;
+
+ for (version = &isa_specs[0]; version->name != NULL; ++version)
+ if (strcmp (version->name, s) == 0)
+ {
+ *class = version->class;
+ return TRUE;
+ }
+
+ /* Can not find the supported ISA spec. */
+ return FALSE;
+}
--
2.7.4
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [PATCH v2 3/9] RISC-V: Support GAS option -misa-spec to set ISA versions.
2020-05-06 2:55 ` [PATCH v2 3/9] RISC-V: Support GAS option -misa-spec to set ISA versions Nelson Chu
@ 2020-05-19 9:07 ` Nelson Chu
0 siblings, 0 replies; 25+ messages in thread
From: Nelson Chu @ 2020-05-19 9:07 UTC (permalink / raw)
To: Binutils, gdb-patches
Cc: Palmer Dabbelt, Kito Cheng, Jim Wilson, Andrew Waterman,
Andrew Burgess, Alex Bradbury, Maxim Blinov
PING :)
On Wed, May 6, 2020 at 10:55 AM Nelson Chu <nelson.chu@sifive.com> wrote:
>
> For now, we can only use the GAS option -march and ELF arch attribute
> to set the versions for ISA extensions. It seems not so friendly for
> user. Therefore, we support new GAS option to make it easiler.
>
> * -misa-spec = [2.2|20190608|20191213]
> You can simply choose the ISA spec by this option, and then assembler
> will set the version for the standard extensions if you do not set in
> the ELF arch attributes or -march option.
>
> The default ISA spec is set to 2.2 rather than the lastest version, if
> the -misa-spec is not set. The reason is that compiler generates the ISA
> string with fixed 2p0 verisons only for the RISCV ELF architecture attributes,
> but not for the -march option. We should resolve this in the future patches.
>
> gas/
> * config/tc-riscv.c (default_arch_with_ext, default_isa_spec):
> Static variables which are used to set the ISA extensions. You can
> use -march (or ELF build attributes) and -misa-spec to set them,
> respectively.
>
> (ext_version_hash): The hash table used to handle the extensions
> with versions.
> (init_ext_version_hash): Initialize the ext_version_hash according
> to riscv_ext_version_table.
>
> (riscv_get_default_ext_version): The callback function of
> riscv_parse_subset_t. According to the choosed ISA spec,
> get the default version for the specific extension.
> (riscv_set_arch): Set the callback function.
>
> (enum options, struct option md_longopts): Add new option -misa-spec.
> (md_parse_option): Do not call riscv_set_arch for -march. We will
> call it later in riscv_after_parse_args. Call riscv_get_isa_spec_class
> to set default_isa_spec class.
> (riscv_after_parse_args): Call init_ext_version_hash to initialize the
> ext_version_hash, and then call riscv_set_arch to set the architecture
> with versions according to default_arch_with_ext.
>
> * testsuite/gas/riscv/attribute-02.d: Set 0p0 as default version for
> x extensions.
> * testsuite/gas/riscv/attribute-03.d: Likewise.
> * testsuite/gas/riscv/attribute-09.d: New testcase. For i-ext, we
> already set it's version to 2p1 by march, so no need to use the default
> 2p2 version. For m-ext, we do not set the version by -march and ELF arch
> attribute, so set the default 2p0 to it. For zicsr, it is not defined in
> ISA spec 2p2, so set 0p0 to it.
> * testsuite/gas/riscv/attribute-10.d: New testcase. The version of
> zicsr is 2p0 according to ISA spec 20191213.
>
> bfd/
> * elfxx-riscv.h (riscv_parse_subset_t): Add new callback function
> get_default_version. It is used to find the default version for
> the specific extension.
>
> * elfxx-riscv.c (riscv_parsing_subset_version): Remove the parameters
> default_major_version and default_minor_version. Add new bfd_boolean
> parameter *use_default_version. Set it to TRUE if we need to call
> the callback rps->get_default_version to find the default version.
> (riscv_parse_std_ext): Call rps->get_default_version if we fail to find
> the default version in riscv_parsing_subset_version, and then call
> riscv_add_subset to add the subset into subset list.
> (riscv_parse_prefixed_ext): Likewise.
> (riscv_std_z_ext_strtab): Support Zicsr extensions.
>
> * elfnn-riscv.c (riscv_merge_std_ext): Use strcasecmp to compare the
> strings rather than characters.
> riscv_merge_arch_attr_info): The callback function get_default_version
> is only needed for assembler, so set it to NULL int the linker.
>
> include/
> * opcode/riscv.h: Include "bfd.h" to support bfd_boolean.
> (enum riscv_isa_spec_class): New enum class. All supported ISA spec
> belong to one of the class
> (struct riscv_ext_version): New structure holds version information
> for the specific ISA.
>
> opcodes/
> * riscv-opc.c (riscv_ext_version_table): The table used to store
> all information about the supported spec and the corresponding ISA
> versions. Currently, only Zicsr is supported to verify the
> correctness of Z sub extension settings. Others will be supported
> in the future patches.
> (struct isa_spec_t, isa_specs): List for all supported ISA spec
> classes and the corresponding strings.
> (riscv_get_isa_spec_class): New function. Get the corresponding ISA
> spec class by giving a ISA spec string.
> ---
> bfd/elfnn-riscv.c | 6 +-
> bfd/elfxx-riscv.c | 203 +++++++++++++++++++--------------
> bfd/elfxx-riscv.h | 3 +
> gas/config/tc-riscv.c | 100 +++++++++++++++-
> gas/testsuite/gas/riscv/attribute-02.d | 2 +-
> gas/testsuite/gas/riscv/attribute-03.d | 2 +-
> gas/testsuite/gas/riscv/attribute-09.d | 6 +
> gas/testsuite/gas/riscv/attribute-10.d | 6 +
> include/opcode/riscv.h | 26 +++++
> opcodes/riscv-opc.c | 93 +++++++++++++++
> 10 files changed, 355 insertions(+), 92 deletions(-)
> create mode 100644 gas/testsuite/gas/riscv/attribute-09.d
> create mode 100644 gas/testsuite/gas/riscv/attribute-10.d
>
> diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
> index 473bf50..2b5e713 100644
> --- a/bfd/elfnn-riscv.c
> +++ b/bfd/elfnn-riscv.c
> @@ -2802,7 +2802,7 @@ riscv_merge_std_ext (bfd *ibfd,
> if (!riscv_i_or_e_p (ibfd, out_arch, out))
> return FALSE;
>
> - if (in->name[0] != out->name[0])
> + if (strcasecmp (in->name, out->name) != 0)
> {
> /* TODO: We might allow merge 'i' with 'e'. */
> _bfd_error_handler
> @@ -2975,13 +2975,17 @@ riscv_merge_arch_attr_info (bfd *ibfd, char *in_arch, char *out_arch)
> riscv_parse_subset_t rpe_in;
> riscv_parse_subset_t rpe_out;
>
> + /* Only assembler needs to check the default version of ISA, so just set
> + the rpe_in.get_default_version and rpe_out.get_default_version to NULL. */
> rpe_in.subset_list = &in_subsets;
> rpe_in.error_handler = _bfd_error_handler;
> rpe_in.xlen = &xlen_in;
> + rpe_in.get_default_version = NULL;
>
> rpe_out.subset_list = &out_subsets;
> rpe_out.error_handler = _bfd_error_handler;
> rpe_out.xlen = &xlen_out;
> + rpe_out.get_default_version = NULL;
>
> if (in_arch == NULL && out_arch == NULL)
> return NULL;
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index b15fdee..e025689 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1025,9 +1025,8 @@ riscv_elf_add_sub_reloc (bfd *abfd,
> `minor_version`: Parsing result of minor version, set to 0 if version is
> not present in arch string, but set to `default_minor_version` if
> `major_version` using default_major_version.
> - `default_major_version`: Default major version.
> - `default_minor_version`: Default minor version.
> - `std_ext_p`: True if parsing std extension. */
> + `std_ext_p`: True if parsing std extension.
> + `use_default_version`: Set it to True if we need the default version. */
>
> static const char *
> riscv_parsing_subset_version (riscv_parse_subset_t *rps,
> @@ -1035,17 +1034,16 @@ riscv_parsing_subset_version (riscv_parse_subset_t *rps,
> const char *p,
> unsigned *major_version,
> unsigned *minor_version,
> - unsigned default_major_version,
> - unsigned default_minor_version,
> - bfd_boolean std_ext_p)
> + bfd_boolean std_ext_p,
> + bfd_boolean *use_default_version)
> {
> bfd_boolean major_p = TRUE;
> unsigned version = 0;
> - unsigned major = 0;
> - unsigned minor = 0;
> char np;
>
> - for (;*p; ++p)
> + *major_version = 0;
> + *minor_version = 0;
> + for (; *p; ++p)
> {
> if (*p == 'p')
> {
> @@ -1057,7 +1055,6 @@ riscv_parsing_subset_version (riscv_parse_subset_t *rps,
> if (std_ext_p)
> {
> *major_version = version;
> - *minor_version = 0;
> return p;
> }
> else
> @@ -1068,7 +1065,7 @@ riscv_parsing_subset_version (riscv_parse_subset_t *rps,
> }
> }
>
> - major = version;
> + *major_version = version;
> major_p = FALSE;
> version = 0;
> }
> @@ -1079,21 +1076,15 @@ riscv_parsing_subset_version (riscv_parse_subset_t *rps,
> }
>
> if (major_p)
> - major = version;
> + *major_version = version;
> else
> - minor = version;
> + *minor_version = version;
>
> - if (major == 0 && minor == 0)
> - {
> - /* We don't found any version string, use default version. */
> - *major_version = default_major_version;
> - *minor_version = default_minor_version;
> - }
> - else
> - {
> - *major_version = major;
> - *minor_version = minor;
> - }
> + /* We can not find any version in string, need to parse default version. */
> + if (use_default_version != NULL
> + && *major_version == 0
> + && *minor_version == 0)
> + *use_default_version = TRUE;
> return p;
> }
>
> @@ -1122,38 +1113,58 @@ riscv_parse_std_ext (riscv_parse_subset_t *rps,
> {
> const char *all_std_exts = riscv_supported_std_ext ();
> const char *std_exts = all_std_exts;
> -
> unsigned major_version = 0;
> unsigned minor_version = 0;
> char std_ext = '\0';
> + bfd_boolean use_default_version = FALSE;
>
> /* First letter must start with i, e or g. */
> switch (*p)
> {
> case 'i':
> - p++;
> - p = riscv_parsing_subset_version (
> - rps,
> - march,
> - p, &major_version, &minor_version,
> - /* default_major_version= */ 2,
> - /* default_minor_version= */ 0,
> - /* std_ext_p= */TRUE);
> - riscv_add_subset (rps->subset_list, "i", major_version, minor_version);
> + p = riscv_parsing_subset_version (rps,
> + march,
> + ++p,
> + &major_version,
> + &minor_version,
> + /* std_ext_p= */TRUE,
> + &use_default_version);
> +
> + /* Find the default version if needed. */
> + if (use_default_version
> + && rps->get_default_version != NULL)
> + rps->get_default_version ("i",
> + &major_version,
> + &minor_version);
> + riscv_add_subset (rps->subset_list, "i",
> + major_version, minor_version);
> break;
>
> case 'e':
> - p++;
> - p = riscv_parsing_subset_version (
> - rps,
> - march,
> - p, &major_version, &minor_version,
> - /* default_major_version= */ 1,
> - /* default_minor_version= */ 9,
> - /* std_ext_p= */TRUE);
> -
> - riscv_add_subset (rps->subset_list, "e", major_version, minor_version);
> - riscv_add_subset (rps->subset_list, "i", 2, 0);
> + p = riscv_parsing_subset_version (rps,
> + march,
> + ++p,
> + &major_version,
> + &minor_version,
> + /* std_ext_p= */TRUE,
> + &use_default_version);
> +
> + /* Find the default version if needed. */
> + if (use_default_version
> + && rps->get_default_version != NULL)
> + rps->get_default_version ("e",
> + &major_version,
> + &minor_version);
> + riscv_add_subset (rps->subset_list, "e",
> + major_version, minor_version);
> +
> + /* i-ext must be enabled. */
> + if (rps->get_default_version != NULL)
> + rps->get_default_version ("i",
> + &major_version,
> + &minor_version);
> + riscv_add_subset (rps->subset_list, "i",
> + major_version, minor_version);
>
> if (*rps->xlen > 32)
> {
> @@ -1161,25 +1172,36 @@ riscv_parse_std_ext (riscv_parse_subset_t *rps,
> march, *rps->xlen);
> return NULL;
> }
> -
> break;
>
> case 'g':
> - p++;
> - p = riscv_parsing_subset_version (
> - rps,
> - march,
> - p, &major_version, &minor_version,
> - /* default_major_version= */ 2,
> - /* default_minor_version= */ 0,
> - /* std_ext_p= */TRUE);
> - riscv_add_subset (rps->subset_list, "i", major_version, minor_version);
> + /* The g-ext shouldn't has the version, so we just skip the setting if
> + user set a version to it. */
> + p = riscv_parsing_subset_version (rps,
> + march,
> + ++p,
> + &major_version,
> + &minor_version,
> + TRUE,
> + &use_default_version);
> +
> + /* i-ext must be enabled. */
> + if (rps->get_default_version != NULL)
> + rps->get_default_version ("i",
> + &major_version,
> + &minor_version);
> + riscv_add_subset (rps->subset_list, "i",
> + major_version, minor_version);
>
> for ( ; *std_exts != 'q'; std_exts++)
> {
> const char subset[] = {*std_exts, '\0'};
> - riscv_add_subset (
> - rps->subset_list, subset, major_version, minor_version);
> + if (rps->get_default_version != NULL)
> + rps->get_default_version (subset,
> + &major_version,
> + &minor_version);
> + riscv_add_subset (rps->subset_list, subset,
> + major_version, minor_version);
> }
> break;
>
> @@ -1189,7 +1211,9 @@ riscv_parse_std_ext (riscv_parse_subset_t *rps,
> return NULL;
> }
>
> - while (*p)
> + /* The riscv_parsing_subset_version may set `p` to NULL, so I think we should
> + skip parsing the string if `p` is NULL or value of `p` is `\0`. */
> + while (p != NULL && *p != '\0')
> {
> char subset[2] = {0, 0};
>
> @@ -1218,21 +1242,26 @@ riscv_parse_std_ext (riscv_parse_subset_t *rps,
> march, *p);
> return NULL;
> }
> -
> std_exts++;
>
> - p++;
> - p = riscv_parsing_subset_version (
> - rps,
> - march,
> - p, &major_version, &minor_version,
> - /* default_major_version= */ 2,
> - /* default_minor_version= */ 0,
> - /* std_ext_p= */TRUE);
> -
> + use_default_version = FALSE;
> subset[0] = std_ext;
> -
> - riscv_add_subset (rps->subset_list, subset, major_version, minor_version);
> + p = riscv_parsing_subset_version (rps,
> + march,
> + ++p,
> + &major_version,
> + &minor_version,
> + TRUE,
> + &use_default_version);
> +
> + /* Find the default version if needed. */
> + if (use_default_version
> + && rps->get_default_version != NULL)
> + rps->get_default_version (subset,
> + &major_version,
> + &minor_version);
> + riscv_add_subset (rps->subset_list, subset,
> + major_version, minor_version);
> }
> return p;
> }
> @@ -1272,9 +1301,10 @@ typedef struct riscv_parse_config
> } riscv_parse_config_t;
>
> /* Parse a generic prefixed extension.
> - march: The full architecture string as passed in by "-march=...".
> - p: Point from which to start parsing the -march string.
> - config: What class of extensions to parse, predicate funcs,
> + `rps`: Hooks and status for parsing subset.
> + `march`: The full architecture string as passed in by "-march=...".
> + `p`: Point from which to start parsing the -march string.
> + `config`: What class of extensions to parse, predicate funcs,
> and strings to use in error reporting. */
>
> static const char *
> @@ -1287,6 +1317,7 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
> unsigned minor_version = 0;
> const char *last_name;
> riscv_isa_ext_class_t class;
> + bfd_boolean use_default_version;
>
> while (*p)
> {
> @@ -1309,15 +1340,11 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
> while (*++q != '\0' && *q != '_' && !ISDIGIT (*q))
> ;
>
> + use_default_version = FALSE;
> end_of_version =
> - riscv_parsing_subset_version (
> - rps,
> - march,
> - q, &major_version, &minor_version,
> - /* default_major_version= */ 2,
> - /* default_minor_version= */ 0,
> - /* std_ext_p= */FALSE);
> -
> + riscv_parsing_subset_version (rps, march, q, &major_version,
> + &minor_version, FALSE,
> + &use_default_version);
> *q = '\0';
>
> /* Check that the name is valid.
> @@ -1337,7 +1364,6 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
>
> /* Check that the last item is not the same as this. */
> last_name = rps->subset_list->tail->name;
> -
> if (!strcasecmp (last_name, subset))
> {
> rps->error_handler ("-march=%s: Duplicate %s ISA extension: \'%s\'",
> @@ -1357,7 +1383,15 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
> return NULL;
> }
>
> - riscv_add_subset (rps->subset_list, subset, major_version, minor_version);
> + /* Find the default version if needed. */
> + if (use_default_version
> + && rps->get_default_version != NULL)
> + rps->get_default_version (subset,
> + &major_version,
> + &minor_version);
> + riscv_add_subset (rps->subset_list, subset,
> + major_version, minor_version);
> +
> free (subset);
> p += end_of_version - subset;
>
> @@ -1384,7 +1418,7 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
>
> static const char * const riscv_std_z_ext_strtab[] =
> {
> - NULL
> + "zicsr", NULL
> };
>
> /* Same as `riscv_std_z_ext_strtab', but for S-class extensions. */
> @@ -1490,7 +1524,6 @@ riscv_parse_subset (riscv_parse_subset_t *rps,
> return FALSE;
>
> /* Parse the different classes of extensions in the specified order. */
> -
> for (i = 0; i < ARRAY_SIZE (parse_config); ++i) {
> p = riscv_parse_prefixed_ext (rps, arch, p, &parse_config[i]);
>
> diff --git a/bfd/elfxx-riscv.h b/bfd/elfxx-riscv.h
> index 76ee274..cbafd28 100644
> --- a/bfd/elfxx-riscv.h
> +++ b/bfd/elfxx-riscv.h
> @@ -72,6 +72,9 @@ typedef struct {
> void (*error_handler) (const char *,
> ...) ATTRIBUTE_PRINTF_1;
> unsigned *xlen;
> + void (*get_default_version) (const char *,
> + unsigned int *,
> + unsigned int *);
> } riscv_parse_subset_t;
>
> extern bfd_boolean
> diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
> index 168561e..5ef257e 100644
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -64,6 +64,8 @@ struct riscv_cl_insn
> #endif
>
> static const char default_arch[] = DEFAULT_ARCH;
> +static const char *default_arch_with_ext = NULL;
> +static enum riscv_isa_spec_class default_isa_spec = ISA_SPEC_CLASS_NONE;
>
> static unsigned xlen = 0; /* width of an x-register */
> static unsigned abi_xlen = 0; /* width of a pointer in the ABI */
> @@ -147,6 +149,67 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
> }
> }
>
> +/* Handle of the extension with version hash table. */
> +static struct hash_control *ext_version_hash = NULL;
> +
> +static struct hash_control *
> +init_ext_version_hash (const struct riscv_ext_version *table)
> +{
> + int i = 0;
> + struct hash_control *hash = hash_new ();
> +
> + while (table[i].name)
> + {
> + const char *name = table[i].name;
> + const char *hash_error =
> + hash_insert (hash, name, (void *) &table[i]);
> +
> + if (hash_error != NULL)
> + {
> + fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
> + table[i].name, hash_error);
> + /* Probably a memory allocation problem? Give up now. */
> + as_fatal (_("Broken assembler. No assembly attempted."));
> + return NULL;
> + }
> +
> + i++;
> + while (table[i].name
> + && strcmp (table[i].name, name) == 0)
> + i++;
> + }
> +
> + return hash;
> +}
> +
> +static void
> +riscv_get_default_ext_version (const char *name,
> + unsigned int *major_version,
> + unsigned int *minor_version)
> +{
> + struct riscv_ext_version *ext;
> +
> + *major_version = 0;
> + *minor_version = 0;
> +
> + if (name == NULL || default_isa_spec == ISA_SPEC_CLASS_NONE)
> + return;
> +
> + ext = (struct riscv_ext_version *) hash_find (ext_version_hash, name);
> + while (ext
> + && ext->name
> + && strcmp (ext->name, name) == 0)
> + {
> + if (ext->isa_spec_class == default_isa_spec)
> + {
> + *major_version = ext->major_version;
> + *minor_version = ext->minor_version;
> + return;
> + }
> + ext++;
> + }
> +}
> +
> /* Set which ISA and extensions are available. */
>
> static void
> @@ -156,6 +219,10 @@ riscv_set_arch (const char *s)
> rps.subset_list = &riscv_subsets;
> rps.error_handler = as_fatal;
> rps.xlen = &xlen;
> + rps.get_default_version = riscv_get_default_ext_version;
> +
> + if (s == NULL)
> + return;
>
> riscv_release_subset_list (&riscv_subsets);
> riscv_parse_subset (&rps, s);
> @@ -2348,6 +2415,7 @@ enum options
> OPTION_NO_ARCH_ATTR,
> OPTION_CSR_CHECK,
> OPTION_NO_CSR_CHECK,
> + OPTION_MISA_SPEC,
> OPTION_END_OF_ENUM
> };
>
> @@ -2364,6 +2432,7 @@ struct option md_longopts[] =
> {"mno-arch-attr", no_argument, NULL, OPTION_NO_ARCH_ATTR},
> {"mcsr-check", no_argument, NULL, OPTION_CSR_CHECK},
> {"mno-csr-check", no_argument, NULL, OPTION_NO_CSR_CHECK},
> + {"misa-spec", required_argument, NULL, OPTION_MISA_SPEC},
>
> {NULL, no_argument, NULL, 0}
> };
> @@ -2392,7 +2461,9 @@ md_parse_option (int c, const char *arg)
> switch (c)
> {
> case OPTION_MARCH:
> - riscv_set_arch (arg);
> + /* riscv_after_parse_args will call riscv_set_arch to parse
> + the architecture. */
> + default_arch_with_ext = arg;
> break;
>
> case OPTION_NO_PIC:
> @@ -2450,6 +2521,14 @@ md_parse_option (int c, const char *arg)
> riscv_opts.csr_check = FALSE;
> break;
>
> + case OPTION_MISA_SPEC:
> + if (!riscv_get_isa_spec_class (arg, &default_isa_spec))
> + {
> + as_bad ("Unknown default ISA spec `%s' set by -misa-spec", arg);
> + return 0;
> + }
> + break;
> +
> default:
> return 0;
> }
> @@ -2469,9 +2548,22 @@ riscv_after_parse_args (void)
> else
> as_bad ("unknown default architecture `%s'", default_arch);
> }
> -
> - if (riscv_subsets.head == NULL)
> - riscv_set_arch (xlen == 64 ? "rv64g" : "rv32g");
> + if (default_arch_with_ext == NULL)
> + default_arch_with_ext = xlen == 64 ? "rv64g" : "rv32g";
> +
> + /* Initialize the hash table for extensions with default version. */
> + ext_version_hash = init_ext_version_hash (riscv_ext_version_table);
> +
> + /* The default ISA spec is set to 2.2 rather than the lastest version.
> + The reason is that compiler generates the ISA string with fixed 2p0
> + verisons only for the RISCV ELF architecture attributes, but not for
> + the -march option. Therefore, we should update the compiler or linker
> + to resolve this problem. */
> + if (default_isa_spec == ISA_SPEC_CLASS_NONE)
> + default_isa_spec = ISA_SPEC_CLASS_2P2;
> +
> + /* Set the architecture according to -march. */
> + riscv_set_arch (default_arch_with_ext);
>
> /* Add the RVC extension, regardless of -march, to support .option rvc. */
> riscv_set_rvc (FALSE);
> diff --git a/gas/testsuite/gas/riscv/attribute-02.d b/gas/testsuite/gas/riscv/attribute-02.d
> index bc3295b..e1e8ce3 100644
> --- a/gas/testsuite/gas/riscv/attribute-02.d
> +++ b/gas/testsuite/gas/riscv/attribute-02.d
> @@ -3,4 +3,4 @@
> #source: empty.s
> Attribute Section: riscv
> File Attributes
> - Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_xargle2p0"
> + Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_xargle0p0"
> diff --git a/gas/testsuite/gas/riscv/attribute-03.d b/gas/testsuite/gas/riscv/attribute-03.d
> index 78b706a..fa38bf3 100644
> --- a/gas/testsuite/gas/riscv/attribute-03.d
> +++ b/gas/testsuite/gas/riscv/attribute-03.d
> @@ -3,4 +3,4 @@
> #source: empty.s
> Attribute Section: riscv
> File Attributes
> - Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_xargle2p0_xfoo2p0"
> + Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_xargle0p0_xfoo0p0"
> diff --git a/gas/testsuite/gas/riscv/attribute-09.d b/gas/testsuite/gas/riscv/attribute-09.d
> new file mode 100644
> index 0000000..cad1713
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/attribute-09.d
> @@ -0,0 +1,6 @@
> +#as: -march-attr -march=rv32i2p1m_zicsr -misa-spec=2.2
> +#readelf: -A
> +#source: empty.s
> +Attribute Section: riscv
> +File Attributes
> + Tag_RISCV_arch: "rv32i2p1_m2p0_zicsr0p0"
> diff --git a/gas/testsuite/gas/riscv/attribute-10.d b/gas/testsuite/gas/riscv/attribute-10.d
> new file mode 100644
> index 0000000..ba903d1
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/attribute-10.d
> @@ -0,0 +1,6 @@
> +#as: -march-attr -march=rv32gc_zicsr -misa-spec=20191213
> +#readelf: -A
> +#source: empty.s
> +Attribute Section: riscv
> +File Attributes
> + Tag_RISCV_arch: "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0"
> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
> index ac6e861..d83e9ca 100644
> --- a/include/opcode/riscv.h
> +++ b/include/opcode/riscv.h
> @@ -24,6 +24,7 @@
> #include "riscv-opc.h"
> #include <stdlib.h>
> #include <stdint.h>
> +#include "bfd.h"
>
> typedef uint64_t insn_t;
>
> @@ -343,6 +344,27 @@ struct riscv_opcode
> unsigned long pinfo;
> };
>
> +/* The current supported ISA spec versions. */
> +
> +enum riscv_isa_spec_class
> +{
> + ISA_SPEC_CLASS_NONE,
> +
> + ISA_SPEC_CLASS_2P2,
> + ISA_SPEC_CLASS_20190608,
> + ISA_SPEC_CLASS_20191213
> +};
> +
> +/* This structure holds version information for specific ISA. */
> +
> +struct riscv_ext_version
> +{
> + const char *name;
> + enum riscv_isa_spec_class isa_spec_class;
> + unsigned int major_version;
> + unsigned int minor_version;
> +};
> +
> /* Instruction is a simple alias (e.g. "mv" for "addi"). */
> #define INSN_ALIAS 0x00000001
>
> @@ -420,5 +442,9 @@ extern const char * const riscv_fpr_names_abi[NFPR];
>
> extern const struct riscv_opcode riscv_opcodes[];
> extern const struct riscv_opcode riscv_insn_types[];
> +extern const struct riscv_ext_version riscv_ext_version_table[];
> +
> +extern bfd_boolean
> +riscv_get_isa_spec_class (const char *, enum riscv_isa_spec_class *);
>
> #endif /* _RISCV_H_ */
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index ceedcaf..f08b15e 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -884,3 +884,96 @@ const struct riscv_opcode riscv_insn_types[] =
> /* Terminate the list. */
> {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
> };
> +
> +/* All standard extensions defined in all supported ISA spec. */
> +const struct riscv_ext_version riscv_ext_version_table[] =
> +{
> +/* name, ISA spec, major version, minor_version. */
> +{"e", ISA_SPEC_CLASS_20191213, 1, 9},
> +{"e", ISA_SPEC_CLASS_20190608, 1, 9},
> +{"e", ISA_SPEC_CLASS_2P2, 1, 9},
> +
> +{"i", ISA_SPEC_CLASS_20191213, 2, 1},
> +{"i", ISA_SPEC_CLASS_20190608, 2, 1},
> +{"i", ISA_SPEC_CLASS_2P2, 2, 0},
> +
> +{"m", ISA_SPEC_CLASS_20191213, 2, 0},
> +{"m", ISA_SPEC_CLASS_20190608, 2, 0},
> +{"m", ISA_SPEC_CLASS_2P2, 2, 0},
> +
> +{"a", ISA_SPEC_CLASS_20191213, 2, 1},
> +{"a", ISA_SPEC_CLASS_20190608, 2, 0},
> +{"a", ISA_SPEC_CLASS_2P2, 2, 0},
> +
> +{"f", ISA_SPEC_CLASS_20191213, 2, 2},
> +{"f", ISA_SPEC_CLASS_20190608, 2, 2},
> +{"f", ISA_SPEC_CLASS_2P2, 2, 0},
> +
> +{"d", ISA_SPEC_CLASS_20191213, 2, 2},
> +{"d", ISA_SPEC_CLASS_20190608, 2, 2},
> +{"d", ISA_SPEC_CLASS_2P2, 2, 0},
> +
> +{"q", ISA_SPEC_CLASS_20191213, 2, 2},
> +{"q", ISA_SPEC_CLASS_20190608, 2, 2},
> +{"q", ISA_SPEC_CLASS_2P2, 2, 0},
> +
> +{"c", ISA_SPEC_CLASS_20191213, 2, 0},
> +{"c", ISA_SPEC_CLASS_20190608, 2, 0},
> +{"c", ISA_SPEC_CLASS_2P2, 2, 0},
> +
> +{"p", ISA_SPEC_CLASS_20191213, 0, 2},
> +{"p", ISA_SPEC_CLASS_20190608, 0, 2},
> +{"p", ISA_SPEC_CLASS_2P2, 0, 1},
> +
> +{"v", ISA_SPEC_CLASS_20191213, 0, 7},
> +{"v", ISA_SPEC_CLASS_20190608, 0, 7},
> +{"v", ISA_SPEC_CLASS_2P2, 0, 7},
> +
> +{"n", ISA_SPEC_CLASS_20190608, 1, 1},
> +{"n", ISA_SPEC_CLASS_2P2, 1, 1},
> +
> +{"zicsr", ISA_SPEC_CLASS_20191213, 2, 0},
> +{"zicsr", ISA_SPEC_CLASS_20190608, 2, 0},
> +
> +/* Terminate the list. */
> +{NULL, 0, 0, 0}
> +};
> +
> +struct isa_spec_t
> +{
> + const char *name;
> + enum riscv_isa_spec_class class;
> +};
> +
> +/* List for all supported ISA spec versions. */
> +static const struct isa_spec_t isa_specs[] =
> +{
> + {"2.2", ISA_SPEC_CLASS_2P2},
> + {"20190608", ISA_SPEC_CLASS_20190608},
> + {"20191213", ISA_SPEC_CLASS_20191213},
> +
> +/* Terminate the list. */
> + {NULL, 0}
> +};
> +
> +/* Get the corresponding ISA spec class by giving a ISA spec string. */
> +
> +bfd_boolean
> +riscv_get_isa_spec_class (const char *s,
> + enum riscv_isa_spec_class *class)
> +{
> + const struct isa_spec_t *version;
> +
> + if (s == NULL)
> + return FALSE;
> +
> + for (version = &isa_specs[0]; version->name != NULL; ++version)
> + if (strcmp (version->name, s) == 0)
> + {
> + *class = version->class;
> + return TRUE;
> + }
> +
> + /* Can not find the supported ISA spec. */
> + return FALSE;
> +}
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 4/9] RISC-V: Support configure options to set ISA versions by default.
2020-05-06 2:55 [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR Nelson Chu
` (2 preceding siblings ...)
2020-05-06 2:55 ` [PATCH v2 3/9] RISC-V: Support GAS option -misa-spec to set ISA versions Nelson Chu
@ 2020-05-06 2:55 ` Nelson Chu
2020-05-19 9:07 ` Nelson Chu
2020-05-06 2:55 ` [PATCH v2 5/9] RISC-V: Support version checking for CSR according to privilege spec version Nelson Chu
` (5 subsequent siblings)
9 siblings, 1 reply; 25+ messages in thread
From: Nelson Chu @ 2020-05-06 2:55 UTC (permalink / raw)
To: binutils, gdb-patches
Cc: palmer, kito.cheng, jimw, andrew, andrew.burgess, asb,
maxim.blinov, nelson.chu
Support new configure options --with-arch and --with-isa-spec to set
ISA versions if we do not set the -march and -misa-spec options.
* --with-arch = <ISA-string>
The syntax of <ISA-string> is same as -march option. Assembler will
check this if -march option and ELF arch attributes are not set.
* --with-isa-spec = [2.2|20190608|20191213]
The syntax is same as -misa-spec option. Assembler will check this if
-misa-spec option is not set.
The Priority of these options,
* ELF arch attributes > Assembler options > Default configure options
* For GAS options, -march > -misa-spec
* For configure options, --with-arch > --with-isa-spec
gas/
* config/tc-riscv.c (DEFAULT_RISCV_ARCH_WITH_EXT,
DEFAULT_RISCV_ISA_SPEC): Default configure option settings.
You can set them by configure options --with-arch and
--with-isa-spec, respectively.
(riscv_set_default_isa_spec): New function used to set the
default ISA spec.
(md_parse_option): Call riscv_set_default_isa_spec rather than
call riscv_get_isa_spec_class directly.
(riscv_after_parse_args): If the -isa-spec is not set, then we
set the default ISA spec according to DEFAULT_RISCV_ISA_SPEC by
calling riscv_set_default_isa_spec.
* testsuite/gas/riscv/attribute-01.d: Add -misa-spec=2.2, since
the --with-isa-spec may be set to different ISA spec.
* testsuite/gas/riscv/attribute-02.d: Likewise.
* testsuite/gas/riscv/attribute-03.d: Likewise.
* testsuite/gas/riscv/attribute-04.d: Likewise.
* testsuite/gas/riscv/attribute-05.d: Likewise.
* testsuite/gas/riscv/attribute-06.d: Likewise.
* testsuite/gas/riscv/attribute-07.d: Likewise.
* configure.ac: Add configure options, --with-arch and
--with-isa-spec.
* configure: Regenerated.
* config.in: Regenerated.
---
gas/config.in | 6 ++++
gas/config/tc-riscv.c | 58 ++++++++++++++++++++++++++--------
gas/configure | 39 ++++++++++++++++++++++-
gas/configure.ac | 25 ++++++++++++++-
gas/testsuite/gas/riscv/attribute-01.d | 2 +-
gas/testsuite/gas/riscv/attribute-02.d | 2 +-
gas/testsuite/gas/riscv/attribute-03.d | 2 +-
gas/testsuite/gas/riscv/attribute-04.d | 2 +-
gas/testsuite/gas/riscv/attribute-05.d | 2 +-
gas/testsuite/gas/riscv/attribute-06.d | 2 +-
gas/testsuite/gas/riscv/attribute-07.d | 2 +-
11 files changed, 119 insertions(+), 23 deletions(-)
diff --git a/gas/config.in b/gas/config.in
index 8724eb1..e20d3c3 100644
--- a/gas/config.in
+++ b/gas/config.in
@@ -53,9 +53,15 @@
/* Define to 1 if you want to fix Loongson3 LLSC Errata by default. */
#undef DEFAULT_MIPS_FIX_LOONGSON3_LLSC
+/* Define default value for RISC-V -march. */
+#undef DEFAULT_RISCV_ARCH_WITH_EXT
+
/* Define to 1 if you want to generate RISC-V arch attribute by default. */
#undef DEFAULT_RISCV_ATTR
+/* Define default value for RISC-V -misa-spec. */
+#undef DEFAULT_RISCV_ISA_SPEC
+
/* Define to 1 if you want to generate GNU x86 used ISA and feature properties
by default. */
#undef DEFAULT_X86_USED_NOTE
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 5ef257e..3b6c429 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -63,8 +63,24 @@ struct riscv_cl_insn
#define DEFAULT_RISCV_ATTR 0
#endif
+/* Let riscv_after_parse_args set the default value according to xlen. */
+
+#ifndef DEFAULT_RISCV_ARCH_WITH_EXT
+#define DEFAULT_RISCV_ARCH_WITH_EXT NULL
+#endif
+
+/* The default ISA spec is set to 2.2 rather than the lastest version.
+ The reason is that compiler generates the ISA string with fixed 2p0
+ verisons only for the RISCV ELF architecture attributes, but not for
+ the -march option. Therefore, we should update the compiler or linker
+ to resolve this problem. */
+
+#ifndef DEFAULT_RISCV_ISA_SPEC
+#define DEFAULT_RISCV_ISA_SPEC "2.2"
+#endif
+
static const char default_arch[] = DEFAULT_ARCH;
-static const char *default_arch_with_ext = NULL;
+static const char *default_arch_with_ext = DEFAULT_RISCV_ARCH_WITH_EXT;
static enum riscv_isa_spec_class default_isa_spec = ISA_SPEC_CLASS_NONE;
static unsigned xlen = 0; /* width of an x-register */
@@ -76,6 +92,24 @@ static bfd_boolean rve_abi = FALSE;
static unsigned elf_flags = 0;
+/* Set the default_isa_spec. Return 0 if the input spec string isn't
+ supported. Otherwise, return 1. */
+
+static int
+riscv_set_default_isa_spec (const char *s)
+{
+ enum riscv_isa_spec_class class;
+ if (!riscv_get_isa_spec_class (s, &class))
+ {
+ as_bad ("Unknown default ISA spec `%s' set by "
+ "-misa-spec or --with-isa-spec", s);
+ return 0;
+ }
+ else
+ default_isa_spec = class;
+ return 1;
+}
+
/* This is the set of options which the .option pseudo-op may modify. */
struct riscv_set_options
@@ -2522,12 +2556,7 @@ md_parse_option (int c, const char *arg)
break;
case OPTION_MISA_SPEC:
- if (!riscv_get_isa_spec_class (arg, &default_isa_spec))
- {
- as_bad ("Unknown default ISA spec `%s' set by -misa-spec", arg);
- return 0;
- }
- break;
+ return riscv_set_default_isa_spec (arg);
default:
return 0;
@@ -2539,6 +2568,10 @@ md_parse_option (int c, const char *arg)
void
riscv_after_parse_args (void)
{
+ /* The --with-arch is optional for now, so we have to set the xlen
+ according to the default_arch, which is set by the --targte, first.
+ Then, we use the xlen to set the default_arch_with_ext if the
+ -march and --with-arch are not set. */
if (xlen == 0)
{
if (strcmp (default_arch, "riscv32") == 0)
@@ -2554,15 +2587,12 @@ riscv_after_parse_args (void)
/* Initialize the hash table for extensions with default version. */
ext_version_hash = init_ext_version_hash (riscv_ext_version_table);
- /* The default ISA spec is set to 2.2 rather than the lastest version.
- The reason is that compiler generates the ISA string with fixed 2p0
- verisons only for the RISCV ELF architecture attributes, but not for
- the -march option. Therefore, we should update the compiler or linker
- to resolve this problem. */
+ /* If the -misa-spec isn't set, then we set the default ISA spec according
+ to DEFAULT_RISCV_ISA_SPEC. */
if (default_isa_spec == ISA_SPEC_CLASS_NONE)
- default_isa_spec = ISA_SPEC_CLASS_2P2;
+ riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC);
- /* Set the architecture according to -march. */
+ /* Set the architecture according to -march or or --with-arch. */
riscv_set_arch (default_arch_with_ext);
/* Add the RVC extension, regardless of -march, to support .option rvc. */
diff --git a/gas/configure b/gas/configure
index 1515787..cc21e0a 100755
--- a/gas/configure
+++ b/gas/configure
@@ -13009,7 +13009,7 @@ $as_echo "#define NDS32_DEFAULT_ZOL_EXT 1" >>confdefs.h
$as_echo "$enable_zol_ext" >&6; }
;;
- aarch64 | i386 | riscv | s390 | sparc)
+ aarch64 | i386 | s390 | sparc)
if test $this_target = $target ; then
cat >>confdefs.h <<_ACEOF
@@ -13019,6 +13019,43 @@ _ACEOF
fi
;;
+ riscv)
+ # --target=riscv[32|64]-*-*. */
+ if test $this_target = $target ; then
+
+cat >>confdefs.h <<_ACEOF
+#define DEFAULT_ARCH "${arch}"
+_ACEOF
+
+ fi
+
+ # --with-arch=<value>. The syntax of <value> is same as Gas option -march.
+ { $as_echo "$as_me:${as_lineno-$LINENO}: checking for default configuration of --with-arch" >&5
+$as_echo_n "checking for default configuration of --with-arch... " >&6; }
+ if test "x${with_arch}" != x; then
+
+cat >>confdefs.h <<_ACEOF
+#define DEFAULT_RISCV_ARCH_WITH_EXT "$with_arch"
+_ACEOF
+
+ fi
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $with_arch" >&5
+$as_echo "$with_arch" >&6; }
+
+ # --with-isa-spec=[2.2|20190608|20191213].
+ { $as_echo "$as_me:${as_lineno-$LINENO}: checking for default configuration of --with-isa-spec" >&5
+$as_echo_n "checking for default configuration of --with-isa-spec... " >&6; }
+ if test "x${with_isa_spec}" != x; then
+
+cat >>confdefs.h <<_ACEOF
+#define DEFAULT_RISCV_ISA_SPEC "$with_isa_spec"
+_ACEOF
+
+ fi
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $with_isa_spec" >&5
+$as_echo "$with_isa_spec" >&6; }
+ ;;
+
rl78)
f=rl78-parse.o
case " $extra_objects " in
diff --git a/gas/configure.ac b/gas/configure.ac
index 6f32e55..8a5f5c5 100644
--- a/gas/configure.ac
+++ b/gas/configure.ac
@@ -569,12 +569,35 @@ changequote([,])dnl
AC_MSG_RESULT($enable_zol_ext)
;;
- aarch64 | i386 | riscv | s390 | sparc)
+ aarch64 | i386 | s390 | sparc)
if test $this_target = $target ; then
AC_DEFINE_UNQUOTED(DEFAULT_ARCH, "${arch}", [Default architecture.])
fi
;;
+ riscv)
+ # --target=riscv[32|64]-*-*. */
+ if test $this_target = $target ; then
+ AC_DEFINE_UNQUOTED(DEFAULT_ARCH, "${arch}", [Default architecture.])
+ fi
+
+ # --with-arch=<value>. The syntax of <value> is same as Gas option -march.
+ AC_MSG_CHECKING(for default configuration of --with-arch)
+ if test "x${with_arch}" != x; then
+ AC_DEFINE_UNQUOTED(DEFAULT_RISCV_ARCH_WITH_EXT, "$with_arch",
+ [Define default value for RISC-V -march.])
+ fi
+ AC_MSG_RESULT($with_arch)
+
+ # --with-isa-spec=[2.2|20190608|20191213].
+ AC_MSG_CHECKING(for default configuration of --with-isa-spec)
+ if test "x${with_isa_spec}" != x; then
+ AC_DEFINE_UNQUOTED(DEFAULT_RISCV_ISA_SPEC, "$with_isa_spec",
+ [Define default value for RISC-V -misa-spec.])
+ fi
+ AC_MSG_RESULT($with_isa_spec)
+ ;;
+
rl78)
f=rl78-parse.o
case " $extra_objects " in
diff --git a/gas/testsuite/gas/riscv/attribute-01.d b/gas/testsuite/gas/riscv/attribute-01.d
index e22773e..2e19e09 100644
--- a/gas/testsuite/gas/riscv/attribute-01.d
+++ b/gas/testsuite/gas/riscv/attribute-01.d
@@ -1,4 +1,4 @@
-#as: -march=rv32g -march-attr
+#as: -march=rv32g -march-attr -misa-spec=2.2
#readelf: -A
#source: empty.s
Attribute Section: riscv
diff --git a/gas/testsuite/gas/riscv/attribute-02.d b/gas/testsuite/gas/riscv/attribute-02.d
index e1e8ce3..ae0195e 100644
--- a/gas/testsuite/gas/riscv/attribute-02.d
+++ b/gas/testsuite/gas/riscv/attribute-02.d
@@ -1,4 +1,4 @@
-#as: -march=rv32gxargle -march-attr
+#as: -march=rv32gxargle -march-attr -misa-spec=2.2
#readelf: -A
#source: empty.s
Attribute Section: riscv
diff --git a/gas/testsuite/gas/riscv/attribute-03.d b/gas/testsuite/gas/riscv/attribute-03.d
index fa38bf3..9916ff6 100644
--- a/gas/testsuite/gas/riscv/attribute-03.d
+++ b/gas/testsuite/gas/riscv/attribute-03.d
@@ -1,4 +1,4 @@
-#as: -march=rv32gxargle_xfoo -march-attr
+#as: -march=rv32gxargle_xfoo -march-attr -misa-spec=2.2
#readelf: -A
#source: empty.s
Attribute Section: riscv
diff --git a/gas/testsuite/gas/riscv/attribute-04.d b/gas/testsuite/gas/riscv/attribute-04.d
index c97bf03..408464d 100644
--- a/gas/testsuite/gas/riscv/attribute-04.d
+++ b/gas/testsuite/gas/riscv/attribute-04.d
@@ -1,4 +1,4 @@
-#as: -march-attr
+#as: -march-attr -misa-spec=2.2
#readelf: -A
#source: attribute-04.s
Attribute Section: riscv
diff --git a/gas/testsuite/gas/riscv/attribute-05.d b/gas/testsuite/gas/riscv/attribute-05.d
index f9b65f2..ad24834 100644
--- a/gas/testsuite/gas/riscv/attribute-05.d
+++ b/gas/testsuite/gas/riscv/attribute-05.d
@@ -1,4 +1,4 @@
-#as: -march-attr
+#as: -march-attr -misa-spec=2.2
#readelf: -A
#source: attribute-05.s
Attribute Section: riscv
diff --git a/gas/testsuite/gas/riscv/attribute-06.d b/gas/testsuite/gas/riscv/attribute-06.d
index 1abeb47..a2dd9fb 100644
--- a/gas/testsuite/gas/riscv/attribute-06.d
+++ b/gas/testsuite/gas/riscv/attribute-06.d
@@ -1,4 +1,4 @@
-#as: -march=rv32g2p0 -march-attr
+#as: -march=rv32g2p0 -march-attr -misa-spec=2.2
#readelf: -A
#source: attribute-06.s
Attribute Section: riscv
diff --git a/gas/testsuite/gas/riscv/attribute-07.d b/gas/testsuite/gas/riscv/attribute-07.d
index dfd7e6b..342a537 100644
--- a/gas/testsuite/gas/riscv/attribute-07.d
+++ b/gas/testsuite/gas/riscv/attribute-07.d
@@ -1,4 +1,4 @@
-#as: -march=rv64g2p0 -march-attr
+#as: -march=rv64g2p0 -march-attr -misa-spec=2.2
#readelf: -A
#source: attribute-07.s
Attribute Section: riscv
--
2.7.4
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [PATCH v2 4/9] RISC-V: Support configure options to set ISA versions by default.
2020-05-06 2:55 ` [PATCH v2 4/9] RISC-V: Support configure options to set ISA versions by default Nelson Chu
@ 2020-05-19 9:07 ` Nelson Chu
0 siblings, 0 replies; 25+ messages in thread
From: Nelson Chu @ 2020-05-19 9:07 UTC (permalink / raw)
To: Binutils, gdb-patches
Cc: Palmer Dabbelt, Kito Cheng, Jim Wilson, Andrew Waterman,
Andrew Burgess, Alex Bradbury, Maxim Blinov
PING :)
On Wed, May 6, 2020 at 10:55 AM Nelson Chu <nelson.chu@sifive.com> wrote:
>
> Support new configure options --with-arch and --with-isa-spec to set
> ISA versions if we do not set the -march and -misa-spec options.
>
> * --with-arch = <ISA-string>
> The syntax of <ISA-string> is same as -march option. Assembler will
> check this if -march option and ELF arch attributes are not set.
>
> * --with-isa-spec = [2.2|20190608|20191213]
> The syntax is same as -misa-spec option. Assembler will check this if
> -misa-spec option is not set.
>
> The Priority of these options,
>
> * ELF arch attributes > Assembler options > Default configure options
> * For GAS options, -march > -misa-spec
> * For configure options, --with-arch > --with-isa-spec
>
> gas/
> * config/tc-riscv.c (DEFAULT_RISCV_ARCH_WITH_EXT,
> DEFAULT_RISCV_ISA_SPEC): Default configure option settings.
> You can set them by configure options --with-arch and
> --with-isa-spec, respectively.
> (riscv_set_default_isa_spec): New function used to set the
> default ISA spec.
> (md_parse_option): Call riscv_set_default_isa_spec rather than
> call riscv_get_isa_spec_class directly.
> (riscv_after_parse_args): If the -isa-spec is not set, then we
> set the default ISA spec according to DEFAULT_RISCV_ISA_SPEC by
> calling riscv_set_default_isa_spec.
>
> * testsuite/gas/riscv/attribute-01.d: Add -misa-spec=2.2, since
> the --with-isa-spec may be set to different ISA spec.
> * testsuite/gas/riscv/attribute-02.d: Likewise.
> * testsuite/gas/riscv/attribute-03.d: Likewise.
> * testsuite/gas/riscv/attribute-04.d: Likewise.
> * testsuite/gas/riscv/attribute-05.d: Likewise.
> * testsuite/gas/riscv/attribute-06.d: Likewise.
> * testsuite/gas/riscv/attribute-07.d: Likewise.
>
> * configure.ac: Add configure options, --with-arch and
> --with-isa-spec.
> * configure: Regenerated.
> * config.in: Regenerated.
> ---
> gas/config.in | 6 ++++
> gas/config/tc-riscv.c | 58 ++++++++++++++++++++++++++--------
> gas/configure | 39 ++++++++++++++++++++++-
> gas/configure.ac | 25 ++++++++++++++-
> gas/testsuite/gas/riscv/attribute-01.d | 2 +-
> gas/testsuite/gas/riscv/attribute-02.d | 2 +-
> gas/testsuite/gas/riscv/attribute-03.d | 2 +-
> gas/testsuite/gas/riscv/attribute-04.d | 2 +-
> gas/testsuite/gas/riscv/attribute-05.d | 2 +-
> gas/testsuite/gas/riscv/attribute-06.d | 2 +-
> gas/testsuite/gas/riscv/attribute-07.d | 2 +-
> 11 files changed, 119 insertions(+), 23 deletions(-)
>
> diff --git a/gas/config.in b/gas/config.in
> index 8724eb1..e20d3c3 100644
> --- a/gas/config.in
> +++ b/gas/config.in
> @@ -53,9 +53,15 @@
> /* Define to 1 if you want to fix Loongson3 LLSC Errata by default. */
> #undef DEFAULT_MIPS_FIX_LOONGSON3_LLSC
>
> +/* Define default value for RISC-V -march. */
> +#undef DEFAULT_RISCV_ARCH_WITH_EXT
> +
> /* Define to 1 if you want to generate RISC-V arch attribute by default. */
> #undef DEFAULT_RISCV_ATTR
>
> +/* Define default value for RISC-V -misa-spec. */
> +#undef DEFAULT_RISCV_ISA_SPEC
> +
> /* Define to 1 if you want to generate GNU x86 used ISA and feature properties
> by default. */
> #undef DEFAULT_X86_USED_NOTE
> diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
> index 5ef257e..3b6c429 100644
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -63,8 +63,24 @@ struct riscv_cl_insn
> #define DEFAULT_RISCV_ATTR 0
> #endif
>
> +/* Let riscv_after_parse_args set the default value according to xlen. */
> +
> +#ifndef DEFAULT_RISCV_ARCH_WITH_EXT
> +#define DEFAULT_RISCV_ARCH_WITH_EXT NULL
> +#endif
> +
> +/* The default ISA spec is set to 2.2 rather than the lastest version.
> + The reason is that compiler generates the ISA string with fixed 2p0
> + verisons only for the RISCV ELF architecture attributes, but not for
> + the -march option. Therefore, we should update the compiler or linker
> + to resolve this problem. */
> +
> +#ifndef DEFAULT_RISCV_ISA_SPEC
> +#define DEFAULT_RISCV_ISA_SPEC "2.2"
> +#endif
> +
> static const char default_arch[] = DEFAULT_ARCH;
> -static const char *default_arch_with_ext = NULL;
> +static const char *default_arch_with_ext = DEFAULT_RISCV_ARCH_WITH_EXT;
> static enum riscv_isa_spec_class default_isa_spec = ISA_SPEC_CLASS_NONE;
>
> static unsigned xlen = 0; /* width of an x-register */
> @@ -76,6 +92,24 @@ static bfd_boolean rve_abi = FALSE;
>
> static unsigned elf_flags = 0;
>
> +/* Set the default_isa_spec. Return 0 if the input spec string isn't
> + supported. Otherwise, return 1. */
> +
> +static int
> +riscv_set_default_isa_spec (const char *s)
> +{
> + enum riscv_isa_spec_class class;
> + if (!riscv_get_isa_spec_class (s, &class))
> + {
> + as_bad ("Unknown default ISA spec `%s' set by "
> + "-misa-spec or --with-isa-spec", s);
> + return 0;
> + }
> + else
> + default_isa_spec = class;
> + return 1;
> +}
> +
> /* This is the set of options which the .option pseudo-op may modify. */
>
> struct riscv_set_options
> @@ -2522,12 +2556,7 @@ md_parse_option (int c, const char *arg)
> break;
>
> case OPTION_MISA_SPEC:
> - if (!riscv_get_isa_spec_class (arg, &default_isa_spec))
> - {
> - as_bad ("Unknown default ISA spec `%s' set by -misa-spec", arg);
> - return 0;
> - }
> - break;
> + return riscv_set_default_isa_spec (arg);
>
> default:
> return 0;
> @@ -2539,6 +2568,10 @@ md_parse_option (int c, const char *arg)
> void
> riscv_after_parse_args (void)
> {
> + /* The --with-arch is optional for now, so we have to set the xlen
> + according to the default_arch, which is set by the --targte, first.
> + Then, we use the xlen to set the default_arch_with_ext if the
> + -march and --with-arch are not set. */
> if (xlen == 0)
> {
> if (strcmp (default_arch, "riscv32") == 0)
> @@ -2554,15 +2587,12 @@ riscv_after_parse_args (void)
> /* Initialize the hash table for extensions with default version. */
> ext_version_hash = init_ext_version_hash (riscv_ext_version_table);
>
> - /* The default ISA spec is set to 2.2 rather than the lastest version.
> - The reason is that compiler generates the ISA string with fixed 2p0
> - verisons only for the RISCV ELF architecture attributes, but not for
> - the -march option. Therefore, we should update the compiler or linker
> - to resolve this problem. */
> + /* If the -misa-spec isn't set, then we set the default ISA spec according
> + to DEFAULT_RISCV_ISA_SPEC. */
> if (default_isa_spec == ISA_SPEC_CLASS_NONE)
> - default_isa_spec = ISA_SPEC_CLASS_2P2;
> + riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC);
>
> - /* Set the architecture according to -march. */
> + /* Set the architecture according to -march or or --with-arch. */
> riscv_set_arch (default_arch_with_ext);
>
> /* Add the RVC extension, regardless of -march, to support .option rvc. */
> diff --git a/gas/configure b/gas/configure
> index 1515787..cc21e0a 100755
> --- a/gas/configure
> +++ b/gas/configure
> @@ -13009,7 +13009,7 @@ $as_echo "#define NDS32_DEFAULT_ZOL_EXT 1" >>confdefs.h
> $as_echo "$enable_zol_ext" >&6; }
> ;;
>
> - aarch64 | i386 | riscv | s390 | sparc)
> + aarch64 | i386 | s390 | sparc)
> if test $this_target = $target ; then
>
> cat >>confdefs.h <<_ACEOF
> @@ -13019,6 +13019,43 @@ _ACEOF
> fi
> ;;
>
> + riscv)
> + # --target=riscv[32|64]-*-*. */
> + if test $this_target = $target ; then
> +
> +cat >>confdefs.h <<_ACEOF
> +#define DEFAULT_ARCH "${arch}"
> +_ACEOF
> +
> + fi
> +
> + # --with-arch=<value>. The syntax of <value> is same as Gas option -march.
> + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for default configuration of --with-arch" >&5
> +$as_echo_n "checking for default configuration of --with-arch... " >&6; }
> + if test "x${with_arch}" != x; then
> +
> +cat >>confdefs.h <<_ACEOF
> +#define DEFAULT_RISCV_ARCH_WITH_EXT "$with_arch"
> +_ACEOF
> +
> + fi
> + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $with_arch" >&5
> +$as_echo "$with_arch" >&6; }
> +
> + # --with-isa-spec=[2.2|20190608|20191213].
> + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for default configuration of --with-isa-spec" >&5
> +$as_echo_n "checking for default configuration of --with-isa-spec... " >&6; }
> + if test "x${with_isa_spec}" != x; then
> +
> +cat >>confdefs.h <<_ACEOF
> +#define DEFAULT_RISCV_ISA_SPEC "$with_isa_spec"
> +_ACEOF
> +
> + fi
> + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $with_isa_spec" >&5
> +$as_echo "$with_isa_spec" >&6; }
> + ;;
> +
> rl78)
> f=rl78-parse.o
> case " $extra_objects " in
> diff --git a/gas/configure.ac b/gas/configure.ac
> index 6f32e55..8a5f5c5 100644
> --- a/gas/configure.ac
> +++ b/gas/configure.ac
> @@ -569,12 +569,35 @@ changequote([,])dnl
> AC_MSG_RESULT($enable_zol_ext)
> ;;
>
> - aarch64 | i386 | riscv | s390 | sparc)
> + aarch64 | i386 | s390 | sparc)
> if test $this_target = $target ; then
> AC_DEFINE_UNQUOTED(DEFAULT_ARCH, "${arch}", [Default architecture.])
> fi
> ;;
>
> + riscv)
> + # --target=riscv[32|64]-*-*. */
> + if test $this_target = $target ; then
> + AC_DEFINE_UNQUOTED(DEFAULT_ARCH, "${arch}", [Default architecture.])
> + fi
> +
> + # --with-arch=<value>. The syntax of <value> is same as Gas option -march.
> + AC_MSG_CHECKING(for default configuration of --with-arch)
> + if test "x${with_arch}" != x; then
> + AC_DEFINE_UNQUOTED(DEFAULT_RISCV_ARCH_WITH_EXT, "$with_arch",
> + [Define default value for RISC-V -march.])
> + fi
> + AC_MSG_RESULT($with_arch)
> +
> + # --with-isa-spec=[2.2|20190608|20191213].
> + AC_MSG_CHECKING(for default configuration of --with-isa-spec)
> + if test "x${with_isa_spec}" != x; then
> + AC_DEFINE_UNQUOTED(DEFAULT_RISCV_ISA_SPEC, "$with_isa_spec",
> + [Define default value for RISC-V -misa-spec.])
> + fi
> + AC_MSG_RESULT($with_isa_spec)
> + ;;
> +
> rl78)
> f=rl78-parse.o
> case " $extra_objects " in
> diff --git a/gas/testsuite/gas/riscv/attribute-01.d b/gas/testsuite/gas/riscv/attribute-01.d
> index e22773e..2e19e09 100644
> --- a/gas/testsuite/gas/riscv/attribute-01.d
> +++ b/gas/testsuite/gas/riscv/attribute-01.d
> @@ -1,4 +1,4 @@
> -#as: -march=rv32g -march-attr
> +#as: -march=rv32g -march-attr -misa-spec=2.2
> #readelf: -A
> #source: empty.s
> Attribute Section: riscv
> diff --git a/gas/testsuite/gas/riscv/attribute-02.d b/gas/testsuite/gas/riscv/attribute-02.d
> index e1e8ce3..ae0195e 100644
> --- a/gas/testsuite/gas/riscv/attribute-02.d
> +++ b/gas/testsuite/gas/riscv/attribute-02.d
> @@ -1,4 +1,4 @@
> -#as: -march=rv32gxargle -march-attr
> +#as: -march=rv32gxargle -march-attr -misa-spec=2.2
> #readelf: -A
> #source: empty.s
> Attribute Section: riscv
> diff --git a/gas/testsuite/gas/riscv/attribute-03.d b/gas/testsuite/gas/riscv/attribute-03.d
> index fa38bf3..9916ff6 100644
> --- a/gas/testsuite/gas/riscv/attribute-03.d
> +++ b/gas/testsuite/gas/riscv/attribute-03.d
> @@ -1,4 +1,4 @@
> -#as: -march=rv32gxargle_xfoo -march-attr
> +#as: -march=rv32gxargle_xfoo -march-attr -misa-spec=2.2
> #readelf: -A
> #source: empty.s
> Attribute Section: riscv
> diff --git a/gas/testsuite/gas/riscv/attribute-04.d b/gas/testsuite/gas/riscv/attribute-04.d
> index c97bf03..408464d 100644
> --- a/gas/testsuite/gas/riscv/attribute-04.d
> +++ b/gas/testsuite/gas/riscv/attribute-04.d
> @@ -1,4 +1,4 @@
> -#as: -march-attr
> +#as: -march-attr -misa-spec=2.2
> #readelf: -A
> #source: attribute-04.s
> Attribute Section: riscv
> diff --git a/gas/testsuite/gas/riscv/attribute-05.d b/gas/testsuite/gas/riscv/attribute-05.d
> index f9b65f2..ad24834 100644
> --- a/gas/testsuite/gas/riscv/attribute-05.d
> +++ b/gas/testsuite/gas/riscv/attribute-05.d
> @@ -1,4 +1,4 @@
> -#as: -march-attr
> +#as: -march-attr -misa-spec=2.2
> #readelf: -A
> #source: attribute-05.s
> Attribute Section: riscv
> diff --git a/gas/testsuite/gas/riscv/attribute-06.d b/gas/testsuite/gas/riscv/attribute-06.d
> index 1abeb47..a2dd9fb 100644
> --- a/gas/testsuite/gas/riscv/attribute-06.d
> +++ b/gas/testsuite/gas/riscv/attribute-06.d
> @@ -1,4 +1,4 @@
> -#as: -march=rv32g2p0 -march-attr
> +#as: -march=rv32g2p0 -march-attr -misa-spec=2.2
> #readelf: -A
> #source: attribute-06.s
> Attribute Section: riscv
> diff --git a/gas/testsuite/gas/riscv/attribute-07.d b/gas/testsuite/gas/riscv/attribute-07.d
> index dfd7e6b..342a537 100644
> --- a/gas/testsuite/gas/riscv/attribute-07.d
> +++ b/gas/testsuite/gas/riscv/attribute-07.d
> @@ -1,4 +1,4 @@
> -#as: -march=rv64g2p0 -march-attr
> +#as: -march=rv64g2p0 -march-attr -misa-spec=2.2
> #readelf: -A
> #source: attribute-07.s
> Attribute Section: riscv
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 5/9] RISC-V: Support version checking for CSR according to privilege spec version.
2020-05-06 2:55 [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR Nelson Chu
` (3 preceding siblings ...)
2020-05-06 2:55 ` [PATCH v2 4/9] RISC-V: Support configure options to set ISA versions by default Nelson Chu
@ 2020-05-06 2:55 ` Nelson Chu
2020-05-19 9:08 ` Nelson Chu
2020-05-06 2:55 ` [PATCH v2 6/9] RISC-V: Support configure option to choose the " Nelson Chu
` (4 subsequent siblings)
9 siblings, 1 reply; 25+ messages in thread
From: Nelson Chu @ 2020-05-06 2:55 UTC (permalink / raw)
To: binutils, gdb-patches
Cc: palmer, kito.cheng, jimw, andrew, andrew.burgess, asb,
maxim.blinov, nelson.chu
Support new GAS option -mpriv-spec to choose the privilege spec version, and
then assembler will generates the correct CSR address. If the obselete CSR
name is used, then report the warning message when the -mcsr-check is set,
and use the latest defined address for the CSR (Since we build hash table by
the DECLARE_CSR first, and then use the DECLARE_CSR_ALIAS). Maybe we can
insert the CSR hash entries in version's order, then we probably don't need
the DECLARE_CSR_ALIAS any more.
* -mpriv-spec=[1.9|1.9.1|1.10|1.11]
This is used to set the privileged spec version, and we can decide whether
the CSR is valid or not.
gas/
* config/tc-riscv.c (default_priv_spec): Static variable which is
used to check if the CSR is valid for the chosen privilege spec. You
can use -mpriv-spec to set it.
(enum reg_class): We now get the CSR address from csr_extra_hash rather
than reg_names_hash. Therefore, move RCLASS_CSR behind RCLASS_MAX.
(riscv_init_csr_hashes): Only need to initialize one hash table
csr_extra_hash.
(riscv_csr_class_check): Change the return type to void. Don't check
the ISA dependency if -mcsr-check isn't set.
(riscv_csr_version_check): New function. Check and find the CSR address
from csr_extra_hash, according to default_priv_spec. Report warning
for the invalid CSR if -mcsr-check is set.
(reg_csr_lookup_internal): Updated.
(reg_lookup_internal): Likewise.
(md_begin): Updated since DECLARE_CSR and DECLARE_CSR_ALIAS are changed.
(enum options, struct option md_longopts): Add new GAS option -mpriv-spec.
(md_parse_option): Call riscv_set_default_priv_version to set
default_priv_spec.
(riscv_after_parse_args): If -mpriv-spec isn't set, then set the default
privilege spec to the newest one.
(enum riscv_csr_class, struct riscv_csr_extra): Move them to
include/opcode/riscv.h.
* testsuite/gas/riscv/priv-reg-fail-fext.d: This test case just want
to check the ISA dependency for CSR, so fix the spec version by adding
-mpriv-spec=1.11.
* testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise. There are some
version warnings for the test case.
* gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d: New test case.
Check whether the CSR is valid when privilege version 1.9 is choosed.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: New test case.
Check whether the CSR is valid when privilege version 1.9.1 is choosed.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d: New test case.
Check whether the CSR is valid when privilege version 1.10 is choosed.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d: New test case.
Check whether the CSR is valid when privilege version 1.11 is choosed.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
include/
* opcode/riscv-opc.h (DECLARE_CSR): There are two version information,
define_version and abort_version. The define_version means which
privilege spec is started to define the CSR, and the abort_version
means which privilege spec is started to abort the CSR. If the CSR is
valid for the newest spec, then the abort_version should be
PRIV_SPEC_CLASS_DRAFT.
(DECLARE_CSR_ALIAS): Same as DECLARE_CSR, but only for the obselete CSR.
* opcode/riscv.h (enum riscv_priv_spec_class): New enum class. Define
the current supported privilege spec versions.
(struct riscv_csr_extra): Add new fields to store more information
about the CSR. We use these information to find the suitable CSR
address when user choosing a specific privilege spec.
opcodes/
* riscv-opc.c (struct priv_spec_t): New structure.
(struct priv_spec_t priv_specs): List for all supported privilege spec
classes and the corresponding strings.
(riscv_get_priv_spec_class): New function. Get the corresponding
privilege spec class by giving a spec string.
(riscv_get_priv_spec_name): New function. Get the corresponding
privilege spec string by giving a CSR version class.
* riscv-dis.c: Updated since DECLARE_CSR is changed.
gdb/
* riscv-tdep.c: Updated since DECLARE_CSR is changed.
* riscv-tdep.h: Likewise.
binutils/
* dwarf.c: Updated since DECLARE_CSR is changed.
---
binutils/dwarf.c | 3 +-
gas/config/tc-riscv.c | 200 +++++---
gas/testsuite/gas/riscv/priv-reg-fail-fext.d | 2 +-
gas/testsuite/gas/riscv/priv-reg-fail-fext.l | 25 +
.../gas/riscv/priv-reg-fail-read-only-01.d | 2 +-
.../gas/riscv/priv-reg-fail-read-only-01.l | 25 +
.../gas/riscv/priv-reg-fail-read-only-02.d | 2 +-
gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d | 2 +-
gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l | 25 +
.../gas/riscv/priv-reg-fail-version-1p10.d | 3 +
.../gas/riscv/priv-reg-fail-version-1p10.l | 27 ++
.../gas/riscv/priv-reg-fail-version-1p11.d | 3 +
.../gas/riscv/priv-reg-fail-version-1p11.l | 25 +
.../gas/riscv/priv-reg-fail-version-1p9.d | 3 +
.../gas/riscv/priv-reg-fail-version-1p9.l | 30 ++
.../gas/riscv/priv-reg-fail-version-1p9p1.d | 3 +
.../gas/riscv/priv-reg-fail-version-1p9p1.l | 30 ++
gdb/riscv-tdep.c | 6 +-
gdb/riscv-tdep.h | 2 +-
include/opcode/riscv-opc.h | 509 ++++++++++-----------
include/opcode/riscv.h | 50 ++
opcodes/riscv-dis.c | 3 +-
opcodes/riscv-opc.c | 51 +++
23 files changed, 700 insertions(+), 331 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d
create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l
create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d
create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l
create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d
create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.l
create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d
create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l
diff --git a/binutils/dwarf.c b/binutils/dwarf.c
index 7b5f7af..598f856 100644
--- a/binutils/dwarf.c
+++ b/binutils/dwarf.c
@@ -7409,7 +7409,8 @@ regname_internal_riscv (unsigned int regno)
document. */
switch (regno)
{
-#define DECLARE_CSR(NAME,VALUE,CLASS) case VALUE + 4096: name = #NAME; break;
+#define DECLARE_CSR(NAME,VALUE,CLASS,DEFINE_VER,ABORT_VER) \
+ case VALUE + 4096: name = #NAME; break;
#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 3b6c429..743e4bb 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -82,6 +82,7 @@ struct riscv_cl_insn
static const char default_arch[] = DEFAULT_ARCH;
static const char *default_arch_with_ext = DEFAULT_RISCV_ARCH_WITH_EXT;
static enum riscv_isa_spec_class default_isa_spec = ISA_SPEC_CLASS_NONE;
+static enum riscv_priv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE;
static unsigned xlen = 0; /* width of an x-register */
static unsigned abi_xlen = 0; /* width of a pointer in the ABI */
@@ -553,8 +554,9 @@ enum reg_class
{
RCLASS_GPR,
RCLASS_FPR,
- RCLASS_CSR,
- RCLASS_MAX
+ RCLASS_MAX,
+
+ RCLASS_CSR
};
static struct hash_control *reg_names_hash = NULL;
@@ -584,102 +586,163 @@ hash_reg_names (enum reg_class class, const char * const names[], unsigned n)
hash_reg_name (class, names[i], i);
}
-/* All RISC-V CSRs belong to one of these classes. */
-
-enum riscv_csr_class
-{
- CSR_CLASS_NONE,
+/* Init hash table csr_extra_hash to handle CSR. */
- CSR_CLASS_I,
- CSR_CLASS_I_32, /* rv32 only */
- CSR_CLASS_F, /* f-ext only */
-};
+static void
+riscv_init_csr_hash (const char *name,
+ unsigned address,
+ enum riscv_csr_class class,
+ enum riscv_priv_spec_class define_version,
+ enum riscv_priv_spec_class abort_version)
+{
+ struct riscv_csr_extra *entry, *pre_entry;
+ const char *hash_error = NULL;
+ bfd_boolean need_enrty = TRUE;
+
+ pre_entry = NULL;
+ entry = (struct riscv_csr_extra *) hash_find (csr_extra_hash, name);
+ while (need_enrty && entry != NULL)
+ {
+ if (entry->csr_class == class
+ && entry->address == address
+ && entry->define_version == define_version
+ && entry->abort_version == abort_version)
+ need_enrty = FALSE;
+ pre_entry = entry;
+ entry = entry->next;
+ }
-/* This structure holds all restricted conditions for a CSR. */
+ /* Duplicate setting for the CSR, just return and do nothing. */
+ if (!need_enrty)
+ return;
-struct riscv_csr_extra
-{
- /* Class to which this CSR belongs. Used to decide whether or
- not this CSR is legal in the current -march context. */
- enum riscv_csr_class csr_class;
-};
+ entry = XNEW (struct riscv_csr_extra);
+ entry->csr_class = class;
+ entry->address = address;
+ entry->define_version = define_version;
+ entry->abort_version = abort_version;
+
+ /* If the CSR hasn't been inserted in the hash table, then insert it.
+ Otherwise, attach the extra information to the entry which is already
+ in the hash table. */
+ if (pre_entry == NULL)
+ {
+ hash_error = hash_insert (csr_extra_hash, name, (void *) entry);
+ if (hash_error != NULL)
+ {
+ fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
+ name, hash_error);
+ /* Probably a memory allocation problem? Give up now. */
+ as_fatal (_("Broken assembler. No assembly attempted."));
+ }
+ }
+ else
+ pre_entry->next = entry;
+}
-/* Init two hashes, csr_extra_hash and reg_names_hash, for CSR. */
+/* Check wether the CSR is valid according to the ISA. */
static void
-riscv_init_csr_hashes (const char *name,
- unsigned address,
- enum riscv_csr_class class)
+riscv_csr_class_check (const char *s,
+ enum riscv_csr_class csr_class)
{
- struct riscv_csr_extra *entry = XNEW (struct riscv_csr_extra);
- entry->csr_class = class;
+ bfd_boolean result = TRUE;
- const char *hash_error =
- hash_insert (csr_extra_hash, name, (void *) entry);
- if (hash_error != NULL)
+ /* Don't check the ISA dependency when -mcsr-check isn't set. */
+ if (!riscv_opts.csr_check)
+ return;
+
+ switch (csr_class)
{
- fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
- name, hash_error);
- /* Probably a memory allocation problem? Give up now. */
- as_fatal (_("Broken assembler. No assembly attempted."));
+ case CSR_CLASS_I:
+ result = riscv_subset_supports ("i");
+ break;
+ case CSR_CLASS_F:
+ result = riscv_subset_supports ("f");
+ break;
+ case CSR_CLASS_I_32:
+ result = (xlen == 32 && riscv_subset_supports ("i"));
+ break;
+ default:
+ as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class);
}
-
- hash_reg_name (RCLASS_CSR, name, address);
+ if (!result)
+ as_warn (_("Invalid CSR `%s' for the current ISA"), s);
}
-/* Check wether the CSR is valid according to the ISA. */
+/* Check and find the CSR address according to the privilege spec version. */
-static bfd_boolean
-riscv_csr_class_check (enum riscv_csr_class csr_class)
+static void
+riscv_csr_version_check (const char *csr_name,
+ struct riscv_csr_extra **entryP)
{
- switch (csr_class)
+ struct riscv_csr_extra *entry = *entryP;
+ while (entry != NULL)
{
- case CSR_CLASS_I: return riscv_subset_supports ("i");
- case CSR_CLASS_F: return riscv_subset_supports ("f");
- case CSR_CLASS_I_32:
- return (xlen == 32 && riscv_subset_supports ("i"));
+ if (default_priv_spec >= entry->define_version
+ && default_priv_spec < entry->abort_version)
+ {
+ /* Find the suitable CSR according to the specific version. */
+ *entryP = entry;
+ return;
+ }
+ entry = entry->next;
+ }
- default:
- return FALSE;
+ /* We can not find the suitable CSR address according to the privilege
+ version. Therefore, we use the last defined value. Report the warning
+ only when the -mcsr-check is set. Enable the -mcsr-check is recommended,
+ otherwise, you may get the unexpected CSR address. */
+ if (riscv_opts.csr_check)
+ {
+ const char *priv_name = riscv_get_priv_spec_name (default_priv_spec);
+ if (priv_name != NULL)
+ as_warn (_("Invalid CSR `%s' for the privilege spec `%s'"),
+ csr_name, priv_name);
}
}
-/* If the CSR is defined, then we call `riscv_csr_class_check` to do the
- further checking. Return FALSE if the CSR is not defined. Otherwise,
- return TRUE. */
+/* Once the CSR is defined, including the old privilege spec, then we call
+ riscv_csr_class_check and riscv_csr_version_check to do the further checking
+ and get the corresponding address. Return -1 if the CSR is never been
+ defined. Otherwise, return the address. */
-static bfd_boolean
+static unsigned int
reg_csr_lookup_internal (const char *s)
{
struct riscv_csr_extra *r =
(struct riscv_csr_extra *) hash_find (csr_extra_hash, s);
if (r == NULL)
- return FALSE;
+ return -1;
- /* We just report the warning when the CSR is invalid. */
- if (!riscv_csr_class_check (r->csr_class))
- as_warn (_("Invalid CSR `%s' for the current ISA"), s);
+ /* We just report the warning when the CSR is invalid. "Invalid CSR" means
+ the CSR was defined, but isn't allowed for the current ISA setting or
+ the privilege spec. If the CSR is never been defined, then assembler
+ will regard it as a "Unknown CSR" and report error. If user use number
+ to set the CSR, but over the range (> 0xfff), then assembler will report
+ "Improper CSR" error for it. */
+ riscv_csr_class_check (s, r->csr_class);
+ riscv_csr_version_check (s, &r);
- return TRUE;
+ return r->address;
}
static unsigned int
reg_lookup_internal (const char *s, enum reg_class class)
{
- void *r = hash_find (reg_names_hash, s);
+ void *r;
+
+ if (class == RCLASS_CSR)
+ return reg_csr_lookup_internal (s);
+ r = hash_find (reg_names_hash, s);
if (r == NULL || DECODE_REG_CLASS (r) != class)
return -1;
if (riscv_opts.rve && class == RCLASS_GPR && DECODE_REG_NUM (r) > 15)
return -1;
- if (class == RCLASS_CSR
- && riscv_opts.csr_check
- && !reg_csr_lookup_internal (s))
- return -1;
-
return DECODE_REG_NUM (r);
}
@@ -963,8 +1026,10 @@ md_begin (void)
/* Create and insert CSR hash tables. */
csr_extra_hash = hash_new ();
-#define DECLARE_CSR(name, num, class) riscv_init_csr_hashes (#name, num, class);
-#define DECLARE_CSR_ALIAS(name, num, class) DECLARE_CSR(name, num, class);
+#define DECLARE_CSR(name, num, class, define_version, abort_version) \
+ riscv_init_csr_hash (#name, num, class, define_version, abort_version);
+#define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
+ DECLARE_CSR(name, num, class, define_version, abort_version);
#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
@@ -2450,6 +2515,7 @@ enum options
OPTION_CSR_CHECK,
OPTION_NO_CSR_CHECK,
OPTION_MISA_SPEC,
+ OPTION_MPRIV_SPEC,
OPTION_END_OF_ENUM
};
@@ -2467,6 +2533,7 @@ struct option md_longopts[] =
{"mcsr-check", no_argument, NULL, OPTION_CSR_CHECK},
{"mno-csr-check", no_argument, NULL, OPTION_NO_CSR_CHECK},
{"misa-spec", required_argument, NULL, OPTION_MISA_SPEC},
+ {"mpriv-spec", required_argument, NULL, OPTION_MPRIV_SPEC},
{NULL, no_argument, NULL, 0}
};
@@ -2558,6 +2625,15 @@ md_parse_option (int c, const char *arg)
case OPTION_MISA_SPEC:
return riscv_set_default_isa_spec (arg);
+ case OPTION_MPRIV_SPEC:
+ if (!riscv_get_priv_spec_class (arg, &default_priv_spec))
+ {
+ as_bad ("Unknown default privilege spec `%s' set by "
+ "-mpriv-spec", arg);
+ return 0;
+ }
+ break;
+
default:
return 0;
}
@@ -2605,6 +2681,10 @@ riscv_after_parse_args (void)
if (riscv_subset_supports ("e"))
riscv_set_rve (TRUE);
+ /* Set the default privilege spec to the newest one. */
+ if (default_priv_spec == PRIV_SPEC_CLASS_NONE)
+ default_priv_spec = PRIV_SPEC_CLASS_1P11;
+
/* Infer ABI from ISA if not specified on command line. */
if (abi_xlen == 0)
abi_xlen = xlen;
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-fext.d b/gas/testsuite/gas/riscv/priv-reg-fail-fext.d
index da53566..d9939eb 100644
--- a/gas/testsuite/gas/riscv/priv-reg-fail-fext.d
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-fext.d
@@ -1,3 +1,3 @@
-#as: -march=rv32i -mcsr-check
+#as: -march=rv32i -mcsr-check -mpriv-spec=1.11
#source: priv-reg.s
#warning_output: priv-reg-fail-fext.l
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-fext.l b/gas/testsuite/gas/riscv/priv-reg-fail-fext.l
index 76818c8..d74863e 100644
--- a/gas/testsuite/gas/riscv/priv-reg-fail-fext.l
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-fext.l
@@ -2,3 +2,28 @@
.*Warning: Invalid CSR `fflags' for the current ISA
.*Warning: Invalid CSR `frm' for the current ISA
.*Warning: Invalid CSR `fcsr' for the current ISA
+
+.*Warning: Invalid CSR `ubadaddr' for the privilege spec `1.11'
+.*Warning: Invalid CSR `sbadaddr' for the privilege spec `1.11'
+.*Warning: Invalid CSR `sptbr' for the privilege spec `1.11'
+.*Warning: Invalid CSR `mbadaddr' for the privilege spec `1.11'
+.*Warning: Invalid CSR `mucounteren' for the privilege spec `1.11'
+.*Warning: Invalid CSR `dscratch' for the privilege spec `1.11'
+.*Warning: Invalid CSR `hstatus' for the privilege spec `1.11'
+.*Warning: Invalid CSR `hedeleg' for the privilege spec `1.11'
+.*Warning: Invalid CSR `hideleg' for the privilege spec `1.11'
+.*Warning: Invalid CSR `hie' for the privilege spec `1.11'
+.*Warning: Invalid CSR `htvec' for the privilege spec `1.11'
+.*Warning: Invalid CSR `hscratch' for the privilege spec `1.11'
+.*Warning: Invalid CSR `hepc' for the privilege spec `1.11'
+.*Warning: Invalid CSR `hcause' for the privilege spec `1.11'
+.*Warning: Invalid CSR `hbadaddr' for the privilege spec `1.11'
+.*Warning: Invalid CSR `hip' for the privilege spec `1.11'
+.*Warning: Invalid CSR `mbase' for the privilege spec `1.11'
+.*Warning: Invalid CSR `mbound' for the privilege spec `1.11'
+.*Warning: Invalid CSR `mibase' for the privilege spec `1.11'
+.*Warning: Invalid CSR `mibound' for the privilege spec `1.11'
+.*Warning: Invalid CSR `mdbase' for the privilege spec `1.11'
+.*Warning: Invalid CSR `mdbound' for the privilege spec `1.11'
+.*Warning: Invalid CSR `mscounteren' for the privilege spec `1.11'
+.*Warning: Invalid CSR `mhcounteren' for the privilege spec `1.11'
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d
index ae190c0..b0f6726 100644
--- a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d
@@ -1,3 +1,3 @@
-#as: -march=rv32if -mcsr-check
+#as: -march=rv32if -mcsr-check -mpriv-spec=1.11
#source: priv-reg-fail-read-only-01.s
#warning_output: priv-reg-fail-read-only-01.l
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l
index 7e52bd7..2dc82f4 100644
--- a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l
@@ -67,3 +67,28 @@
.*Warning: Read-only CSR is written `csrw marchid,a1'
.*Warning: Read-only CSR is written `csrw mimpid,a1'
.*Warning: Read-only CSR is written `csrw mhartid,a1'
+
+.*Warning: Invalid CSR `ubadaddr' for the privilege spec `1.11'
+.*Warning: Invalid CSR `sbadaddr' for the privilege spec `1.11'
+.*Warning: Invalid CSR `sptbr' for the privilege spec `1.11'
+.*Warning: Invalid CSR `mbadaddr' for the privilege spec `1.11'
+.*Warning: Invalid CSR `mucounteren' for the privilege spec `1.11'
+.*Warning: Invalid CSR `dscratch' for the privilege spec `1.11'
+.*Warning: Invalid CSR `hstatus' for the privilege spec `1.11'
+.*Warning: Invalid CSR `hedeleg' for the privilege spec `1.11'
+.*Warning: Invalid CSR `hideleg' for the privilege spec `1.11'
+.*Warning: Invalid CSR `hie' for the privilege spec `1.11'
+.*Warning: Invalid CSR `htvec' for the privilege spec `1.11'
+.*Warning: Invalid CSR `hscratch' for the privilege spec `1.11'
+.*Warning: Invalid CSR `hepc' for the privilege spec `1.11'
+.*Warning: Invalid CSR `hcause' for the privilege spec `1.11'
+.*Warning: Invalid CSR `hbadaddr' for the privilege spec `1.11'
+.*Warning: Invalid CSR `hip' for the privilege spec `1.11'
+.*Warning: Invalid CSR `mbase' for the privilege spec `1.11'
+.*Warning: Invalid CSR `mbound' for the privilege spec `1.11'
+.*Warning: Invalid CSR `mibase' for the privilege spec `1.11'
+.*Warning: Invalid CSR `mibound' for the privilege spec `1.11'
+.*Warning: Invalid CSR `mdbase' for the privilege spec `1.11'
+.*Warning: Invalid CSR `mdbound' for the privilege spec `1.11'
+.*Warning: Invalid CSR `mscounteren' for the privilege spec `1.11'
+.*Warning: Invalid CSR `mhcounteren' for the privilege spec `1.11'
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d
index 3c4715f..ec206e4 100644
--- a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d
@@ -1,3 +1,3 @@
-#as: -march=rv32if -mcsr-check
+#as: -march=rv32if -mcsr-check -mpriv-spec=1.11
#source: priv-reg-fail-read-only-02.s
#warning_output: priv-reg-fail-read-only-02.l
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d
index d71b261..eced438 100644
--- a/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d
@@ -1,3 +1,3 @@
-#as: -march=rv64if -mcsr-check
+#as: -march=rv64if -mcsr-check -mpriv-spec=1.11
#source: priv-reg.s
#warning_output: priv-reg-fail-rv32-only.l
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l
index fa5a1b4..19f13a0 100644
--- a/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l
@@ -64,3 +64,28 @@
.*Warning: Invalid CSR `mhpmcounter29h' for the current ISA
.*Warning: Invalid CSR `mhpmcounter30h' for the current ISA
.*Warning: Invalid CSR `mhpmcounter31h' for the current ISA
+
+.*Warning: Invalid CSR `ubadaddr' for the privilege spec `1.11'
+.*Warning: Invalid CSR `sbadaddr' for the privilege spec `1.11'
+.*Warning: Invalid CSR `sptbr' for the privilege spec `1.11'
+.*Warning: Invalid CSR `mbadaddr' for the privilege spec `1.11'
+.*Warning: Invalid CSR `mucounteren' for the privilege spec `1.11'
+.*Warning: Invalid CSR `dscratch' for the privilege spec `1.11'
+.*Warning: Invalid CSR `hstatus' for the privilege spec `1.11'
+.*Warning: Invalid CSR `hedeleg' for the privilege spec `1.11'
+.*Warning: Invalid CSR `hideleg' for the privilege spec `1.11'
+.*Warning: Invalid CSR `hie' for the privilege spec `1.11'
+.*Warning: Invalid CSR `htvec' for the privilege spec `1.11'
+.*Warning: Invalid CSR `hscratch' for the privilege spec `1.11'
+.*Warning: Invalid CSR `hepc' for the privilege spec `1.11'
+.*Warning: Invalid CSR `hcause' for the privilege spec `1.11'
+.*Warning: Invalid CSR `hbadaddr' for the privilege spec `1.11'
+.*Warning: Invalid CSR `hip' for the privilege spec `1.11'
+.*Warning: Invalid CSR `mbase' for the privilege spec `1.11'
+.*Warning: Invalid CSR `mbound' for the privilege spec `1.11'
+.*Warning: Invalid CSR `mibase' for the privilege spec `1.11'
+.*Warning: Invalid CSR `mibound' for the privilege spec `1.11'
+.*Warning: Invalid CSR `mdbase' for the privilege spec `1.11'
+.*Warning: Invalid CSR `mdbound' for the privilege spec `1.11'
+.*Warning: Invalid CSR `mscounteren' for the privilege spec `1.11'
+.*Warning: Invalid CSR `mhcounteren' for the privilege spec `1.11'
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d
new file mode 100644
index 0000000..8dc2a10
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d
@@ -0,0 +1,3 @@
+#as: -march=rv32if -mcsr-check -mpriv-spec=1.10
+#source: priv-reg.s
+#warning_output: priv-reg-fail-version-1p10.l
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l
new file mode 100644
index 0000000..4146174
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l
@@ -0,0 +1,27 @@
+.*Assembler messages:
+.*Warning: Invalid CSR `mcountinhibit' for the privilege spec `1.10'
+.*Warning: Invalid CSR `dscratch0' for the privilege spec `1.10'
+.*Warning: Invalid CSR `dscratch1' for the privilege spec `1.10'
+.*Warning: Invalid CSR `ubadaddr' for the privilege spec `1.10'
+.*Warning: Invalid CSR `sbadaddr' for the privilege spec `1.10'
+.*Warning: Invalid CSR `sptbr' for the privilege spec `1.10'
+.*Warning: Invalid CSR `mbadaddr' for the privilege spec `1.10'
+.*Warning: Invalid CSR `mucounteren' for the privilege spec `1.10'
+.*Warning: Invalid CSR `hstatus' for the privilege spec `1.10'
+.*Warning: Invalid CSR `hedeleg' for the privilege spec `1.10'
+.*Warning: Invalid CSR `hideleg' for the privilege spec `1.10'
+.*Warning: Invalid CSR `hie' for the privilege spec `1.10'
+.*Warning: Invalid CSR `htvec' for the privilege spec `1.10'
+.*Warning: Invalid CSR `hscratch' for the privilege spec `1.10'
+.*Warning: Invalid CSR `hepc' for the privilege spec `1.10'
+.*Warning: Invalid CSR `hcause' for the privilege spec `1.10'
+.*Warning: Invalid CSR `hbadaddr' for the privilege spec `1.10'
+.*Warning: Invalid CSR `hip' for the privilege spec `1.10'
+.*Warning: Invalid CSR `mbase' for the privilege spec `1.10'
+.*Warning: Invalid CSR `mbound' for the privilege spec `1.10'
+.*Warning: Invalid CSR `mibase' for the privilege spec `1.10'
+.*Warning: Invalid CSR `mibound' for the privilege spec `1.10'
+.*Warning: Invalid CSR `mdbase' for the privilege spec `1.10'
+.*Warning: Invalid CSR `mdbound' for the privilege spec `1.10'
+.*Warning: Invalid CSR `mscounteren' for the privilege spec `1.10'
+.*Warning: Invalid CSR `mhcounteren' for the privilege spec `1.10'
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d
new file mode 100644
index 0000000..7d2406c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d
@@ -0,0 +1,3 @@
+#as: -march=rv32if -mcsr-check -mpriv-spec=1.11
+#source: priv-reg.s
+#warning_output: priv-reg-fail-version-1p11.l
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l
new file mode 100644
index 0000000..eadcb5c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l
@@ -0,0 +1,25 @@
+.*Assembler messages:
+.*Warning: Invalid CSR `ubadaddr' for the privilege spec `1.11'
+.*Warning: Invalid CSR `sbadaddr' for the privilege spec `1.11'
+.*Warning: Invalid CSR `sptbr' for the privilege spec `1.11'
+.*Warning: Invalid CSR `mbadaddr' for the privilege spec `1.11'
+.*Warning: Invalid CSR `mucounteren' for the privilege spec `1.11'
+.*Warning: Invalid CSR `dscratch' for the privilege spec `1.11'
+.*Warning: Invalid CSR `hstatus' for the privilege spec `1.11'
+.*Warning: Invalid CSR `hedeleg' for the privilege spec `1.11'
+.*Warning: Invalid CSR `hideleg' for the privilege spec `1.11'
+.*Warning: Invalid CSR `hie' for the privilege spec `1.11'
+.*Warning: Invalid CSR `htvec' for the privilege spec `1.11'
+.*Warning: Invalid CSR `hscratch' for the privilege spec `1.11'
+.*Warning: Invalid CSR `hepc' for the privilege spec `1.11'
+.*Warning: Invalid CSR `hcause' for the privilege spec `1.11'
+.*Warning: Invalid CSR `hbadaddr' for the privilege spec `1.11'
+.*Warning: Invalid CSR `hip' for the privilege spec `1.11'
+.*Warning: Invalid CSR `mbase' for the privilege spec `1.11'
+.*Warning: Invalid CSR `mbound' for the privilege spec `1.11'
+.*Warning: Invalid CSR `mibase' for the privilege spec `1.11'
+.*Warning: Invalid CSR `mibound' for the privilege spec `1.11'
+.*Warning: Invalid CSR `mdbase' for the privilege spec `1.11'
+.*Warning: Invalid CSR `mdbound' for the privilege spec `1.11'
+.*Warning: Invalid CSR `mscounteren' for the privilege spec `1.11'
+.*Warning: Invalid CSR `mhcounteren' for the privilege spec `1.11'
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d
new file mode 100644
index 0000000..a2db291
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d
@@ -0,0 +1,3 @@
+#as: -march=rv32if -mcsr-check -mpriv-spec=1.9
+#source: priv-reg.s
+#warning_output: priv-reg-fail-version-1p9.l
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.l b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.l
new file mode 100644
index 0000000..d7cee80
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.l
@@ -0,0 +1,30 @@
+.*Assembler messages:
+.*Warning: Invalid CSR `utval' for the privilege spec `1.9'
+.*Warning: Invalid CSR `scounteren' for the privilege spec `1.9'
+.*Warning: Invalid CSR `stval' for the privilege spec `1.9'
+.*Warning: Invalid CSR `satp' for the privilege spec `1.9'
+.*Warning: Invalid CSR `mcounteren' for the privilege spec `1.9'
+.*Warning: Invalid CSR `mtval' for the privilege spec `1.9'
+.*Warning: Invalid CSR `pmpcfg0' for the privilege spec `1.9'
+.*Warning: Invalid CSR `pmpcfg1' for the privilege spec `1.9'
+.*Warning: Invalid CSR `pmpcfg2' for the privilege spec `1.9'
+.*Warning: Invalid CSR `pmpcfg3' for the privilege spec `1.9'
+.*Warning: Invalid CSR `pmpaddr0' for the privilege spec `1.9'
+.*Warning: Invalid CSR `pmpaddr1' for the privilege spec `1.9'
+.*Warning: Invalid CSR `pmpaddr2' for the privilege spec `1.9'
+.*Warning: Invalid CSR `pmpaddr3' for the privilege spec `1.9'
+.*Warning: Invalid CSR `pmpaddr4' for the privilege spec `1.9'
+.*Warning: Invalid CSR `pmpaddr5' for the privilege spec `1.9'
+.*Warning: Invalid CSR `pmpaddr6' for the privilege spec `1.9'
+.*Warning: Invalid CSR `pmpaddr7' for the privilege spec `1.9'
+.*Warning: Invalid CSR `pmpaddr8' for the privilege spec `1.9'
+.*Warning: Invalid CSR `pmpaddr9' for the privilege spec `1.9'
+.*Warning: Invalid CSR `pmpaddr10' for the privilege spec `1.9'
+.*Warning: Invalid CSR `pmpaddr11' for the privilege spec `1.9'
+.*Warning: Invalid CSR `pmpaddr12' for the privilege spec `1.9'
+.*Warning: Invalid CSR `pmpaddr13' for the privilege spec `1.9'
+.*Warning: Invalid CSR `pmpaddr14' for the privilege spec `1.9'
+.*Warning: Invalid CSR `pmpaddr15' for the privilege spec `1.9'
+.*Warning: Invalid CSR `mcountinhibit' for the privilege spec `1.9'
+.*Warning: Invalid CSR `dscratch0' for the privilege spec `1.9'
+.*Warning: Invalid CSR `dscratch1' for the privilege spec `1.9'
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d
new file mode 100644
index 0000000..e870cf5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d
@@ -0,0 +1,3 @@
+#as: -march=rv32if -mcsr-check -mpriv-spec=1.9.1
+#source: priv-reg.s
+#warning_output: priv-reg-fail-version-1p9p1.l
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l
new file mode 100644
index 0000000..907ed73
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l
@@ -0,0 +1,30 @@
+.*Assembler messages:
+.*Warning: Invalid CSR `utval' for the privilege spec `1.9.1'
+.*Warning: Invalid CSR `scounteren' for the privilege spec `1.9.1'
+.*Warning: Invalid CSR `stval' for the privilege spec `1.9.1'
+.*Warning: Invalid CSR `satp' for the privilege spec `1.9.1'
+.*Warning: Invalid CSR `mcounteren' for the privilege spec `1.9.1'
+.*Warning: Invalid CSR `mtval' for the privilege spec `1.9.1'
+.*Warning: Invalid CSR `pmpcfg0' for the privilege spec `1.9.1'
+.*Warning: Invalid CSR `pmpcfg1' for the privilege spec `1.9.1'
+.*Warning: Invalid CSR `pmpcfg2' for the privilege spec `1.9.1'
+.*Warning: Invalid CSR `pmpcfg3' for the privilege spec `1.9.1'
+.*Warning: Invalid CSR `pmpaddr0' for the privilege spec `1.9.1'
+.*Warning: Invalid CSR `pmpaddr1' for the privilege spec `1.9.1'
+.*Warning: Invalid CSR `pmpaddr2' for the privilege spec `1.9.1'
+.*Warning: Invalid CSR `pmpaddr3' for the privilege spec `1.9.1'
+.*Warning: Invalid CSR `pmpaddr4' for the privilege spec `1.9.1'
+.*Warning: Invalid CSR `pmpaddr5' for the privilege spec `1.9.1'
+.*Warning: Invalid CSR `pmpaddr6' for the privilege spec `1.9.1'
+.*Warning: Invalid CSR `pmpaddr7' for the privilege spec `1.9.1'
+.*Warning: Invalid CSR `pmpaddr8' for the privilege spec `1.9.1'
+.*Warning: Invalid CSR `pmpaddr9' for the privilege spec `1.9.1'
+.*Warning: Invalid CSR `pmpaddr10' for the privilege spec `1.9.1'
+.*Warning: Invalid CSR `pmpaddr11' for the privilege spec `1.9.1'
+.*Warning: Invalid CSR `pmpaddr12' for the privilege spec `1.9.1'
+.*Warning: Invalid CSR `pmpaddr13' for the privilege spec `1.9.1'
+.*Warning: Invalid CSR `pmpaddr14' for the privilege spec `1.9.1'
+.*Warning: Invalid CSR `pmpaddr15' for the privilege spec `1.9.1'
+.*Warning: Invalid CSR `mcountinhibit' for the privilege spec `1.9.1'
+.*Warning: Invalid CSR `dscratch0' for the privilege spec `1.9.1'
+.*Warning: Invalid CSR `dscratch1' for the privilege spec `1.9.1'
diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index 1bb824e..e67f661 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -240,7 +240,7 @@ static struct riscv_register_feature riscv_csr_feature =
{
"org.gnu.gdb.riscv.csr",
{
-#define DECLARE_CSR(NAME,VALUE,CLASS) \
+#define DECLARE_CSR(NAME,VALUE,CLASS,DEFINE_VER,ABORT_VER) \
{ RISCV_ ## VALUE ## _REGNUM, { # NAME }, false },
#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
@@ -498,7 +498,7 @@ riscv_register_name (struct gdbarch *gdbarch, int regnum)
if (regnum >= RISCV_FIRST_CSR_REGNUM && regnum <= RISCV_LAST_CSR_REGNUM)
{
-#define DECLARE_CSR(NAME,VALUE,CLASS) \
+#define DECLARE_CSR(NAME,VALUE,CLASS,DEFINE_VER,ABORT_VER) \
case RISCV_ ## VALUE ## _REGNUM: return # NAME;
switch (regnum)
@@ -828,7 +828,7 @@ riscv_is_regnum_a_named_csr (int regnum)
switch (regnum)
{
-#define DECLARE_CSR(name, num, class) case RISCV_ ## num ## _REGNUM:
+#define DECLARE_CSR(name, num, class, define_ver, abort_ver) case RISCV_ ## num ## _REGNUM:
#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
return true;
diff --git a/gdb/riscv-tdep.h b/gdb/riscv-tdep.h
index 90bae08..e415fb4 100644
--- a/gdb/riscv-tdep.h
+++ b/gdb/riscv-tdep.h
@@ -44,7 +44,7 @@ enum
RISCV_LAST_FP_REGNUM = 64, /* Last Floating Point Register */
RISCV_FIRST_CSR_REGNUM = 65, /* First CSR */
-#define DECLARE_CSR(name, num, class) \
+#define DECLARE_CSR(name, num, class, define_version, abort_version) \
RISCV_ ## num ## _REGNUM = RISCV_FIRST_CSR_REGNUM + num,
#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index fe00bb6..a6a5de3 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -656,7 +656,6 @@
#define CSR_SIDELEG 0x103
#define CSR_SIE 0x104
#define CSR_STVEC 0x105
-/* scounteren is present int priv spec 1.10. */
#define CSR_SCOUNTEREN 0x106
#define CSR_SSCRATCH 0x140
#define CSR_SEPC 0x141
@@ -669,20 +668,17 @@
#define CSR_MIMPID 0xf13
#define CSR_MHARTID 0xf14
#define CSR_MSTATUS 0x300
-/* misa is 0xf10 in 1.9, but 0x301 in 1.9.1. */
#define CSR_MISA 0x301
#define CSR_MEDELEG 0x302
#define CSR_MIDELEG 0x303
#define CSR_MIE 0x304
#define CSR_MTVEC 0x305
-/* mcounteren is present in priv spec 1.10. */
#define CSR_MCOUNTEREN 0x306
#define CSR_MSCRATCH 0x340
#define CSR_MEPC 0x341
#define CSR_MCAUSE 0x342
#define CSR_MTVAL 0x343
#define CSR_MIP 0x344
-/* pmpcfg0 to pmpcfg3, pmpaddr0 to pmpaddr15 are present in priv spec 1.10. */
#define CSR_PMPCFG0 0x3a0
#define CSR_PMPCFG1 0x3a1
#define CSR_PMPCFG2 0x3a2
@@ -765,7 +761,6 @@
#define CSR_MHPMCOUNTER29H 0xb9d
#define CSR_MHPMCOUNTER30H 0xb9e
#define CSR_MHPMCOUNTER31H 0xb9f
-/* mcountinhibit is present in priv spec 1.11. */
#define CSR_MCOUNTINHIBIT 0x320
#define CSR_MHPMEVENT3 0x323
#define CSR_MHPMEVENT4 0x324
@@ -802,10 +797,8 @@
#define CSR_TDATA3 0x7a3
#define CSR_DCSR 0x7b0
#define CSR_DPC 0x7b1
-/* dscratch0 and dscratch1 are present in priv spec 1.11. */
#define CSR_DSCRATCH0 0x7b2
#define CSR_DSCRATCH1 0x7b3
-/* These registers are present in priv spec 1.9.1, but are dropped in 1.10. */
#define CSR_HSTATUS 0x200
#define CSR_HEDELEG 0x202
#define CSR_HIDELEG 0x203
@@ -1124,262 +1117,256 @@ DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
#endif
#ifdef DECLARE_CSR
-DECLARE_CSR(ustatus, CSR_USTATUS, CSR_CLASS_I)
-DECLARE_CSR(uie, CSR_UIE, CSR_CLASS_I)
-DECLARE_CSR(utvec, CSR_UTVEC, CSR_CLASS_I)
-DECLARE_CSR(uscratch, CSR_USCRATCH, CSR_CLASS_I)
-DECLARE_CSR(uepc, CSR_UEPC, CSR_CLASS_I)
-DECLARE_CSR(ucause, CSR_UCAUSE, CSR_CLASS_I)
-DECLARE_CSR(utval, CSR_UTVAL, CSR_CLASS_I)
-DECLARE_CSR(uip, CSR_UIP, CSR_CLASS_I)
-DECLARE_CSR(fflags, CSR_FFLAGS, CSR_CLASS_F)
-DECLARE_CSR(frm, CSR_FRM, CSR_CLASS_F)
-DECLARE_CSR(fcsr, CSR_FCSR, CSR_CLASS_F)
-DECLARE_CSR(cycle, CSR_CYCLE, CSR_CLASS_I)
-DECLARE_CSR(time, CSR_TIME, CSR_CLASS_I)
-DECLARE_CSR(instret, CSR_INSTRET, CSR_CLASS_I)
-DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3, CSR_CLASS_I)
-DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4, CSR_CLASS_I)
-DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5, CSR_CLASS_I)
-DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6, CSR_CLASS_I)
-DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7, CSR_CLASS_I)
-DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8, CSR_CLASS_I)
-DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9, CSR_CLASS_I)
-DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10, CSR_CLASS_I)
-DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11, CSR_CLASS_I)
-DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12, CSR_CLASS_I)
-DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13, CSR_CLASS_I)
-DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14, CSR_CLASS_I)
-DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15, CSR_CLASS_I)
-DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16, CSR_CLASS_I)
-DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17, CSR_CLASS_I)
-DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18, CSR_CLASS_I)
-DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19, CSR_CLASS_I)
-DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20, CSR_CLASS_I)
-DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21, CSR_CLASS_I)
-DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22, CSR_CLASS_I)
-DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23, CSR_CLASS_I)
-DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24, CSR_CLASS_I)
-DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25, CSR_CLASS_I)
-DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26, CSR_CLASS_I)
-DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27, CSR_CLASS_I)
-DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28, CSR_CLASS_I)
-DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29, CSR_CLASS_I)
-DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30, CSR_CLASS_I)
-DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31, CSR_CLASS_I)
-DECLARE_CSR(cycleh, CSR_CYCLEH, CSR_CLASS_I_32)
-DECLARE_CSR(timeh, CSR_TIMEH, CSR_CLASS_I_32)
-DECLARE_CSR(instreth, CSR_INSTRETH, CSR_CLASS_I_32)
-DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H, CSR_CLASS_I_32)
-DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H, CSR_CLASS_I_32)
-DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H, CSR_CLASS_I_32)
-DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H, CSR_CLASS_I_32)
-DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H, CSR_CLASS_I_32)
-DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H, CSR_CLASS_I_32)
-DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H, CSR_CLASS_I_32)
-DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H, CSR_CLASS_I_32)
-DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H, CSR_CLASS_I_32)
-DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H, CSR_CLASS_I_32)
-DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H, CSR_CLASS_I_32)
-DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H, CSR_CLASS_I_32)
-DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H, CSR_CLASS_I_32)
-DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H, CSR_CLASS_I_32)
-DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H, CSR_CLASS_I_32)
-DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H, CSR_CLASS_I_32)
-DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H, CSR_CLASS_I_32)
-DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H, CSR_CLASS_I_32)
-DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H, CSR_CLASS_I_32)
-DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H, CSR_CLASS_I_32)
-DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H, CSR_CLASS_I_32)
-DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H, CSR_CLASS_I_32)
-DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H, CSR_CLASS_I_32)
-DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H, CSR_CLASS_I_32)
-DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H, CSR_CLASS_I_32)
-DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H, CSR_CLASS_I_32)
-DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H, CSR_CLASS_I_32)
-DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H, CSR_CLASS_I_32)
-DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H, CSR_CLASS_I_32)
-DECLARE_CSR(sstatus, CSR_SSTATUS, CSR_CLASS_I)
-DECLARE_CSR(sedeleg, CSR_SEDELEG, CSR_CLASS_I)
-DECLARE_CSR(sideleg, CSR_SIDELEG, CSR_CLASS_I)
-DECLARE_CSR(sie, CSR_SIE, CSR_CLASS_I)
-DECLARE_CSR(stvec, CSR_STVEC, CSR_CLASS_I)
-DECLARE_CSR(scounteren, CSR_SCOUNTEREN, CSR_CLASS_I)
-DECLARE_CSR(sscratch, CSR_SSCRATCH, CSR_CLASS_I)
-DECLARE_CSR(sepc, CSR_SEPC, CSR_CLASS_I)
-DECLARE_CSR(scause, CSR_SCAUSE, CSR_CLASS_I)
-DECLARE_CSR(stval, CSR_STVAL, CSR_CLASS_I)
-DECLARE_CSR(sip, CSR_SIP, CSR_CLASS_I)
-DECLARE_CSR(satp, CSR_SATP, CSR_CLASS_I)
-DECLARE_CSR(mvendorid, CSR_MVENDORID, CSR_CLASS_I)
-DECLARE_CSR(marchid, CSR_MARCHID, CSR_CLASS_I)
-DECLARE_CSR(mimpid, CSR_MIMPID, CSR_CLASS_I)
-DECLARE_CSR(mhartid, CSR_MHARTID, CSR_CLASS_I)
-DECLARE_CSR(mstatus, CSR_MSTATUS, CSR_CLASS_I)
-DECLARE_CSR(misa, CSR_MISA, CSR_CLASS_I)
-DECLARE_CSR(medeleg, CSR_MEDELEG, CSR_CLASS_I)
-DECLARE_CSR(mideleg, CSR_MIDELEG, CSR_CLASS_I)
-DECLARE_CSR(mie, CSR_MIE, CSR_CLASS_I)
-DECLARE_CSR(mtvec, CSR_MTVEC, CSR_CLASS_I)
-DECLARE_CSR(mcounteren, CSR_MCOUNTEREN, CSR_CLASS_I)
-DECLARE_CSR(mscratch, CSR_MSCRATCH, CSR_CLASS_I)
-DECLARE_CSR(mepc, CSR_MEPC, CSR_CLASS_I)
-DECLARE_CSR(mcause, CSR_MCAUSE, CSR_CLASS_I)
-DECLARE_CSR(mtval, CSR_MTVAL, CSR_CLASS_I)
-DECLARE_CSR(mip, CSR_MIP, CSR_CLASS_I)
-DECLARE_CSR(pmpcfg0, CSR_PMPCFG0, CSR_CLASS_I)
-DECLARE_CSR(pmpcfg1, CSR_PMPCFG1, CSR_CLASS_I_32)
-DECLARE_CSR(pmpcfg2, CSR_PMPCFG2, CSR_CLASS_I)
-DECLARE_CSR(pmpcfg3, CSR_PMPCFG3, CSR_CLASS_I_32)
-DECLARE_CSR(pmpaddr0, CSR_PMPADDR0, CSR_CLASS_I)
-DECLARE_CSR(pmpaddr1, CSR_PMPADDR1, CSR_CLASS_I)
-DECLARE_CSR(pmpaddr2, CSR_PMPADDR2, CSR_CLASS_I)
-DECLARE_CSR(pmpaddr3, CSR_PMPADDR3, CSR_CLASS_I)
-DECLARE_CSR(pmpaddr4, CSR_PMPADDR4, CSR_CLASS_I)
-DECLARE_CSR(pmpaddr5, CSR_PMPADDR5, CSR_CLASS_I)
-DECLARE_CSR(pmpaddr6, CSR_PMPADDR6, CSR_CLASS_I)
-DECLARE_CSR(pmpaddr7, CSR_PMPADDR7, CSR_CLASS_I)
-DECLARE_CSR(pmpaddr8, CSR_PMPADDR8, CSR_CLASS_I)
-DECLARE_CSR(pmpaddr9, CSR_PMPADDR9, CSR_CLASS_I)
-DECLARE_CSR(pmpaddr10, CSR_PMPADDR10, CSR_CLASS_I)
-DECLARE_CSR(pmpaddr11, CSR_PMPADDR11, CSR_CLASS_I)
-DECLARE_CSR(pmpaddr12, CSR_PMPADDR12, CSR_CLASS_I)
-DECLARE_CSR(pmpaddr13, CSR_PMPADDR13, CSR_CLASS_I)
-DECLARE_CSR(pmpaddr14, CSR_PMPADDR14, CSR_CLASS_I)
-DECLARE_CSR(pmpaddr15, CSR_PMPADDR15, CSR_CLASS_I)
-DECLARE_CSR(mcycle, CSR_MCYCLE, CSR_CLASS_I)
-DECLARE_CSR(minstret, CSR_MINSTRET, CSR_CLASS_I)
-DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3, CSR_CLASS_I)
-DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4, CSR_CLASS_I)
-DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5, CSR_CLASS_I)
-DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6, CSR_CLASS_I)
-DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7, CSR_CLASS_I)
-DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8, CSR_CLASS_I)
-DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9, CSR_CLASS_I)
-DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10, CSR_CLASS_I)
-DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11, CSR_CLASS_I)
-DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12, CSR_CLASS_I)
-DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13, CSR_CLASS_I)
-DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14, CSR_CLASS_I)
-DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15, CSR_CLASS_I)
-DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16, CSR_CLASS_I)
-DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17, CSR_CLASS_I)
-DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18, CSR_CLASS_I)
-DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19, CSR_CLASS_I)
-DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20, CSR_CLASS_I)
-DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21, CSR_CLASS_I)
-DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22, CSR_CLASS_I)
-DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23, CSR_CLASS_I)
-DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24, CSR_CLASS_I)
-DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25, CSR_CLASS_I)
-DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26, CSR_CLASS_I)
-DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27, CSR_CLASS_I)
-DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28, CSR_CLASS_I)
-DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29, CSR_CLASS_I)
-DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30, CSR_CLASS_I)
-DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31, CSR_CLASS_I)
-DECLARE_CSR(mcycleh, CSR_MCYCLEH, CSR_CLASS_I_32)
-DECLARE_CSR(minstreth, CSR_MINSTRETH, CSR_CLASS_I_32)
-DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H, CSR_CLASS_I_32)
-DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H, CSR_CLASS_I_32)
-DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H, CSR_CLASS_I_32)
-DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H, CSR_CLASS_I_32)
-DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H, CSR_CLASS_I_32)
-DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H, CSR_CLASS_I_32)
-DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H, CSR_CLASS_I_32)
-DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H, CSR_CLASS_I_32)
-DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H, CSR_CLASS_I_32)
-DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H, CSR_CLASS_I_32)
-DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H, CSR_CLASS_I_32)
-DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H, CSR_CLASS_I_32)
-DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H, CSR_CLASS_I_32)
-DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H, CSR_CLASS_I_32)
-DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H, CSR_CLASS_I_32)
-DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H, CSR_CLASS_I_32)
-DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H, CSR_CLASS_I_32)
-DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H, CSR_CLASS_I_32)
-DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H, CSR_CLASS_I_32)
-DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H, CSR_CLASS_I_32)
-DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H, CSR_CLASS_I_32)
-DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H, CSR_CLASS_I_32)
-DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H, CSR_CLASS_I_32)
-DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H, CSR_CLASS_I_32)
-DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H, CSR_CLASS_I_32)
-DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H, CSR_CLASS_I_32)
-DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H, CSR_CLASS_I_32)
-DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H, CSR_CLASS_I_32)
-DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H, CSR_CLASS_I_32)
-DECLARE_CSR(mcountinhibit, CSR_MCOUNTINHIBIT, CSR_CLASS_I)
-DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3, CSR_CLASS_I)
-DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4, CSR_CLASS_I)
-DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5, CSR_CLASS_I)
-DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6, CSR_CLASS_I)
-DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7, CSR_CLASS_I)
-DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8, CSR_CLASS_I)
-DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9, CSR_CLASS_I)
-DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10, CSR_CLASS_I)
-DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11, CSR_CLASS_I)
-DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12, CSR_CLASS_I)
-DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13, CSR_CLASS_I)
-DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14, CSR_CLASS_I)
-DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15, CSR_CLASS_I)
-DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16, CSR_CLASS_I)
-DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17, CSR_CLASS_I)
-DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18, CSR_CLASS_I)
-DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19, CSR_CLASS_I)
-DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20, CSR_CLASS_I)
-DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21, CSR_CLASS_I)
-DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22, CSR_CLASS_I)
-DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23, CSR_CLASS_I)
-DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24, CSR_CLASS_I)
-DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25, CSR_CLASS_I)
-DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26, CSR_CLASS_I)
-DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27, CSR_CLASS_I)
-DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28, CSR_CLASS_I)
-DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29, CSR_CLASS_I)
-DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30, CSR_CLASS_I)
-DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31, CSR_CLASS_I)
-DECLARE_CSR(tselect, CSR_TSELECT, CSR_CLASS_I)
-DECLARE_CSR(tdata1, CSR_TDATA1, CSR_CLASS_I)
-DECLARE_CSR(tdata2, CSR_TDATA2, CSR_CLASS_I)
-DECLARE_CSR(tdata3, CSR_TDATA3, CSR_CLASS_I)
-DECLARE_CSR(dcsr, CSR_DCSR, CSR_CLASS_I)
-DECLARE_CSR(dpc, CSR_DPC, CSR_CLASS_I)
-DECLARE_CSR(dscratch0, CSR_DSCRATCH0, CSR_CLASS_I)
-DECLARE_CSR(dscratch1, CSR_DSCRATCH1, CSR_CLASS_I)
-/* These registers are present in priv spec 1.9.1, dropped in 1.10. */
-DECLARE_CSR(hstatus, CSR_HSTATUS, CSR_CLASS_I)
-DECLARE_CSR(hedeleg, CSR_HEDELEG, CSR_CLASS_I)
-DECLARE_CSR(hideleg, CSR_HIDELEG, CSR_CLASS_I)
-DECLARE_CSR(hie, CSR_HIE, CSR_CLASS_I)
-DECLARE_CSR(htvec, CSR_HTVEC, CSR_CLASS_I)
-DECLARE_CSR(hscratch, CSR_HSCRATCH, CSR_CLASS_I)
-DECLARE_CSR(hepc, CSR_HEPC, CSR_CLASS_I)
-DECLARE_CSR(hcause, CSR_HCAUSE, CSR_CLASS_I)
-DECLARE_CSR(hbadaddr, CSR_HBADADDR, CSR_CLASS_I)
-DECLARE_CSR(hip, CSR_HIP, CSR_CLASS_I)
-DECLARE_CSR(mbase, CSR_MBASE, CSR_CLASS_I)
-DECLARE_CSR(mbound, CSR_MBOUND, CSR_CLASS_I)
-DECLARE_CSR(mibase, CSR_MIBASE, CSR_CLASS_I)
-DECLARE_CSR(mibound, CSR_MIBOUND, CSR_CLASS_I)
-DECLARE_CSR(mdbase, CSR_MDBASE, CSR_CLASS_I)
-DECLARE_CSR(mdbound, CSR_MDBOUND, CSR_CLASS_I)
-DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN, CSR_CLASS_I)
-DECLARE_CSR(mhcounteren, CSR_MHCOUNTEREN, CSR_CLASS_I)
+DECLARE_CSR(ustatus, CSR_USTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(uie, CSR_UIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(utvec, CSR_UTVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(uscratch, CSR_USCRATCH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(uepc, CSR_UEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(ucause, CSR_UCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(utval, CSR_UTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(uip, CSR_UIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(fflags, CSR_FFLAGS, CSR_CLASS_F, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(frm, CSR_FRM, CSR_CLASS_F, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(fcsr, CSR_FCSR, CSR_CLASS_F, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(cycle, CSR_CYCLE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(time, CSR_TIME, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(instret, CSR_INSTRET, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(cycleh, CSR_CYCLEH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(timeh, CSR_TIMEH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(instreth, CSR_INSTRETH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(sstatus, CSR_SSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(sedeleg, CSR_SEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(sideleg, CSR_SIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(sie, CSR_SIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(stvec, CSR_STVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(scounteren, CSR_SCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(sscratch, CSR_SSCRATCH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(sepc, CSR_SEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(scause, CSR_SCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(stval, CSR_STVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(sip, CSR_SIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(satp, CSR_SATP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mvendorid, CSR_MVENDORID, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(marchid, CSR_MARCHID, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mimpid, CSR_MIMPID, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhartid, CSR_MHARTID, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mstatus, CSR_MSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(misa, CSR_MISA, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(medeleg, CSR_MEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mideleg, CSR_MIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mie, CSR_MIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mtvec, CSR_MTVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mcounteren, CSR_MCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mscratch, CSR_MSCRATCH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mepc, CSR_MEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mcause, CSR_MCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mtval, CSR_MTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mip, CSR_MIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(pmpcfg0, CSR_PMPCFG0, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(pmpcfg1, CSR_PMPCFG1, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(pmpcfg2, CSR_PMPCFG2, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(pmpcfg3, CSR_PMPCFG3, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(pmpaddr0, CSR_PMPADDR0, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(pmpaddr1, CSR_PMPADDR1, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(pmpaddr2, CSR_PMPADDR2, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(pmpaddr3, CSR_PMPADDR3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(pmpaddr4, CSR_PMPADDR4, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(pmpaddr5, CSR_PMPADDR5, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(pmpaddr6, CSR_PMPADDR6, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(pmpaddr7, CSR_PMPADDR7, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(pmpaddr8, CSR_PMPADDR8, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(pmpaddr9, CSR_PMPADDR9, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(pmpaddr10, CSR_PMPADDR10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(pmpaddr11, CSR_PMPADDR11, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(pmpaddr12, CSR_PMPADDR12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(pmpaddr13, CSR_PMPADDR13, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(pmpaddr14, CSR_PMPADDR14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(pmpaddr15, CSR_PMPADDR15, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mcycle, CSR_MCYCLE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(minstret, CSR_MINSTRET, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mcycleh, CSR_MCYCLEH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(minstreth, CSR_MINSTRETH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mcountinhibit, CSR_MCOUNTINHIBIT, CSR_CLASS_I, PRIV_SPEC_CLASS_1P11, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(tselect, CSR_TSELECT, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(tdata1, CSR_TDATA1, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(tdata2, CSR_TDATA2, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(tdata3, CSR_TDATA3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(dcsr, CSR_DCSR, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(dpc, CSR_DPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(dscratch0, CSR_DSCRATCH0, CSR_CLASS_I, PRIV_SPEC_CLASS_1P11, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(dscratch1, CSR_DSCRATCH1, CSR_CLASS_I, PRIV_SPEC_CLASS_1P11, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hstatus, CSR_HSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
+DECLARE_CSR(hedeleg, CSR_HEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
+DECLARE_CSR(hideleg, CSR_HIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
+DECLARE_CSR(hie, CSR_HIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
+DECLARE_CSR(htvec, CSR_HTVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
+DECLARE_CSR(hscratch, CSR_HSCRATCH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
+DECLARE_CSR(hepc, CSR_HEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
+DECLARE_CSR(hcause, CSR_HCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
+DECLARE_CSR(hbadaddr, CSR_HBADADDR, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
+DECLARE_CSR(hip, CSR_HIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
+DECLARE_CSR(mbase, CSR_MBASE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
+DECLARE_CSR(mbound, CSR_MBOUND, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
+DECLARE_CSR(mibase, CSR_MIBASE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
+DECLARE_CSR(mibound, CSR_MIBOUND, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
+DECLARE_CSR(mdbase, CSR_MDBASE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
+DECLARE_CSR(mdbound, CSR_MDBOUND, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
+DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
+DECLARE_CSR(mhcounteren, CSR_MHCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
#endif
#ifdef DECLARE_CSR_ALIAS
-/* Ubadaddr is 0x043 in 1.9.1, but 0x043 is utval in 1.10. */
-DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL, CSR_CLASS_I)
-/* Sbadaddr is 0x143 in 1.9.1, but 0x143 is stval in 1.10. */
-DECLARE_CSR_ALIAS(sbadaddr, CSR_STVAL, CSR_CLASS_I)
-/* Sptbr is 0x180 in 1.9.1, but 0x180 is satp in 1.10. */
-DECLARE_CSR_ALIAS(sptbr, CSR_SATP, CSR_CLASS_I)
-/* Mbadaddr is 0x343 in 1.9.1, but 0x343 is mtval in 1.10. */
-DECLARE_CSR_ALIAS(mbadaddr, CSR_MTVAL, CSR_CLASS_I)
-/* Mucounteren is 0x320 in 1.10, but 0x320 is mcountinhibit in 1.11. */
-DECLARE_CSR_ALIAS(mucounteren, CSR_MCOUNTINHIBIT, CSR_CLASS_I)
-/* Dscratch is 0x7b2 in 1.10, but 0x7b2 is dscratch0 in 1.11. */
-DECLARE_CSR_ALIAS(dscratch, CSR_DSCRATCH0, CSR_CLASS_I)
+DECLARE_CSR_ALIAS(misa, 0xf10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P9P1)
+DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
+DECLARE_CSR_ALIAS(sbadaddr, CSR_STVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
+DECLARE_CSR_ALIAS(sptbr, CSR_SATP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
+DECLARE_CSR_ALIAS(mbadaddr, CSR_MTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
+DECLARE_CSR_ALIAS(mucounteren, CSR_MCOUNTINHIBIT, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
+DECLARE_CSR_ALIAS(dscratch, CSR_DSCRATCH0, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P11)
#endif
#ifdef DECLARE_CAUSE
DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index d83e9ca..84f7c2a 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -365,6 +365,52 @@ struct riscv_ext_version
unsigned int minor_version;
};
+/* All RISC-V CSR belong to one of these classes. */
+
+enum riscv_csr_class
+{
+ CSR_CLASS_NONE,
+
+ CSR_CLASS_I,
+ CSR_CLASS_I_32, /* rv32 only */
+ CSR_CLASS_F, /* f-ext only */
+};
+
+/* The current supported privilege spec versions. */
+
+enum riscv_priv_spec_class
+{
+ PRIV_SPEC_CLASS_NONE,
+
+ PRIV_SPEC_CLASS_1P9,
+ PRIV_SPEC_CLASS_1P9P1,
+ PRIV_SPEC_CLASS_1P10,
+ PRIV_SPEC_CLASS_1P11,
+ PRIV_SPEC_CLASS_DRAFT
+};
+
+/* This structure holds all restricted conditions for a CSR. */
+
+struct riscv_csr_extra
+{
+ /* Class to which this CSR belongs. Used to decide whether or
+ not this CSR is legal in the current -march context. */
+ enum riscv_csr_class csr_class;
+
+ /* CSR may have differnet numbers in the previous priv spec. */
+ unsigned address;
+
+ /* Record the CSR is defined/valid in which versions. */
+ enum riscv_priv_spec_class define_version;
+
+ /* Record the CSR is aborted/invalid from which versions. If it isn't
+ aborted in the current version, then it should be CSR_CLASS_VDRAFT. */
+ enum riscv_priv_spec_class abort_version;
+
+ /* The CSR may have more than one setting. */
+ struct riscv_csr_extra *next;
+};
+
/* Instruction is a simple alias (e.g. "mv" for "addi"). */
#define INSN_ALIAS 0x00000001
@@ -446,5 +492,9 @@ extern const struct riscv_ext_version riscv_ext_version_table[];
extern bfd_boolean
riscv_get_isa_spec_class (const char *, enum riscv_isa_spec_class *);
+extern bfd_boolean
+riscv_get_priv_spec_class (const char *, enum riscv_priv_spec_class *);
+extern const char *
+riscv_get_priv_spec_name (enum riscv_priv_spec_class);
#endif /* _RISCV_H_ */
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index d7a184c..98302ff 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -326,7 +326,8 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
unsigned int csr = EXTRACT_OPERAND (CSR, l);
switch (csr)
{
-#define DECLARE_CSR(name, num, class) case num: csr_name = #name; break;
+#define DECLARE_CSR(name, num, class, define_version, abort_version) \
+ case num: csr_name = #name; break;
#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
}
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index f08b15e..da376ad 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -977,3 +977,54 @@ riscv_get_isa_spec_class (const char *s,
/* Can not find the supported ISA spec. */
return FALSE;
}
+
+struct priv_spec_t
+{
+ const char *name;
+ enum riscv_priv_spec_class class;
+};
+
+/* List for all supported privilege versions. */
+static const struct priv_spec_t priv_specs[] =
+{
+ {"1.9", PRIV_SPEC_CLASS_1P9},
+ {"1.9.1", PRIV_SPEC_CLASS_1P9P1},
+ {"1.10", PRIV_SPEC_CLASS_1P10},
+ {"1.11", PRIV_SPEC_CLASS_1P11},
+
+/* Terminate the list. */
+ {NULL, 0}
+};
+
+/* Get the corresponding CSR version class by giving a privilege
+ version string. */
+
+bfd_boolean
+riscv_get_priv_spec_class (const char *s,
+ enum riscv_priv_spec_class *class)
+{
+ const struct priv_spec_t *version;
+
+ if (s == NULL)
+ return FALSE;
+
+ for (version = &priv_specs[0]; version->name != NULL; ++version)
+ if (strcmp (version->name, s) == 0)
+ {
+ *class = version->class;
+ return TRUE;
+ }
+
+ /* Can not find the supported privilege version. */
+ return FALSE;
+}
+
+/* Get the corresponding privilege version string by giving a CSR
+ version class. */
+
+const char *
+riscv_get_priv_spec_name (enum riscv_priv_spec_class class)
+{
+ /* The first enum is PRIV_SPEC_CLASS_NONE. */
+ return priv_specs[class - 1].name;
+}
--
2.7.4
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [PATCH v2 5/9] RISC-V: Support version checking for CSR according to privilege spec version.
2020-05-06 2:55 ` [PATCH v2 5/9] RISC-V: Support version checking for CSR according to privilege spec version Nelson Chu
@ 2020-05-19 9:08 ` Nelson Chu
0 siblings, 0 replies; 25+ messages in thread
From: Nelson Chu @ 2020-05-19 9:08 UTC (permalink / raw)
To: Binutils, gdb-patches
Cc: Palmer Dabbelt, Kito Cheng, Jim Wilson, Andrew Waterman,
Andrew Burgess, Alex Bradbury, Maxim Blinov
PING :)
On Wed, May 6, 2020 at 10:55 AM Nelson Chu <nelson.chu@sifive.com> wrote:
>
> Support new GAS option -mpriv-spec to choose the privilege spec version, and
> then assembler will generates the correct CSR address. If the obselete CSR
> name is used, then report the warning message when the -mcsr-check is set,
> and use the latest defined address for the CSR (Since we build hash table by
> the DECLARE_CSR first, and then use the DECLARE_CSR_ALIAS). Maybe we can
> insert the CSR hash entries in version's order, then we probably don't need
> the DECLARE_CSR_ALIAS any more.
>
> * -mpriv-spec=[1.9|1.9.1|1.10|1.11]
> This is used to set the privileged spec version, and we can decide whether
> the CSR is valid or not.
>
> gas/
> * config/tc-riscv.c (default_priv_spec): Static variable which is
> used to check if the CSR is valid for the chosen privilege spec. You
> can use -mpriv-spec to set it.
> (enum reg_class): We now get the CSR address from csr_extra_hash rather
> than reg_names_hash. Therefore, move RCLASS_CSR behind RCLASS_MAX.
> (riscv_init_csr_hashes): Only need to initialize one hash table
> csr_extra_hash.
> (riscv_csr_class_check): Change the return type to void. Don't check
> the ISA dependency if -mcsr-check isn't set.
> (riscv_csr_version_check): New function. Check and find the CSR address
> from csr_extra_hash, according to default_priv_spec. Report warning
> for the invalid CSR if -mcsr-check is set.
> (reg_csr_lookup_internal): Updated.
> (reg_lookup_internal): Likewise.
> (md_begin): Updated since DECLARE_CSR and DECLARE_CSR_ALIAS are changed.
> (enum options, struct option md_longopts): Add new GAS option -mpriv-spec.
> (md_parse_option): Call riscv_set_default_priv_version to set
> default_priv_spec.
> (riscv_after_parse_args): If -mpriv-spec isn't set, then set the default
> privilege spec to the newest one.
> (enum riscv_csr_class, struct riscv_csr_extra): Move them to
> include/opcode/riscv.h.
>
> * testsuite/gas/riscv/priv-reg-fail-fext.d: This test case just want
> to check the ISA dependency for CSR, so fix the spec version by adding
> -mpriv-spec=1.11.
> * testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise. There are some
> version warnings for the test case.
> * gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
> * gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
> * gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise.
> * gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
> * gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
> * gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d: New test case.
> Check whether the CSR is valid when privilege version 1.9 is choosed.
> * gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise.
> * gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: New test case.
> Check whether the CSR is valid when privilege version 1.9.1 is choosed.
> * gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
> * gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d: New test case.
> Check whether the CSR is valid when privilege version 1.10 is choosed.
> * gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
> * gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d: New test case.
> Check whether the CSR is valid when privilege version 1.11 is choosed.
> * gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
>
> include/
> * opcode/riscv-opc.h (DECLARE_CSR): There are two version information,
> define_version and abort_version. The define_version means which
> privilege spec is started to define the CSR, and the abort_version
> means which privilege spec is started to abort the CSR. If the CSR is
> valid for the newest spec, then the abort_version should be
> PRIV_SPEC_CLASS_DRAFT.
> (DECLARE_CSR_ALIAS): Same as DECLARE_CSR, but only for the obselete CSR.
>
> * opcode/riscv.h (enum riscv_priv_spec_class): New enum class. Define
> the current supported privilege spec versions.
> (struct riscv_csr_extra): Add new fields to store more information
> about the CSR. We use these information to find the suitable CSR
> address when user choosing a specific privilege spec.
>
> opcodes/
> * riscv-opc.c (struct priv_spec_t): New structure.
> (struct priv_spec_t priv_specs): List for all supported privilege spec
> classes and the corresponding strings.
> (riscv_get_priv_spec_class): New function. Get the corresponding
> privilege spec class by giving a spec string.
> (riscv_get_priv_spec_name): New function. Get the corresponding
> privilege spec string by giving a CSR version class.
> * riscv-dis.c: Updated since DECLARE_CSR is changed.
>
> gdb/
> * riscv-tdep.c: Updated since DECLARE_CSR is changed.
> * riscv-tdep.h: Likewise.
>
> binutils/
> * dwarf.c: Updated since DECLARE_CSR is changed.
> ---
> binutils/dwarf.c | 3 +-
> gas/config/tc-riscv.c | 200 +++++---
> gas/testsuite/gas/riscv/priv-reg-fail-fext.d | 2 +-
> gas/testsuite/gas/riscv/priv-reg-fail-fext.l | 25 +
> .../gas/riscv/priv-reg-fail-read-only-01.d | 2 +-
> .../gas/riscv/priv-reg-fail-read-only-01.l | 25 +
> .../gas/riscv/priv-reg-fail-read-only-02.d | 2 +-
> gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d | 2 +-
> gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l | 25 +
> .../gas/riscv/priv-reg-fail-version-1p10.d | 3 +
> .../gas/riscv/priv-reg-fail-version-1p10.l | 27 ++
> .../gas/riscv/priv-reg-fail-version-1p11.d | 3 +
> .../gas/riscv/priv-reg-fail-version-1p11.l | 25 +
> .../gas/riscv/priv-reg-fail-version-1p9.d | 3 +
> .../gas/riscv/priv-reg-fail-version-1p9.l | 30 ++
> .../gas/riscv/priv-reg-fail-version-1p9p1.d | 3 +
> .../gas/riscv/priv-reg-fail-version-1p9p1.l | 30 ++
> gdb/riscv-tdep.c | 6 +-
> gdb/riscv-tdep.h | 2 +-
> include/opcode/riscv-opc.h | 509 ++++++++++-----------
> include/opcode/riscv.h | 50 ++
> opcodes/riscv-dis.c | 3 +-
> opcodes/riscv-opc.c | 51 +++
> 23 files changed, 700 insertions(+), 331 deletions(-)
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.l
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l
>
> diff --git a/binutils/dwarf.c b/binutils/dwarf.c
> index 7b5f7af..598f856 100644
> --- a/binutils/dwarf.c
> +++ b/binutils/dwarf.c
> @@ -7409,7 +7409,8 @@ regname_internal_riscv (unsigned int regno)
> document. */
> switch (regno)
> {
> -#define DECLARE_CSR(NAME,VALUE,CLASS) case VALUE + 4096: name = #NAME; break;
> +#define DECLARE_CSR(NAME,VALUE,CLASS,DEFINE_VER,ABORT_VER) \
> + case VALUE + 4096: name = #NAME; break;
> #include "opcode/riscv-opc.h"
> #undef DECLARE_CSR
>
> diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
> index 3b6c429..743e4bb 100644
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -82,6 +82,7 @@ struct riscv_cl_insn
> static const char default_arch[] = DEFAULT_ARCH;
> static const char *default_arch_with_ext = DEFAULT_RISCV_ARCH_WITH_EXT;
> static enum riscv_isa_spec_class default_isa_spec = ISA_SPEC_CLASS_NONE;
> +static enum riscv_priv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE;
>
> static unsigned xlen = 0; /* width of an x-register */
> static unsigned abi_xlen = 0; /* width of a pointer in the ABI */
> @@ -553,8 +554,9 @@ enum reg_class
> {
> RCLASS_GPR,
> RCLASS_FPR,
> - RCLASS_CSR,
> - RCLASS_MAX
> + RCLASS_MAX,
> +
> + RCLASS_CSR
> };
>
> static struct hash_control *reg_names_hash = NULL;
> @@ -584,102 +586,163 @@ hash_reg_names (enum reg_class class, const char * const names[], unsigned n)
> hash_reg_name (class, names[i], i);
> }
>
> -/* All RISC-V CSRs belong to one of these classes. */
> -
> -enum riscv_csr_class
> -{
> - CSR_CLASS_NONE,
> +/* Init hash table csr_extra_hash to handle CSR. */
>
> - CSR_CLASS_I,
> - CSR_CLASS_I_32, /* rv32 only */
> - CSR_CLASS_F, /* f-ext only */
> -};
> +static void
> +riscv_init_csr_hash (const char *name,
> + unsigned address,
> + enum riscv_csr_class class,
> + enum riscv_priv_spec_class define_version,
> + enum riscv_priv_spec_class abort_version)
> +{
> + struct riscv_csr_extra *entry, *pre_entry;
> + const char *hash_error = NULL;
> + bfd_boolean need_enrty = TRUE;
> +
> + pre_entry = NULL;
> + entry = (struct riscv_csr_extra *) hash_find (csr_extra_hash, name);
> + while (need_enrty && entry != NULL)
> + {
> + if (entry->csr_class == class
> + && entry->address == address
> + && entry->define_version == define_version
> + && entry->abort_version == abort_version)
> + need_enrty = FALSE;
> + pre_entry = entry;
> + entry = entry->next;
> + }
>
> -/* This structure holds all restricted conditions for a CSR. */
> + /* Duplicate setting for the CSR, just return and do nothing. */
> + if (!need_enrty)
> + return;
>
> -struct riscv_csr_extra
> -{
> - /* Class to which this CSR belongs. Used to decide whether or
> - not this CSR is legal in the current -march context. */
> - enum riscv_csr_class csr_class;
> -};
> + entry = XNEW (struct riscv_csr_extra);
> + entry->csr_class = class;
> + entry->address = address;
> + entry->define_version = define_version;
> + entry->abort_version = abort_version;
> +
> + /* If the CSR hasn't been inserted in the hash table, then insert it.
> + Otherwise, attach the extra information to the entry which is already
> + in the hash table. */
> + if (pre_entry == NULL)
> + {
> + hash_error = hash_insert (csr_extra_hash, name, (void *) entry);
> + if (hash_error != NULL)
> + {
> + fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
> + name, hash_error);
> + /* Probably a memory allocation problem? Give up now. */
> + as_fatal (_("Broken assembler. No assembly attempted."));
> + }
> + }
> + else
> + pre_entry->next = entry;
> +}
>
> -/* Init two hashes, csr_extra_hash and reg_names_hash, for CSR. */
> +/* Check wether the CSR is valid according to the ISA. */
>
> static void
> -riscv_init_csr_hashes (const char *name,
> - unsigned address,
> - enum riscv_csr_class class)
> +riscv_csr_class_check (const char *s,
> + enum riscv_csr_class csr_class)
> {
> - struct riscv_csr_extra *entry = XNEW (struct riscv_csr_extra);
> - entry->csr_class = class;
> + bfd_boolean result = TRUE;
>
> - const char *hash_error =
> - hash_insert (csr_extra_hash, name, (void *) entry);
> - if (hash_error != NULL)
> + /* Don't check the ISA dependency when -mcsr-check isn't set. */
> + if (!riscv_opts.csr_check)
> + return;
> +
> + switch (csr_class)
> {
> - fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
> - name, hash_error);
> - /* Probably a memory allocation problem? Give up now. */
> - as_fatal (_("Broken assembler. No assembly attempted."));
> + case CSR_CLASS_I:
> + result = riscv_subset_supports ("i");
> + break;
> + case CSR_CLASS_F:
> + result = riscv_subset_supports ("f");
> + break;
> + case CSR_CLASS_I_32:
> + result = (xlen == 32 && riscv_subset_supports ("i"));
> + break;
> + default:
> + as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class);
> }
> -
> - hash_reg_name (RCLASS_CSR, name, address);
> + if (!result)
> + as_warn (_("Invalid CSR `%s' for the current ISA"), s);
> }
>
> -/* Check wether the CSR is valid according to the ISA. */
> +/* Check and find the CSR address according to the privilege spec version. */
>
> -static bfd_boolean
> -riscv_csr_class_check (enum riscv_csr_class csr_class)
> +static void
> +riscv_csr_version_check (const char *csr_name,
> + struct riscv_csr_extra **entryP)
> {
> - switch (csr_class)
> + struct riscv_csr_extra *entry = *entryP;
> + while (entry != NULL)
> {
> - case CSR_CLASS_I: return riscv_subset_supports ("i");
> - case CSR_CLASS_F: return riscv_subset_supports ("f");
> - case CSR_CLASS_I_32:
> - return (xlen == 32 && riscv_subset_supports ("i"));
> + if (default_priv_spec >= entry->define_version
> + && default_priv_spec < entry->abort_version)
> + {
> + /* Find the suitable CSR according to the specific version. */
> + *entryP = entry;
> + return;
> + }
> + entry = entry->next;
> + }
>
> - default:
> - return FALSE;
> + /* We can not find the suitable CSR address according to the privilege
> + version. Therefore, we use the last defined value. Report the warning
> + only when the -mcsr-check is set. Enable the -mcsr-check is recommended,
> + otherwise, you may get the unexpected CSR address. */
> + if (riscv_opts.csr_check)
> + {
> + const char *priv_name = riscv_get_priv_spec_name (default_priv_spec);
> + if (priv_name != NULL)
> + as_warn (_("Invalid CSR `%s' for the privilege spec `%s'"),
> + csr_name, priv_name);
> }
> }
>
> -/* If the CSR is defined, then we call `riscv_csr_class_check` to do the
> - further checking. Return FALSE if the CSR is not defined. Otherwise,
> - return TRUE. */
> +/* Once the CSR is defined, including the old privilege spec, then we call
> + riscv_csr_class_check and riscv_csr_version_check to do the further checking
> + and get the corresponding address. Return -1 if the CSR is never been
> + defined. Otherwise, return the address. */
>
> -static bfd_boolean
> +static unsigned int
> reg_csr_lookup_internal (const char *s)
> {
> struct riscv_csr_extra *r =
> (struct riscv_csr_extra *) hash_find (csr_extra_hash, s);
>
> if (r == NULL)
> - return FALSE;
> + return -1;
>
> - /* We just report the warning when the CSR is invalid. */
> - if (!riscv_csr_class_check (r->csr_class))
> - as_warn (_("Invalid CSR `%s' for the current ISA"), s);
> + /* We just report the warning when the CSR is invalid. "Invalid CSR" means
> + the CSR was defined, but isn't allowed for the current ISA setting or
> + the privilege spec. If the CSR is never been defined, then assembler
> + will regard it as a "Unknown CSR" and report error. If user use number
> + to set the CSR, but over the range (> 0xfff), then assembler will report
> + "Improper CSR" error for it. */
> + riscv_csr_class_check (s, r->csr_class);
> + riscv_csr_version_check (s, &r);
>
> - return TRUE;
> + return r->address;
> }
>
> static unsigned int
> reg_lookup_internal (const char *s, enum reg_class class)
> {
> - void *r = hash_find (reg_names_hash, s);
> + void *r;
> +
> + if (class == RCLASS_CSR)
> + return reg_csr_lookup_internal (s);
>
> + r = hash_find (reg_names_hash, s);
> if (r == NULL || DECODE_REG_CLASS (r) != class)
> return -1;
>
> if (riscv_opts.rve && class == RCLASS_GPR && DECODE_REG_NUM (r) > 15)
> return -1;
>
> - if (class == RCLASS_CSR
> - && riscv_opts.csr_check
> - && !reg_csr_lookup_internal (s))
> - return -1;
> -
> return DECODE_REG_NUM (r);
> }
>
> @@ -963,8 +1026,10 @@ md_begin (void)
>
> /* Create and insert CSR hash tables. */
> csr_extra_hash = hash_new ();
> -#define DECLARE_CSR(name, num, class) riscv_init_csr_hashes (#name, num, class);
> -#define DECLARE_CSR_ALIAS(name, num, class) DECLARE_CSR(name, num, class);
> +#define DECLARE_CSR(name, num, class, define_version, abort_version) \
> + riscv_init_csr_hash (#name, num, class, define_version, abort_version);
> +#define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
> + DECLARE_CSR(name, num, class, define_version, abort_version);
> #include "opcode/riscv-opc.h"
> #undef DECLARE_CSR
>
> @@ -2450,6 +2515,7 @@ enum options
> OPTION_CSR_CHECK,
> OPTION_NO_CSR_CHECK,
> OPTION_MISA_SPEC,
> + OPTION_MPRIV_SPEC,
> OPTION_END_OF_ENUM
> };
>
> @@ -2467,6 +2533,7 @@ struct option md_longopts[] =
> {"mcsr-check", no_argument, NULL, OPTION_CSR_CHECK},
> {"mno-csr-check", no_argument, NULL, OPTION_NO_CSR_CHECK},
> {"misa-spec", required_argument, NULL, OPTION_MISA_SPEC},
> + {"mpriv-spec", required_argument, NULL, OPTION_MPRIV_SPEC},
>
> {NULL, no_argument, NULL, 0}
> };
> @@ -2558,6 +2625,15 @@ md_parse_option (int c, const char *arg)
> case OPTION_MISA_SPEC:
> return riscv_set_default_isa_spec (arg);
>
> + case OPTION_MPRIV_SPEC:
> + if (!riscv_get_priv_spec_class (arg, &default_priv_spec))
> + {
> + as_bad ("Unknown default privilege spec `%s' set by "
> + "-mpriv-spec", arg);
> + return 0;
> + }
> + break;
> +
> default:
> return 0;
> }
> @@ -2605,6 +2681,10 @@ riscv_after_parse_args (void)
> if (riscv_subset_supports ("e"))
> riscv_set_rve (TRUE);
>
> + /* Set the default privilege spec to the newest one. */
> + if (default_priv_spec == PRIV_SPEC_CLASS_NONE)
> + default_priv_spec = PRIV_SPEC_CLASS_1P11;
> +
> /* Infer ABI from ISA if not specified on command line. */
> if (abi_xlen == 0)
> abi_xlen = xlen;
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-fext.d b/gas/testsuite/gas/riscv/priv-reg-fail-fext.d
> index da53566..d9939eb 100644
> --- a/gas/testsuite/gas/riscv/priv-reg-fail-fext.d
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-fext.d
> @@ -1,3 +1,3 @@
> -#as: -march=rv32i -mcsr-check
> +#as: -march=rv32i -mcsr-check -mpriv-spec=1.11
> #source: priv-reg.s
> #warning_output: priv-reg-fail-fext.l
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-fext.l b/gas/testsuite/gas/riscv/priv-reg-fail-fext.l
> index 76818c8..d74863e 100644
> --- a/gas/testsuite/gas/riscv/priv-reg-fail-fext.l
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-fext.l
> @@ -2,3 +2,28 @@
> .*Warning: Invalid CSR `fflags' for the current ISA
> .*Warning: Invalid CSR `frm' for the current ISA
> .*Warning: Invalid CSR `fcsr' for the current ISA
> +
> +.*Warning: Invalid CSR `ubadaddr' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `sbadaddr' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `sptbr' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `mbadaddr' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `mucounteren' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `dscratch' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `hstatus' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `hedeleg' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `hideleg' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `hie' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `htvec' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `hscratch' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `hepc' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `hcause' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `hbadaddr' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `hip' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `mbase' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `mbound' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `mibase' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `mibound' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `mdbase' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `mdbound' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `mscounteren' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `mhcounteren' for the privilege spec `1.11'
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d
> index ae190c0..b0f6726 100644
> --- a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d
> @@ -1,3 +1,3 @@
> -#as: -march=rv32if -mcsr-check
> +#as: -march=rv32if -mcsr-check -mpriv-spec=1.11
> #source: priv-reg-fail-read-only-01.s
> #warning_output: priv-reg-fail-read-only-01.l
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l
> index 7e52bd7..2dc82f4 100644
> --- a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l
> @@ -67,3 +67,28 @@
> .*Warning: Read-only CSR is written `csrw marchid,a1'
> .*Warning: Read-only CSR is written `csrw mimpid,a1'
> .*Warning: Read-only CSR is written `csrw mhartid,a1'
> +
> +.*Warning: Invalid CSR `ubadaddr' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `sbadaddr' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `sptbr' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `mbadaddr' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `mucounteren' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `dscratch' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `hstatus' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `hedeleg' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `hideleg' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `hie' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `htvec' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `hscratch' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `hepc' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `hcause' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `hbadaddr' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `hip' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `mbase' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `mbound' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `mibase' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `mibound' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `mdbase' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `mdbound' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `mscounteren' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `mhcounteren' for the privilege spec `1.11'
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d
> index 3c4715f..ec206e4 100644
> --- a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d
> @@ -1,3 +1,3 @@
> -#as: -march=rv32if -mcsr-check
> +#as: -march=rv32if -mcsr-check -mpriv-spec=1.11
> #source: priv-reg-fail-read-only-02.s
> #warning_output: priv-reg-fail-read-only-02.l
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d
> index d71b261..eced438 100644
> --- a/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d
> @@ -1,3 +1,3 @@
> -#as: -march=rv64if -mcsr-check
> +#as: -march=rv64if -mcsr-check -mpriv-spec=1.11
> #source: priv-reg.s
> #warning_output: priv-reg-fail-rv32-only.l
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l
> index fa5a1b4..19f13a0 100644
> --- a/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l
> @@ -64,3 +64,28 @@
> .*Warning: Invalid CSR `mhpmcounter29h' for the current ISA
> .*Warning: Invalid CSR `mhpmcounter30h' for the current ISA
> .*Warning: Invalid CSR `mhpmcounter31h' for the current ISA
> +
> +.*Warning: Invalid CSR `ubadaddr' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `sbadaddr' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `sptbr' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `mbadaddr' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `mucounteren' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `dscratch' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `hstatus' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `hedeleg' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `hideleg' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `hie' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `htvec' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `hscratch' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `hepc' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `hcause' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `hbadaddr' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `hip' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `mbase' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `mbound' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `mibase' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `mibound' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `mdbase' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `mdbound' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `mscounteren' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `mhcounteren' for the privilege spec `1.11'
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d
> new file mode 100644
> index 0000000..8dc2a10
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32if -mcsr-check -mpriv-spec=1.10
> +#source: priv-reg.s
> +#warning_output: priv-reg-fail-version-1p10.l
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l
> new file mode 100644
> index 0000000..4146174
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l
> @@ -0,0 +1,27 @@
> +.*Assembler messages:
> +.*Warning: Invalid CSR `mcountinhibit' for the privilege spec `1.10'
> +.*Warning: Invalid CSR `dscratch0' for the privilege spec `1.10'
> +.*Warning: Invalid CSR `dscratch1' for the privilege spec `1.10'
> +.*Warning: Invalid CSR `ubadaddr' for the privilege spec `1.10'
> +.*Warning: Invalid CSR `sbadaddr' for the privilege spec `1.10'
> +.*Warning: Invalid CSR `sptbr' for the privilege spec `1.10'
> +.*Warning: Invalid CSR `mbadaddr' for the privilege spec `1.10'
> +.*Warning: Invalid CSR `mucounteren' for the privilege spec `1.10'
> +.*Warning: Invalid CSR `hstatus' for the privilege spec `1.10'
> +.*Warning: Invalid CSR `hedeleg' for the privilege spec `1.10'
> +.*Warning: Invalid CSR `hideleg' for the privilege spec `1.10'
> +.*Warning: Invalid CSR `hie' for the privilege spec `1.10'
> +.*Warning: Invalid CSR `htvec' for the privilege spec `1.10'
> +.*Warning: Invalid CSR `hscratch' for the privilege spec `1.10'
> +.*Warning: Invalid CSR `hepc' for the privilege spec `1.10'
> +.*Warning: Invalid CSR `hcause' for the privilege spec `1.10'
> +.*Warning: Invalid CSR `hbadaddr' for the privilege spec `1.10'
> +.*Warning: Invalid CSR `hip' for the privilege spec `1.10'
> +.*Warning: Invalid CSR `mbase' for the privilege spec `1.10'
> +.*Warning: Invalid CSR `mbound' for the privilege spec `1.10'
> +.*Warning: Invalid CSR `mibase' for the privilege spec `1.10'
> +.*Warning: Invalid CSR `mibound' for the privilege spec `1.10'
> +.*Warning: Invalid CSR `mdbase' for the privilege spec `1.10'
> +.*Warning: Invalid CSR `mdbound' for the privilege spec `1.10'
> +.*Warning: Invalid CSR `mscounteren' for the privilege spec `1.10'
> +.*Warning: Invalid CSR `mhcounteren' for the privilege spec `1.10'
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d
> new file mode 100644
> index 0000000..7d2406c
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32if -mcsr-check -mpriv-spec=1.11
> +#source: priv-reg.s
> +#warning_output: priv-reg-fail-version-1p11.l
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l
> new file mode 100644
> index 0000000..eadcb5c
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l
> @@ -0,0 +1,25 @@
> +.*Assembler messages:
> +.*Warning: Invalid CSR `ubadaddr' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `sbadaddr' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `sptbr' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `mbadaddr' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `mucounteren' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `dscratch' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `hstatus' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `hedeleg' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `hideleg' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `hie' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `htvec' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `hscratch' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `hepc' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `hcause' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `hbadaddr' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `hip' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `mbase' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `mbound' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `mibase' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `mibound' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `mdbase' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `mdbound' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `mscounteren' for the privilege spec `1.11'
> +.*Warning: Invalid CSR `mhcounteren' for the privilege spec `1.11'
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d
> new file mode 100644
> index 0000000..a2db291
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32if -mcsr-check -mpriv-spec=1.9
> +#source: priv-reg.s
> +#warning_output: priv-reg-fail-version-1p9.l
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.l b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.l
> new file mode 100644
> index 0000000..d7cee80
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.l
> @@ -0,0 +1,30 @@
> +.*Assembler messages:
> +.*Warning: Invalid CSR `utval' for the privilege spec `1.9'
> +.*Warning: Invalid CSR `scounteren' for the privilege spec `1.9'
> +.*Warning: Invalid CSR `stval' for the privilege spec `1.9'
> +.*Warning: Invalid CSR `satp' for the privilege spec `1.9'
> +.*Warning: Invalid CSR `mcounteren' for the privilege spec `1.9'
> +.*Warning: Invalid CSR `mtval' for the privilege spec `1.9'
> +.*Warning: Invalid CSR `pmpcfg0' for the privilege spec `1.9'
> +.*Warning: Invalid CSR `pmpcfg1' for the privilege spec `1.9'
> +.*Warning: Invalid CSR `pmpcfg2' for the privilege spec `1.9'
> +.*Warning: Invalid CSR `pmpcfg3' for the privilege spec `1.9'
> +.*Warning: Invalid CSR `pmpaddr0' for the privilege spec `1.9'
> +.*Warning: Invalid CSR `pmpaddr1' for the privilege spec `1.9'
> +.*Warning: Invalid CSR `pmpaddr2' for the privilege spec `1.9'
> +.*Warning: Invalid CSR `pmpaddr3' for the privilege spec `1.9'
> +.*Warning: Invalid CSR `pmpaddr4' for the privilege spec `1.9'
> +.*Warning: Invalid CSR `pmpaddr5' for the privilege spec `1.9'
> +.*Warning: Invalid CSR `pmpaddr6' for the privilege spec `1.9'
> +.*Warning: Invalid CSR `pmpaddr7' for the privilege spec `1.9'
> +.*Warning: Invalid CSR `pmpaddr8' for the privilege spec `1.9'
> +.*Warning: Invalid CSR `pmpaddr9' for the privilege spec `1.9'
> +.*Warning: Invalid CSR `pmpaddr10' for the privilege spec `1.9'
> +.*Warning: Invalid CSR `pmpaddr11' for the privilege spec `1.9'
> +.*Warning: Invalid CSR `pmpaddr12' for the privilege spec `1.9'
> +.*Warning: Invalid CSR `pmpaddr13' for the privilege spec `1.9'
> +.*Warning: Invalid CSR `pmpaddr14' for the privilege spec `1.9'
> +.*Warning: Invalid CSR `pmpaddr15' for the privilege spec `1.9'
> +.*Warning: Invalid CSR `mcountinhibit' for the privilege spec `1.9'
> +.*Warning: Invalid CSR `dscratch0' for the privilege spec `1.9'
> +.*Warning: Invalid CSR `dscratch1' for the privilege spec `1.9'
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d
> new file mode 100644
> index 0000000..e870cf5
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32if -mcsr-check -mpriv-spec=1.9.1
> +#source: priv-reg.s
> +#warning_output: priv-reg-fail-version-1p9p1.l
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l
> new file mode 100644
> index 0000000..907ed73
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l
> @@ -0,0 +1,30 @@
> +.*Assembler messages:
> +.*Warning: Invalid CSR `utval' for the privilege spec `1.9.1'
> +.*Warning: Invalid CSR `scounteren' for the privilege spec `1.9.1'
> +.*Warning: Invalid CSR `stval' for the privilege spec `1.9.1'
> +.*Warning: Invalid CSR `satp' for the privilege spec `1.9.1'
> +.*Warning: Invalid CSR `mcounteren' for the privilege spec `1.9.1'
> +.*Warning: Invalid CSR `mtval' for the privilege spec `1.9.1'
> +.*Warning: Invalid CSR `pmpcfg0' for the privilege spec `1.9.1'
> +.*Warning: Invalid CSR `pmpcfg1' for the privilege spec `1.9.1'
> +.*Warning: Invalid CSR `pmpcfg2' for the privilege spec `1.9.1'
> +.*Warning: Invalid CSR `pmpcfg3' for the privilege spec `1.9.1'
> +.*Warning: Invalid CSR `pmpaddr0' for the privilege spec `1.9.1'
> +.*Warning: Invalid CSR `pmpaddr1' for the privilege spec `1.9.1'
> +.*Warning: Invalid CSR `pmpaddr2' for the privilege spec `1.9.1'
> +.*Warning: Invalid CSR `pmpaddr3' for the privilege spec `1.9.1'
> +.*Warning: Invalid CSR `pmpaddr4' for the privilege spec `1.9.1'
> +.*Warning: Invalid CSR `pmpaddr5' for the privilege spec `1.9.1'
> +.*Warning: Invalid CSR `pmpaddr6' for the privilege spec `1.9.1'
> +.*Warning: Invalid CSR `pmpaddr7' for the privilege spec `1.9.1'
> +.*Warning: Invalid CSR `pmpaddr8' for the privilege spec `1.9.1'
> +.*Warning: Invalid CSR `pmpaddr9' for the privilege spec `1.9.1'
> +.*Warning: Invalid CSR `pmpaddr10' for the privilege spec `1.9.1'
> +.*Warning: Invalid CSR `pmpaddr11' for the privilege spec `1.9.1'
> +.*Warning: Invalid CSR `pmpaddr12' for the privilege spec `1.9.1'
> +.*Warning: Invalid CSR `pmpaddr13' for the privilege spec `1.9.1'
> +.*Warning: Invalid CSR `pmpaddr14' for the privilege spec `1.9.1'
> +.*Warning: Invalid CSR `pmpaddr15' for the privilege spec `1.9.1'
> +.*Warning: Invalid CSR `mcountinhibit' for the privilege spec `1.9.1'
> +.*Warning: Invalid CSR `dscratch0' for the privilege spec `1.9.1'
> +.*Warning: Invalid CSR `dscratch1' for the privilege spec `1.9.1'
> diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
> index 1bb824e..e67f661 100644
> --- a/gdb/riscv-tdep.c
> +++ b/gdb/riscv-tdep.c
> @@ -240,7 +240,7 @@ static struct riscv_register_feature riscv_csr_feature =
> {
> "org.gnu.gdb.riscv.csr",
> {
> -#define DECLARE_CSR(NAME,VALUE,CLASS) \
> +#define DECLARE_CSR(NAME,VALUE,CLASS,DEFINE_VER,ABORT_VER) \
> { RISCV_ ## VALUE ## _REGNUM, { # NAME }, false },
> #include "opcode/riscv-opc.h"
> #undef DECLARE_CSR
> @@ -498,7 +498,7 @@ riscv_register_name (struct gdbarch *gdbarch, int regnum)
>
> if (regnum >= RISCV_FIRST_CSR_REGNUM && regnum <= RISCV_LAST_CSR_REGNUM)
> {
> -#define DECLARE_CSR(NAME,VALUE,CLASS) \
> +#define DECLARE_CSR(NAME,VALUE,CLASS,DEFINE_VER,ABORT_VER) \
> case RISCV_ ## VALUE ## _REGNUM: return # NAME;
>
> switch (regnum)
> @@ -828,7 +828,7 @@ riscv_is_regnum_a_named_csr (int regnum)
>
> switch (regnum)
> {
> -#define DECLARE_CSR(name, num, class) case RISCV_ ## num ## _REGNUM:
> +#define DECLARE_CSR(name, num, class, define_ver, abort_ver) case RISCV_ ## num ## _REGNUM:
> #include "opcode/riscv-opc.h"
> #undef DECLARE_CSR
> return true;
> diff --git a/gdb/riscv-tdep.h b/gdb/riscv-tdep.h
> index 90bae08..e415fb4 100644
> --- a/gdb/riscv-tdep.h
> +++ b/gdb/riscv-tdep.h
> @@ -44,7 +44,7 @@ enum
> RISCV_LAST_FP_REGNUM = 64, /* Last Floating Point Register */
>
> RISCV_FIRST_CSR_REGNUM = 65, /* First CSR */
> -#define DECLARE_CSR(name, num, class) \
> +#define DECLARE_CSR(name, num, class, define_version, abort_version) \
> RISCV_ ## num ## _REGNUM = RISCV_FIRST_CSR_REGNUM + num,
> #include "opcode/riscv-opc.h"
> #undef DECLARE_CSR
> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> index fe00bb6..a6a5de3 100644
> --- a/include/opcode/riscv-opc.h
> +++ b/include/opcode/riscv-opc.h
> @@ -656,7 +656,6 @@
> #define CSR_SIDELEG 0x103
> #define CSR_SIE 0x104
> #define CSR_STVEC 0x105
> -/* scounteren is present int priv spec 1.10. */
> #define CSR_SCOUNTEREN 0x106
> #define CSR_SSCRATCH 0x140
> #define CSR_SEPC 0x141
> @@ -669,20 +668,17 @@
> #define CSR_MIMPID 0xf13
> #define CSR_MHARTID 0xf14
> #define CSR_MSTATUS 0x300
> -/* misa is 0xf10 in 1.9, but 0x301 in 1.9.1. */
> #define CSR_MISA 0x301
> #define CSR_MEDELEG 0x302
> #define CSR_MIDELEG 0x303
> #define CSR_MIE 0x304
> #define CSR_MTVEC 0x305
> -/* mcounteren is present in priv spec 1.10. */
> #define CSR_MCOUNTEREN 0x306
> #define CSR_MSCRATCH 0x340
> #define CSR_MEPC 0x341
> #define CSR_MCAUSE 0x342
> #define CSR_MTVAL 0x343
> #define CSR_MIP 0x344
> -/* pmpcfg0 to pmpcfg3, pmpaddr0 to pmpaddr15 are present in priv spec 1.10. */
> #define CSR_PMPCFG0 0x3a0
> #define CSR_PMPCFG1 0x3a1
> #define CSR_PMPCFG2 0x3a2
> @@ -765,7 +761,6 @@
> #define CSR_MHPMCOUNTER29H 0xb9d
> #define CSR_MHPMCOUNTER30H 0xb9e
> #define CSR_MHPMCOUNTER31H 0xb9f
> -/* mcountinhibit is present in priv spec 1.11. */
> #define CSR_MCOUNTINHIBIT 0x320
> #define CSR_MHPMEVENT3 0x323
> #define CSR_MHPMEVENT4 0x324
> @@ -802,10 +797,8 @@
> #define CSR_TDATA3 0x7a3
> #define CSR_DCSR 0x7b0
> #define CSR_DPC 0x7b1
> -/* dscratch0 and dscratch1 are present in priv spec 1.11. */
> #define CSR_DSCRATCH0 0x7b2
> #define CSR_DSCRATCH1 0x7b3
> -/* These registers are present in priv spec 1.9.1, but are dropped in 1.10. */
> #define CSR_HSTATUS 0x200
> #define CSR_HEDELEG 0x202
> #define CSR_HIDELEG 0x203
> @@ -1124,262 +1117,256 @@ DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
> DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
> #endif
> #ifdef DECLARE_CSR
> -DECLARE_CSR(ustatus, CSR_USTATUS, CSR_CLASS_I)
> -DECLARE_CSR(uie, CSR_UIE, CSR_CLASS_I)
> -DECLARE_CSR(utvec, CSR_UTVEC, CSR_CLASS_I)
> -DECLARE_CSR(uscratch, CSR_USCRATCH, CSR_CLASS_I)
> -DECLARE_CSR(uepc, CSR_UEPC, CSR_CLASS_I)
> -DECLARE_CSR(ucause, CSR_UCAUSE, CSR_CLASS_I)
> -DECLARE_CSR(utval, CSR_UTVAL, CSR_CLASS_I)
> -DECLARE_CSR(uip, CSR_UIP, CSR_CLASS_I)
> -DECLARE_CSR(fflags, CSR_FFLAGS, CSR_CLASS_F)
> -DECLARE_CSR(frm, CSR_FRM, CSR_CLASS_F)
> -DECLARE_CSR(fcsr, CSR_FCSR, CSR_CLASS_F)
> -DECLARE_CSR(cycle, CSR_CYCLE, CSR_CLASS_I)
> -DECLARE_CSR(time, CSR_TIME, CSR_CLASS_I)
> -DECLARE_CSR(instret, CSR_INSTRET, CSR_CLASS_I)
> -DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3, CSR_CLASS_I)
> -DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4, CSR_CLASS_I)
> -DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5, CSR_CLASS_I)
> -DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6, CSR_CLASS_I)
> -DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7, CSR_CLASS_I)
> -DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8, CSR_CLASS_I)
> -DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9, CSR_CLASS_I)
> -DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10, CSR_CLASS_I)
> -DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11, CSR_CLASS_I)
> -DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12, CSR_CLASS_I)
> -DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13, CSR_CLASS_I)
> -DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14, CSR_CLASS_I)
> -DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15, CSR_CLASS_I)
> -DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16, CSR_CLASS_I)
> -DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17, CSR_CLASS_I)
> -DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18, CSR_CLASS_I)
> -DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19, CSR_CLASS_I)
> -DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20, CSR_CLASS_I)
> -DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21, CSR_CLASS_I)
> -DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22, CSR_CLASS_I)
> -DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23, CSR_CLASS_I)
> -DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24, CSR_CLASS_I)
> -DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25, CSR_CLASS_I)
> -DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26, CSR_CLASS_I)
> -DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27, CSR_CLASS_I)
> -DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28, CSR_CLASS_I)
> -DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29, CSR_CLASS_I)
> -DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30, CSR_CLASS_I)
> -DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31, CSR_CLASS_I)
> -DECLARE_CSR(cycleh, CSR_CYCLEH, CSR_CLASS_I_32)
> -DECLARE_CSR(timeh, CSR_TIMEH, CSR_CLASS_I_32)
> -DECLARE_CSR(instreth, CSR_INSTRETH, CSR_CLASS_I_32)
> -DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H, CSR_CLASS_I_32)
> -DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H, CSR_CLASS_I_32)
> -DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H, CSR_CLASS_I_32)
> -DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H, CSR_CLASS_I_32)
> -DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H, CSR_CLASS_I_32)
> -DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H, CSR_CLASS_I_32)
> -DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H, CSR_CLASS_I_32)
> -DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H, CSR_CLASS_I_32)
> -DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H, CSR_CLASS_I_32)
> -DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H, CSR_CLASS_I_32)
> -DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H, CSR_CLASS_I_32)
> -DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H, CSR_CLASS_I_32)
> -DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H, CSR_CLASS_I_32)
> -DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H, CSR_CLASS_I_32)
> -DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H, CSR_CLASS_I_32)
> -DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H, CSR_CLASS_I_32)
> -DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H, CSR_CLASS_I_32)
> -DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H, CSR_CLASS_I_32)
> -DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H, CSR_CLASS_I_32)
> -DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H, CSR_CLASS_I_32)
> -DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H, CSR_CLASS_I_32)
> -DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H, CSR_CLASS_I_32)
> -DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H, CSR_CLASS_I_32)
> -DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H, CSR_CLASS_I_32)
> -DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H, CSR_CLASS_I_32)
> -DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H, CSR_CLASS_I_32)
> -DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H, CSR_CLASS_I_32)
> -DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H, CSR_CLASS_I_32)
> -DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H, CSR_CLASS_I_32)
> -DECLARE_CSR(sstatus, CSR_SSTATUS, CSR_CLASS_I)
> -DECLARE_CSR(sedeleg, CSR_SEDELEG, CSR_CLASS_I)
> -DECLARE_CSR(sideleg, CSR_SIDELEG, CSR_CLASS_I)
> -DECLARE_CSR(sie, CSR_SIE, CSR_CLASS_I)
> -DECLARE_CSR(stvec, CSR_STVEC, CSR_CLASS_I)
> -DECLARE_CSR(scounteren, CSR_SCOUNTEREN, CSR_CLASS_I)
> -DECLARE_CSR(sscratch, CSR_SSCRATCH, CSR_CLASS_I)
> -DECLARE_CSR(sepc, CSR_SEPC, CSR_CLASS_I)
> -DECLARE_CSR(scause, CSR_SCAUSE, CSR_CLASS_I)
> -DECLARE_CSR(stval, CSR_STVAL, CSR_CLASS_I)
> -DECLARE_CSR(sip, CSR_SIP, CSR_CLASS_I)
> -DECLARE_CSR(satp, CSR_SATP, CSR_CLASS_I)
> -DECLARE_CSR(mvendorid, CSR_MVENDORID, CSR_CLASS_I)
> -DECLARE_CSR(marchid, CSR_MARCHID, CSR_CLASS_I)
> -DECLARE_CSR(mimpid, CSR_MIMPID, CSR_CLASS_I)
> -DECLARE_CSR(mhartid, CSR_MHARTID, CSR_CLASS_I)
> -DECLARE_CSR(mstatus, CSR_MSTATUS, CSR_CLASS_I)
> -DECLARE_CSR(misa, CSR_MISA, CSR_CLASS_I)
> -DECLARE_CSR(medeleg, CSR_MEDELEG, CSR_CLASS_I)
> -DECLARE_CSR(mideleg, CSR_MIDELEG, CSR_CLASS_I)
> -DECLARE_CSR(mie, CSR_MIE, CSR_CLASS_I)
> -DECLARE_CSR(mtvec, CSR_MTVEC, CSR_CLASS_I)
> -DECLARE_CSR(mcounteren, CSR_MCOUNTEREN, CSR_CLASS_I)
> -DECLARE_CSR(mscratch, CSR_MSCRATCH, CSR_CLASS_I)
> -DECLARE_CSR(mepc, CSR_MEPC, CSR_CLASS_I)
> -DECLARE_CSR(mcause, CSR_MCAUSE, CSR_CLASS_I)
> -DECLARE_CSR(mtval, CSR_MTVAL, CSR_CLASS_I)
> -DECLARE_CSR(mip, CSR_MIP, CSR_CLASS_I)
> -DECLARE_CSR(pmpcfg0, CSR_PMPCFG0, CSR_CLASS_I)
> -DECLARE_CSR(pmpcfg1, CSR_PMPCFG1, CSR_CLASS_I_32)
> -DECLARE_CSR(pmpcfg2, CSR_PMPCFG2, CSR_CLASS_I)
> -DECLARE_CSR(pmpcfg3, CSR_PMPCFG3, CSR_CLASS_I_32)
> -DECLARE_CSR(pmpaddr0, CSR_PMPADDR0, CSR_CLASS_I)
> -DECLARE_CSR(pmpaddr1, CSR_PMPADDR1, CSR_CLASS_I)
> -DECLARE_CSR(pmpaddr2, CSR_PMPADDR2, CSR_CLASS_I)
> -DECLARE_CSR(pmpaddr3, CSR_PMPADDR3, CSR_CLASS_I)
> -DECLARE_CSR(pmpaddr4, CSR_PMPADDR4, CSR_CLASS_I)
> -DECLARE_CSR(pmpaddr5, CSR_PMPADDR5, CSR_CLASS_I)
> -DECLARE_CSR(pmpaddr6, CSR_PMPADDR6, CSR_CLASS_I)
> -DECLARE_CSR(pmpaddr7, CSR_PMPADDR7, CSR_CLASS_I)
> -DECLARE_CSR(pmpaddr8, CSR_PMPADDR8, CSR_CLASS_I)
> -DECLARE_CSR(pmpaddr9, CSR_PMPADDR9, CSR_CLASS_I)
> -DECLARE_CSR(pmpaddr10, CSR_PMPADDR10, CSR_CLASS_I)
> -DECLARE_CSR(pmpaddr11, CSR_PMPADDR11, CSR_CLASS_I)
> -DECLARE_CSR(pmpaddr12, CSR_PMPADDR12, CSR_CLASS_I)
> -DECLARE_CSR(pmpaddr13, CSR_PMPADDR13, CSR_CLASS_I)
> -DECLARE_CSR(pmpaddr14, CSR_PMPADDR14, CSR_CLASS_I)
> -DECLARE_CSR(pmpaddr15, CSR_PMPADDR15, CSR_CLASS_I)
> -DECLARE_CSR(mcycle, CSR_MCYCLE, CSR_CLASS_I)
> -DECLARE_CSR(minstret, CSR_MINSTRET, CSR_CLASS_I)
> -DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3, CSR_CLASS_I)
> -DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4, CSR_CLASS_I)
> -DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5, CSR_CLASS_I)
> -DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6, CSR_CLASS_I)
> -DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7, CSR_CLASS_I)
> -DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8, CSR_CLASS_I)
> -DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9, CSR_CLASS_I)
> -DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10, CSR_CLASS_I)
> -DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11, CSR_CLASS_I)
> -DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12, CSR_CLASS_I)
> -DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13, CSR_CLASS_I)
> -DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14, CSR_CLASS_I)
> -DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15, CSR_CLASS_I)
> -DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16, CSR_CLASS_I)
> -DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17, CSR_CLASS_I)
> -DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18, CSR_CLASS_I)
> -DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19, CSR_CLASS_I)
> -DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20, CSR_CLASS_I)
> -DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21, CSR_CLASS_I)
> -DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22, CSR_CLASS_I)
> -DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23, CSR_CLASS_I)
> -DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24, CSR_CLASS_I)
> -DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25, CSR_CLASS_I)
> -DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26, CSR_CLASS_I)
> -DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27, CSR_CLASS_I)
> -DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28, CSR_CLASS_I)
> -DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29, CSR_CLASS_I)
> -DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30, CSR_CLASS_I)
> -DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31, CSR_CLASS_I)
> -DECLARE_CSR(mcycleh, CSR_MCYCLEH, CSR_CLASS_I_32)
> -DECLARE_CSR(minstreth, CSR_MINSTRETH, CSR_CLASS_I_32)
> -DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H, CSR_CLASS_I_32)
> -DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H, CSR_CLASS_I_32)
> -DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H, CSR_CLASS_I_32)
> -DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H, CSR_CLASS_I_32)
> -DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H, CSR_CLASS_I_32)
> -DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H, CSR_CLASS_I_32)
> -DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H, CSR_CLASS_I_32)
> -DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H, CSR_CLASS_I_32)
> -DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H, CSR_CLASS_I_32)
> -DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H, CSR_CLASS_I_32)
> -DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H, CSR_CLASS_I_32)
> -DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H, CSR_CLASS_I_32)
> -DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H, CSR_CLASS_I_32)
> -DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H, CSR_CLASS_I_32)
> -DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H, CSR_CLASS_I_32)
> -DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H, CSR_CLASS_I_32)
> -DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H, CSR_CLASS_I_32)
> -DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H, CSR_CLASS_I_32)
> -DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H, CSR_CLASS_I_32)
> -DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H, CSR_CLASS_I_32)
> -DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H, CSR_CLASS_I_32)
> -DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H, CSR_CLASS_I_32)
> -DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H, CSR_CLASS_I_32)
> -DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H, CSR_CLASS_I_32)
> -DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H, CSR_CLASS_I_32)
> -DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H, CSR_CLASS_I_32)
> -DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H, CSR_CLASS_I_32)
> -DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H, CSR_CLASS_I_32)
> -DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H, CSR_CLASS_I_32)
> -DECLARE_CSR(mcountinhibit, CSR_MCOUNTINHIBIT, CSR_CLASS_I)
> -DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3, CSR_CLASS_I)
> -DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4, CSR_CLASS_I)
> -DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5, CSR_CLASS_I)
> -DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6, CSR_CLASS_I)
> -DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7, CSR_CLASS_I)
> -DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8, CSR_CLASS_I)
> -DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9, CSR_CLASS_I)
> -DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10, CSR_CLASS_I)
> -DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11, CSR_CLASS_I)
> -DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12, CSR_CLASS_I)
> -DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13, CSR_CLASS_I)
> -DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14, CSR_CLASS_I)
> -DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15, CSR_CLASS_I)
> -DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16, CSR_CLASS_I)
> -DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17, CSR_CLASS_I)
> -DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18, CSR_CLASS_I)
> -DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19, CSR_CLASS_I)
> -DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20, CSR_CLASS_I)
> -DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21, CSR_CLASS_I)
> -DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22, CSR_CLASS_I)
> -DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23, CSR_CLASS_I)
> -DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24, CSR_CLASS_I)
> -DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25, CSR_CLASS_I)
> -DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26, CSR_CLASS_I)
> -DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27, CSR_CLASS_I)
> -DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28, CSR_CLASS_I)
> -DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29, CSR_CLASS_I)
> -DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30, CSR_CLASS_I)
> -DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31, CSR_CLASS_I)
> -DECLARE_CSR(tselect, CSR_TSELECT, CSR_CLASS_I)
> -DECLARE_CSR(tdata1, CSR_TDATA1, CSR_CLASS_I)
> -DECLARE_CSR(tdata2, CSR_TDATA2, CSR_CLASS_I)
> -DECLARE_CSR(tdata3, CSR_TDATA3, CSR_CLASS_I)
> -DECLARE_CSR(dcsr, CSR_DCSR, CSR_CLASS_I)
> -DECLARE_CSR(dpc, CSR_DPC, CSR_CLASS_I)
> -DECLARE_CSR(dscratch0, CSR_DSCRATCH0, CSR_CLASS_I)
> -DECLARE_CSR(dscratch1, CSR_DSCRATCH1, CSR_CLASS_I)
> -/* These registers are present in priv spec 1.9.1, dropped in 1.10. */
> -DECLARE_CSR(hstatus, CSR_HSTATUS, CSR_CLASS_I)
> -DECLARE_CSR(hedeleg, CSR_HEDELEG, CSR_CLASS_I)
> -DECLARE_CSR(hideleg, CSR_HIDELEG, CSR_CLASS_I)
> -DECLARE_CSR(hie, CSR_HIE, CSR_CLASS_I)
> -DECLARE_CSR(htvec, CSR_HTVEC, CSR_CLASS_I)
> -DECLARE_CSR(hscratch, CSR_HSCRATCH, CSR_CLASS_I)
> -DECLARE_CSR(hepc, CSR_HEPC, CSR_CLASS_I)
> -DECLARE_CSR(hcause, CSR_HCAUSE, CSR_CLASS_I)
> -DECLARE_CSR(hbadaddr, CSR_HBADADDR, CSR_CLASS_I)
> -DECLARE_CSR(hip, CSR_HIP, CSR_CLASS_I)
> -DECLARE_CSR(mbase, CSR_MBASE, CSR_CLASS_I)
> -DECLARE_CSR(mbound, CSR_MBOUND, CSR_CLASS_I)
> -DECLARE_CSR(mibase, CSR_MIBASE, CSR_CLASS_I)
> -DECLARE_CSR(mibound, CSR_MIBOUND, CSR_CLASS_I)
> -DECLARE_CSR(mdbase, CSR_MDBASE, CSR_CLASS_I)
> -DECLARE_CSR(mdbound, CSR_MDBOUND, CSR_CLASS_I)
> -DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN, CSR_CLASS_I)
> -DECLARE_CSR(mhcounteren, CSR_MHCOUNTEREN, CSR_CLASS_I)
> +DECLARE_CSR(ustatus, CSR_USTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(uie, CSR_UIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(utvec, CSR_UTVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(uscratch, CSR_USCRATCH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(uepc, CSR_UEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(ucause, CSR_UCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(utval, CSR_UTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(uip, CSR_UIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(fflags, CSR_FFLAGS, CSR_CLASS_F, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(frm, CSR_FRM, CSR_CLASS_F, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(fcsr, CSR_FCSR, CSR_CLASS_F, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(cycle, CSR_CYCLE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(time, CSR_TIME, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(instret, CSR_INSTRET, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(cycleh, CSR_CYCLEH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(timeh, CSR_TIMEH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(instreth, CSR_INSTRETH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(sstatus, CSR_SSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(sedeleg, CSR_SEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(sideleg, CSR_SIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(sie, CSR_SIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(stvec, CSR_STVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(scounteren, CSR_SCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(sscratch, CSR_SSCRATCH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(sepc, CSR_SEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(scause, CSR_SCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(stval, CSR_STVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(sip, CSR_SIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(satp, CSR_SATP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mvendorid, CSR_MVENDORID, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(marchid, CSR_MARCHID, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mimpid, CSR_MIMPID, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhartid, CSR_MHARTID, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mstatus, CSR_MSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(misa, CSR_MISA, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(medeleg, CSR_MEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mideleg, CSR_MIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mie, CSR_MIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mtvec, CSR_MTVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mcounteren, CSR_MCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mscratch, CSR_MSCRATCH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mepc, CSR_MEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mcause, CSR_MCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mtval, CSR_MTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mip, CSR_MIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(pmpcfg0, CSR_PMPCFG0, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(pmpcfg1, CSR_PMPCFG1, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(pmpcfg2, CSR_PMPCFG2, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(pmpcfg3, CSR_PMPCFG3, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(pmpaddr0, CSR_PMPADDR0, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(pmpaddr1, CSR_PMPADDR1, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(pmpaddr2, CSR_PMPADDR2, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(pmpaddr3, CSR_PMPADDR3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(pmpaddr4, CSR_PMPADDR4, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(pmpaddr5, CSR_PMPADDR5, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(pmpaddr6, CSR_PMPADDR6, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(pmpaddr7, CSR_PMPADDR7, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(pmpaddr8, CSR_PMPADDR8, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(pmpaddr9, CSR_PMPADDR9, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(pmpaddr10, CSR_PMPADDR10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(pmpaddr11, CSR_PMPADDR11, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(pmpaddr12, CSR_PMPADDR12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(pmpaddr13, CSR_PMPADDR13, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(pmpaddr14, CSR_PMPADDR14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(pmpaddr15, CSR_PMPADDR15, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mcycle, CSR_MCYCLE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(minstret, CSR_MINSTRET, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mcycleh, CSR_MCYCLEH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(minstreth, CSR_MINSTRETH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mcountinhibit, CSR_MCOUNTINHIBIT, CSR_CLASS_I, PRIV_SPEC_CLASS_1P11, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(tselect, CSR_TSELECT, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(tdata1, CSR_TDATA1, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(tdata2, CSR_TDATA2, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(tdata3, CSR_TDATA3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(dcsr, CSR_DCSR, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(dpc, CSR_DPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(dscratch0, CSR_DSCRATCH0, CSR_CLASS_I, PRIV_SPEC_CLASS_1P11, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(dscratch1, CSR_DSCRATCH1, CSR_CLASS_I, PRIV_SPEC_CLASS_1P11, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(hstatus, CSR_HSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
> +DECLARE_CSR(hedeleg, CSR_HEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
> +DECLARE_CSR(hideleg, CSR_HIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
> +DECLARE_CSR(hie, CSR_HIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
> +DECLARE_CSR(htvec, CSR_HTVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
> +DECLARE_CSR(hscratch, CSR_HSCRATCH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
> +DECLARE_CSR(hepc, CSR_HEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
> +DECLARE_CSR(hcause, CSR_HCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
> +DECLARE_CSR(hbadaddr, CSR_HBADADDR, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
> +DECLARE_CSR(hip, CSR_HIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
> +DECLARE_CSR(mbase, CSR_MBASE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
> +DECLARE_CSR(mbound, CSR_MBOUND, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
> +DECLARE_CSR(mibase, CSR_MIBASE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
> +DECLARE_CSR(mibound, CSR_MIBOUND, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
> +DECLARE_CSR(mdbase, CSR_MDBASE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
> +DECLARE_CSR(mdbound, CSR_MDBOUND, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
> +DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
> +DECLARE_CSR(mhcounteren, CSR_MHCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
> #endif
> #ifdef DECLARE_CSR_ALIAS
> -/* Ubadaddr is 0x043 in 1.9.1, but 0x043 is utval in 1.10. */
> -DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL, CSR_CLASS_I)
> -/* Sbadaddr is 0x143 in 1.9.1, but 0x143 is stval in 1.10. */
> -DECLARE_CSR_ALIAS(sbadaddr, CSR_STVAL, CSR_CLASS_I)
> -/* Sptbr is 0x180 in 1.9.1, but 0x180 is satp in 1.10. */
> -DECLARE_CSR_ALIAS(sptbr, CSR_SATP, CSR_CLASS_I)
> -/* Mbadaddr is 0x343 in 1.9.1, but 0x343 is mtval in 1.10. */
> -DECLARE_CSR_ALIAS(mbadaddr, CSR_MTVAL, CSR_CLASS_I)
> -/* Mucounteren is 0x320 in 1.10, but 0x320 is mcountinhibit in 1.11. */
> -DECLARE_CSR_ALIAS(mucounteren, CSR_MCOUNTINHIBIT, CSR_CLASS_I)
> -/* Dscratch is 0x7b2 in 1.10, but 0x7b2 is dscratch0 in 1.11. */
> -DECLARE_CSR_ALIAS(dscratch, CSR_DSCRATCH0, CSR_CLASS_I)
> +DECLARE_CSR_ALIAS(misa, 0xf10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P9P1)
> +DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
> +DECLARE_CSR_ALIAS(sbadaddr, CSR_STVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
> +DECLARE_CSR_ALIAS(sptbr, CSR_SATP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
> +DECLARE_CSR_ALIAS(mbadaddr, CSR_MTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
> +DECLARE_CSR_ALIAS(mucounteren, CSR_MCOUNTINHIBIT, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
> +DECLARE_CSR_ALIAS(dscratch, CSR_DSCRATCH0, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P11)
> #endif
> #ifdef DECLARE_CAUSE
> DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
> index d83e9ca..84f7c2a 100644
> --- a/include/opcode/riscv.h
> +++ b/include/opcode/riscv.h
> @@ -365,6 +365,52 @@ struct riscv_ext_version
> unsigned int minor_version;
> };
>
> +/* All RISC-V CSR belong to one of these classes. */
> +
> +enum riscv_csr_class
> +{
> + CSR_CLASS_NONE,
> +
> + CSR_CLASS_I,
> + CSR_CLASS_I_32, /* rv32 only */
> + CSR_CLASS_F, /* f-ext only */
> +};
> +
> +/* The current supported privilege spec versions. */
> +
> +enum riscv_priv_spec_class
> +{
> + PRIV_SPEC_CLASS_NONE,
> +
> + PRIV_SPEC_CLASS_1P9,
> + PRIV_SPEC_CLASS_1P9P1,
> + PRIV_SPEC_CLASS_1P10,
> + PRIV_SPEC_CLASS_1P11,
> + PRIV_SPEC_CLASS_DRAFT
> +};
> +
> +/* This structure holds all restricted conditions for a CSR. */
> +
> +struct riscv_csr_extra
> +{
> + /* Class to which this CSR belongs. Used to decide whether or
> + not this CSR is legal in the current -march context. */
> + enum riscv_csr_class csr_class;
> +
> + /* CSR may have differnet numbers in the previous priv spec. */
> + unsigned address;
> +
> + /* Record the CSR is defined/valid in which versions. */
> + enum riscv_priv_spec_class define_version;
> +
> + /* Record the CSR is aborted/invalid from which versions. If it isn't
> + aborted in the current version, then it should be CSR_CLASS_VDRAFT. */
> + enum riscv_priv_spec_class abort_version;
> +
> + /* The CSR may have more than one setting. */
> + struct riscv_csr_extra *next;
> +};
> +
> /* Instruction is a simple alias (e.g. "mv" for "addi"). */
> #define INSN_ALIAS 0x00000001
>
> @@ -446,5 +492,9 @@ extern const struct riscv_ext_version riscv_ext_version_table[];
>
> extern bfd_boolean
> riscv_get_isa_spec_class (const char *, enum riscv_isa_spec_class *);
> +extern bfd_boolean
> +riscv_get_priv_spec_class (const char *, enum riscv_priv_spec_class *);
> +extern const char *
> +riscv_get_priv_spec_name (enum riscv_priv_spec_class);
>
> #endif /* _RISCV_H_ */
> diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
> index d7a184c..98302ff 100644
> --- a/opcodes/riscv-dis.c
> +++ b/opcodes/riscv-dis.c
> @@ -326,7 +326,8 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
> unsigned int csr = EXTRACT_OPERAND (CSR, l);
> switch (csr)
> {
> -#define DECLARE_CSR(name, num, class) case num: csr_name = #name; break;
> +#define DECLARE_CSR(name, num, class, define_version, abort_version) \
> + case num: csr_name = #name; break;
> #include "opcode/riscv-opc.h"
> #undef DECLARE_CSR
> }
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index f08b15e..da376ad 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -977,3 +977,54 @@ riscv_get_isa_spec_class (const char *s,
> /* Can not find the supported ISA spec. */
> return FALSE;
> }
> +
> +struct priv_spec_t
> +{
> + const char *name;
> + enum riscv_priv_spec_class class;
> +};
> +
> +/* List for all supported privilege versions. */
> +static const struct priv_spec_t priv_specs[] =
> +{
> + {"1.9", PRIV_SPEC_CLASS_1P9},
> + {"1.9.1", PRIV_SPEC_CLASS_1P9P1},
> + {"1.10", PRIV_SPEC_CLASS_1P10},
> + {"1.11", PRIV_SPEC_CLASS_1P11},
> +
> +/* Terminate the list. */
> + {NULL, 0}
> +};
> +
> +/* Get the corresponding CSR version class by giving a privilege
> + version string. */
> +
> +bfd_boolean
> +riscv_get_priv_spec_class (const char *s,
> + enum riscv_priv_spec_class *class)
> +{
> + const struct priv_spec_t *version;
> +
> + if (s == NULL)
> + return FALSE;
> +
> + for (version = &priv_specs[0]; version->name != NULL; ++version)
> + if (strcmp (version->name, s) == 0)
> + {
> + *class = version->class;
> + return TRUE;
> + }
> +
> + /* Can not find the supported privilege version. */
> + return FALSE;
> +}
> +
> +/* Get the corresponding privilege version string by giving a CSR
> + version class. */
> +
> +const char *
> +riscv_get_priv_spec_name (enum riscv_priv_spec_class class)
> +{
> + /* The first enum is PRIV_SPEC_CLASS_NONE. */
> + return priv_specs[class - 1].name;
> +}
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 6/9] RISC-V: Support configure option to choose the privilege spec version.
2020-05-06 2:55 [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR Nelson Chu
` (4 preceding siblings ...)
2020-05-06 2:55 ` [PATCH v2 5/9] RISC-V: Support version checking for CSR according to privilege spec version Nelson Chu
@ 2020-05-06 2:55 ` Nelson Chu
2020-05-19 9:08 ` Nelson Chu
2020-05-06 2:55 ` [PATCH v2 7/9] RISC-V: Make privilege spec attributes workable Nelson Chu
` (3 subsequent siblings)
9 siblings, 1 reply; 25+ messages in thread
From: Nelson Chu @ 2020-05-06 2:55 UTC (permalink / raw)
To: binutils, gdb-patches
Cc: palmer, kito.cheng, jimw, andrew, andrew.burgess, asb,
maxim.blinov, nelson.chu
Support new configure option --with-priv-spec to choose the privilege spec
version if we don't set the --mpriv-spec option.
* --with-priv-spec = [1.9|1.9.1|1.10|1.11]
The syntax is same as -mpriv-spec option. Assembler will check this setting
if -mpriv-spec option isn’t set.
gas/
* config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Default configure option
setting. You can set it by configure option --with-priv-spec.
(riscv_set_default_priv_spec): New function used to set the default
privilege spec.
(md_parse_option): Call riscv_set_default_priv_spec rather than
call riscv_get_priv_spec_class directly.
(riscv_after_parse_args): If -mpriv-spec isn't set, then we set the
default privilege spec according to DEFAULT_RISCV_PRIV_SPEC by
calling riscv_set_default_priv_spec.
* testsuite/gas/riscv/csr-dw-regnums.d: Add -mpriv-spec=1.11, since
the --with-priv-spec may be set to different privilege spec.
* testsuite/gas/riscv/priv-reg.d: Likewise.
* configure.ac: Add configure option --with-priv-spec.
* configure: Regenerated.
* config.in: Regenerated.
---
gas/config.in | 3 +++
gas/config/tc-riscv.c | 36 ++++++++++++++++++++++++--------
gas/configure | 13 ++++++++++++
gas/configure.ac | 8 +++++++
gas/testsuite/gas/riscv/csr-dw-regnums.d | 2 +-
gas/testsuite/gas/riscv/priv-reg.d | 2 +-
6 files changed, 53 insertions(+), 11 deletions(-)
diff --git a/gas/config.in b/gas/config.in
index e20d3c3..bd12504 100644
--- a/gas/config.in
+++ b/gas/config.in
@@ -62,6 +62,9 @@
/* Define default value for RISC-V -misa-spec. */
#undef DEFAULT_RISCV_ISA_SPEC
+/* Define default value for RISC-V -mpriv-spec */
+#undef DEFAULT_RISCV_PRIV_SPEC
+
/* Define to 1 if you want to generate GNU x86 used ISA and feature properties
by default. */
#undef DEFAULT_X86_USED_NOTE
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 743e4bb..6fd1dcf 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -79,6 +79,10 @@ struct riscv_cl_insn
#define DEFAULT_RISCV_ISA_SPEC "2.2"
#endif
+#ifndef DEFAULT_RISCV_PRIV_SPEC
+#define DEFAULT_RISCV_PRIV_SPEC "1.11"
+#endif
+
static const char default_arch[] = DEFAULT_ARCH;
static const char *default_arch_with_ext = DEFAULT_RISCV_ARCH_WITH_EXT;
static enum riscv_isa_spec_class default_isa_spec = ISA_SPEC_CLASS_NONE;
@@ -111,6 +115,25 @@ riscv_set_default_isa_spec (const char *s)
return 1;
}
+/* Set the default_priv_spec, assembler will find the suitable CSR address
+ according to default_priv_spec. Return 0 if the input priv name isn't
+ supported. Otherwise, return 1. */
+
+static int
+riscv_set_default_priv_spec (const char *s)
+{
+ enum riscv_priv_spec_class class;
+ if (!riscv_get_priv_spec_class (s, &class))
+ {
+ as_bad (_("Unknown default privilege spec `%s' set by "
+ "-mpriv-spec or --with-priv-spec"), s);
+ return 0;
+ }
+ else
+ default_priv_spec = class;
+ return 1;
+}
+
/* This is the set of options which the .option pseudo-op may modify. */
struct riscv_set_options
@@ -2626,13 +2649,7 @@ md_parse_option (int c, const char *arg)
return riscv_set_default_isa_spec (arg);
case OPTION_MPRIV_SPEC:
- if (!riscv_get_priv_spec_class (arg, &default_priv_spec))
- {
- as_bad ("Unknown default privilege spec `%s' set by "
- "-mpriv-spec", arg);
- return 0;
- }
- break;
+ return riscv_set_default_priv_spec (arg);
default:
return 0;
@@ -2681,9 +2698,10 @@ riscv_after_parse_args (void)
if (riscv_subset_supports ("e"))
riscv_set_rve (TRUE);
- /* Set the default privilege spec to the newest one. */
+ /* If the -mpriv-spec isn't set, then we set the default privilege spec
+ according to DEFAULT_PRIV_SPEC. */
if (default_priv_spec == PRIV_SPEC_CLASS_NONE)
- default_priv_spec = PRIV_SPEC_CLASS_1P11;
+ riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC);
/* Infer ABI from ISA if not specified on command line. */
if (abi_xlen == 0)
diff --git a/gas/configure b/gas/configure
index cc21e0a..72e33d9 100755
--- a/gas/configure
+++ b/gas/configure
@@ -13054,6 +13054,19 @@ _ACEOF
fi
{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $with_isa_spec" >&5
$as_echo "$with_isa_spec" >&6; }
+
+ # --with-priv-spec=[1.9|1.9.1|1.10|1.11].
+ { $as_echo "$as_me:${as_lineno-$LINENO}: checking for default configuration of --with-priv-spec" >&5
+$as_echo_n "checking for default configuration of --with-priv-spec... " >&6; }
+ if test "x${with_priv_spec}" != x; then
+
+cat >>confdefs.h <<_ACEOF
+#define DEFAULT_RISCV_PRIV_SPEC "$with_priv_spec"
+_ACEOF
+
+ fi
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $with_priv_spec" >&5
+$as_echo "$with_priv_spec" >&6; }
;;
rl78)
diff --git a/gas/configure.ac b/gas/configure.ac
index 8a5f5c5..82122e8 100644
--- a/gas/configure.ac
+++ b/gas/configure.ac
@@ -596,6 +596,14 @@ changequote([,])dnl
[Define default value for RISC-V -misa-spec.])
fi
AC_MSG_RESULT($with_isa_spec)
+
+ # --with-priv-spec=[1.9|1.9.1|1.10|1.11].
+ AC_MSG_CHECKING(for default configuration of --with-priv-spec)
+ if test "x${with_priv_spec}" != x; then
+ AC_DEFINE_UNQUOTED(DEFAULT_RISCV_PRIV_SPEC, "$with_priv_spec",
+ [Define default value for RISC-V -mpriv-spec])
+ fi
+ AC_MSG_RESULT($with_priv_spec)
;;
rl78)
diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.d b/gas/testsuite/gas/riscv/csr-dw-regnums.d
index df9642f..c03d459 100644
--- a/gas/testsuite/gas/riscv/csr-dw-regnums.d
+++ b/gas/testsuite/gas/riscv/csr-dw-regnums.d
@@ -1,4 +1,4 @@
-#as: -march=rv32if
+#as: -march=rv32if -mpriv-spec=1.11
#objdump: --dwarf=frames
diff --git a/gas/testsuite/gas/riscv/priv-reg.d b/gas/testsuite/gas/riscv/priv-reg.d
index 8fc41d2..a0c3cd7 100644
--- a/gas/testsuite/gas/riscv/priv-reg.d
+++ b/gas/testsuite/gas/riscv/priv-reg.d
@@ -1,4 +1,4 @@
-#as: -march=rv32if
+#as: -march=rv32if -mpriv-spec=1.11
#objdump: -dr
.*:[ ]+file format .*
--
2.7.4
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [PATCH v2 6/9] RISC-V: Support configure option to choose the privilege spec version.
2020-05-06 2:55 ` [PATCH v2 6/9] RISC-V: Support configure option to choose the " Nelson Chu
@ 2020-05-19 9:08 ` Nelson Chu
0 siblings, 0 replies; 25+ messages in thread
From: Nelson Chu @ 2020-05-19 9:08 UTC (permalink / raw)
To: Binutils, gdb-patches
Cc: Palmer Dabbelt, Kito Cheng, Jim Wilson, Andrew Waterman,
Andrew Burgess, Alex Bradbury, Maxim Blinov
PING :)
On Wed, May 6, 2020 at 10:55 AM Nelson Chu <nelson.chu@sifive.com> wrote:
>
> Support new configure option --with-priv-spec to choose the privilege spec
> version if we don't set the --mpriv-spec option.
>
> * --with-priv-spec = [1.9|1.9.1|1.10|1.11]
> The syntax is same as -mpriv-spec option. Assembler will check this setting
> if -mpriv-spec option isn’t set.
>
> gas/
> * config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Default configure option
> setting. You can set it by configure option --with-priv-spec.
> (riscv_set_default_priv_spec): New function used to set the default
> privilege spec.
> (md_parse_option): Call riscv_set_default_priv_spec rather than
> call riscv_get_priv_spec_class directly.
> (riscv_after_parse_args): If -mpriv-spec isn't set, then we set the
> default privilege spec according to DEFAULT_RISCV_PRIV_SPEC by
> calling riscv_set_default_priv_spec.
>
> * testsuite/gas/riscv/csr-dw-regnums.d: Add -mpriv-spec=1.11, since
> the --with-priv-spec may be set to different privilege spec.
> * testsuite/gas/riscv/priv-reg.d: Likewise.
>
> * configure.ac: Add configure option --with-priv-spec.
> * configure: Regenerated.
> * config.in: Regenerated.
> ---
> gas/config.in | 3 +++
> gas/config/tc-riscv.c | 36 ++++++++++++++++++++++++--------
> gas/configure | 13 ++++++++++++
> gas/configure.ac | 8 +++++++
> gas/testsuite/gas/riscv/csr-dw-regnums.d | 2 +-
> gas/testsuite/gas/riscv/priv-reg.d | 2 +-
> 6 files changed, 53 insertions(+), 11 deletions(-)
>
> diff --git a/gas/config.in b/gas/config.in
> index e20d3c3..bd12504 100644
> --- a/gas/config.in
> +++ b/gas/config.in
> @@ -62,6 +62,9 @@
> /* Define default value for RISC-V -misa-spec. */
> #undef DEFAULT_RISCV_ISA_SPEC
>
> +/* Define default value for RISC-V -mpriv-spec */
> +#undef DEFAULT_RISCV_PRIV_SPEC
> +
> /* Define to 1 if you want to generate GNU x86 used ISA and feature properties
> by default. */
> #undef DEFAULT_X86_USED_NOTE
> diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
> index 743e4bb..6fd1dcf 100644
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -79,6 +79,10 @@ struct riscv_cl_insn
> #define DEFAULT_RISCV_ISA_SPEC "2.2"
> #endif
>
> +#ifndef DEFAULT_RISCV_PRIV_SPEC
> +#define DEFAULT_RISCV_PRIV_SPEC "1.11"
> +#endif
> +
> static const char default_arch[] = DEFAULT_ARCH;
> static const char *default_arch_with_ext = DEFAULT_RISCV_ARCH_WITH_EXT;
> static enum riscv_isa_spec_class default_isa_spec = ISA_SPEC_CLASS_NONE;
> @@ -111,6 +115,25 @@ riscv_set_default_isa_spec (const char *s)
> return 1;
> }
>
> +/* Set the default_priv_spec, assembler will find the suitable CSR address
> + according to default_priv_spec. Return 0 if the input priv name isn't
> + supported. Otherwise, return 1. */
> +
> +static int
> +riscv_set_default_priv_spec (const char *s)
> +{
> + enum riscv_priv_spec_class class;
> + if (!riscv_get_priv_spec_class (s, &class))
> + {
> + as_bad (_("Unknown default privilege spec `%s' set by "
> + "-mpriv-spec or --with-priv-spec"), s);
> + return 0;
> + }
> + else
> + default_priv_spec = class;
> + return 1;
> +}
> +
> /* This is the set of options which the .option pseudo-op may modify. */
>
> struct riscv_set_options
> @@ -2626,13 +2649,7 @@ md_parse_option (int c, const char *arg)
> return riscv_set_default_isa_spec (arg);
>
> case OPTION_MPRIV_SPEC:
> - if (!riscv_get_priv_spec_class (arg, &default_priv_spec))
> - {
> - as_bad ("Unknown default privilege spec `%s' set by "
> - "-mpriv-spec", arg);
> - return 0;
> - }
> - break;
> + return riscv_set_default_priv_spec (arg);
>
> default:
> return 0;
> @@ -2681,9 +2698,10 @@ riscv_after_parse_args (void)
> if (riscv_subset_supports ("e"))
> riscv_set_rve (TRUE);
>
> - /* Set the default privilege spec to the newest one. */
> + /* If the -mpriv-spec isn't set, then we set the default privilege spec
> + according to DEFAULT_PRIV_SPEC. */
> if (default_priv_spec == PRIV_SPEC_CLASS_NONE)
> - default_priv_spec = PRIV_SPEC_CLASS_1P11;
> + riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC);
>
> /* Infer ABI from ISA if not specified on command line. */
> if (abi_xlen == 0)
> diff --git a/gas/configure b/gas/configure
> index cc21e0a..72e33d9 100755
> --- a/gas/configure
> +++ b/gas/configure
> @@ -13054,6 +13054,19 @@ _ACEOF
> fi
> { $as_echo "$as_me:${as_lineno-$LINENO}: result: $with_isa_spec" >&5
> $as_echo "$with_isa_spec" >&6; }
> +
> + # --with-priv-spec=[1.9|1.9.1|1.10|1.11].
> + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for default configuration of --with-priv-spec" >&5
> +$as_echo_n "checking for default configuration of --with-priv-spec... " >&6; }
> + if test "x${with_priv_spec}" != x; then
> +
> +cat >>confdefs.h <<_ACEOF
> +#define DEFAULT_RISCV_PRIV_SPEC "$with_priv_spec"
> +_ACEOF
> +
> + fi
> + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $with_priv_spec" >&5
> +$as_echo "$with_priv_spec" >&6; }
> ;;
>
> rl78)
> diff --git a/gas/configure.ac b/gas/configure.ac
> index 8a5f5c5..82122e8 100644
> --- a/gas/configure.ac
> +++ b/gas/configure.ac
> @@ -596,6 +596,14 @@ changequote([,])dnl
> [Define default value for RISC-V -misa-spec.])
> fi
> AC_MSG_RESULT($with_isa_spec)
> +
> + # --with-priv-spec=[1.9|1.9.1|1.10|1.11].
> + AC_MSG_CHECKING(for default configuration of --with-priv-spec)
> + if test "x${with_priv_spec}" != x; then
> + AC_DEFINE_UNQUOTED(DEFAULT_RISCV_PRIV_SPEC, "$with_priv_spec",
> + [Define default value for RISC-V -mpriv-spec])
> + fi
> + AC_MSG_RESULT($with_priv_spec)
> ;;
>
> rl78)
> diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.d b/gas/testsuite/gas/riscv/csr-dw-regnums.d
> index df9642f..c03d459 100644
> --- a/gas/testsuite/gas/riscv/csr-dw-regnums.d
> +++ b/gas/testsuite/gas/riscv/csr-dw-regnums.d
> @@ -1,4 +1,4 @@
> -#as: -march=rv32if
> +#as: -march=rv32if -mpriv-spec=1.11
> #objdump: --dwarf=frames
>
>
> diff --git a/gas/testsuite/gas/riscv/priv-reg.d b/gas/testsuite/gas/riscv/priv-reg.d
> index 8fc41d2..a0c3cd7 100644
> --- a/gas/testsuite/gas/riscv/priv-reg.d
> +++ b/gas/testsuite/gas/riscv/priv-reg.d
> @@ -1,4 +1,4 @@
> -#as: -march=rv32if
> +#as: -march=rv32if -mpriv-spec=1.11
> #objdump: -dr
>
> .*:[ ]+file format .*
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 7/9] RISC-V: Make privilege spec attributes workable.
2020-05-06 2:55 [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR Nelson Chu
` (5 preceding siblings ...)
2020-05-06 2:55 ` [PATCH v2 6/9] RISC-V: Support configure option to choose the " Nelson Chu
@ 2020-05-06 2:55 ` Nelson Chu
2020-05-19 9:08 ` Nelson Chu
2020-05-06 2:55 ` [PATCH v2 8/9] RISC-V: Disassembler dumps the CSR according to the chosen privilege spec Nelson Chu
` (2 subsequent siblings)
9 siblings, 1 reply; 25+ messages in thread
From: Nelson Chu @ 2020-05-06 2:55 UTC (permalink / raw)
To: binutils, gdb-patches
Cc: palmer, kito.cheng, jimw, andrew, andrew.burgess, asb,
maxim.blinov, nelson.chu
There are three privilege spec attributes, Tag_RISCV_priv_spec,
Tag_RISCV_priv_spec_minor and Tag_RISCV_priv_spec_revision, are used to choose
which version of privilege spec you want. You can also use -mpriv-spec option
to choose the priv spec, but the priority of ELF attributes is the highest.
Beside, we have to make sure all arch and priv attributes are set before any
instruction.
The Priority of these options,
* ELF priv attributes > -mpriv-spec > --with-priv-spec
bfd/
* elfxx-riscv.c (riscv_estimate_digit): Remove the static.
* elfxx-riscv.h: Updated.
gas/
* config/tc-riscv.c (explicit_attr): Rename explicit_arch_attr to
explicit_attr. Set it to TRUE if any ELF attribute is found.
(riscv_set_default_priv_spec): Try to set the default_priv_spec if
the priv attributes are set.
(md_assemble): Set the default_priv_spec according to the priv
attributes when we start to assemble instruction.
(riscv_write_out_attrs): Rename riscv_write_out_arch_attr to
riscv_write_out_attrs. Update the arch and priv attributes. If we
don't set the corresponding ELF attributes, then try to output the
default ones.
(riscv_set_public_attributes): If any ELF attribute or -march-attr
options is set (explicit_attr is TRUE), then call riscv_write_out_attrs
to update the arch and priv attributes.
(s_riscv_attribute): Make sure all arch and priv attributes are set
before any instruction.
* testsuite/gas/riscv/attribute-01.d: Update the priv attributes if any
ELF attribute or -march-attr is set. If the priv attributes are not
set, then try to update them by the default setting (-mpriv-spec or
--with-priv-spec).
* testsuite/gas/riscv/attribute-02.d: Likewise.
* testsuite/gas/riscv/attribute-03.d: Likewise.
* testsuite/gas/riscv/attribute-04.d: Likewise.
* testsuite/gas/riscv/attribute-06.d: Likewise.
* testsuite/gas/riscv/attribute-07.d: Likewise.
* testsuite/gas/riscv/attribute-08.d: Likewise.
* testsuite/gas/riscv/attribute-09.d: Likewise.
* testsuite/gas/riscv/attribute-10.d: Likewise.
* testsuite/gas/riscv/attribute-unknown.d: Likewise.
* testsuite/gas/riscv/attribute-05.d: Likewise. Also, the priv spec
set by priv attributes must be supported.
* testsuite/gas/riscv/attribute-05.s: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Likewise. Updated
priv attributes according to the -mpriv-spec option.
* testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise.
ld/
* testsuite/ld-riscv-elf/attr-merge-arch-01.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise.
---
bfd/elfxx-riscv.c | 2 +-
bfd/elfxx-riscv.h | 3 +
gas/config/tc-riscv.c | 154 ++++++++++++++++++---
gas/testsuite/gas/riscv/attribute-01.d | 3 +
gas/testsuite/gas/riscv/attribute-02.d | 3 +
gas/testsuite/gas/riscv/attribute-03.d | 3 +
gas/testsuite/gas/riscv/attribute-04.d | 3 +
gas/testsuite/gas/riscv/attribute-05.d | 4 +-
gas/testsuite/gas/riscv/attribute-05.s | 4 +-
gas/testsuite/gas/riscv/attribute-06.d | 3 +
gas/testsuite/gas/riscv/attribute-07.d | 3 +
gas/testsuite/gas/riscv/attribute-08.d | 3 +
gas/testsuite/gas/riscv/attribute-09.d | 3 +
gas/testsuite/gas/riscv/attribute-10.d | 3 +
gas/testsuite/gas/riscv/attribute-unknown.d | 3 +
.../gas/riscv/priv-reg-fail-version-1p10.d | 10 +-
.../gas/riscv/priv-reg-fail-version-1p11.d | 10 +-
.../gas/riscv/priv-reg-fail-version-1p9.d | 10 +-
.../gas/riscv/priv-reg-fail-version-1p9p1.d | 11 +-
ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d | 3 +
ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d | 3 +
ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d | 3 +
ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s | 4 +-
ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s | 4 +-
ld/testsuite/ld-riscv-elf/attr-merge-priv-spec.d | 4 +-
ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d | 3 +
.../ld-riscv-elf/attr-merge-strict-align-01.d | 3 +
.../ld-riscv-elf/attr-merge-strict-align-02.d | 3 +
.../ld-riscv-elf/attr-merge-strict-align-03.d | 3 +
.../ld-riscv-elf/attr-merge-strict-align-04.d | 3 +
.../ld-riscv-elf/attr-merge-strict-align-05.d | 3 +
31 files changed, 241 insertions(+), 36 deletions(-)
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index e025689..d06c2a5 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1650,7 +1650,7 @@ riscv_release_subset_list (riscv_subset_list_t *subset_list)
/* Return the number of digits for the input. */
-static size_t
+size_t
riscv_estimate_digit (unsigned num)
{
size_t digit = 0;
diff --git a/bfd/elfxx-riscv.h b/bfd/elfxx-riscv.h
index cbafd28..a3a0862 100644
--- a/bfd/elfxx-riscv.h
+++ b/bfd/elfxx-riscv.h
@@ -90,6 +90,9 @@ riscv_release_subset_list (riscv_subset_list_t *);
extern char *
riscv_arch_str (unsigned, const riscv_subset_list_t *);
+extern size_t
+riscv_estimate_digit (unsigned);
+
/* ISA extension name class. E.g. "zbb" corresponds to RV_ISA_CLASS_Z,
"xargs" corresponds to RV_ISA_CLASS_X, etc. Order is important
here. */
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 6fd1dcf..6e30a06 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -116,22 +116,74 @@ riscv_set_default_isa_spec (const char *s)
}
/* Set the default_priv_spec, assembler will find the suitable CSR address
- according to default_priv_spec. Return 0 if the input priv name isn't
+ according to default_priv_spec. We will try to check priv attributes if
+ the input string is NULL. Return 0 if the input priv spec string isn't
supported. Otherwise, return 1. */
static int
riscv_set_default_priv_spec (const char *s)
{
enum riscv_priv_spec_class class;
- if (!riscv_get_priv_spec_class (s, &class))
+ unsigned major, minor, revision;
+ obj_attribute *attr;
+ size_t buf_size;
+ char *buf;
+
+ /* Find the corresponding priv spec class. */
+ if (riscv_get_priv_spec_class (s, &class))
+ {
+ default_priv_spec = class;
+ return 1;
+ }
+
+ if (s != NULL)
{
as_bad (_("Unknown default privilege spec `%s' set by "
"-mpriv-spec or --with-priv-spec"), s);
return 0;
}
+
+ /* Try to set the default_priv_spec according to the priv attributes. */
+ attr = elf_known_obj_attributes_proc (stdoutput);
+ major = (unsigned) attr[Tag_RISCV_priv_spec].i;
+ minor = (unsigned) attr[Tag_RISCV_priv_spec_minor].i;
+ revision = (unsigned) attr[Tag_RISCV_priv_spec_revision].i;
+
+ /* The priv attributes setting 0.0.0 is meaningless. We should have set
+ the default_priv_spec by md_parse_option and riscv_after_parse_args,
+ so just skip the following setting. */
+ if (major == 0 && minor == 0 && revision == 0)
+ return 1;
+
+ buf_size = riscv_estimate_digit (major)
+ + 1 /* '.' */
+ + riscv_estimate_digit (minor)
+ + 1; /* string terminator */
+ if (revision != 0)
+ {
+ buf_size += 1 /* '.' */
+ + riscv_estimate_digit (revision);
+ buf = xmalloc (buf_size);
+ snprintf (buf, buf_size, "%d.%d.%d", major, minor, revision);
+ }
else
- default_priv_spec = class;
- return 1;
+ {
+ buf = xmalloc (buf_size);
+ snprintf (buf, buf_size, "%d.%d", major, minor);
+ }
+
+ if (riscv_get_priv_spec_class (buf, &class))
+ {
+ default_priv_spec = class;
+ free (buf);
+ return 1;
+ }
+
+ /* Still can not find the priv spec class. */
+ as_bad (_("Unknown default privilege spec `%d.%d.%d' set by "
+ "privilege attributes"), major, minor, revision);
+ free (buf);
+ return 0;
}
/* This is the set of options which the .option pseudo-op may modify. */
@@ -319,8 +371,8 @@ const char FLT_CHARS[] = "rRsSfFdDxXpP";
/* Indicate we are already assemble any instructions or not. */
static bfd_boolean start_assemble = FALSE;
-/* Indicate arch attribute is explictly set. */
-static bfd_boolean explicit_arch_attr = FALSE;
+/* Indicate ELF attributes are explictly set. */
+static bfd_boolean explicit_attr = FALSE;
/* Macros for encoding relaxation state for RVC branches and far jumps. */
#define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
@@ -2495,9 +2547,17 @@ md_assemble (char *str)
expressionS imm_expr;
bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
- const char *error = riscv_ip (str, &insn, &imm_expr, &imm_reloc, op_hash);
+ /* The arch and priv attributes should be set before assembling. */
+ if (!start_assemble)
+ {
+ start_assemble = TRUE;
- start_assemble = TRUE;
+ /* Set the default_priv_spec according to the priv attributes. */
+ if (!riscv_set_default_priv_spec (NULL))
+ return;
+ }
+
+ const char *error = riscv_ip (str, &insn, &imm_expr, &imm_reloc, op_hash);
if (error)
{
@@ -3504,26 +3564,66 @@ s_riscv_insn (int x ATTRIBUTE_UNUSED)
demand_empty_rest_of_line ();
}
-/* Update arch attributes. */
+/* Update arch and priv attributes. If we don't set the corresponding ELF
+ attributes, then try to output the default ones. */
static void
-riscv_write_out_arch_attr (void)
+riscv_write_out_attrs (void)
{
- const char *arch_str = riscv_arch_str (xlen, &riscv_subsets);
+ const char *arch_str, *priv_str, *p;
+ /* versions[0] is major, versions[1] is minor,
+ and versions[3] is revision. */
+ unsigned versions[3] = {0}, number = 0;
+ unsigned int i;
+ /* Re-write arch attribute to normalize the arch string. */
+ arch_str = riscv_arch_str (xlen, &riscv_subsets);
bfd_elf_add_proc_attr_string (stdoutput, Tag_RISCV_arch, arch_str);
-
xfree ((void *)arch_str);
+
+ /* For the file without any instruction, we don't set the default_priv_spec
+ according to the priv attributes since the md_assemble isn't called.
+ Call riscv_set_default_priv_spec here for the above case, although
+ it seems strange. */
+ if (!start_assemble
+ && !riscv_set_default_priv_spec (NULL))
+ return;
+
+ /* Re-write priv attributes by default_priv_spec. */
+ priv_str = riscv_get_priv_spec_name (default_priv_spec);
+ p = priv_str;
+ for (i = 0; *p; ++p)
+ {
+ if (*p == '.' && i < 3)
+ {
+ versions[i++] = number;
+ number = 0;
+ }
+ else if (ISDIGIT (*p))
+ number = (number * 10) + (*p - '0');
+ else
+ {
+ as_bad (_("internal: bad RISC-V priv spec string (%s)"), priv_str);
+ return;
+ }
+ }
+ versions[i] = number;
+
+ /* Set the priv attributes. */
+ bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec, versions[0]);
+ bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec_minor, versions[1]);
+ bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec_revision, versions[2]);
}
-/* Add the default contents for the .riscv.attributes section. */
+/* Add the default contents for the .riscv.attributes section. If any
+ ELF attribute or -march-attr options is set, call riscv_write_out_attrs
+ to update the arch and priv attributes. */
static void
riscv_set_public_attributes (void)
{
- if (riscv_opts.arch_attr || explicit_arch_attr)
- /* Re-write arch attribute to normalize the arch string. */
- riscv_write_out_arch_attr ();
+ if (riscv_opts.arch_attr || explicit_attr)
+ riscv_write_out_attrs ();
}
/* Called after all assembly has been done. */
@@ -3577,13 +3677,14 @@ static void
s_riscv_attribute (int ignored ATTRIBUTE_UNUSED)
{
int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
+ unsigned old_xlen;
+ obj_attribute *attr;
- if (tag == Tag_RISCV_arch)
+ explicit_attr = TRUE;
+ switch (tag)
{
- unsigned old_xlen = xlen;
-
- explicit_arch_attr = TRUE;
- obj_attribute *attr;
+ case Tag_RISCV_arch:
+ old_xlen = xlen;
attr = elf_known_obj_attributes_proc (stdoutput);
if (!start_assemble)
riscv_set_arch (attr[Tag_RISCV_arch].s);
@@ -3599,6 +3700,17 @@ s_riscv_attribute (int ignored ATTRIBUTE_UNUSED)
if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach))
as_warn (_("Could not set architecture and machine"));
}
+ break;
+
+ case Tag_RISCV_priv_spec:
+ case Tag_RISCV_priv_spec_minor:
+ case Tag_RISCV_priv_spec_revision:
+ if (start_assemble)
+ as_fatal (_(".attribute priv spec must set before any instructions"));
+ break;
+
+ default:
+ break;
}
}
diff --git a/gas/testsuite/gas/riscv/attribute-01.d b/gas/testsuite/gas/riscv/attribute-01.d
index 2e19e09..f027347 100644
--- a/gas/testsuite/gas/riscv/attribute-01.d
+++ b/gas/testsuite/gas/riscv/attribute-01.d
@@ -4,3 +4,6 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0"
+ Tag_RISCV_priv_spec: [0-9_\"].*
+ Tag_RISCV_priv_spec_minor: [0-9_\"].*
+#...
diff --git a/gas/testsuite/gas/riscv/attribute-02.d b/gas/testsuite/gas/riscv/attribute-02.d
index ae0195e..02b532d 100644
--- a/gas/testsuite/gas/riscv/attribute-02.d
+++ b/gas/testsuite/gas/riscv/attribute-02.d
@@ -4,3 +4,6 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_xargle0p0"
+ Tag_RISCV_priv_spec: [0-9_\"].*
+ Tag_RISCV_priv_spec_minor: [0-9_\"].*
+#...
diff --git a/gas/testsuite/gas/riscv/attribute-03.d b/gas/testsuite/gas/riscv/attribute-03.d
index 9916ff6..ded529a 100644
--- a/gas/testsuite/gas/riscv/attribute-03.d
+++ b/gas/testsuite/gas/riscv/attribute-03.d
@@ -4,3 +4,6 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_xargle0p0_xfoo0p0"
+ Tag_RISCV_priv_spec: [0-9_\"].*
+ Tag_RISCV_priv_spec_minor: [0-9_\"].*
+#...
diff --git a/gas/testsuite/gas/riscv/attribute-04.d b/gas/testsuite/gas/riscv/attribute-04.d
index 408464d..df6c818 100644
--- a/gas/testsuite/gas/riscv/attribute-04.d
+++ b/gas/testsuite/gas/riscv/attribute-04.d
@@ -4,3 +4,6 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0"
+ Tag_RISCV_priv_spec: [0-9_\"].*
+ Tag_RISCV_priv_spec_minor: [0-9_\"].*
+#...
diff --git a/gas/testsuite/gas/riscv/attribute-05.d b/gas/testsuite/gas/riscv/attribute-05.d
index ad24834..247f52e 100644
--- a/gas/testsuite/gas/riscv/attribute-05.d
+++ b/gas/testsuite/gas/riscv/attribute-05.d
@@ -7,5 +7,5 @@ File Attributes
Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0"
Tag_RISCV_unaligned_access: Unaligned access
Tag_RISCV_priv_spec: 1
- Tag_RISCV_priv_spec_minor: 2
- Tag_RISCV_priv_spec_revision: 3
+ Tag_RISCV_priv_spec_minor: 9
+ Tag_RISCV_priv_spec_revision: 1
diff --git a/gas/testsuite/gas/riscv/attribute-05.s b/gas/testsuite/gas/riscv/attribute-05.s
index 3b3b7f6..4920309 100644
--- a/gas/testsuite/gas/riscv/attribute-05.s
+++ b/gas/testsuite/gas/riscv/attribute-05.s
@@ -1,6 +1,6 @@
.attribute arch, "rv32g"
.attribute priv_spec, 1
- .attribute priv_spec_minor, 2
- .attribute priv_spec_revision, 3
+ .attribute priv_spec_minor, 9
+ .attribute priv_spec_revision, 1
.attribute unaligned_access, 1
.attribute stack_align, 16
diff --git a/gas/testsuite/gas/riscv/attribute-06.d b/gas/testsuite/gas/riscv/attribute-06.d
index a2dd9fb..e1d62c4 100644
--- a/gas/testsuite/gas/riscv/attribute-06.d
+++ b/gas/testsuite/gas/riscv/attribute-06.d
@@ -4,3 +4,6 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0"
+ Tag_RISCV_priv_spec: [0-9_\"].*
+ Tag_RISCV_priv_spec_minor: [0-9_\"].*
+#...
diff --git a/gas/testsuite/gas/riscv/attribute-07.d b/gas/testsuite/gas/riscv/attribute-07.d
index 342a537..59f02b4 100644
--- a/gas/testsuite/gas/riscv/attribute-07.d
+++ b/gas/testsuite/gas/riscv/attribute-07.d
@@ -4,3 +4,6 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv64i2p0"
+ Tag_RISCV_priv_spec: [0-9_\"].*
+ Tag_RISCV_priv_spec_minor: [0-9_\"].*
+#...
diff --git a/gas/testsuite/gas/riscv/attribute-08.d b/gas/testsuite/gas/riscv/attribute-08.d
index c10ac0c..13b82a9 100644
--- a/gas/testsuite/gas/riscv/attribute-08.d
+++ b/gas/testsuite/gas/riscv/attribute-08.d
@@ -4,3 +4,6 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32e1p9"
+ Tag_RISCV_priv_spec: [0-9_\"].*
+ Tag_RISCV_priv_spec_minor: [0-9_\"].*
+#...
diff --git a/gas/testsuite/gas/riscv/attribute-09.d b/gas/testsuite/gas/riscv/attribute-09.d
index cad1713..53945a2 100644
--- a/gas/testsuite/gas/riscv/attribute-09.d
+++ b/gas/testsuite/gas/riscv/attribute-09.d
@@ -4,3 +4,6 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p1_m2p0_zicsr0p0"
+ Tag_RISCV_priv_spec: [0-9_\"].*
+ Tag_RISCV_priv_spec_minor: [0-9_\"].*
+#...
diff --git a/gas/testsuite/gas/riscv/attribute-10.d b/gas/testsuite/gas/riscv/attribute-10.d
index ba903d1..91691fd 100644
--- a/gas/testsuite/gas/riscv/attribute-10.d
+++ b/gas/testsuite/gas/riscv/attribute-10.d
@@ -4,3 +4,6 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0"
+ Tag_RISCV_priv_spec: [0-9_\"].*
+ Tag_RISCV_priv_spec_minor: [0-9_\"].*
+#...
diff --git a/gas/testsuite/gas/riscv/attribute-unknown.d b/gas/testsuite/gas/riscv/attribute-unknown.d
index 667f21a..120e3de 100644
--- a/gas/testsuite/gas/riscv/attribute-unknown.d
+++ b/gas/testsuite/gas/riscv/attribute-unknown.d
@@ -4,5 +4,8 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
+ Tag_RISCV_priv_spec: [0-9_\"].*
+ Tag_RISCV_priv_spec_minor: [0-9_\"].*
+#...
Tag_unknown_255: "test"
Tag_unknown_256: 123 \(0x7b\)
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d
index 8dc2a10..07cf05a 100644
--- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d
@@ -1,3 +1,11 @@
-#as: -march=rv32if -mcsr-check -mpriv-spec=1.10
+#as: -march=rv32if -mcsr-check -mpriv-spec=1.10 -march-attr
#source: priv-reg.s
#warning_output: priv-reg-fail-version-1p10.l
+#readelf: -A
+
+Attribute Section: riscv
+File Attributes
+ Tag_RISCV_arch: [a-zA-Z0-9_\"].*
+ Tag_RISCV_priv_spec: 1
+ Tag_RISCV_priv_spec_minor: 10
+#...
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d
index 7d2406c..bf4b1db 100644
--- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d
@@ -1,3 +1,11 @@
-#as: -march=rv32if -mcsr-check -mpriv-spec=1.11
+#as: -march=rv32if -mcsr-check -mpriv-spec=1.11 -march-attr
#source: priv-reg.s
#warning_output: priv-reg-fail-version-1p11.l
+#readelf: -A
+
+Attribute Section: riscv
+File Attributes
+ Tag_RISCV_arch: [a-zA-Z0-9_\"].*
+ Tag_RISCV_priv_spec: 1
+ Tag_RISCV_priv_spec_minor: 11
+#...
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d
index a2db291..c914334 100644
--- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d
@@ -1,3 +1,11 @@
-#as: -march=rv32if -mcsr-check -mpriv-spec=1.9
+#as: -march=rv32if -mcsr-check -mpriv-spec=1.9 -march-attr
#source: priv-reg.s
#warning_output: priv-reg-fail-version-1p9.l
+#readelf: -A
+
+Attribute Section: riscv
+File Attributes
+ Tag_RISCV_arch: [a-zA-Z0-9_\"].*
+ Tag_RISCV_priv_spec: 1
+ Tag_RISCV_priv_spec_minor: 9
+#...
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d
index e870cf5..e2c33d8 100644
--- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d
@@ -1,3 +1,12 @@
-#as: -march=rv32if -mcsr-check -mpriv-spec=1.9.1
+#as: -march=rv32if -mcsr-check -mpriv-spec=1.9.1 -march-attr
#source: priv-reg.s
#warning_output: priv-reg-fail-version-1p9p1.l
+#readelf: -A
+
+Attribute Section: riscv
+File Attributes
+ Tag_RISCV_arch: [a-zA-Z0-9_\"].*
+ Tag_RISCV_priv_spec: 1
+ Tag_RISCV_priv_spec_minor: 9
+ Tag_RISCV_priv_spec_revision: 1
+#...
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
index 5baaba4..032f964 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
@@ -7,3 +7,6 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0_m2p0"
+ Tag_RISCV_priv_spec: [0-9_\"].*
+ Tag_RISCV_priv_spec_minor: [0-9_\"].*
+#...
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
index a7d79a1..54a7621 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
@@ -7,3 +7,6 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0_m2p0"
+ Tag_RISCV_priv_spec: [0-9_\"].*
+ Tag_RISCV_priv_spec_minor: [0-9_\"].*
+#...
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
index d46dee8..67f0437 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
@@ -7,3 +7,6 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0_m2p0_xbar2p0_xfoo2p0"
+ Tag_RISCV_priv_spec: [0-9_\"].*
+ Tag_RISCV_priv_spec_minor: [0-9_\"].*
+#...
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s
index 1ad9500..0b7ffea 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s
@@ -1,3 +1,3 @@
.attribute priv_spec, 1
- .attribute priv_spec_minor, 2
- .attribute priv_spec_revision, 3
+ .attribute priv_spec_minor, 9
+ .attribute priv_spec_revision, 1
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s
index 1ad9500..0b7ffea 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s
@@ -1,3 +1,3 @@
.attribute priv_spec, 1
- .attribute priv_spec_minor, 2
- .attribute priv_spec_revision, 3
+ .attribute priv_spec_minor, 9
+ .attribute priv_spec_revision, 1
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec.d b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec.d
index dc4c4e0..0aa6fe0 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec.d
@@ -8,5 +8,5 @@ Attribute Section: riscv
File Attributes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
Tag_RISCV_priv_spec: 1
- Tag_RISCV_priv_spec_minor: 2
- Tag_RISCV_priv_spec_revision: 3
+ Tag_RISCV_priv_spec_minor: 9
+ Tag_RISCV_priv_spec_revision: 1
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d b/ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d
index 7a5bc81..5585fac 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d
@@ -8,3 +8,6 @@ Attribute Section: riscv
File Attributes
Tag_RISCV_stack_align: 16-bytes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
+ Tag_RISCV_priv_spec: [0-9_\"].*
+ Tag_RISCV_priv_spec_minor: [0-9_\"].*
+#...
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d
index 1039930..91011a2 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d
@@ -8,3 +8,6 @@ Attribute Section: riscv
File Attributes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
Tag_RISCV_unaligned_access: Unaligned access
+ Tag_RISCV_priv_spec: [0-9_\"].*
+ Tag_RISCV_priv_spec_minor: [0-9_\"].*
+#...
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d
index 12ca1c4..5bdea27 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d
@@ -8,3 +8,6 @@ Attribute Section: riscv
File Attributes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
Tag_RISCV_unaligned_access: Unaligned access
+ Tag_RISCV_priv_spec: [0-9_\"].*
+ Tag_RISCV_priv_spec_minor: [0-9_\"].*
+#...
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d
index e41351d..ac886fb 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d
@@ -8,3 +8,6 @@ Attribute Section: riscv
File Attributes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
Tag_RISCV_unaligned_access: Unaligned access
+ Tag_RISCV_priv_spec: [0-9_\"].*
+ Tag_RISCV_priv_spec_minor: [0-9_\"].*
+#...
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d
index ac2a766..dd45f76 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d
@@ -7,3 +7,6 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
+ Tag_RISCV_priv_spec: [0-9_\"].*
+ Tag_RISCV_priv_spec_minor: [0-9_\"].*
+#...
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d
index 608c05e..ef0c154 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d
@@ -8,3 +8,6 @@ Attribute Section: riscv
File Attributes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
Tag_RISCV_unaligned_access: Unaligned access
+ Tag_RISCV_priv_spec: [0-9_\"].*
+ Tag_RISCV_priv_spec_minor: [0-9_\"].*
+#...
--
2.7.4
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [PATCH v2 7/9] RISC-V: Make privilege spec attributes workable.
2020-05-06 2:55 ` [PATCH v2 7/9] RISC-V: Make privilege spec attributes workable Nelson Chu
@ 2020-05-19 9:08 ` Nelson Chu
0 siblings, 0 replies; 25+ messages in thread
From: Nelson Chu @ 2020-05-19 9:08 UTC (permalink / raw)
To: Binutils, gdb-patches
Cc: Palmer Dabbelt, Kito Cheng, Jim Wilson, Andrew Waterman,
Andrew Burgess, Alex Bradbury, Maxim Blinov
PING :)
On Wed, May 6, 2020 at 10:55 AM Nelson Chu <nelson.chu@sifive.com> wrote:
>
> There are three privilege spec attributes, Tag_RISCV_priv_spec,
> Tag_RISCV_priv_spec_minor and Tag_RISCV_priv_spec_revision, are used to choose
> which version of privilege spec you want. You can also use -mpriv-spec option
> to choose the priv spec, but the priority of ELF attributes is the highest.
>
> Beside, we have to make sure all arch and priv attributes are set before any
> instruction.
>
> The Priority of these options,
> * ELF priv attributes > -mpriv-spec > --with-priv-spec
>
> bfd/
> * elfxx-riscv.c (riscv_estimate_digit): Remove the static.
> * elfxx-riscv.h: Updated.
>
> gas/
> * config/tc-riscv.c (explicit_attr): Rename explicit_arch_attr to
> explicit_attr. Set it to TRUE if any ELF attribute is found.
> (riscv_set_default_priv_spec): Try to set the default_priv_spec if
> the priv attributes are set.
> (md_assemble): Set the default_priv_spec according to the priv
> attributes when we start to assemble instruction.
> (riscv_write_out_attrs): Rename riscv_write_out_arch_attr to
> riscv_write_out_attrs. Update the arch and priv attributes. If we
> don't set the corresponding ELF attributes, then try to output the
> default ones.
> (riscv_set_public_attributes): If any ELF attribute or -march-attr
> options is set (explicit_attr is TRUE), then call riscv_write_out_attrs
> to update the arch and priv attributes.
> (s_riscv_attribute): Make sure all arch and priv attributes are set
> before any instruction.
>
> * testsuite/gas/riscv/attribute-01.d: Update the priv attributes if any
> ELF attribute or -march-attr is set. If the priv attributes are not
> set, then try to update them by the default setting (-mpriv-spec or
> --with-priv-spec).
> * testsuite/gas/riscv/attribute-02.d: Likewise.
> * testsuite/gas/riscv/attribute-03.d: Likewise.
> * testsuite/gas/riscv/attribute-04.d: Likewise.
> * testsuite/gas/riscv/attribute-06.d: Likewise.
> * testsuite/gas/riscv/attribute-07.d: Likewise.
> * testsuite/gas/riscv/attribute-08.d: Likewise.
> * testsuite/gas/riscv/attribute-09.d: Likewise.
> * testsuite/gas/riscv/attribute-10.d: Likewise.
> * testsuite/gas/riscv/attribute-unknown.d: Likewise.
> * testsuite/gas/riscv/attribute-05.d: Likewise. Also, the priv spec
> set by priv attributes must be supported.
> * testsuite/gas/riscv/attribute-05.s: Likewise.
>
> * testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Likewise. Updated
> priv attributes according to the -mpriv-spec option.
> * testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise.
> * testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Likewise.
> * testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise.
>
> ld/
> * testsuite/ld-riscv-elf/attr-merge-arch-01.d: Likewise.
> * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
> * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
> * testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s: Likewise.
> * testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s: Likewise.
> * testsuite/ld-riscv-elf/attr-merge-priv-spec.d: Likewise.
> * testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise.
> * testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise.
> * testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise.
> * testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise.
> * testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise.
> * testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise.
> ---
> bfd/elfxx-riscv.c | 2 +-
> bfd/elfxx-riscv.h | 3 +
> gas/config/tc-riscv.c | 154 ++++++++++++++++++---
> gas/testsuite/gas/riscv/attribute-01.d | 3 +
> gas/testsuite/gas/riscv/attribute-02.d | 3 +
> gas/testsuite/gas/riscv/attribute-03.d | 3 +
> gas/testsuite/gas/riscv/attribute-04.d | 3 +
> gas/testsuite/gas/riscv/attribute-05.d | 4 +-
> gas/testsuite/gas/riscv/attribute-05.s | 4 +-
> gas/testsuite/gas/riscv/attribute-06.d | 3 +
> gas/testsuite/gas/riscv/attribute-07.d | 3 +
> gas/testsuite/gas/riscv/attribute-08.d | 3 +
> gas/testsuite/gas/riscv/attribute-09.d | 3 +
> gas/testsuite/gas/riscv/attribute-10.d | 3 +
> gas/testsuite/gas/riscv/attribute-unknown.d | 3 +
> .../gas/riscv/priv-reg-fail-version-1p10.d | 10 +-
> .../gas/riscv/priv-reg-fail-version-1p11.d | 10 +-
> .../gas/riscv/priv-reg-fail-version-1p9.d | 10 +-
> .../gas/riscv/priv-reg-fail-version-1p9p1.d | 11 +-
> ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d | 3 +
> ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d | 3 +
> ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d | 3 +
> ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s | 4 +-
> ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s | 4 +-
> ld/testsuite/ld-riscv-elf/attr-merge-priv-spec.d | 4 +-
> ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d | 3 +
> .../ld-riscv-elf/attr-merge-strict-align-01.d | 3 +
> .../ld-riscv-elf/attr-merge-strict-align-02.d | 3 +
> .../ld-riscv-elf/attr-merge-strict-align-03.d | 3 +
> .../ld-riscv-elf/attr-merge-strict-align-04.d | 3 +
> .../ld-riscv-elf/attr-merge-strict-align-05.d | 3 +
> 31 files changed, 241 insertions(+), 36 deletions(-)
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index e025689..d06c2a5 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1650,7 +1650,7 @@ riscv_release_subset_list (riscv_subset_list_t *subset_list)
>
> /* Return the number of digits for the input. */
>
> -static size_t
> +size_t
> riscv_estimate_digit (unsigned num)
> {
> size_t digit = 0;
> diff --git a/bfd/elfxx-riscv.h b/bfd/elfxx-riscv.h
> index cbafd28..a3a0862 100644
> --- a/bfd/elfxx-riscv.h
> +++ b/bfd/elfxx-riscv.h
> @@ -90,6 +90,9 @@ riscv_release_subset_list (riscv_subset_list_t *);
> extern char *
> riscv_arch_str (unsigned, const riscv_subset_list_t *);
>
> +extern size_t
> +riscv_estimate_digit (unsigned);
> +
> /* ISA extension name class. E.g. "zbb" corresponds to RV_ISA_CLASS_Z,
> "xargs" corresponds to RV_ISA_CLASS_X, etc. Order is important
> here. */
> diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
> index 6fd1dcf..6e30a06 100644
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -116,22 +116,74 @@ riscv_set_default_isa_spec (const char *s)
> }
>
> /* Set the default_priv_spec, assembler will find the suitable CSR address
> - according to default_priv_spec. Return 0 if the input priv name isn't
> + according to default_priv_spec. We will try to check priv attributes if
> + the input string is NULL. Return 0 if the input priv spec string isn't
> supported. Otherwise, return 1. */
>
> static int
> riscv_set_default_priv_spec (const char *s)
> {
> enum riscv_priv_spec_class class;
> - if (!riscv_get_priv_spec_class (s, &class))
> + unsigned major, minor, revision;
> + obj_attribute *attr;
> + size_t buf_size;
> + char *buf;
> +
> + /* Find the corresponding priv spec class. */
> + if (riscv_get_priv_spec_class (s, &class))
> + {
> + default_priv_spec = class;
> + return 1;
> + }
> +
> + if (s != NULL)
> {
> as_bad (_("Unknown default privilege spec `%s' set by "
> "-mpriv-spec or --with-priv-spec"), s);
> return 0;
> }
> +
> + /* Try to set the default_priv_spec according to the priv attributes. */
> + attr = elf_known_obj_attributes_proc (stdoutput);
> + major = (unsigned) attr[Tag_RISCV_priv_spec].i;
> + minor = (unsigned) attr[Tag_RISCV_priv_spec_minor].i;
> + revision = (unsigned) attr[Tag_RISCV_priv_spec_revision].i;
> +
> + /* The priv attributes setting 0.0.0 is meaningless. We should have set
> + the default_priv_spec by md_parse_option and riscv_after_parse_args,
> + so just skip the following setting. */
> + if (major == 0 && minor == 0 && revision == 0)
> + return 1;
> +
> + buf_size = riscv_estimate_digit (major)
> + + 1 /* '.' */
> + + riscv_estimate_digit (minor)
> + + 1; /* string terminator */
> + if (revision != 0)
> + {
> + buf_size += 1 /* '.' */
> + + riscv_estimate_digit (revision);
> + buf = xmalloc (buf_size);
> + snprintf (buf, buf_size, "%d.%d.%d", major, minor, revision);
> + }
> else
> - default_priv_spec = class;
> - return 1;
> + {
> + buf = xmalloc (buf_size);
> + snprintf (buf, buf_size, "%d.%d", major, minor);
> + }
> +
> + if (riscv_get_priv_spec_class (buf, &class))
> + {
> + default_priv_spec = class;
> + free (buf);
> + return 1;
> + }
> +
> + /* Still can not find the priv spec class. */
> + as_bad (_("Unknown default privilege spec `%d.%d.%d' set by "
> + "privilege attributes"), major, minor, revision);
> + free (buf);
> + return 0;
> }
>
> /* This is the set of options which the .option pseudo-op may modify. */
> @@ -319,8 +371,8 @@ const char FLT_CHARS[] = "rRsSfFdDxXpP";
> /* Indicate we are already assemble any instructions or not. */
> static bfd_boolean start_assemble = FALSE;
>
> -/* Indicate arch attribute is explictly set. */
> -static bfd_boolean explicit_arch_attr = FALSE;
> +/* Indicate ELF attributes are explictly set. */
> +static bfd_boolean explicit_attr = FALSE;
>
> /* Macros for encoding relaxation state for RVC branches and far jumps. */
> #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
> @@ -2495,9 +2547,17 @@ md_assemble (char *str)
> expressionS imm_expr;
> bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
>
> - const char *error = riscv_ip (str, &insn, &imm_expr, &imm_reloc, op_hash);
> + /* The arch and priv attributes should be set before assembling. */
> + if (!start_assemble)
> + {
> + start_assemble = TRUE;
>
> - start_assemble = TRUE;
> + /* Set the default_priv_spec according to the priv attributes. */
> + if (!riscv_set_default_priv_spec (NULL))
> + return;
> + }
> +
> + const char *error = riscv_ip (str, &insn, &imm_expr, &imm_reloc, op_hash);
>
> if (error)
> {
> @@ -3504,26 +3564,66 @@ s_riscv_insn (int x ATTRIBUTE_UNUSED)
> demand_empty_rest_of_line ();
> }
>
> -/* Update arch attributes. */
> +/* Update arch and priv attributes. If we don't set the corresponding ELF
> + attributes, then try to output the default ones. */
>
> static void
> -riscv_write_out_arch_attr (void)
> +riscv_write_out_attrs (void)
> {
> - const char *arch_str = riscv_arch_str (xlen, &riscv_subsets);
> + const char *arch_str, *priv_str, *p;
> + /* versions[0] is major, versions[1] is minor,
> + and versions[3] is revision. */
> + unsigned versions[3] = {0}, number = 0;
> + unsigned int i;
>
> + /* Re-write arch attribute to normalize the arch string. */
> + arch_str = riscv_arch_str (xlen, &riscv_subsets);
> bfd_elf_add_proc_attr_string (stdoutput, Tag_RISCV_arch, arch_str);
> -
> xfree ((void *)arch_str);
> +
> + /* For the file without any instruction, we don't set the default_priv_spec
> + according to the priv attributes since the md_assemble isn't called.
> + Call riscv_set_default_priv_spec here for the above case, although
> + it seems strange. */
> + if (!start_assemble
> + && !riscv_set_default_priv_spec (NULL))
> + return;
> +
> + /* Re-write priv attributes by default_priv_spec. */
> + priv_str = riscv_get_priv_spec_name (default_priv_spec);
> + p = priv_str;
> + for (i = 0; *p; ++p)
> + {
> + if (*p == '.' && i < 3)
> + {
> + versions[i++] = number;
> + number = 0;
> + }
> + else if (ISDIGIT (*p))
> + number = (number * 10) + (*p - '0');
> + else
> + {
> + as_bad (_("internal: bad RISC-V priv spec string (%s)"), priv_str);
> + return;
> + }
> + }
> + versions[i] = number;
> +
> + /* Set the priv attributes. */
> + bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec, versions[0]);
> + bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec_minor, versions[1]);
> + bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec_revision, versions[2]);
> }
>
> -/* Add the default contents for the .riscv.attributes section. */
> +/* Add the default contents for the .riscv.attributes section. If any
> + ELF attribute or -march-attr options is set, call riscv_write_out_attrs
> + to update the arch and priv attributes. */
>
> static void
> riscv_set_public_attributes (void)
> {
> - if (riscv_opts.arch_attr || explicit_arch_attr)
> - /* Re-write arch attribute to normalize the arch string. */
> - riscv_write_out_arch_attr ();
> + if (riscv_opts.arch_attr || explicit_attr)
> + riscv_write_out_attrs ();
> }
>
> /* Called after all assembly has been done. */
> @@ -3577,13 +3677,14 @@ static void
> s_riscv_attribute (int ignored ATTRIBUTE_UNUSED)
> {
> int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
> + unsigned old_xlen;
> + obj_attribute *attr;
>
> - if (tag == Tag_RISCV_arch)
> + explicit_attr = TRUE;
> + switch (tag)
> {
> - unsigned old_xlen = xlen;
> -
> - explicit_arch_attr = TRUE;
> - obj_attribute *attr;
> + case Tag_RISCV_arch:
> + old_xlen = xlen;
> attr = elf_known_obj_attributes_proc (stdoutput);
> if (!start_assemble)
> riscv_set_arch (attr[Tag_RISCV_arch].s);
> @@ -3599,6 +3700,17 @@ s_riscv_attribute (int ignored ATTRIBUTE_UNUSED)
> if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach))
> as_warn (_("Could not set architecture and machine"));
> }
> + break;
> +
> + case Tag_RISCV_priv_spec:
> + case Tag_RISCV_priv_spec_minor:
> + case Tag_RISCV_priv_spec_revision:
> + if (start_assemble)
> + as_fatal (_(".attribute priv spec must set before any instructions"));
> + break;
> +
> + default:
> + break;
> }
> }
>
> diff --git a/gas/testsuite/gas/riscv/attribute-01.d b/gas/testsuite/gas/riscv/attribute-01.d
> index 2e19e09..f027347 100644
> --- a/gas/testsuite/gas/riscv/attribute-01.d
> +++ b/gas/testsuite/gas/riscv/attribute-01.d
> @@ -4,3 +4,6 @@
> Attribute Section: riscv
> File Attributes
> Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0"
> + Tag_RISCV_priv_spec: [0-9_\"].*
> + Tag_RISCV_priv_spec_minor: [0-9_\"].*
> +#...
> diff --git a/gas/testsuite/gas/riscv/attribute-02.d b/gas/testsuite/gas/riscv/attribute-02.d
> index ae0195e..02b532d 100644
> --- a/gas/testsuite/gas/riscv/attribute-02.d
> +++ b/gas/testsuite/gas/riscv/attribute-02.d
> @@ -4,3 +4,6 @@
> Attribute Section: riscv
> File Attributes
> Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_xargle0p0"
> + Tag_RISCV_priv_spec: [0-9_\"].*
> + Tag_RISCV_priv_spec_minor: [0-9_\"].*
> +#...
> diff --git a/gas/testsuite/gas/riscv/attribute-03.d b/gas/testsuite/gas/riscv/attribute-03.d
> index 9916ff6..ded529a 100644
> --- a/gas/testsuite/gas/riscv/attribute-03.d
> +++ b/gas/testsuite/gas/riscv/attribute-03.d
> @@ -4,3 +4,6 @@
> Attribute Section: riscv
> File Attributes
> Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_xargle0p0_xfoo0p0"
> + Tag_RISCV_priv_spec: [0-9_\"].*
> + Tag_RISCV_priv_spec_minor: [0-9_\"].*
> +#...
> diff --git a/gas/testsuite/gas/riscv/attribute-04.d b/gas/testsuite/gas/riscv/attribute-04.d
> index 408464d..df6c818 100644
> --- a/gas/testsuite/gas/riscv/attribute-04.d
> +++ b/gas/testsuite/gas/riscv/attribute-04.d
> @@ -4,3 +4,6 @@
> Attribute Section: riscv
> File Attributes
> Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0"
> + Tag_RISCV_priv_spec: [0-9_\"].*
> + Tag_RISCV_priv_spec_minor: [0-9_\"].*
> +#...
> diff --git a/gas/testsuite/gas/riscv/attribute-05.d b/gas/testsuite/gas/riscv/attribute-05.d
> index ad24834..247f52e 100644
> --- a/gas/testsuite/gas/riscv/attribute-05.d
> +++ b/gas/testsuite/gas/riscv/attribute-05.d
> @@ -7,5 +7,5 @@ File Attributes
> Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0"
> Tag_RISCV_unaligned_access: Unaligned access
> Tag_RISCV_priv_spec: 1
> - Tag_RISCV_priv_spec_minor: 2
> - Tag_RISCV_priv_spec_revision: 3
> + Tag_RISCV_priv_spec_minor: 9
> + Tag_RISCV_priv_spec_revision: 1
> diff --git a/gas/testsuite/gas/riscv/attribute-05.s b/gas/testsuite/gas/riscv/attribute-05.s
> index 3b3b7f6..4920309 100644
> --- a/gas/testsuite/gas/riscv/attribute-05.s
> +++ b/gas/testsuite/gas/riscv/attribute-05.s
> @@ -1,6 +1,6 @@
> .attribute arch, "rv32g"
> .attribute priv_spec, 1
> - .attribute priv_spec_minor, 2
> - .attribute priv_spec_revision, 3
> + .attribute priv_spec_minor, 9
> + .attribute priv_spec_revision, 1
> .attribute unaligned_access, 1
> .attribute stack_align, 16
> diff --git a/gas/testsuite/gas/riscv/attribute-06.d b/gas/testsuite/gas/riscv/attribute-06.d
> index a2dd9fb..e1d62c4 100644
> --- a/gas/testsuite/gas/riscv/attribute-06.d
> +++ b/gas/testsuite/gas/riscv/attribute-06.d
> @@ -4,3 +4,6 @@
> Attribute Section: riscv
> File Attributes
> Tag_RISCV_arch: "rv32i2p0"
> + Tag_RISCV_priv_spec: [0-9_\"].*
> + Tag_RISCV_priv_spec_minor: [0-9_\"].*
> +#...
> diff --git a/gas/testsuite/gas/riscv/attribute-07.d b/gas/testsuite/gas/riscv/attribute-07.d
> index 342a537..59f02b4 100644
> --- a/gas/testsuite/gas/riscv/attribute-07.d
> +++ b/gas/testsuite/gas/riscv/attribute-07.d
> @@ -4,3 +4,6 @@
> Attribute Section: riscv
> File Attributes
> Tag_RISCV_arch: "rv64i2p0"
> + Tag_RISCV_priv_spec: [0-9_\"].*
> + Tag_RISCV_priv_spec_minor: [0-9_\"].*
> +#...
> diff --git a/gas/testsuite/gas/riscv/attribute-08.d b/gas/testsuite/gas/riscv/attribute-08.d
> index c10ac0c..13b82a9 100644
> --- a/gas/testsuite/gas/riscv/attribute-08.d
> +++ b/gas/testsuite/gas/riscv/attribute-08.d
> @@ -4,3 +4,6 @@
> Attribute Section: riscv
> File Attributes
> Tag_RISCV_arch: "rv32e1p9"
> + Tag_RISCV_priv_spec: [0-9_\"].*
> + Tag_RISCV_priv_spec_minor: [0-9_\"].*
> +#...
> diff --git a/gas/testsuite/gas/riscv/attribute-09.d b/gas/testsuite/gas/riscv/attribute-09.d
> index cad1713..53945a2 100644
> --- a/gas/testsuite/gas/riscv/attribute-09.d
> +++ b/gas/testsuite/gas/riscv/attribute-09.d
> @@ -4,3 +4,6 @@
> Attribute Section: riscv
> File Attributes
> Tag_RISCV_arch: "rv32i2p1_m2p0_zicsr0p0"
> + Tag_RISCV_priv_spec: [0-9_\"].*
> + Tag_RISCV_priv_spec_minor: [0-9_\"].*
> +#...
> diff --git a/gas/testsuite/gas/riscv/attribute-10.d b/gas/testsuite/gas/riscv/attribute-10.d
> index ba903d1..91691fd 100644
> --- a/gas/testsuite/gas/riscv/attribute-10.d
> +++ b/gas/testsuite/gas/riscv/attribute-10.d
> @@ -4,3 +4,6 @@
> Attribute Section: riscv
> File Attributes
> Tag_RISCV_arch: "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0"
> + Tag_RISCV_priv_spec: [0-9_\"].*
> + Tag_RISCV_priv_spec_minor: [0-9_\"].*
> +#...
> diff --git a/gas/testsuite/gas/riscv/attribute-unknown.d b/gas/testsuite/gas/riscv/attribute-unknown.d
> index 667f21a..120e3de 100644
> --- a/gas/testsuite/gas/riscv/attribute-unknown.d
> +++ b/gas/testsuite/gas/riscv/attribute-unknown.d
> @@ -4,5 +4,8 @@
> Attribute Section: riscv
> File Attributes
> Tag_RISCV_arch: [a-zA-Z0-9_\"].*
> + Tag_RISCV_priv_spec: [0-9_\"].*
> + Tag_RISCV_priv_spec_minor: [0-9_\"].*
> +#...
> Tag_unknown_255: "test"
> Tag_unknown_256: 123 \(0x7b\)
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d
> index 8dc2a10..07cf05a 100644
> --- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d
> @@ -1,3 +1,11 @@
> -#as: -march=rv32if -mcsr-check -mpriv-spec=1.10
> +#as: -march=rv32if -mcsr-check -mpriv-spec=1.10 -march-attr
> #source: priv-reg.s
> #warning_output: priv-reg-fail-version-1p10.l
> +#readelf: -A
> +
> +Attribute Section: riscv
> +File Attributes
> + Tag_RISCV_arch: [a-zA-Z0-9_\"].*
> + Tag_RISCV_priv_spec: 1
> + Tag_RISCV_priv_spec_minor: 10
> +#...
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d
> index 7d2406c..bf4b1db 100644
> --- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d
> @@ -1,3 +1,11 @@
> -#as: -march=rv32if -mcsr-check -mpriv-spec=1.11
> +#as: -march=rv32if -mcsr-check -mpriv-spec=1.11 -march-attr
> #source: priv-reg.s
> #warning_output: priv-reg-fail-version-1p11.l
> +#readelf: -A
> +
> +Attribute Section: riscv
> +File Attributes
> + Tag_RISCV_arch: [a-zA-Z0-9_\"].*
> + Tag_RISCV_priv_spec: 1
> + Tag_RISCV_priv_spec_minor: 11
> +#...
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d
> index a2db291..c914334 100644
> --- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d
> @@ -1,3 +1,11 @@
> -#as: -march=rv32if -mcsr-check -mpriv-spec=1.9
> +#as: -march=rv32if -mcsr-check -mpriv-spec=1.9 -march-attr
> #source: priv-reg.s
> #warning_output: priv-reg-fail-version-1p9.l
> +#readelf: -A
> +
> +Attribute Section: riscv
> +File Attributes
> + Tag_RISCV_arch: [a-zA-Z0-9_\"].*
> + Tag_RISCV_priv_spec: 1
> + Tag_RISCV_priv_spec_minor: 9
> +#...
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d
> index e870cf5..e2c33d8 100644
> --- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d
> @@ -1,3 +1,12 @@
> -#as: -march=rv32if -mcsr-check -mpriv-spec=1.9.1
> +#as: -march=rv32if -mcsr-check -mpriv-spec=1.9.1 -march-attr
> #source: priv-reg.s
> #warning_output: priv-reg-fail-version-1p9p1.l
> +#readelf: -A
> +
> +Attribute Section: riscv
> +File Attributes
> + Tag_RISCV_arch: [a-zA-Z0-9_\"].*
> + Tag_RISCV_priv_spec: 1
> + Tag_RISCV_priv_spec_minor: 9
> + Tag_RISCV_priv_spec_revision: 1
> +#...
> diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
> index 5baaba4..032f964 100644
> --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
> +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
> @@ -7,3 +7,6 @@
> Attribute Section: riscv
> File Attributes
> Tag_RISCV_arch: "rv32i2p0_m2p0"
> + Tag_RISCV_priv_spec: [0-9_\"].*
> + Tag_RISCV_priv_spec_minor: [0-9_\"].*
> +#...
> diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
> index a7d79a1..54a7621 100644
> --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
> +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
> @@ -7,3 +7,6 @@
> Attribute Section: riscv
> File Attributes
> Tag_RISCV_arch: "rv32i2p0_m2p0"
> + Tag_RISCV_priv_spec: [0-9_\"].*
> + Tag_RISCV_priv_spec_minor: [0-9_\"].*
> +#...
> diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
> index d46dee8..67f0437 100644
> --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
> +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
> @@ -7,3 +7,6 @@
> Attribute Section: riscv
> File Attributes
> Tag_RISCV_arch: "rv32i2p0_m2p0_xbar2p0_xfoo2p0"
> + Tag_RISCV_priv_spec: [0-9_\"].*
> + Tag_RISCV_priv_spec_minor: [0-9_\"].*
> +#...
> diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s
> index 1ad9500..0b7ffea 100644
> --- a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s
> +++ b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s
> @@ -1,3 +1,3 @@
> .attribute priv_spec, 1
> - .attribute priv_spec_minor, 2
> - .attribute priv_spec_revision, 3
> + .attribute priv_spec_minor, 9
> + .attribute priv_spec_revision, 1
> diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s
> index 1ad9500..0b7ffea 100644
> --- a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s
> +++ b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s
> @@ -1,3 +1,3 @@
> .attribute priv_spec, 1
> - .attribute priv_spec_minor, 2
> - .attribute priv_spec_revision, 3
> + .attribute priv_spec_minor, 9
> + .attribute priv_spec_revision, 1
> diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec.d b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec.d
> index dc4c4e0..0aa6fe0 100644
> --- a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec.d
> +++ b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec.d
> @@ -8,5 +8,5 @@ Attribute Section: riscv
> File Attributes
> Tag_RISCV_arch: [a-zA-Z0-9_\"].*
> Tag_RISCV_priv_spec: 1
> - Tag_RISCV_priv_spec_minor: 2
> - Tag_RISCV_priv_spec_revision: 3
> + Tag_RISCV_priv_spec_minor: 9
> + Tag_RISCV_priv_spec_revision: 1
> diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d b/ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d
> index 7a5bc81..5585fac 100644
> --- a/ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d
> +++ b/ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d
> @@ -8,3 +8,6 @@ Attribute Section: riscv
> File Attributes
> Tag_RISCV_stack_align: 16-bytes
> Tag_RISCV_arch: [a-zA-Z0-9_\"].*
> + Tag_RISCV_priv_spec: [0-9_\"].*
> + Tag_RISCV_priv_spec_minor: [0-9_\"].*
> +#...
> diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d
> index 1039930..91011a2 100644
> --- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d
> +++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d
> @@ -8,3 +8,6 @@ Attribute Section: riscv
> File Attributes
> Tag_RISCV_arch: [a-zA-Z0-9_\"].*
> Tag_RISCV_unaligned_access: Unaligned access
> + Tag_RISCV_priv_spec: [0-9_\"].*
> + Tag_RISCV_priv_spec_minor: [0-9_\"].*
> +#...
> diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d
> index 12ca1c4..5bdea27 100644
> --- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d
> +++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d
> @@ -8,3 +8,6 @@ Attribute Section: riscv
> File Attributes
> Tag_RISCV_arch: [a-zA-Z0-9_\"].*
> Tag_RISCV_unaligned_access: Unaligned access
> + Tag_RISCV_priv_spec: [0-9_\"].*
> + Tag_RISCV_priv_spec_minor: [0-9_\"].*
> +#...
> diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d
> index e41351d..ac886fb 100644
> --- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d
> +++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d
> @@ -8,3 +8,6 @@ Attribute Section: riscv
> File Attributes
> Tag_RISCV_arch: [a-zA-Z0-9_\"].*
> Tag_RISCV_unaligned_access: Unaligned access
> + Tag_RISCV_priv_spec: [0-9_\"].*
> + Tag_RISCV_priv_spec_minor: [0-9_\"].*
> +#...
> diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d
> index ac2a766..dd45f76 100644
> --- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d
> +++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d
> @@ -7,3 +7,6 @@
> Attribute Section: riscv
> File Attributes
> Tag_RISCV_arch: [a-zA-Z0-9_\"].*
> + Tag_RISCV_priv_spec: [0-9_\"].*
> + Tag_RISCV_priv_spec_minor: [0-9_\"].*
> +#...
> diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d
> index 608c05e..ef0c154 100644
> --- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d
> +++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d
> @@ -8,3 +8,6 @@ Attribute Section: riscv
> File Attributes
> Tag_RISCV_arch: [a-zA-Z0-9_\"].*
> Tag_RISCV_unaligned_access: Unaligned access
> + Tag_RISCV_priv_spec: [0-9_\"].*
> + Tag_RISCV_priv_spec_minor: [0-9_\"].*
> +#...
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 8/9] RISC-V: Disassembler dumps the CSR according to the chosen privilege spec.
2020-05-06 2:55 [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR Nelson Chu
` (6 preceding siblings ...)
2020-05-06 2:55 ` [PATCH v2 7/9] RISC-V: Make privilege spec attributes workable Nelson Chu
@ 2020-05-06 2:55 ` Nelson Chu
2020-05-19 9:08 ` Nelson Chu
2020-05-06 2:55 ` [PATCH v2 9/9] RISC-V: Add documents and --help for the new GAS and OBJDUMP options Nelson Chu
2020-05-19 9:07 ` [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR Nelson Chu
9 siblings, 1 reply; 25+ messages in thread
From: Nelson Chu @ 2020-05-06 2:55 UTC (permalink / raw)
To: binutils, gdb-patches
Cc: palmer, kito.cheng, jimw, andrew, andrew.burgess, asb,
maxim.blinov, nelson.chu
Add new disassembler option -Mpriv-spec=[1.9|1.9.1|1.10|1.11] to dump the CSR
correctly. Report error message if the chosen priv version isn't supported.
Dump the CSR address direclty if it is invalid for the chosen spec.
gas/
* testsuite/gas/riscv/priv-reg.d: Removed.
* testsuite/gas/riscv/priv-reg-version-1p9.d: New test case. Dump the
CSR according to the priv spec 1.9.
* testsuite/gas/riscv/priv-reg-version-1p9p1.d: New test case. Dump the
CSR according to the priv spec 1.9.1.
* testsuite/gas/riscv/priv-reg-version-1p10.d: New test case. Dump the
CSR according to the priv spec 1.10.
* testsuite/gas/riscv/priv-reg-version-1p11.d: New test case. Dump the
CSR according to the priv spec 1.11.
opcodes/
* riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
according to the chosen version. Build a hash table riscv_csr_hash to
store the valid CSR for the chosen pirv verison. Dump the direct
CSR address rather than it's name if it is invalid.
(parse_riscv_dis_option_without_args): New function. Parse the options
without arguments.
(parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
parse the options without arguments first, and then handle the options
with arguments. Add the new option -Mpriv-spec, which has argument.
---
gas/testsuite/gas/riscv/priv-reg-version-1p10.d | 257 +++++++++++++++++++++++
gas/testsuite/gas/riscv/priv-reg-version-1p11.d | 257 +++++++++++++++++++++++
gas/testsuite/gas/riscv/priv-reg-version-1p9.d | 257 +++++++++++++++++++++++
gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d | 257 +++++++++++++++++++++++
gas/testsuite/gas/riscv/priv-reg.d | 256 ----------------------
opcodes/riscv-dis.c | 69 +++++-
6 files changed, 1090 insertions(+), 263 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/priv-reg-version-1p10.d
create mode 100644 gas/testsuite/gas/riscv/priv-reg-version-1p11.d
create mode 100644 gas/testsuite/gas/riscv/priv-reg-version-1p9.d
create mode 100644 gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
delete mode 100644 gas/testsuite/gas/riscv/priv-reg.d
diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p10.d b/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
new file mode 100644
index 0000000..3739b89
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
@@ -0,0 +1,257 @@
+#as: -march=rv32if -mpriv-spec=1.10
+#source: priv-reg.s
+#objdump: -dr -Mpriv-spec=1.10
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
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diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p11.d b/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
new file mode 100644
index 0000000..ca48abcc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
@@ -0,0 +1,257 @@
+#as: -march=rv32if -mpriv-spec=1.11
+#source: priv-reg.s
+#objdump: -dr -Mpriv-spec=1.11
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
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diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p9.d b/gas/testsuite/gas/riscv/priv-reg-version-1p9.d
new file mode 100644
index 0000000..fa3c08f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-version-1p9.d
@@ -0,0 +1,257 @@
+#as: -march=rv32if -mpriv-spec=1.9
+#source: priv-reg.s
+#objdump: -dr -Mpriv-spec=1.9
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
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diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d b/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
new file mode 100644
index 0000000..18011ed
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
@@ -0,0 +1,257 @@
+#as: -march=rv32if -mpriv-spec=1.9.1
+#source: priv-reg.s
+#objdump: -dr -Mpriv-spec=1.9.1
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
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diff --git a/gas/testsuite/gas/riscv/priv-reg.d b/gas/testsuite/gas/riscv/priv-reg.d
deleted file mode 100644
index a0c3cd7..0000000
--- a/gas/testsuite/gas/riscv/priv-reg.d
+++ /dev/null
@@ -1,256 +0,0 @@
-#as: -march=rv32if -mpriv-spec=1.11
-#objdump: -dr
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
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-[ ]+[0-9a-f]+:[ ]+3bd02573[ ]+csrr[ ]+a0,pmpaddr13
-[ ]+[0-9a-f]+:[ ]+3be02573[ ]+csrr[ ]+a0,pmpaddr14
-[ ]+[0-9a-f]+:[ ]+3bf02573[ ]+csrr[ ]+a0,pmpaddr15
-[ ]+[0-9a-f]+:[ ]+b0002573[ ]+csrr[ ]+a0,mcycle
-[ ]+[0-9a-f]+:[ ]+b0202573[ ]+csrr[ ]+a0,minstret
-[ ]+[0-9a-f]+:[ ]+b0302573[ ]+csrr[ ]+a0,mhpmcounter3
-[ ]+[0-9a-f]+:[ ]+b0402573[ ]+csrr[ ]+a0,mhpmcounter4
-[ ]+[0-9a-f]+:[ ]+b0502573[ ]+csrr[ ]+a0,mhpmcounter5
-[ ]+[0-9a-f]+:[ ]+b0602573[ ]+csrr[ ]+a0,mhpmcounter6
-[ ]+[0-9a-f]+:[ ]+b0702573[ ]+csrr[ ]+a0,mhpmcounter7
-[ ]+[0-9a-f]+:[ ]+b0802573[ ]+csrr[ ]+a0,mhpmcounter8
-[ ]+[0-9a-f]+:[ ]+b0902573[ ]+csrr[ ]+a0,mhpmcounter9
-[ ]+[0-9a-f]+:[ ]+b0a02573[ ]+csrr[ ]+a0,mhpmcounter10
-[ ]+[0-9a-f]+:[ ]+b0b02573[ ]+csrr[ ]+a0,mhpmcounter11
-[ ]+[0-9a-f]+:[ ]+b0c02573[ ]+csrr[ ]+a0,mhpmcounter12
-[ ]+[0-9a-f]+:[ ]+b0d02573[ ]+csrr[ ]+a0,mhpmcounter13
-[ ]+[0-9a-f]+:[ ]+b0e02573[ ]+csrr[ ]+a0,mhpmcounter14
-[ ]+[0-9a-f]+:[ ]+b0f02573[ ]+csrr[ ]+a0,mhpmcounter15
-[ ]+[0-9a-f]+:[ ]+b1002573[ ]+csrr[ ]+a0,mhpmcounter16
-[ ]+[0-9a-f]+:[ ]+b1102573[ ]+csrr[ ]+a0,mhpmcounter17
-[ ]+[0-9a-f]+:[ ]+b1202573[ ]+csrr[ ]+a0,mhpmcounter18
-[ ]+[0-9a-f]+:[ ]+b1302573[ ]+csrr[ ]+a0,mhpmcounter19
-[ ]+[0-9a-f]+:[ ]+b1402573[ ]+csrr[ ]+a0,mhpmcounter20
-[ ]+[0-9a-f]+:[ ]+b1502573[ ]+csrr[ ]+a0,mhpmcounter21
-[ ]+[0-9a-f]+:[ ]+b1602573[ ]+csrr[ ]+a0,mhpmcounter22
-[ ]+[0-9a-f]+:[ ]+b1702573[ ]+csrr[ ]+a0,mhpmcounter23
-[ ]+[0-9a-f]+:[ ]+b1802573[ ]+csrr[ ]+a0,mhpmcounter24
-[ ]+[0-9a-f]+:[ ]+b1902573[ ]+csrr[ ]+a0,mhpmcounter25
-[ ]+[0-9a-f]+:[ ]+b1a02573[ ]+csrr[ ]+a0,mhpmcounter26
-[ ]+[0-9a-f]+:[ ]+b1b02573[ ]+csrr[ ]+a0,mhpmcounter27
-[ ]+[0-9a-f]+:[ ]+b1c02573[ ]+csrr[ ]+a0,mhpmcounter28
-[ ]+[0-9a-f]+:[ ]+b1d02573[ ]+csrr[ ]+a0,mhpmcounter29
-[ ]+[0-9a-f]+:[ ]+b1e02573[ ]+csrr[ ]+a0,mhpmcounter30
-[ ]+[0-9a-f]+:[ ]+b1f02573[ ]+csrr[ ]+a0,mhpmcounter31
-[ ]+[0-9a-f]+:[ ]+b8002573[ ]+csrr[ ]+a0,mcycleh
-[ ]+[0-9a-f]+:[ ]+b8202573[ ]+csrr[ ]+a0,minstreth
-[ ]+[0-9a-f]+:[ ]+b8302573[ ]+csrr[ ]+a0,mhpmcounter3h
-[ ]+[0-9a-f]+:[ ]+b8402573[ ]+csrr[ ]+a0,mhpmcounter4h
-[ ]+[0-9a-f]+:[ ]+b8502573[ ]+csrr[ ]+a0,mhpmcounter5h
-[ ]+[0-9a-f]+:[ ]+b8602573[ ]+csrr[ ]+a0,mhpmcounter6h
-[ ]+[0-9a-f]+:[ ]+b8702573[ ]+csrr[ ]+a0,mhpmcounter7h
-[ ]+[0-9a-f]+:[ ]+b8802573[ ]+csrr[ ]+a0,mhpmcounter8h
-[ ]+[0-9a-f]+:[ ]+b8902573[ ]+csrr[ ]+a0,mhpmcounter9h
-[ ]+[0-9a-f]+:[ ]+b8a02573[ ]+csrr[ ]+a0,mhpmcounter10h
-[ ]+[0-9a-f]+:[ ]+b8b02573[ ]+csrr[ ]+a0,mhpmcounter11h
-[ ]+[0-9a-f]+:[ ]+b8c02573[ ]+csrr[ ]+a0,mhpmcounter12h
-[ ]+[0-9a-f]+:[ ]+b8d02573[ ]+csrr[ ]+a0,mhpmcounter13h
-[ ]+[0-9a-f]+:[ ]+b8e02573[ ]+csrr[ ]+a0,mhpmcounter14h
-[ ]+[0-9a-f]+:[ ]+b8f02573[ ]+csrr[ ]+a0,mhpmcounter15h
-[ ]+[0-9a-f]+:[ ]+b9002573[ ]+csrr[ ]+a0,mhpmcounter16h
-[ ]+[0-9a-f]+:[ ]+b9102573[ ]+csrr[ ]+a0,mhpmcounter17h
-[ ]+[0-9a-f]+:[ ]+b9202573[ ]+csrr[ ]+a0,mhpmcounter18h
-[ ]+[0-9a-f]+:[ ]+b9302573[ ]+csrr[ ]+a0,mhpmcounter19h
-[ ]+[0-9a-f]+:[ ]+b9402573[ ]+csrr[ ]+a0,mhpmcounter20h
-[ ]+[0-9a-f]+:[ ]+b9502573[ ]+csrr[ ]+a0,mhpmcounter21h
-[ ]+[0-9a-f]+:[ ]+b9602573[ ]+csrr[ ]+a0,mhpmcounter22h
-[ ]+[0-9a-f]+:[ ]+b9702573[ ]+csrr[ ]+a0,mhpmcounter23h
-[ ]+[0-9a-f]+:[ ]+b9802573[ ]+csrr[ ]+a0,mhpmcounter24h
-[ ]+[0-9a-f]+:[ ]+b9902573[ ]+csrr[ ]+a0,mhpmcounter25h
-[ ]+[0-9a-f]+:[ ]+b9a02573[ ]+csrr[ ]+a0,mhpmcounter26h
-[ ]+[0-9a-f]+:[ ]+b9b02573[ ]+csrr[ ]+a0,mhpmcounter27h
-[ ]+[0-9a-f]+:[ ]+b9c02573[ ]+csrr[ ]+a0,mhpmcounter28h
-[ ]+[0-9a-f]+:[ ]+b9d02573[ ]+csrr[ ]+a0,mhpmcounter29h
-[ ]+[0-9a-f]+:[ ]+b9e02573[ ]+csrr[ ]+a0,mhpmcounter30h
-[ ]+[0-9a-f]+:[ ]+b9f02573[ ]+csrr[ ]+a0,mhpmcounter31h
-[ ]+[0-9a-f]+:[ ]+32002573[ ]+csrr[ ]+a0,mcountinhibit
-[ ]+[0-9a-f]+:[ ]+32302573[ ]+csrr[ ]+a0,mhpmevent3
-[ ]+[0-9a-f]+:[ ]+32402573[ ]+csrr[ ]+a0,mhpmevent4
-[ ]+[0-9a-f]+:[ ]+32502573[ ]+csrr[ ]+a0,mhpmevent5
-[ ]+[0-9a-f]+:[ ]+32602573[ ]+csrr[ ]+a0,mhpmevent6
-[ ]+[0-9a-f]+:[ ]+32702573[ ]+csrr[ ]+a0,mhpmevent7
-[ ]+[0-9a-f]+:[ ]+32802573[ ]+csrr[ ]+a0,mhpmevent8
-[ ]+[0-9a-f]+:[ ]+32902573[ ]+csrr[ ]+a0,mhpmevent9
-[ ]+[0-9a-f]+:[ ]+32a02573[ ]+csrr[ ]+a0,mhpmevent10
-[ ]+[0-9a-f]+:[ ]+32b02573[ ]+csrr[ ]+a0,mhpmevent11
-[ ]+[0-9a-f]+:[ ]+32c02573[ ]+csrr[ ]+a0,mhpmevent12
-[ ]+[0-9a-f]+:[ ]+32d02573[ ]+csrr[ ]+a0,mhpmevent13
-[ ]+[0-9a-f]+:[ ]+32e02573[ ]+csrr[ ]+a0,mhpmevent14
-[ ]+[0-9a-f]+:[ ]+32f02573[ ]+csrr[ ]+a0,mhpmevent15
-[ ]+[0-9a-f]+:[ ]+33002573[ ]+csrr[ ]+a0,mhpmevent16
-[ ]+[0-9a-f]+:[ ]+33102573[ ]+csrr[ ]+a0,mhpmevent17
-[ ]+[0-9a-f]+:[ ]+33202573[ ]+csrr[ ]+a0,mhpmevent18
-[ ]+[0-9a-f]+:[ ]+33302573[ ]+csrr[ ]+a0,mhpmevent19
-[ ]+[0-9a-f]+:[ ]+33402573[ ]+csrr[ ]+a0,mhpmevent20
-[ ]+[0-9a-f]+:[ ]+33502573[ ]+csrr[ ]+a0,mhpmevent21
-[ ]+[0-9a-f]+:[ ]+33602573[ ]+csrr[ ]+a0,mhpmevent22
-[ ]+[0-9a-f]+:[ ]+33702573[ ]+csrr[ ]+a0,mhpmevent23
-[ ]+[0-9a-f]+:[ ]+33802573[ ]+csrr[ ]+a0,mhpmevent24
-[ ]+[0-9a-f]+:[ ]+33902573[ ]+csrr[ ]+a0,mhpmevent25
-[ ]+[0-9a-f]+:[ ]+33a02573[ ]+csrr[ ]+a0,mhpmevent26
-[ ]+[0-9a-f]+:[ ]+33b02573[ ]+csrr[ ]+a0,mhpmevent27
-[ ]+[0-9a-f]+:[ ]+33c02573[ ]+csrr[ ]+a0,mhpmevent28
-[ ]+[0-9a-f]+:[ ]+33d02573[ ]+csrr[ ]+a0,mhpmevent29
-[ ]+[0-9a-f]+:[ ]+33e02573[ ]+csrr[ ]+a0,mhpmevent30
-[ ]+[0-9a-f]+:[ ]+33f02573[ ]+csrr[ ]+a0,mhpmevent31
-[ ]+[0-9a-f]+:[ ]+7a002573[ ]+csrr[ ]+a0,tselect
-[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
-[ ]+[0-9a-f]+:[ ]+7a202573[ ]+csrr[ ]+a0,tdata2
-[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
-[ ]+[0-9a-f]+:[ ]+7b002573[ ]+csrr[ ]+a0,dcsr
-[ ]+[0-9a-f]+:[ ]+7b102573[ ]+csrr[ ]+a0,dpc
-[ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch0
-[ ]+[0-9a-f]+:[ ]+7b302573[ ]+csrr[ ]+a0,dscratch1
-[ ]+[0-9a-f]+:[ ]+04302573[ ]+csrr[ ]+a0,utval
-[ ]+[0-9a-f]+:[ ]+14302573[ ]+csrr[ ]+a0,stval
-[ ]+[0-9a-f]+:[ ]+18002573[ ]+csrr[ ]+a0,satp
-[ ]+[0-9a-f]+:[ ]+34302573[ ]+csrr[ ]+a0,mtval
-[ ]+[0-9a-f]+:[ ]+32002573[ ]+csrr[ ]+a0,mcountinhibit
-[ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch0
-[ ]+[0-9a-f]+:[ ]+20002573[ ]+csrr[ ]+a0,hstatus
-[ ]+[0-9a-f]+:[ ]+20202573[ ]+csrr[ ]+a0,hedeleg
-[ ]+[0-9a-f]+:[ ]+20302573[ ]+csrr[ ]+a0,hideleg
-[ ]+[0-9a-f]+:[ ]+20402573[ ]+csrr[ ]+a0,hie
-[ ]+[0-9a-f]+:[ ]+20502573[ ]+csrr[ ]+a0,htvec
-[ ]+[0-9a-f]+:[ ]+24002573[ ]+csrr[ ]+a0,hscratch
-[ ]+[0-9a-f]+:[ ]+24102573[ ]+csrr[ ]+a0,hepc
-[ ]+[0-9a-f]+:[ ]+24202573[ ]+csrr[ ]+a0,hcause
-[ ]+[0-9a-f]+:[ ]+24302573[ ]+csrr[ ]+a0,hbadaddr
-[ ]+[0-9a-f]+:[ ]+24402573[ ]+csrr[ ]+a0,hip
-[ ]+[0-9a-f]+:[ ]+38002573[ ]+csrr[ ]+a0,mbase
-[ ]+[0-9a-f]+:[ ]+38102573[ ]+csrr[ ]+a0,mbound
-[ ]+[0-9a-f]+:[ ]+38202573[ ]+csrr[ ]+a0,mibase
-[ ]+[0-9a-f]+:[ ]+38302573[ ]+csrr[ ]+a0,mibound
-[ ]+[0-9a-f]+:[ ]+38402573[ ]+csrr[ ]+a0,mdbase
-[ ]+[0-9a-f]+:[ ]+38502573[ ]+csrr[ ]+a0,mdbound
-[ ]+[0-9a-f]+:[ ]+32102573[ ]+csrr[ ]+a0,mscounteren
-[ ]+[0-9a-f]+:[ ]+32202573[ ]+csrr[ ]+a0,mhcounteren
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 98302ff..c5a0d36 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -31,6 +31,8 @@
#include "bfd_stdint.h"
#include <ctype.h>
+static enum riscv_priv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE;
+
struct riscv_private_data
{
bfd_vma gp;
@@ -52,8 +54,8 @@ set_default_riscv_dis_options (void)
no_aliases = 0;
}
-static void
-parse_riscv_dis_option (const char *option)
+static bfd_boolean
+parse_riscv_dis_option_without_args (const char *option)
{
if (strcmp (option, "no-aliases") == 0)
no_aliases = 1;
@@ -63,6 +65,44 @@ parse_riscv_dis_option (const char *option)
riscv_fpr_names = riscv_fpr_names_numeric;
}
else
+ return FALSE;
+ return TRUE;
+}
+
+static void
+parse_riscv_dis_option (const char *option)
+{
+ char *equal, *value;
+
+ if (parse_riscv_dis_option_without_args (option))
+ return;
+
+ equal = strchr (option, '=');
+ if (equal == NULL)
+ {
+ /* The option without '=' should be defined above. */
+ opcodes_error_handler (_("unrecognized disassembler option: %s"), option);
+ return;
+ }
+ if (equal == option
+ || *(equal + 1) == '\0')
+ {
+ /* Invalid options with '=', no option name before '=',
+ and no value after '='. */
+ opcodes_error_handler (_("unrecognized disassembler option with '=': %s"),
+ option);
+ return;
+ }
+
+ *equal = '\0';
+ value = equal + 1;
+ if (strcmp (option, "priv-spec") == 0)
+ {
+ if (!riscv_get_priv_spec_class (value, &default_priv_spec))
+ opcodes_error_handler (_("unknown privilege spec set by %s=%s"),
+ option, value);
+ }
+ else
{
/* xgettext:c-format */
opcodes_error_handler (_("unrecognized disassembler option: %s"), option);
@@ -322,17 +362,32 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
case 'E':
{
- const char* csr_name = NULL;
+ static const char *riscv_csr_hash[4096]; /* Total 2^12 CSR */
+ static bfd_boolean init_csr = FALSE;
unsigned int csr = EXTRACT_OPERAND (CSR, l);
- switch (csr)
+
+ if (!init_csr)
{
+ unsigned int i;
+ for (i = 0; i < 4096; i++)
+ riscv_csr_hash[i] = NULL;
+
+ /* Set to the newest privilege version. */
+ if (default_priv_spec == PRIV_SPEC_CLASS_NONE)
+ default_priv_spec = PRIV_SPEC_CLASS_DRAFT - 1;
+
#define DECLARE_CSR(name, num, class, define_version, abort_version) \
- case num: csr_name = #name; break;
+ if (default_priv_spec >= define_version \
+ && default_priv_spec < abort_version) \
+ riscv_csr_hash[num] = #name;
+#define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
+ DECLARE_CSR(name, num, class, define_version, abort_version)
#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
}
- if (csr_name)
- print (info->stream, "%s", csr_name);
+
+ if (riscv_csr_hash[csr] != NULL)
+ print (info->stream, "%s", riscv_csr_hash[csr]);
else
print (info->stream, "0x%x", csr);
break;
--
2.7.4
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [PATCH v2 8/9] RISC-V: Disassembler dumps the CSR according to the chosen privilege spec.
2020-05-06 2:55 ` [PATCH v2 8/9] RISC-V: Disassembler dumps the CSR according to the chosen privilege spec Nelson Chu
@ 2020-05-19 9:08 ` Nelson Chu
0 siblings, 0 replies; 25+ messages in thread
From: Nelson Chu @ 2020-05-19 9:08 UTC (permalink / raw)
To: Binutils, gdb-patches
Cc: Palmer Dabbelt, Kito Cheng, Jim Wilson, Andrew Waterman,
Andrew Burgess, Alex Bradbury, Maxim Blinov
PING :)
On Wed, May 6, 2020 at 10:56 AM Nelson Chu <nelson.chu@sifive.com> wrote:
>
> Add new disassembler option -Mpriv-spec=[1.9|1.9.1|1.10|1.11] to dump the CSR
> correctly. Report error message if the chosen priv version isn't supported.
> Dump the CSR address direclty if it is invalid for the chosen spec.
>
> gas/
> * testsuite/gas/riscv/priv-reg.d: Removed.
> * testsuite/gas/riscv/priv-reg-version-1p9.d: New test case. Dump the
> CSR according to the priv spec 1.9.
> * testsuite/gas/riscv/priv-reg-version-1p9p1.d: New test case. Dump the
> CSR according to the priv spec 1.9.1.
> * testsuite/gas/riscv/priv-reg-version-1p10.d: New test case. Dump the
> CSR according to the priv spec 1.10.
> * testsuite/gas/riscv/priv-reg-version-1p11.d: New test case. Dump the
> CSR according to the priv spec 1.11.
>
> opcodes/
> * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
> according to the chosen version. Build a hash table riscv_csr_hash to
> store the valid CSR for the chosen pirv verison. Dump the direct
> CSR address rather than it's name if it is invalid.
> (parse_riscv_dis_option_without_args): New function. Parse the options
> without arguments.
> (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
> parse the options without arguments first, and then handle the options
> with arguments. Add the new option -Mpriv-spec, which has argument.
> ---
> gas/testsuite/gas/riscv/priv-reg-version-1p10.d | 257 +++++++++++++++++++++++
> gas/testsuite/gas/riscv/priv-reg-version-1p11.d | 257 +++++++++++++++++++++++
> gas/testsuite/gas/riscv/priv-reg-version-1p9.d | 257 +++++++++++++++++++++++
> gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d | 257 +++++++++++++++++++++++
> gas/testsuite/gas/riscv/priv-reg.d | 256 ----------------------
> opcodes/riscv-dis.c | 69 +++++-
> 6 files changed, 1090 insertions(+), 263 deletions(-)
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-version-1p10.d
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-version-1p11.d
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-version-1p9.d
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
> delete mode 100644 gas/testsuite/gas/riscv/priv-reg.d
>
> diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p10.d b/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
> new file mode 100644
> index 0000000..3739b89
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
> @@ -0,0 +1,257 @@
> +#as: -march=rv32if -mpriv-spec=1.10
> +#source: priv-reg.s
> +#objdump: -dr -Mpriv-spec=1.10
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <.text>:
> +[ ]+[0-9a-f]+:[ ]+00002573[ ]+csrr[ ]+a0,ustatus
> +[ ]+[0-9a-f]+:[ ]+00402573[ ]+csrr[ ]+a0,uie
> +[ ]+[0-9a-f]+:[ ]+00502573[ ]+csrr[ ]+a0,utvec
> +[ ]+[0-9a-f]+:[ ]+04002573[ ]+csrr[ ]+a0,uscratch
> +[ ]+[0-9a-f]+:[ ]+04102573[ ]+csrr[ ]+a0,uepc
> +[ ]+[0-9a-f]+:[ ]+04202573[ ]+csrr[ ]+a0,ucause
> +[ ]+[0-9a-f]+:[ ]+04302573[ ]+csrr[ ]+a0,utval
> +[ ]+[0-9a-f]+:[ ]+04402573[ ]+csrr[ ]+a0,uip
> +[ ]+[0-9a-f]+:[ ]+00102573[ ]+frflags[ ]+a0
> +[ ]+[0-9a-f]+:[ ]+00202573[ ]+frrm[ ]+a0
> +[ ]+[0-9a-f]+:[ ]+00302573[ ]+frcsr[ ]+a0
> +[ ]+[0-9a-f]+:[ ]+c0002573[ ]+rdcycle[ ]+a0
> +[ ]+[0-9a-f]+:[ ]+c0102573[ ]+rdtime[ ]+a0
> +[ ]+[0-9a-f]+:[ ]+c0202573[ ]+rdinstret[ ]+a0
> +[ ]+[0-9a-f]+:[ ]+c0302573[ ]+csrr[ ]+a0,hpmcounter3
> +[ ]+[0-9a-f]+:[ ]+c0402573[ ]+csrr[ ]+a0,hpmcounter4
> +[ ]+[0-9a-f]+:[ ]+c0502573[ ]+csrr[ ]+a0,hpmcounter5
> +[ ]+[0-9a-f]+:[ ]+c0602573[ ]+csrr[ ]+a0,hpmcounter6
> +[ ]+[0-9a-f]+:[ ]+c0702573[ ]+csrr[ ]+a0,hpmcounter7
> +[ ]+[0-9a-f]+:[ ]+c0802573[ ]+csrr[ ]+a0,hpmcounter8
> +[ ]+[0-9a-f]+:[ ]+c0902573[ ]+csrr[ ]+a0,hpmcounter9
> +[ ]+[0-9a-f]+:[ ]+c0a02573[ ]+csrr[ ]+a0,hpmcounter10
> +[ ]+[0-9a-f]+:[ ]+c0b02573[ ]+csrr[ ]+a0,hpmcounter11
> +[ ]+[0-9a-f]+:[ ]+c0c02573[ ]+csrr[ ]+a0,hpmcounter12
> +[ ]+[0-9a-f]+:[ ]+c0d02573[ ]+csrr[ ]+a0,hpmcounter13
> +[ ]+[0-9a-f]+:[ ]+c0e02573[ ]+csrr[ ]+a0,hpmcounter14
> +[ ]+[0-9a-f]+:[ ]+c0f02573[ ]+csrr[ ]+a0,hpmcounter15
> +[ ]+[0-9a-f]+:[ ]+c1002573[ ]+csrr[ ]+a0,hpmcounter16
> +[ ]+[0-9a-f]+:[ ]+c1102573[ ]+csrr[ ]+a0,hpmcounter17
> +[ ]+[0-9a-f]+:[ ]+c1202573[ ]+csrr[ ]+a0,hpmcounter18
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> diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p11.d b/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
> new file mode 100644
> index 0000000..ca48abcc
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
> @@ -0,0 +1,257 @@
> +#as: -march=rv32if -mpriv-spec=1.11
> +#source: priv-reg.s
> +#objdump: -dr -Mpriv-spec=1.11
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <.text>:
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> diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p9.d b/gas/testsuite/gas/riscv/priv-reg-version-1p9.d
> new file mode 100644
> index 0000000..fa3c08f
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-version-1p9.d
> @@ -0,0 +1,257 @@
> +#as: -march=rv32if -mpriv-spec=1.9
> +#source: priv-reg.s
> +#objdump: -dr -Mpriv-spec=1.9
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <.text>:
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> diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d b/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
> new file mode 100644
> index 0000000..18011ed
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
> @@ -0,0 +1,257 @@
> +#as: -march=rv32if -mpriv-spec=1.9.1
> +#source: priv-reg.s
> +#objdump: -dr -Mpriv-spec=1.9.1
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <.text>:
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> diff --git a/gas/testsuite/gas/riscv/priv-reg.d b/gas/testsuite/gas/riscv/priv-reg.d
> deleted file mode 100644
> index a0c3cd7..0000000
> --- a/gas/testsuite/gas/riscv/priv-reg.d
> +++ /dev/null
> @@ -1,256 +0,0 @@
> -#as: -march=rv32if -mpriv-spec=1.11
> -#objdump: -dr
> -
> -.*:[ ]+file format .*
> -
> -
> -Disassembly of section .text:
> -
> -0+000 <.text>:
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> -[ ]+[0-9a-f]+:[ ]+3b902573[ ]+csrr[ ]+a0,pmpaddr9
> -[ ]+[0-9a-f]+:[ ]+3ba02573[ ]+csrr[ ]+a0,pmpaddr10
> -[ ]+[0-9a-f]+:[ ]+3bb02573[ ]+csrr[ ]+a0,pmpaddr11
> -[ ]+[0-9a-f]+:[ ]+3bc02573[ ]+csrr[ ]+a0,pmpaddr12
> -[ ]+[0-9a-f]+:[ ]+3bd02573[ ]+csrr[ ]+a0,pmpaddr13
> -[ ]+[0-9a-f]+:[ ]+3be02573[ ]+csrr[ ]+a0,pmpaddr14
> -[ ]+[0-9a-f]+:[ ]+3bf02573[ ]+csrr[ ]+a0,pmpaddr15
> -[ ]+[0-9a-f]+:[ ]+b0002573[ ]+csrr[ ]+a0,mcycle
> -[ ]+[0-9a-f]+:[ ]+b0202573[ ]+csrr[ ]+a0,minstret
> -[ ]+[0-9a-f]+:[ ]+b0302573[ ]+csrr[ ]+a0,mhpmcounter3
> -[ ]+[0-9a-f]+:[ ]+b0402573[ ]+csrr[ ]+a0,mhpmcounter4
> -[ ]+[0-9a-f]+:[ ]+b0502573[ ]+csrr[ ]+a0,mhpmcounter5
> -[ ]+[0-9a-f]+:[ ]+b0602573[ ]+csrr[ ]+a0,mhpmcounter6
> -[ ]+[0-9a-f]+:[ ]+b0702573[ ]+csrr[ ]+a0,mhpmcounter7
> -[ ]+[0-9a-f]+:[ ]+b0802573[ ]+csrr[ ]+a0,mhpmcounter8
> -[ ]+[0-9a-f]+:[ ]+b0902573[ ]+csrr[ ]+a0,mhpmcounter9
> -[ ]+[0-9a-f]+:[ ]+b0a02573[ ]+csrr[ ]+a0,mhpmcounter10
> -[ ]+[0-9a-f]+:[ ]+b0b02573[ ]+csrr[ ]+a0,mhpmcounter11
> -[ ]+[0-9a-f]+:[ ]+b0c02573[ ]+csrr[ ]+a0,mhpmcounter12
> -[ ]+[0-9a-f]+:[ ]+b0d02573[ ]+csrr[ ]+a0,mhpmcounter13
> -[ ]+[0-9a-f]+:[ ]+b0e02573[ ]+csrr[ ]+a0,mhpmcounter14
> -[ ]+[0-9a-f]+:[ ]+b0f02573[ ]+csrr[ ]+a0,mhpmcounter15
> -[ ]+[0-9a-f]+:[ ]+b1002573[ ]+csrr[ ]+a0,mhpmcounter16
> -[ ]+[0-9a-f]+:[ ]+b1102573[ ]+csrr[ ]+a0,mhpmcounter17
> -[ ]+[0-9a-f]+:[ ]+b1202573[ ]+csrr[ ]+a0,mhpmcounter18
> -[ ]+[0-9a-f]+:[ ]+b1302573[ ]+csrr[ ]+a0,mhpmcounter19
> -[ ]+[0-9a-f]+:[ ]+b1402573[ ]+csrr[ ]+a0,mhpmcounter20
> -[ ]+[0-9a-f]+:[ ]+b1502573[ ]+csrr[ ]+a0,mhpmcounter21
> -[ ]+[0-9a-f]+:[ ]+b1602573[ ]+csrr[ ]+a0,mhpmcounter22
> -[ ]+[0-9a-f]+:[ ]+b1702573[ ]+csrr[ ]+a0,mhpmcounter23
> -[ ]+[0-9a-f]+:[ ]+b1802573[ ]+csrr[ ]+a0,mhpmcounter24
> -[ ]+[0-9a-f]+:[ ]+b1902573[ ]+csrr[ ]+a0,mhpmcounter25
> -[ ]+[0-9a-f]+:[ ]+b1a02573[ ]+csrr[ ]+a0,mhpmcounter26
> -[ ]+[0-9a-f]+:[ ]+b1b02573[ ]+csrr[ ]+a0,mhpmcounter27
> -[ ]+[0-9a-f]+:[ ]+b1c02573[ ]+csrr[ ]+a0,mhpmcounter28
> -[ ]+[0-9a-f]+:[ ]+b1d02573[ ]+csrr[ ]+a0,mhpmcounter29
> -[ ]+[0-9a-f]+:[ ]+b1e02573[ ]+csrr[ ]+a0,mhpmcounter30
> -[ ]+[0-9a-f]+:[ ]+b1f02573[ ]+csrr[ ]+a0,mhpmcounter31
> -[ ]+[0-9a-f]+:[ ]+b8002573[ ]+csrr[ ]+a0,mcycleh
> -[ ]+[0-9a-f]+:[ ]+b8202573[ ]+csrr[ ]+a0,minstreth
> -[ ]+[0-9a-f]+:[ ]+b8302573[ ]+csrr[ ]+a0,mhpmcounter3h
> -[ ]+[0-9a-f]+:[ ]+b8402573[ ]+csrr[ ]+a0,mhpmcounter4h
> -[ ]+[0-9a-f]+:[ ]+b8502573[ ]+csrr[ ]+a0,mhpmcounter5h
> -[ ]+[0-9a-f]+:[ ]+b8602573[ ]+csrr[ ]+a0,mhpmcounter6h
> -[ ]+[0-9a-f]+:[ ]+b8702573[ ]+csrr[ ]+a0,mhpmcounter7h
> -[ ]+[0-9a-f]+:[ ]+b8802573[ ]+csrr[ ]+a0,mhpmcounter8h
> -[ ]+[0-9a-f]+:[ ]+b8902573[ ]+csrr[ ]+a0,mhpmcounter9h
> -[ ]+[0-9a-f]+:[ ]+b8a02573[ ]+csrr[ ]+a0,mhpmcounter10h
> -[ ]+[0-9a-f]+:[ ]+b8b02573[ ]+csrr[ ]+a0,mhpmcounter11h
> -[ ]+[0-9a-f]+:[ ]+b8c02573[ ]+csrr[ ]+a0,mhpmcounter12h
> -[ ]+[0-9a-f]+:[ ]+b8d02573[ ]+csrr[ ]+a0,mhpmcounter13h
> -[ ]+[0-9a-f]+:[ ]+b8e02573[ ]+csrr[ ]+a0,mhpmcounter14h
> -[ ]+[0-9a-f]+:[ ]+b8f02573[ ]+csrr[ ]+a0,mhpmcounter15h
> -[ ]+[0-9a-f]+:[ ]+b9002573[ ]+csrr[ ]+a0,mhpmcounter16h
> -[ ]+[0-9a-f]+:[ ]+b9102573[ ]+csrr[ ]+a0,mhpmcounter17h
> -[ ]+[0-9a-f]+:[ ]+b9202573[ ]+csrr[ ]+a0,mhpmcounter18h
> -[ ]+[0-9a-f]+:[ ]+b9302573[ ]+csrr[ ]+a0,mhpmcounter19h
> -[ ]+[0-9a-f]+:[ ]+b9402573[ ]+csrr[ ]+a0,mhpmcounter20h
> -[ ]+[0-9a-f]+:[ ]+b9502573[ ]+csrr[ ]+a0,mhpmcounter21h
> -[ ]+[0-9a-f]+:[ ]+b9602573[ ]+csrr[ ]+a0,mhpmcounter22h
> -[ ]+[0-9a-f]+:[ ]+b9702573[ ]+csrr[ ]+a0,mhpmcounter23h
> -[ ]+[0-9a-f]+:[ ]+b9802573[ ]+csrr[ ]+a0,mhpmcounter24h
> -[ ]+[0-9a-f]+:[ ]+b9902573[ ]+csrr[ ]+a0,mhpmcounter25h
> -[ ]+[0-9a-f]+:[ ]+b9a02573[ ]+csrr[ ]+a0,mhpmcounter26h
> -[ ]+[0-9a-f]+:[ ]+b9b02573[ ]+csrr[ ]+a0,mhpmcounter27h
> -[ ]+[0-9a-f]+:[ ]+b9c02573[ ]+csrr[ ]+a0,mhpmcounter28h
> -[ ]+[0-9a-f]+:[ ]+b9d02573[ ]+csrr[ ]+a0,mhpmcounter29h
> -[ ]+[0-9a-f]+:[ ]+b9e02573[ ]+csrr[ ]+a0,mhpmcounter30h
> -[ ]+[0-9a-f]+:[ ]+b9f02573[ ]+csrr[ ]+a0,mhpmcounter31h
> -[ ]+[0-9a-f]+:[ ]+32002573[ ]+csrr[ ]+a0,mcountinhibit
> -[ ]+[0-9a-f]+:[ ]+32302573[ ]+csrr[ ]+a0,mhpmevent3
> -[ ]+[0-9a-f]+:[ ]+32402573[ ]+csrr[ ]+a0,mhpmevent4
> -[ ]+[0-9a-f]+:[ ]+32502573[ ]+csrr[ ]+a0,mhpmevent5
> -[ ]+[0-9a-f]+:[ ]+32602573[ ]+csrr[ ]+a0,mhpmevent6
> -[ ]+[0-9a-f]+:[ ]+32702573[ ]+csrr[ ]+a0,mhpmevent7
> -[ ]+[0-9a-f]+:[ ]+32802573[ ]+csrr[ ]+a0,mhpmevent8
> -[ ]+[0-9a-f]+:[ ]+32902573[ ]+csrr[ ]+a0,mhpmevent9
> -[ ]+[0-9a-f]+:[ ]+32a02573[ ]+csrr[ ]+a0,mhpmevent10
> -[ ]+[0-9a-f]+:[ ]+32b02573[ ]+csrr[ ]+a0,mhpmevent11
> -[ ]+[0-9a-f]+:[ ]+32c02573[ ]+csrr[ ]+a0,mhpmevent12
> -[ ]+[0-9a-f]+:[ ]+32d02573[ ]+csrr[ ]+a0,mhpmevent13
> -[ ]+[0-9a-f]+:[ ]+32e02573[ ]+csrr[ ]+a0,mhpmevent14
> -[ ]+[0-9a-f]+:[ ]+32f02573[ ]+csrr[ ]+a0,mhpmevent15
> -[ ]+[0-9a-f]+:[ ]+33002573[ ]+csrr[ ]+a0,mhpmevent16
> -[ ]+[0-9a-f]+:[ ]+33102573[ ]+csrr[ ]+a0,mhpmevent17
> -[ ]+[0-9a-f]+:[ ]+33202573[ ]+csrr[ ]+a0,mhpmevent18
> -[ ]+[0-9a-f]+:[ ]+33302573[ ]+csrr[ ]+a0,mhpmevent19
> -[ ]+[0-9a-f]+:[ ]+33402573[ ]+csrr[ ]+a0,mhpmevent20
> -[ ]+[0-9a-f]+:[ ]+33502573[ ]+csrr[ ]+a0,mhpmevent21
> -[ ]+[0-9a-f]+:[ ]+33602573[ ]+csrr[ ]+a0,mhpmevent22
> -[ ]+[0-9a-f]+:[ ]+33702573[ ]+csrr[ ]+a0,mhpmevent23
> -[ ]+[0-9a-f]+:[ ]+33802573[ ]+csrr[ ]+a0,mhpmevent24
> -[ ]+[0-9a-f]+:[ ]+33902573[ ]+csrr[ ]+a0,mhpmevent25
> -[ ]+[0-9a-f]+:[ ]+33a02573[ ]+csrr[ ]+a0,mhpmevent26
> -[ ]+[0-9a-f]+:[ ]+33b02573[ ]+csrr[ ]+a0,mhpmevent27
> -[ ]+[0-9a-f]+:[ ]+33c02573[ ]+csrr[ ]+a0,mhpmevent28
> -[ ]+[0-9a-f]+:[ ]+33d02573[ ]+csrr[ ]+a0,mhpmevent29
> -[ ]+[0-9a-f]+:[ ]+33e02573[ ]+csrr[ ]+a0,mhpmevent30
> -[ ]+[0-9a-f]+:[ ]+33f02573[ ]+csrr[ ]+a0,mhpmevent31
> -[ ]+[0-9a-f]+:[ ]+7a002573[ ]+csrr[ ]+a0,tselect
> -[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
> -[ ]+[0-9a-f]+:[ ]+7a202573[ ]+csrr[ ]+a0,tdata2
> -[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
> -[ ]+[0-9a-f]+:[ ]+7b002573[ ]+csrr[ ]+a0,dcsr
> -[ ]+[0-9a-f]+:[ ]+7b102573[ ]+csrr[ ]+a0,dpc
> -[ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch0
> -[ ]+[0-9a-f]+:[ ]+7b302573[ ]+csrr[ ]+a0,dscratch1
> -[ ]+[0-9a-f]+:[ ]+04302573[ ]+csrr[ ]+a0,utval
> -[ ]+[0-9a-f]+:[ ]+14302573[ ]+csrr[ ]+a0,stval
> -[ ]+[0-9a-f]+:[ ]+18002573[ ]+csrr[ ]+a0,satp
> -[ ]+[0-9a-f]+:[ ]+34302573[ ]+csrr[ ]+a0,mtval
> -[ ]+[0-9a-f]+:[ ]+32002573[ ]+csrr[ ]+a0,mcountinhibit
> -[ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch0
> -[ ]+[0-9a-f]+:[ ]+20002573[ ]+csrr[ ]+a0,hstatus
> -[ ]+[0-9a-f]+:[ ]+20202573[ ]+csrr[ ]+a0,hedeleg
> -[ ]+[0-9a-f]+:[ ]+20302573[ ]+csrr[ ]+a0,hideleg
> -[ ]+[0-9a-f]+:[ ]+20402573[ ]+csrr[ ]+a0,hie
> -[ ]+[0-9a-f]+:[ ]+20502573[ ]+csrr[ ]+a0,htvec
> -[ ]+[0-9a-f]+:[ ]+24002573[ ]+csrr[ ]+a0,hscratch
> -[ ]+[0-9a-f]+:[ ]+24102573[ ]+csrr[ ]+a0,hepc
> -[ ]+[0-9a-f]+:[ ]+24202573[ ]+csrr[ ]+a0,hcause
> -[ ]+[0-9a-f]+:[ ]+24302573[ ]+csrr[ ]+a0,hbadaddr
> -[ ]+[0-9a-f]+:[ ]+24402573[ ]+csrr[ ]+a0,hip
> -[ ]+[0-9a-f]+:[ ]+38002573[ ]+csrr[ ]+a0,mbase
> -[ ]+[0-9a-f]+:[ ]+38102573[ ]+csrr[ ]+a0,mbound
> -[ ]+[0-9a-f]+:[ ]+38202573[ ]+csrr[ ]+a0,mibase
> -[ ]+[0-9a-f]+:[ ]+38302573[ ]+csrr[ ]+a0,mibound
> -[ ]+[0-9a-f]+:[ ]+38402573[ ]+csrr[ ]+a0,mdbase
> -[ ]+[0-9a-f]+:[ ]+38502573[ ]+csrr[ ]+a0,mdbound
> -[ ]+[0-9a-f]+:[ ]+32102573[ ]+csrr[ ]+a0,mscounteren
> -[ ]+[0-9a-f]+:[ ]+32202573[ ]+csrr[ ]+a0,mhcounteren
> diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
> index 98302ff..c5a0d36 100644
> --- a/opcodes/riscv-dis.c
> +++ b/opcodes/riscv-dis.c
> @@ -31,6 +31,8 @@
> #include "bfd_stdint.h"
> #include <ctype.h>
>
> +static enum riscv_priv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE;
> +
> struct riscv_private_data
> {
> bfd_vma gp;
> @@ -52,8 +54,8 @@ set_default_riscv_dis_options (void)
> no_aliases = 0;
> }
>
> -static void
> -parse_riscv_dis_option (const char *option)
> +static bfd_boolean
> +parse_riscv_dis_option_without_args (const char *option)
> {
> if (strcmp (option, "no-aliases") == 0)
> no_aliases = 1;
> @@ -63,6 +65,44 @@ parse_riscv_dis_option (const char *option)
> riscv_fpr_names = riscv_fpr_names_numeric;
> }
> else
> + return FALSE;
> + return TRUE;
> +}
> +
> +static void
> +parse_riscv_dis_option (const char *option)
> +{
> + char *equal, *value;
> +
> + if (parse_riscv_dis_option_without_args (option))
> + return;
> +
> + equal = strchr (option, '=');
> + if (equal == NULL)
> + {
> + /* The option without '=' should be defined above. */
> + opcodes_error_handler (_("unrecognized disassembler option: %s"), option);
> + return;
> + }
> + if (equal == option
> + || *(equal + 1) == '\0')
> + {
> + /* Invalid options with '=', no option name before '=',
> + and no value after '='. */
> + opcodes_error_handler (_("unrecognized disassembler option with '=': %s"),
> + option);
> + return;
> + }
> +
> + *equal = '\0';
> + value = equal + 1;
> + if (strcmp (option, "priv-spec") == 0)
> + {
> + if (!riscv_get_priv_spec_class (value, &default_priv_spec))
> + opcodes_error_handler (_("unknown privilege spec set by %s=%s"),
> + option, value);
> + }
> + else
> {
> /* xgettext:c-format */
> opcodes_error_handler (_("unrecognized disassembler option: %s"), option);
> @@ -322,17 +362,32 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
>
> case 'E':
> {
> - const char* csr_name = NULL;
> + static const char *riscv_csr_hash[4096]; /* Total 2^12 CSR */
> + static bfd_boolean init_csr = FALSE;
> unsigned int csr = EXTRACT_OPERAND (CSR, l);
> - switch (csr)
> +
> + if (!init_csr)
> {
> + unsigned int i;
> + for (i = 0; i < 4096; i++)
> + riscv_csr_hash[i] = NULL;
> +
> + /* Set to the newest privilege version. */
> + if (default_priv_spec == PRIV_SPEC_CLASS_NONE)
> + default_priv_spec = PRIV_SPEC_CLASS_DRAFT - 1;
> +
> #define DECLARE_CSR(name, num, class, define_version, abort_version) \
> - case num: csr_name = #name; break;
> + if (default_priv_spec >= define_version \
> + && default_priv_spec < abort_version) \
> + riscv_csr_hash[num] = #name;
> +#define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
> + DECLARE_CSR(name, num, class, define_version, abort_version)
> #include "opcode/riscv-opc.h"
> #undef DECLARE_CSR
> }
> - if (csr_name)
> - print (info->stream, "%s", csr_name);
> +
> + if (riscv_csr_hash[csr] != NULL)
> + print (info->stream, "%s", riscv_csr_hash[csr]);
> else
> print (info->stream, "0x%x", csr);
> break;
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 9/9] RISC-V: Add documents and --help for the new GAS and OBJDUMP options.
2020-05-06 2:55 [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR Nelson Chu
` (7 preceding siblings ...)
2020-05-06 2:55 ` [PATCH v2 8/9] RISC-V: Disassembler dumps the CSR according to the chosen privilege spec Nelson Chu
@ 2020-05-06 2:55 ` Nelson Chu
2020-05-19 9:08 ` Nelson Chu
2020-05-19 9:07 ` [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR Nelson Chu
9 siblings, 1 reply; 25+ messages in thread
From: Nelson Chu @ 2020-05-06 2:55 UTC (permalink / raw)
To: binutils, gdb-patches
Cc: palmer, kito.cheng, jimw, andrew, andrew.burgess, asb,
maxim.blinov, nelson.chu
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset=yes, Size: 3970 bytes --]
gas/
* config/tc-riscv.c (md_show_usage): Add descriptions about
the new GAS options.
* doc/c-riscv.texi: Likewise.
opcodes/
* riscv-dis.c (print_riscv_disassembler_options): Add description
about the new OBJDUMP option.
---
gas/config/tc-riscv.c | 18 ++++++++++--------
gas/doc/c-riscv.texi | 16 ++++++++++++++++
opcodes/riscv-dis.c | 10 +++++++---
3 files changed, 33 insertions(+), 11 deletions(-)
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 6e30a06..b08339c 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -3469,14 +3469,16 @@ md_show_usage (FILE *stream)
{
fprintf (stream, _("\
RISC-V options:\n\
- -fpic generate position-independent code\n\
- -fno-pic don't generate position-independent code (default)\n\
- -march=ISA set the RISC-V architecture\n\
- -mabi=ABI set the RISC-V ABI\n\
- -mrelax enable relax (default)\n\
- -mno-relax disable relax\n\
- -march-attr generate RISC-V arch attribute\n\
- -mno-arch-attr don't generate RISC-V arch attribute\n\
+ -fpic generate position-independent code\n\
+ -fno-pic don't generate position-independent code (default)\n\
+ -march=ISA set the RISC-V architecture\n\
+ -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\
+ -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9, 1.9.1, 1.10, 1.11)\n\
+ -mabi=ABI set the RISC-V ABI\n\
+ -mrelax enable relax (default)\n\
+ -mno-relax disable relax\n\
+ -march-attr generate RISC-V arch attribute\n\
+ -mno-arch-attr don't generate RISC-V arch attribute\n\
"));
}
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 488cf56..bf942c3 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -42,6 +42,22 @@ Don't generate position-independent code (default)
@cindex @samp{-march=ISA} option, RISC-V
@item -march=ISA
Select the base isa, as specified by ISA. For example -march=rv32ima.
+If this option and the architecture attributes aren’t set, then assembler
+will check the default configure setting --with-arch=ISA.
+
+@cindex @samp{-misa-spec=ISAspec} option, RISC-V
+@item -misa-spec=ISAspec
+Select the default isa spec version. If the version of ISA isn't set
+by -march, then assembler helps to set the version according to
+the default chosen spec. If this option isn't set, then assembler will
+check the default configure setting --with-isa-spec=ISAspec.
+
+@cindex @samp{-mpriv-spec=PRIVspec} option, RISC-V
+@item -mpriv-spec=PRIVspec
+Select the privileged spec version. We can decide whether the CSR is valid or
+not according to the chosen spec. If this option and the privilege attributes
+aren't set, then assembler will check the default configure setting
+--with-priv-spec=PRIVspec.
@cindex @samp{-mabi=ABI} option, RISC-V
@item -mabi=ABI
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index c5a0d36..f1f20c6 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -603,11 +603,15 @@ The following RISC-V-specific disassembler options are supported for use\n\
with the -M switch (multiple options should be separated by commas):\n"));
fprintf (stream, _("\n\
- numeric Print numeric register names, rather than ABI names.\n"));
+ numeric Print numeric register names, rather than ABI names.\n"));
fprintf (stream, _("\n\
- no-aliases Disassemble only into canonical instructions, rather\n\
- than into pseudoinstructions.\n"));
+ no-aliases Disassemble only into canonical instructions, rather\n\
+ than into pseudoinstructions.\n"));
+
+ fprintf (stream, _("\n\
+ priv-spec=PRIV Print the CSR according to the chosen privilege spec\n\
+ (1.9, 1.9.1, 1.10, 1.11).\n"));
fprintf (stream, _("\n"));
}
--
2.7.4
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [PATCH v2 9/9] RISC-V: Add documents and --help for the new GAS and OBJDUMP options.
2020-05-06 2:55 ` [PATCH v2 9/9] RISC-V: Add documents and --help for the new GAS and OBJDUMP options Nelson Chu
@ 2020-05-19 9:08 ` Nelson Chu
0 siblings, 0 replies; 25+ messages in thread
From: Nelson Chu @ 2020-05-19 9:08 UTC (permalink / raw)
To: Binutils, gdb-patches
Cc: Palmer Dabbelt, Kito Cheng, Jim Wilson, Andrew Waterman,
Andrew Burgess, Alex Bradbury, Maxim Blinov
PING :)
On Wed, May 6, 2020 at 10:56 AM Nelson Chu <nelson.chu@sifive.com> wrote:
>
> gas/
> * config/tc-riscv.c (md_show_usage): Add descriptions about
> the new GAS options.
> * doc/c-riscv.texi: Likewise.
>
> opcodes/
> * riscv-dis.c (print_riscv_disassembler_options): Add description
> about the new OBJDUMP option.
> ---
> gas/config/tc-riscv.c | 18 ++++++++++--------
> gas/doc/c-riscv.texi | 16 ++++++++++++++++
> opcodes/riscv-dis.c | 10 +++++++---
> 3 files changed, 33 insertions(+), 11 deletions(-)
>
> diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
> index 6e30a06..b08339c 100644
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -3469,14 +3469,16 @@ md_show_usage (FILE *stream)
> {
> fprintf (stream, _("\
> RISC-V options:\n\
> - -fpic generate position-independent code\n\
> - -fno-pic don't generate position-independent code (default)\n\
> - -march=ISA set the RISC-V architecture\n\
> - -mabi=ABI set the RISC-V ABI\n\
> - -mrelax enable relax (default)\n\
> - -mno-relax disable relax\n\
> - -march-attr generate RISC-V arch attribute\n\
> - -mno-arch-attr don't generate RISC-V arch attribute\n\
> + -fpic generate position-independent code\n\
> + -fno-pic don't generate position-independent code (default)\n\
> + -march=ISA set the RISC-V architecture\n\
> + -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\
> + -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9, 1.9.1, 1.10, 1.11)\n\
> + -mabi=ABI set the RISC-V ABI\n\
> + -mrelax enable relax (default)\n\
> + -mno-relax disable relax\n\
> + -march-attr generate RISC-V arch attribute\n\
> + -mno-arch-attr don't generate RISC-V arch attribute\n\
> "));
> }
>
> diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
> index 488cf56..bf942c3 100644
> --- a/gas/doc/c-riscv.texi
> +++ b/gas/doc/c-riscv.texi
> @@ -42,6 +42,22 @@ Don't generate position-independent code (default)
> @cindex @samp{-march=ISA} option, RISC-V
> @item -march=ISA
> Select the base isa, as specified by ISA. For example -march=rv32ima.
> +If this option and the architecture attributes aren’t set, then assembler
> +will check the default configure setting --with-arch=ISA.
> +
> +@cindex @samp{-misa-spec=ISAspec} option, RISC-V
> +@item -misa-spec=ISAspec
> +Select the default isa spec version. If the version of ISA isn't set
> +by -march, then assembler helps to set the version according to
> +the default chosen spec. If this option isn't set, then assembler will
> +check the default configure setting --with-isa-spec=ISAspec.
> +
> +@cindex @samp{-mpriv-spec=PRIVspec} option, RISC-V
> +@item -mpriv-spec=PRIVspec
> +Select the privileged spec version. We can decide whether the CSR is valid or
> +not according to the chosen spec. If this option and the privilege attributes
> +aren't set, then assembler will check the default configure setting
> +--with-priv-spec=PRIVspec.
>
> @cindex @samp{-mabi=ABI} option, RISC-V
> @item -mabi=ABI
> diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
> index c5a0d36..f1f20c6 100644
> --- a/opcodes/riscv-dis.c
> +++ b/opcodes/riscv-dis.c
> @@ -603,11 +603,15 @@ The following RISC-V-specific disassembler options are supported for use\n\
> with the -M switch (multiple options should be separated by commas):\n"));
>
> fprintf (stream, _("\n\
> - numeric Print numeric register names, rather than ABI names.\n"));
> + numeric Print numeric register names, rather than ABI names.\n"));
>
> fprintf (stream, _("\n\
> - no-aliases Disassemble only into canonical instructions, rather\n\
> - than into pseudoinstructions.\n"));
> + no-aliases Disassemble only into canonical instructions, rather\n\
> + than into pseudoinstructions.\n"));
> +
> + fprintf (stream, _("\n\
> + priv-spec=PRIV Print the CSR according to the chosen privilege spec\n\
> + (1.9, 1.9.1, 1.10, 1.11).\n"));
>
> fprintf (stream, _("\n"));
> }
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR
2020-05-06 2:55 [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR Nelson Chu
` (8 preceding siblings ...)
2020-05-06 2:55 ` [PATCH v2 9/9] RISC-V: Add documents and --help for the new GAS and OBJDUMP options Nelson Chu
@ 2020-05-19 9:07 ` Nelson Chu
2020-05-20 16:27 ` Nick Clifton
9 siblings, 1 reply; 25+ messages in thread
From: Nelson Chu @ 2020-05-19 9:07 UTC (permalink / raw)
To: Binutils, gdb-patches
Cc: Palmer Dabbelt, Kito Cheng, Jim Wilson, Andrew Waterman,
Andrew Burgess, Alex Bradbury, Maxim Blinov
PING :)
On Wed, May 6, 2020 at 10:55 AM Nelson Chu <nelson.chu@sifive.com> wrote:
>
> Hi binutils and gdb,
>
> After getting some good feedbacks, I refactor the series of patches.
> These patches are tested and get toolchain regressions pass.
> There are some differences from the last version,
>
> 1. Remove the -mriscv-isa-version and --with-riscv-isa-version options.
> We can still use -march to choose the version for each extensions, so there is
> no need to add these.
>
> 2. Change the arguments of options from [1p9|1p9p1|...] to [1.9|1.9.1|...].
> Unlike the architecture string has specified by spec, ther is no need to do
> the same thing for options.
>
> 3. Spilt the patches to reduce the burdens of review.
>
> [PATCH 3/7] RISC-V: Support new GAS options and configure options to set ISA versions
> to
> [PATCH v2 3/9] RISC-V: Support GAS option -misa-spec to set ISA versions
> [PATCH v2 4/9] RISC-V: Support configure options to set ISA versions by default.
>
> [PATCH 4/7] RISC-V: Support version checking for CSR according to privilege version.
> to
> [PATCH v2 5/9] RISC-V: Support version checking for CSR according to privilege spec version.
> [PATCH v2 6/9] RISC-V: Support configure option to choose the privilege spec version.
>
> 4. Use enum class rather than string to compare the choosen ISA spec in opcodes/riscv-opc.c.
> The behavior is same as comparing the choosen privilege spec.
>
> Thanks
> Nelson
>
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR
2020-05-19 9:07 ` [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR Nelson Chu
@ 2020-05-20 16:27 ` Nick Clifton
2020-05-21 2:38 ` Nelson Chu
0 siblings, 1 reply; 25+ messages in thread
From: Nick Clifton @ 2020-05-20 16:27 UTC (permalink / raw)
To: Nelson Chu, Binutils, gdb-patches; +Cc: Alex Bradbury, Kito Cheng
Hi Nelson,
> PING :)
Oops - sorry - I was hoping that somebody else would get to this.
I had a little trouble applying the patches since the sources have changed
since they were made, but that aside everything worked fine. So I have
gone ahead and applied the entire patch series.
Cheers
Nick
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR
2020-05-20 16:27 ` Nick Clifton
@ 2020-05-21 2:38 ` Nelson Chu
2020-05-21 7:29 ` Nick Clifton
0 siblings, 1 reply; 25+ messages in thread
From: Nelson Chu @ 2020-05-21 2:38 UTC (permalink / raw)
To: Nick Clifton; +Cc: Binutils, gdb-patches, Alex Bradbury, Kito Cheng
Hi Nick,
On Thu, May 21, 2020 at 12:27 AM Nick Clifton <nickc@redhat.com> wrote:
> Oops - sorry - I was hoping that somebody else would get to this.
Thank you very much :)
> I had a little trouble applying the patches since the sources have changed
> since they were made, but that aside everything worked fine. So I have
> gone ahead and applied the entire patch series.
I remember these patches are related to gas and gdb parts. I didn't
realize that the sources have changed recently... Sorry about
that...I should double check these patches before pinging them :(
Thanks again for your help !!
Nelson
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR
2020-05-21 2:38 ` Nelson Chu
@ 2020-05-21 7:29 ` Nick Clifton
2020-05-21 9:11 ` Nelson Chu
0 siblings, 1 reply; 25+ messages in thread
From: Nick Clifton @ 2020-05-21 7:29 UTC (permalink / raw)
To: Nelson Chu; +Cc: Binutils, gdb-patches, Alex Bradbury, Kito Cheng
Hi Nelson,
> I remember these patches are related to gas and gdb parts.
Oh - that reminds me - I have not applied the GDB portion of the patch series.
You will need to get approval from the GDB maintainers for that.
Cheers
Nick
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR
2020-05-21 7:29 ` Nick Clifton
@ 2020-05-21 9:11 ` Nelson Chu
[not found] ` <CAFyWVaZy9e9aRTRKqzfiJGMBXDYFGOShikWio56PwzjG22ODkA@mail.gmail.com>
0 siblings, 1 reply; 25+ messages in thread
From: Nelson Chu @ 2020-05-21 9:11 UTC (permalink / raw)
To: Nick Clifton; +Cc: Binutils, gdb-patches, Alex Bradbury, Kito Cheng
Hi Nick,
On Thu, May 21, 2020 at 3:29 PM Nick Clifton <nickc@redhat.com> wrote:
> Oh - that reminds me - I have not applied the GDB portion of the patch series.
> You will need to get approval from the GDB maintainers for that.
Thanks for reminding me of this :) I extend the DECLARE_CSR macro
which is used both for binutils and gdb. I just let gdb be built
successfully, and make sure the binutils' changes won't affect the
current gdb. Fortunately, the related changes about gdb are approved
by Andrew Burgess in the previous mail [1]. And the gdb changes are
already upstreamed with the binutils' one together.
Thanks for everything, Nick :)
Nelson
[1] https://sourceware.org/pipermail/binutils/2020-April/110826.html
^ permalink raw reply [flat|nested] 25+ messages in thread