From: Tomas Vanek <vanekt@fbl.cz>
To: gdb-patches@sourceware.org
Subject: [PATCH] gdb/arm: fix IPSR field test in arm_m_exception_cache ()
Date: Sat, 22 Oct 2022 10:25:54 +0200 [thread overview]
Message-ID: <1666427154-22766-1-git-send-email-vanekt@fbl.cz> (raw)
Arm v8-M Architecture Reference Manual,
D1.2.141 IPSR, Interrupt Program Status Register reads
"Exception, bits [8:0]"
9 bits, not 8! It is uncommon but true!
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
---
gdb/arm-tdep.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
index b397ca3..923447a 100644
--- a/gdb/arm-tdep.c
+++ b/gdb/arm-tdep.c
@@ -3441,7 +3441,7 @@ struct frame_unwind arm_stub_unwind = {
}
ULONGEST xpsr = get_frame_register_unsigned (this_frame, ARM_PS_REGNUM);
- if ((xpsr & 0xff) != 0)
+ if ((xpsr & 0x1ff) != 0)
/* Handler mode: This is the mode that exceptions are handled in. */
arm_cache_switch_prev_sp (cache, tdep, tdep->m_profile_msp_s_regnum);
else
--
1.9.1
next reply other threads:[~2022-10-22 8:26 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-22 8:25 Tomas Vanek [this message]
2022-10-25 13:22 ` Luis Machado
2022-10-25 15:35 ` Tomas Vanek
2022-10-26 12:04 ` Luis Machado
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