From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 26954 invoked by alias); 7 Mar 2010 14:16:37 -0000 Received: (qmail 26943 invoked by uid 22791); 7 Mar 2010 14:16:36 -0000 X-SWARE-Spam-Status: No, hits=-2.5 required=5.0 tests=AWL,BAYES_00 X-Spam-Check-By: sourceware.org Received: from sibelius.xs4all.nl (HELO glazunov.sibelius.xs4all.nl) (83.163.83.176) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Sun, 07 Mar 2010 14:16:31 +0000 Received: from glazunov.sibelius.xs4all.nl (kettenis@localhost [127.0.0.1]) by glazunov.sibelius.xs4all.nl (8.14.3/8.14.3) with ESMTP id o27EGR2W029098; Sun, 7 Mar 2010 15:16:27 +0100 (CET) Received: (from kettenis@localhost) by glazunov.sibelius.xs4all.nl (8.14.3/8.14.3/Submit) id o27EGPfu007140; Sun, 7 Mar 2010 15:16:25 +0100 (CET) Date: Sun, 07 Mar 2010 14:16:00 -0000 Message-Id: <201003071416.o27EGPfu007140@glazunov.sibelius.xs4all.nl> From: Mark Kettenis To: hjl.tools@gmail.com CC: gdb-patches@sourceware.org In-reply-to: <20100306221634.GA21133@intel.com> (hongjiu.lu@intel.com) Subject: Re: PATCH: 0/6 [2nd try]: Add AVX support References: <20100304180219.GA10826@intel.com> <20100306221634.GA21133@intel.com> Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2010-03/txt/msg00270.txt.bz2 > Date: Sat, 6 Mar 2010 14:16:34 -0800 > From: "H.J. Lu" > > AVX registers are saved and restored via the XSAVE extended state. The > extended control register 0 (the XFEATURE_ENABLED_MASK register), XCR0, > is used to determine which states, x87, SSE, AVX, ... are supported > in the XSAVE extended state. XCR0 can be read with the new "xgetbv" > instruction. The xstate_bv field at byte offset 512 in the XSAVE > extended state indicates what states the current process is in. If > the feature bit is cleared, the corresponding registers should be read as > 0. If we update a register, we should set the corresponding feature > bit in the xstate_bv field. > > We added PTRACE_GETREGSET and PTRACE_SETREGSET to Linux kernel to > fetch and store AVX registers with ptrace. Linux kernel also stores > XCR0 at the first 8 bytes of the software usable bytes, starting at > byte offset 464. > > There are total 6 patches to add AVX support for Linux. They support: > > 1. The upper 128bit YMM registers are added for AVX support. The upper > 128bit YMM registers are hidden from users. Gdb combines XMM register, > %xmmX, with 128bit YMM register, %ymmXh, and present the whole 256bit > YMM register, %ymmX, as pseudo register to users. > 2. Backward compatible. If AVX isn't supported, SSE will be used. > 3. Forward compatible. If new state beyond AVX is supported in > the XSAVE extended state, only AVX state will be used. > 4. Remote gdb protocol extension. GDB will send "x86=xml" in qSupported > request packet to indicate that GDB supports x86 XML target desciption. > The gdb stub will send x86 XML target desciption if it sees "x86=xml" > in qSupported request packet. > > One advantage of this approach is YMM registers are actually stored as > XMM registers and upper YMM registers in the XSAVE extended state. It > is easy and natural to access them as %xmmX and %ymmXh internally. We > just need to hide %ymmXh from users. > > To support AVX on other OSes, the following changes are needed: > > 1. Kernel support to get/set the XSAVE extended state. > 2. Handle 8/16 upper YMM registers. > 3. Provide target to_read_description to return SSE or AVX target > description. > 4. Update gdbarch_core_read_description to return SSE or AVX target > description based on contents of core dump. Wait; there is something important missing here. How are the new %ymm registers referred to in debug info? The AMD64 SysV psABI defines the DWARF register Number Mapping, but the 0.99.4 draft copy I have doesn't define any mappings for the %ymm registers. What mapping does GCC use?