From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 1935 invoked by alias); 29 Mar 2010 00:16:34 -0000 Received: (qmail 1927 invoked by uid 22791); 29 Mar 2010 00:16:33 -0000 X-SWARE-Spam-Status: No, hits=-0.8 required=5.0 tests=AWL,BAYES_00,NO_DNS_FOR_FROM X-Spam-Check-By: sourceware.org Received: from mga05.intel.com (HELO fmsmga101.fm.intel.com) (192.55.52.89) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 29 Mar 2010 00:16:29 +0000 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP; 28 Mar 2010 17:11:43 -0700 X-ExtLoop1: 1 Received: from gnu-6.sc.intel.com ([10.3.194.107]) by fmsmga001.fm.intel.com with ESMTP; 28 Mar 2010 17:16:09 -0700 Received: by gnu-6.sc.intel.com (Postfix, from userid 500) id 7B607812387; Sun, 28 Mar 2010 17:16:27 -0700 (PDT) Date: Mon, 29 Mar 2010 00:16:00 -0000 From: "H.J. Lu" To: Cc@gnu-6.sc.intel.com:GDB Subject: PATCH: 0/6 [3nd try]: Add AVX support Message-ID: <20100329001627.GA26103@intel.com> Reply-To: "H.J. Lu" References: <20100304180219.GA10826@intel.com> <20100306221634.GA21133@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100306221634.GA21133@intel.com> User-Agent: Mutt/1.5.20 (2009-08-17) Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2010-03/txt/msg00966.txt.bz2 AVX registers are saved and restored via the XSAVE extended state. The extended control register 0 (the XFEATURE_ENABLED_MASK register), XCR0, is used to determine which states, x87, SSE, AVX, ... are supported in the XSAVE extended state. XCR0 can be read with the new "xgetbv" instruction. The xstate_bv field at byte offset 512 in the XSAVE extended state indicates what states the current process is in. If the feature bit is cleared, the corresponding registers should be read as 0. If we update a register, we should set the corresponding feature bit in the xstate_bv field. We added PTRACE_GETREGSET and PTRACE_SETREGSET to Linux kernel to fetch and store AVX registers with ptrace. Linux kernel also stores XCR0 at the first 8 bytes of the software usable bytes, starting at byte offset 464. There are total 6 patches to add AVX support for Linux. i387 and XML patches are unchanged from the 2nd try: http://sourceware.org/ml/gdb-patches/2010-03/msg00262.html http://sourceware.org/ml/gdb-patches/2010-03/msg00266.html They support: 1. The upper 128bit YMM registers are added for AVX support. The upper 128bit YMM registers are hidden from users. Gdb combines XMM register, %xmmX, with 128bit YMM register, %ymmXh, and present the whole 256bit YMM register, %ymmX, as pseudo register to users. 2. Backward compatible. If AVX isn't supported, SSE will be used. 3. Forward compatible. If new state beyond AVX is supported in the XSAVE extended state, only AVX state will be used. 4. Remote gdb protocol extension. GDB will send "xmlRegisters=" in qSupported request packet to indicate that GDB supports XML target desciption. The x86 gdb stub will send XML target desciption if it sees "xmlRegisters=" in qSupported request packet. One advantage of this approach is YMM registers are actually stored as XMM registers and upper YMM registers in the XSAVE extended state. It is easy and natural to access them as %xmmX and %ymmXh internally. We just need to hide %ymmXh from users. To support AVX on other OSes, the following changes are needed: 1. Kernel support to get/set the XSAVE extended state. 2. Handle 8/16 upper YMM registers. 3. Provide target to_read_description to return SSE or AVX target description. 4. Update gdbarch_core_read_description to return SSE or AVX target description based on contents of core dump. H.J.