* [PATCH][RX] v2 instructions support
@ 2015-12-27 8:51 Yoshinori Sato
2015-12-27 8:51 ` [PATCH][RX] instructions test set Yoshinori Sato
2015-12-27 21:55 ` [PATCH][RX] v2 instructions support Mike Frysinger
0 siblings, 2 replies; 11+ messages in thread
From: Yoshinori Sato @ 2015-12-27 8:51 UTC (permalink / raw)
To: gdb-patches; +Cc: Yoshinori Sato
include/gdb/ChangeLog
* sim-rx.h: Add v2 enhanced registers.
sim/rx/ChangeLog
* Makefile.in: Add libm.
* cpu.h(acc_t): extend to 96bit.
(regs_type): Add v2 registers.
(extb): New define.
(li): Likewise.
(acc0): Rename from acc64.
(acc1): New define.
(acchi,accmi,acclo): Remove.
(get_acc): New function.
(put_acc): Likewise.
(get_reg64): Remove.
(put_reg64): Likewise.
* fpu.c(FP_Type): Add unique prefix.
(fp_explode): Likewise.
(fp_implode): Likewise.
(double_to_fp): Likewise.
(check_exceptions): Likewise.
(rxfp_ftoi): Likewise.
(check_exceptions): FP_ExceptionCases to const.
(ex_add_tab): Likewise.
(ex_sub_tab): Likewise.
(ex_mul_tab): Likewise.
(ex_div_tab): Likewise.
(ex_cmp_tab): Likewise.
(rx_sqrt_tab): New.
(rxfp_fsqrt): New.
(rxfp_ftou): New.
(rxfp_utof): New.
* fpu.h: Add new function prototype.
* gdb-if.c(reg_size): New registers support.
(sim_fetch_register): Likewise.
(sim_store_register): Likewise.
* reg.c(reg_names): Add new registers.
* rx.c(id_names): Add new instructions.
(FLOAT_OP): 3operands support.
(MULADD): New.
(MULSUB): New.
(MULACC): New.
(RAC): New.
(RXO_emaca): New.
(RXO_emsba): New.
(RXO_emula): New.
(RXO_fsqrt): New.
(RXO_ftou): New.
(RXO_machi): Use MULADD.
(RXO_maclo): Likewise.
(RXO_maclh): New.
(RXO_movli): New.
(RXO_movco): New.
(RXO_msbhi): New.
(RXO_msblo): New.
(RXO_msblh): New.
(RXO_mulhi): Use MULACC.
(RXO_mullo): Likewise.
(RXO_mullh): New.
(RXO_mvfachi): New acc support.
(RXO_mvfaclo): Likewise.
(RXO_mvfacmi): Likewise.
(RXO_mvfacgu): New.
(RXO_mvtachi): New acc support.
(RXO_mvtaclo): New acc support.
(RXO_mvtacgu): New.
(RXO_racw): Use RAC.
(RXO_rdacw): New.
(RXO_racl): New.
(RXO_rdacl): New.
(RXO_rte): Add li clear.
(RXO_utof): New.
---
include/gdb/sim-rx.h | 4 +-
sim/rx/Makefile.in | 1 +
sim/rx/cpu.h | 24 +++--
sim/rx/fpu.c | 252 ++++++++++++++++++++++++++++++++++++++--------
sim/rx/fpu.h | 3 +
sim/rx/gdb-if.c | 70 +++++++++++--
sim/rx/reg.c | 117 ++++++++++------------
sim/rx/rx.c | 276 +++++++++++++++++++++++++++++++++++++++++++--------
8 files changed, 583 insertions(+), 164 deletions(-)
diff --git a/include/gdb/sim-rx.h b/include/gdb/sim-rx.h
index 40e18c1..b55c902 100644
--- a/include/gdb/sim-rx.h
+++ b/include/gdb/sim-rx.h
@@ -49,7 +49,9 @@ enum sim_rx_regnum
sim_rx_bpc_regnum,
sim_rx_fintv_regnum,
sim_rx_fpsw_regnum,
- sim_rx_acc_regnum,
+ sim_rx_acc0_regnum,
+ sim_rx_extb_regnum,
+ sim_rx_acc1_regnum,
sim_rx_num_regs
};
diff --git a/sim/rx/Makefile.in b/sim/rx/Makefile.in
index 64d9f3c..73475fe 100644
--- a/sim/rx/Makefile.in
+++ b/sim/rx/Makefile.in
@@ -40,6 +40,7 @@ SIM_OBJS = \
$(ENDLIST)
LIBS = $B/bfd/libbfd.a $B/libiberty/libiberty.a
+SIM_EXTRA_LIBS = -lm
## COMMON_POST_CONFIG_FRAG
diff --git a/sim/rx/cpu.h b/sim/rx/cpu.h
index 9a82e5e..45e6612 100644
--- a/sim/rx/cpu.h
+++ b/sim/rx/cpu.h
@@ -35,6 +35,12 @@ extern int rx_big_endian;
typedef struct
{
+ SI hi;
+ DI lo;
+} acc_t;
+
+typedef struct
+{
SI r[16];
SI r_psw;
@@ -51,8 +57,8 @@ typedef struct
SI r_isp;
SI r_fintv;
SI r_intb;
- SI r__reserved_cr_13;
- SI r__reserved_cr_14;
+ SI r_extb;
+ SI r_li;
SI r__reserved_cr_15;
SI r__reserved_cr_16;
@@ -75,7 +81,7 @@ typedef struct
SI r_temp;
- DI r_acc;
+ acc_t r_acc[2];
#ifdef CYCLE_ACCURATE
/* If set, RTS/RTSD take 2 fewer cycles. */
@@ -105,12 +111,12 @@ typedef struct
#define isp 26
#define fintv 27
#define intb 28
+#define extb 29
+#define li 30
#define r_temp_idx 48
-#define acc64 49
-#define acchi 50
-#define accmi 51
-#define acclo 52
+#define acc0 49
+#define acc1 50
extern regs_type regs;
@@ -170,9 +176,9 @@ void init_regs (void);
void stack_heap_stats (void);
void set_pointer_width (int bytes);
unsigned int get_reg (int id);
-unsigned long long get_reg64 (int id);
+void get_acc (int id, acc_t *valuel);
void put_reg (int id, unsigned int value);
-void put_reg64 (int id, unsigned long long value);
+void put_acc (int id, acc_t *value);
void set_flags (int mask, int newbits);
void set_oszc (long long value, int bytes, int c);
diff --git a/sim/rx/fpu.c b/sim/rx/fpu.c
index 9e4a103..3a47acb 100644
--- a/sim/rx/fpu.c
+++ b/sim/rx/fpu.c
@@ -21,6 +21,7 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. */
#include "config.h"
#include <stdio.h>
#include <stdlib.h>
+#include <math.h>
#include "cpu.h"
#include "fpu.h"
@@ -77,14 +78,14 @@ fp_raise (int mask)
/* We classify all numbers as one of these. They correspond to the
rows/colums in the exception tables. */
typedef enum {
- FP_NORMAL,
- FP_PZERO,
- FP_NZERO,
- FP_PINFINITY,
- FP_NINFINITY,
- FP_DENORMAL,
- FP_QNAN,
- FP_SNAN
+ RX_FP_NORMAL,
+ RX_FP_PZERO,
+ RX_FP_NZERO,
+ RX_FP_PINFINITY,
+ RX_FP_NINFINITY,
+ RX_FP_DENORMAL,
+ RX_FP_QNAN,
+ RX_FP_SNAN
} FP_Type;
#if defined DEBUG0
@@ -127,24 +128,24 @@ fp_explode (fp_t f, FP_Parts *p)
if (regs.r_fpsw & FPSWBITS_DN)
mant = 0;
if (mant)
- p->type = FP_DENORMAL;
+ p->type = RX_FP_DENORMAL;
else
{
p->mant = 0;
- p->type = sign ? FP_NZERO : FP_PZERO;
+ p->type = sign ? RX_FP_NZERO : RX_FP_PZERO;
}
}
else if (p->exp == EXP_INF)
{
if (mant == 0)
- p->type = sign ? FP_NINFINITY : FP_PINFINITY;
+ p->type = sign ? RX_FP_NINFINITY : RX_FP_PINFINITY;
else if (mant & 0x00400000UL)
- p->type = FP_QNAN;
+ p->type = RX_FP_QNAN;
else
- p->type = FP_SNAN;
+ p->type = RX_FP_SNAN;
}
else
- p->type = FP_NORMAL;
+ p->type = RX_FP_NORMAL;
}
static fp_t
@@ -155,7 +156,7 @@ fp_implode (FP_Parts *p)
exp = p->exp + EXP_BIAS;
mant = p->mant;
/*printf("implode: exp %d mant 0x%x\n", exp, mant);*/
- if (p->type == FP_NORMAL)
+ if (p->type == RX_FP_NORMAL)
{
while (mant
&& exp > 0
@@ -303,7 +304,7 @@ double_to_fp (double d, FP_Parts *p)
p->exp = exp;
p->mant = u.ll >> (52-23) & 0x007fffffUL;
p->mant |= 0x00800000UL;
- p->type = FP_NORMAL;
+ p->type = RX_FP_NORMAL;
if (u.ll & 0x1fffffffULL)
{
@@ -356,19 +357,19 @@ static const char *ex_names[] = {
FALSE, the caller should do the "normal" operation. */
int
check_exceptions (FP_Parts *a, FP_Parts *b, fp_t *c,
- FP_ExceptionCases ex_tab[5][5],
+ const FP_ExceptionCases ex_tab[5][5],
FP_ExceptionCases *case_ret)
{
FP_ExceptionCases fpec;
- if (a->type == FP_SNAN
- || b->type == FP_SNAN)
+ if (a->type == RX_FP_SNAN
+ || b->type == RX_FP_SNAN)
fpec = eIn;
- else if (a->type == FP_QNAN
- || b->type == FP_QNAN)
+ else if (a->type == RX_FP_QNAN
+ || b->type == RX_FP_QNAN)
fpec = eQN;
- else if (a->type == FP_DENORMAL
- || b->type == FP_DENORMAL)
+ else if (a->type == RX_FP_DENORMAL
+ || b->type == RX_FP_DENORMAL)
fpec = eUn;
else
fpec = ex_tab[(int)(a->type)][(int)(b->type)];
@@ -415,14 +416,14 @@ check_exceptions (FP_Parts *a, FP_Parts *b, fp_t *c,
return 1;
case eQN: /* Quiet NANs */
- if (a->type == FP_QNAN)
+ if (a->type == RX_FP_QNAN)
*c = a->orig_value;
else
*c = b->orig_value;
return 1;
case eSN: /* Signalling NANs */
- if (a->type == FP_SNAN)
+ if (a->type == RX_FP_SNAN)
*c = a->orig_value;
else
*c = b->orig_value;
@@ -431,9 +432,9 @@ check_exceptions (FP_Parts *a, FP_Parts *b, fp_t *c,
case eIn: /* Invalid. */
FP_RAISE (V);
- if (a->type == FP_SNAN)
+ if (a->type == RX_FP_SNAN)
*c = a->orig_value | 0x00400000;
- else if (a->type == FP_SNAN)
+ else if (a->type == RX_FP_SNAN)
*c = b->orig_value | 0x00400000;
else
*c = 0x7fc00000;
@@ -461,7 +462,7 @@ check_exceptions (FP_Parts *a, FP_Parts *b, fp_t *c,
handled. The DN=0 case is first, followed by the DN=1 case, with
each table using the following layout: */
-static FP_ExceptionCases ex_add_tab[5][5] = {
+static const FP_ExceptionCases ex_add_tab[5][5] = {
/* N +0 -0 +In -In */
{ eNR, eNR, eNR, ePI, eNI }, /* Normal */
{ eNR, ePZ, eRZ, ePI, eNI }, /* +0 */
@@ -490,7 +491,7 @@ rxfp_add (fp_t fa, fp_t fb)
return rv;
}
-static FP_ExceptionCases ex_sub_tab[5][5] = {
+static const FP_ExceptionCases ex_sub_tab[5][5] = {
/* N +0 -0 +In -In */
{ eNR, eNR, eNR, eNI, ePI }, /* Normal */
{ eNR, eRZ, ePZ, eNI, ePI }, /* +0 */
@@ -520,7 +521,7 @@ rxfp_sub (fp_t fa, fp_t fb)
return rv;
}
-static FP_ExceptionCases ex_mul_tab[5][5] = {
+static const FP_ExceptionCases ex_mul_tab[5][5] = {
/* N +0 -0 +In -In */
{ eNR, eNR, eNR, eSI, eSI }, /* Normal */
{ eNR, ePZ, eNZ, eIn, eIn }, /* +0 */
@@ -550,7 +551,7 @@ rxfp_mul (fp_t fa, fp_t fb)
return rv;
}
-static FP_ExceptionCases ex_div_tab[5][5] = {
+static const FP_ExceptionCases ex_div_tab[5][5] = {
/* N +0 -0 +In -In */
{ eNR, eDZ, eDZ, eSZ, eSZ }, /* Normal */
{ eSZ, eIn, eIn, ePZ, eNZ }, /* +0 */
@@ -580,7 +581,7 @@ rxfp_div (fp_t fa, fp_t fb)
return rv;
}
-static FP_ExceptionCases ex_cmp_tab[5][5] = {
+static const FP_ExceptionCases ex_cmp_tab[5][5] = {
/* N +0 -0 +In -In */
{ eNR, eNR, eNR, eLT, eGT }, /* Normal */
{ eNR, eEQ, eEQ, eLT, eGT }, /* +0 */
@@ -654,22 +655,22 @@ rxfp_ftoi (fp_t fa, int round_mode)
switch (a.type)
{
- case FP_NORMAL:
+ case RX_FP_NORMAL:
break;
- case FP_PZERO:
- case FP_NZERO:
+ case RX_FP_PZERO:
+ case RX_FP_NZERO:
return 0;
- case FP_PINFINITY:
+ case RX_FP_PINFINITY:
FP_RAISE (V);
return 0x7fffffffL;
- case FP_NINFINITY:
+ case RX_FP_NINFINITY:
FP_RAISE (V);
return 0x80000000L;
- case FP_DENORMAL:
+ case RX_FP_DENORMAL:
FP_RAISE (E);
return 0;
- case FP_QNAN:
- case FP_SNAN:
+ case RX_FP_QNAN:
+ case RX_FP_SNAN:
FP_RAISE (V);
return sign ? 0x80000000U : 0x7fffffff;
}
@@ -684,7 +685,7 @@ rxfp_ftoi (fp_t fa, int round_mode)
if (a.exp <= -25)
{
- /* Less than 0.49999 */
+ /* Less than 0.49999. */
frac_bits = a.mant;
whole_bits = 0;
}
@@ -790,3 +791,172 @@ rxfp_itof (long fa, int round_mode)
return rv;
}
+static const FP_ExceptionCases ex_sqrt_tab[5][5] = {
+ /* N +0 -0 +In -In */
+ { eNR, eDZ, eDZ, eSZ, eSZ }, /* Normal */
+ { eSZ, eIn, eIn, ePZ, eNZ }, /* +0 */
+ { eSZ, eIn, eIn, eNZ, ePZ }, /* -0 */
+ { eSI, ePI, eNI, eIn, eIn }, /* +Inf */
+ { eSI, eNI, ePI, eIn, eIn }, /* -Inf */
+};
+
+fp_t
+rxfp_fsqrt (fp_t fa)
+{
+ FP_Parts a, b, c;
+ fp_t rv;
+ double da;
+
+ fp_explode (fa, &a);
+ fp_explode (fa, &b);
+ CHECK_EXCEPTIONS (a, b, rv, ex_sqrt_tab);
+
+ da = fp_to_double (&a);
+ tprintf ("sqrt(%g) = %g\n", da, sqrt (da));
+
+ double_to_fp (sqrt (da), &c);
+ rv = fp_implode (&c);
+
+ return rv;
+}
+
+unsigned long
+rxfp_ftou (fp_t fa, int round_mode)
+{
+ FP_Parts a;
+ fp_t rv;
+ int sign;
+ int whole_bits, frac_bits;
+
+ fp_explode (fa, &a);
+ sign = fa & 0x80000000UL;
+
+ switch (a.type)
+ {
+ case RX_FP_NORMAL:
+ break;
+ case RX_FP_PZERO:
+ case RX_FP_NZERO:
+ return 0;
+ case RX_FP_PINFINITY:
+ FP_RAISE (V);
+ return 0xffffffffL;
+ case RX_FP_NINFINITY:
+ FP_RAISE (V);
+ return 0x00000000L;
+ case RX_FP_DENORMAL:
+ FP_RAISE (E);
+ return 0;
+ case RX_FP_QNAN:
+ case RX_FP_SNAN:
+ FP_RAISE (V);
+ return sign ? 0x00000000 : 0xffffffff;
+ }
+
+ if (sign)
+ return 0;
+ if (a.exp >= 32)
+ {
+ FP_RAISE (V);
+ return 0xffffffff;
+ }
+
+ a.exp -= 23;
+
+ if (a.exp <= -25)
+ {
+ /* Less than 0.49999 */
+ frac_bits = a.mant;
+ whole_bits = 0;
+ }
+ else if (a.exp < 0)
+ {
+ frac_bits = a.mant << (33 + a.exp);
+ whole_bits = a.mant >> (-a.exp);
+ }
+ else
+ {
+ frac_bits = 0;
+ whole_bits = a.mant << a.exp;
+ }
+
+ if (frac_bits)
+ {
+ switch (round_mode & 3)
+ {
+ case FPRM_NEAREST:
+ if (frac_bits & 0x80000000UL)
+ whole_bits ++;
+ break;
+ case FPRM_ZERO:
+ case FPRM_NINF:
+ break;
+ case FPRM_PINF:
+ if (!sign)
+ whole_bits ++;
+ break;
+ }
+ }
+
+ rv = whole_bits;
+
+ return rv;
+}
+
+fp_t
+rxfp_utof (unsigned long fa, int round_mode)
+{
+ fp_t rv;
+ int sign = 0;
+ unsigned int frac_bits;
+ volatile unsigned int whole_bits;
+ FP_Parts a;
+
+ if (fa == 0)
+ return PLUS_ZERO;
+
+ a.sign = 1;
+
+ whole_bits = fa;
+ a.exp = 31;
+
+ while (! (whole_bits & 0x80000000UL))
+ {
+ a.exp --;
+ whole_bits <<= 1;
+ }
+ frac_bits = whole_bits & 0xff;
+ whole_bits = whole_bits >> 8;
+
+ if (frac_bits)
+ {
+ /* We must round. */
+ switch (round_mode & 3)
+ {
+ case FPRM_NEAREST:
+ if (frac_bits & 0x80)
+ whole_bits ++;
+ break;
+ case FPRM_ZERO:
+ break;
+ case FPRM_PINF:
+ if (!sign)
+ whole_bits ++;
+ break;
+ case FPRM_NINF:
+ if (sign)
+ whole_bits ++;
+ break;
+ }
+ }
+
+ a.mant = whole_bits;
+ if (whole_bits & 0xff000000UL)
+ {
+ a.mant >>= 1;
+ a.exp ++;
+ }
+
+ rv = fp_implode (&a);
+ return rv;
+}
diff --git a/sim/rx/fpu.h b/sim/rx/fpu.h
index a20c2a0..dcddf11 100644
--- a/sim/rx/fpu.h
+++ b/sim/rx/fpu.h
@@ -27,3 +27,6 @@ extern fp_t rxfp_div (fp_t fa, fp_t fb);
extern void rxfp_cmp (fp_t fa, fp_t fb);
extern long rxfp_ftoi (fp_t fa, int round_mode);
extern fp_t rxfp_itof (long fa, int round_mode);
+extern fp_t rxfp_fsqrt (fp_t fa);
+extern unsigned long rxfp_ftou (fp_t fa, int round_mode);
+extern fp_t rxfp_utof (unsigned long fa, int round_mode);
diff --git a/sim/rx/gdb-if.c b/sim/rx/gdb-if.c
index 762c3d2..ebf54ee 100644
--- a/sim/rx/gdb-if.c
+++ b/sim/rx/gdb-if.c
@@ -387,6 +387,9 @@ reg_size (enum sim_rx_regnum regno)
case sim_rx_intb_regnum:
size = sizeof (regs.r_intb);
break;
+ case sim_rx_extb_regnum:
+ size = sizeof (regs.r_extb);
+ break;
case sim_rx_pc_regnum:
size = sizeof (regs.r_pc);
break;
@@ -405,8 +408,9 @@ reg_size (enum sim_rx_regnum regno)
case sim_rx_fpsw_regnum:
size = sizeof (regs.r_fpsw);
break;
- case sim_rx_acc_regnum:
- size = sizeof (regs.r_acc);
+ case sim_rx_acc0_regnum:
+ case sim_rx_acc1_regnum:
+ size = 8;
break;
default:
size = 0;
@@ -490,6 +494,9 @@ sim_fetch_register (SIM_DESC sd, int regno, unsigned char *buf, int length)
case sim_rx_intb_regnum:
val = get_reg (intb);
break;
+ case sim_rx_extb_regnum:
+ val = get_reg (extb);
+ break;
case sim_rx_pc_regnum:
val = get_reg (pc);
break;
@@ -508,9 +515,26 @@ sim_fetch_register (SIM_DESC sd, int regno, unsigned char *buf, int length)
case sim_rx_fpsw_regnum:
val = get_reg (fpsw);
break;
- case sim_rx_acc_regnum:
- val = ((DI) get_reg (acchi) << 32) | get_reg (acclo);
- break;
+ case sim_rx_acc0_regnum:
+ {
+ acc_t acc;
+ get_acc (0, &acc);
+ if (rx_big_endian)
+ put_be (buf, 8, acc.lo);
+ else
+ put_le (buf, 8, acc.lo);
+ return 8;
+ }
+ case sim_rx_acc1_regnum:
+ {
+ acc_t acc;
+ get_acc (1, &acc);
+ if (rx_big_endian)
+ put_be (buf, 8, acc.lo);
+ else
+ put_le (buf, 8, acc.lo);
+ return 8;
+ }
default:
fprintf (stderr, "rx minisim: unrecognized register number: %d\n",
regno);
@@ -623,10 +647,38 @@ sim_store_register (SIM_DESC sd, int regno, unsigned char *buf, int length)
case sim_rx_fpsw_regnum:
put_reg (fpsw, val);
break;
- case sim_rx_acc_regnum:
- put_reg (acclo, val & 0xffffffff);
- put_reg (acchi, (val >> 32) & 0xffffffff);
- break;
+ case sim_rx_acc0_regnum:
+ {
+ acc_t acc;
+ if (rx_big_endian)
+ {
+ acc.hi = get_be (buf, 8);
+ acc.lo = get_be (buf + 8, 8);
+ }
+ else
+ {
+ acc.lo = get_le (buf, 8);
+ acc.hi = get_le (buf + 8, 8);
+ }
+ put_acc (0, &acc);
+ break;
+ }
+ case sim_rx_acc1_regnum:
+ {
+ acc_t acc;
+ if (rx_big_endian)
+ {
+ acc.hi = get_be (buf, 8);
+ acc.lo = get_be (buf + 8, 8);
+ }
+ else
+ {
+ acc.lo = get_le (buf, 8);
+ acc.hi = get_le (buf + 8, 8);
+ }
+ put_acc (1, &acc);
+ break;
+ }
default:
fprintf (stderr, "rx minisim: unrecognized register number: %d\n",
regno);
diff --git a/sim/rx/reg.c b/sim/rx/reg.c
index 6effe4b..7971fa2 100644
--- a/sim/rx/reg.c
+++ b/sim/rx/reg.c
@@ -28,6 +28,8 @@
#include "bfd.h"
#include "trace.h"
+#define tprintf if (trace) printf
+
int verbose = 0;
int trace = 0;
int enable_counting = 0;
@@ -45,15 +47,15 @@ unsigned int heapbottom = 0;
unsigned int heaptop = 0;
char *reg_names[] = {
- /* general registers */
+ /* general registers */
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
- /* control register */
+ /* control registers */
"psw", "pc", "usp", "fpsw", "RES", "RES", "RES", "RES",
- "bpsw", "bpc", "isp", "fintv", "intb", "RES", "RES", "RES",
+ "bpsw", "bpc", "isp", "fintv", "intb", "extb", "li", "RES",
"RES", "RES", "RES", "RES", "RES", "RES", "RES", "RES",
"RES", "RES", "RES", "RES", "RES", "RES", "RES", "RES",
- "temp", "acc", "acchi", "accmi", "acclo"
+ "temp", "acc0", "acc1",
};
unsigned int b2mask[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
@@ -69,6 +71,9 @@ init_regs (void)
memset (®s, 0, sizeof (regs));
memset (&oldregs, 0, sizeof (oldregs));
+ regs.r_extb = 0xffffff80;
+ oldregs.r_extb = 0xffffff80;
+
#ifdef CYCLE_ACCURATE
regs.rt = -1;
oldregs.rt = -1;
@@ -102,16 +107,14 @@ get_reg_i (int id)
return regs.r_fintv;
case intb:
return regs.r_intb;
+ case extb:
+ return regs.r_extb;
+ case li:
+ return regs.r_li;
case pc:
return regs.r_pc;
case r_temp_idx:
return regs.r_temp;
- case acchi:
- return (SI)(regs.r_acc >> 32);
- case accmi:
- return (SI)(regs.r_acc >> 16);
- case acclo:
- return (SI)regs.r_acc;
}
abort();
}
@@ -125,25 +128,13 @@ get_reg (int id)
return rv;
}
-static unsigned long long
-get_reg64_i (int id)
-{
- switch (id)
- {
- case acc64:
- return regs.r_acc;
- default:
- abort ();
- }
-}
-
-unsigned long long
-get_reg64 (int id)
+void
+get_acc (int id, acc_t *acc)
{
- unsigned long long rv = get_reg64_i (id);
- if (trace > ((id != pc && id != sp) ? 0 : 1))
- printf ("get_reg (%s) = %016llx\n", reg_names[id], rv);
- return rv;
+ if (id >= 2)
+ abort ();
+ *acc = regs.r_acc[id];
+ tprintf ("get_reg (%s) = %08x%016lx\n", reg_names[acc0 + id], acc->hi, acc->lo);
}
static int highest_sp = 0, lowest_sp = 0xffffff;
@@ -203,18 +194,14 @@ put_reg (int id, unsigned int v)
case intb:
regs.r_intb = v;
break;
- case pc:
- regs.r_pc = v;
- break;
-
- case acchi:
- regs.r_acc = (regs.r_acc & 0xffffffffULL) | ((DI)v << 32);
+ case extb:
+ regs.r_extb = v;
break;
- case accmi:
- regs.r_acc = (regs.r_acc & ~0xffffffff0000ULL) | ((DI)v << 16);
+ case li:
+ regs.r_li = v;
break;
- case acclo:
- regs.r_acc = (regs.r_acc & ~0xffffffffULL) | ((DI)v);
+ case pc:
+ regs.r_pc = v;
break;
case 0: /* Stack pointer is "in" R0. */
@@ -261,19 +248,14 @@ put_reg (int id, unsigned int v)
}
void
-put_reg64 (int id, unsigned long long v)
+put_acc (int id, acc_t *acc)
{
- if (trace > ((id != pc) ? 0 : 1))
- printf ("put_reg (%s) = %016llx\n", reg_names[id], v);
- switch (id)
- {
- case acc64:
- regs.r_acc = v;
- break;
- default:
- abort ();
- }
+ if (id >= 2)
+ abort ();
+ tprintf ("put_reg (%s) = %08x%016lx\n", reg_names[acc0 + id], acc->hi, acc->lo);
+
+ regs.r_acc[id] = *acc;
}
int
@@ -506,14 +488,18 @@ fpsw2str(int rpsw)
return buf;
}
-#define TRC(f,n) \
- if (oldregs.f != regs.f) \
- { \
- if (tag) { printf (tag); tag = 0; } \
- printf(" %s %08x:%08x", n, \
- (unsigned int)oldregs.f, \
- (unsigned int)regs.f); \
- oldregs.f = regs.f; \
+#define TRC(f,n) \
+ if (oldregs.f != regs.f) \
+ { \
+ if (tag) \
+ { \
+ printf (tag); \
+ tag = 0; \
+ } \
+ printf (" %s %08x:%08x", n, \
+ (unsigned int)oldregs.f, \
+ (unsigned int)regs.f); \
+ oldregs.f = regs.f; \
}
void
@@ -545,14 +531,19 @@ trace_register_changes (void)
oldregs.r_fpsw = regs.r_fpsw;
}
- if (oldregs.r_acc != regs.r_acc)
+ for (i = 0; i < 2; i++)
{
- if (tag) { printf (tag); tag = 0; }
- printf(" acc %016llx:", oldregs.r_acc);
- printf("%016llx", regs.r_acc);
- oldregs.r_acc = regs.r_acc;
+ if (oldregs.r_acc[i].hi != regs.r_acc[i].hi ||
+ oldregs.r_acc[i].lo != regs.r_acc[i].lo)
+ {
+ if (tag) { printf (tag); tag = 0; }
+ printf (" acc%d %08x%016lx:", i, oldregs.r_acc[i].hi,
+ oldregs.r_acc[i].lo);
+ printf ("%08x%016lx", regs.r_acc[i].hi,
+ oldregs.r_acc[i].lo);
+ oldregs.r_acc[i] = regs.r_acc[i];
+ }
}
-
if (tag == 0)
printf ("\033[0m\n");
}
diff --git a/sim/rx/rx.c b/sim/rx/rx.c
index e48f6c8..a3cf635 100644
--- a/sim/rx/rx.c
+++ b/sim/rx/rx.c
@@ -137,6 +137,25 @@ static const char * id_names[] = {
"RXO_wait",
"RXO_sccnd", /* d = cond(s) ? 1 : 0 */
+
+ "RXO_fsqrt",
+ "RXO_ftou",
+ "RXO_utof",
+ "RXO_movco",
+ "RXO_movli",
+ "RXO_emaca",
+ "RXO_emsba",
+ "RXO_emula",
+ "RXO_maclh",
+ "RXO_msbhi",
+ "RXO_msblh",
+ "RXO_msblo",
+ "RXO_mullh",
+ "RXO_mvfacgu",
+ "RXO_mvtacgu",
+ "RXO_racl",
+ "RXO_rdacl",
+ "RXO_rdacw",
};
static const char * optype_names[] = {
@@ -806,8 +825,8 @@ fop_fsub (fp_t s1, fp_t s2, fp_t *d)
int do_store; \
fp_t fa, fb, fc; \
FPCLEAR(); \
- fb = GS (); \
- fa = GD (); \
+ fb = US2 (); \
+ fa = US1 (); \
do_store = fop_##func (fa, fb, &fc); \
tprintf("%g " #func " %g = %g %08x\n", int2float(fa), int2float(fb), int2float(fc), fc); \
FPCHECK(); \
@@ -929,6 +948,72 @@ op_is_memory (const RX_Opcode_Decoded *rd, int i)
#define DO_RETURN(x) { longjmp (decode_jmp_buf, x); }
+#define MULADD(val, s) \
+{ \
+ get_acc (opcode->op[0].reg - 32, &acc); \
+ sll = val; \
+ sll <<= s; \
+ if (sll > 0 && (unsigned long long)acc.lo > \
+ (unsigned long long)(acc.lo + sll)) \
+ acc.hi++; \
+ else if (sll < 0 && (unsigned long long)(acc.lo + sll) > \
+ (unsigned long long)acc.lo) \
+ acc.hi--; \
+ acc.lo += sll; \
+ put_acc (opcode->op[0].reg - 32, &acc); \
+ E1; \
+ break; \
+}
+
+#define MULSUB(val, s) \
+{ \
+ get_acc (opcode->op[0].reg - 32, &acc); \
+ sll = val; \
+ sll <<= s; \
+ if (sll > 0 && (unsigned long long)(sll - acc.lo) > \
+ (unsigned long long)acc.lo) \
+ acc.hi--; \
+ else if (sll < 0 && (unsigned long long)acc.lo > \
+ (unsigned long long)(sll - acc.lo)) \
+ acc.hi++; \
+ acc.hi = (signed char)acc.hi; \
+ acc.lo -= sll; \
+ put_acc (opcode->op[0].reg - 32, &acc); \
+ E1; \
+ break; \
+}
+
+#define MULACC(val, s) \
+{ \
+ sll = val; \
+ sll <<= s; \
+ acc.lo = sll; \
+ acc.hi = (sll < 0)? -1 : 0; \
+ put_acc (opcode->op[0].reg - 32, &acc); \
+ E1; \
+ break; \
+}
+
+#define RAC(add, pl, ml) \
+{ \
+ get_acc (opcode->op[0].reg - 32, &acc); \
+ ll = acc.lo << GS (); \
+ ll += add; \
+ if ((signed long long)ll > \
+ (signed long long)0x00007fff00000000ULL) \
+ ll = 0x00007fff00000000ULL; \
+ else if ((signed long long)ll < \
+ (signed long long)0xffff800000000000ULL) \
+ ll = 0xffff800000000000ULL; \
+ else \
+ ll &= 0xffffffff00000000ULL; \
+ acc.hi = ((signed long long)ll < 0) ? -1 : 0; \
+ acc.lo = ll; \
+ put_acc (opcode->op[0].reg - 32, &acc); \
+ E1; \
+ break; \
+}
+
int
decode_opcode ()
{
@@ -940,6 +1025,7 @@ decode_opcode ()
unsigned long opcode_pc;
RX_Data rx_data;
const RX_Opcode_Decoded *opcode;
+ acc_t acc;
#ifdef CYCLE_STATS
unsigned long long prev_cycle_count;
#endif
@@ -1216,6 +1302,12 @@ decode_opcode ()
}
break;
+ case RXO_emaca:
+ MULADD ((long long)GS2 () * (long long)GS (), 0)
+
+ case RXO_emsba:
+ MULSUB ((long long)GS2 () * (long long)GS (), 0)
+
case RXO_emul:
ma = GD ();
mb = GS ();
@@ -1226,6 +1318,18 @@ decode_opcode ()
E2;
break;
+ case RXO_emula:
+ ma = GS2 ();
+ mb = GS ();
+ acc.lo = (long long)ma * (long long)mb;
+ if (acc.lo < 0)
+ acc.hi = -1;
+ else
+ acc.hi = 0;
+ put_acc (opcode->op[0].reg - 32, &acc);
+ E (3);
+ break;
+
case RXO_emulu:
uma = GD ();
umb = GS ();
@@ -1264,12 +1368,24 @@ decode_opcode ()
PRIVILEDGED ();
regs.r_psw = regs.r_bpsw;
regs.r_pc = regs.r_bpc;
+ regs.r_li = 0;
#ifdef CYCLE_ACCURATE
regs.fast_return = 0;
cycles(3);
#endif
break;
+ case RXO_fsqrt:
+ ma = GS ();
+ FPCLEAR ();
+ mb = rxfp_fsqrt (ma);
+ FPCHECK ();
+ PD (mb);
+ tprintf ("(int) %g = %d\n", int2float (ma), mb);
+ set_sz (mb, 4);
+ E (16);
+ break;
+
case RXO_fsub:
FLOAT_OP (fsub);
E (4);
@@ -1281,7 +1397,18 @@ decode_opcode ()
mb = rxfp_ftoi (ma, FPRM_ZERO);
FPCHECK ();
PD (mb);
- tprintf("(int) %g = %d\n", int2float(ma), mb);
+ tprintf ("(int) %g = %d\n", int2float (ma), mb);
+ set_sz (mb, 4);
+ E (2);
+ break;
+
+ case RXO_ftou:
+ ma = GS ();
+ FPCLEAR ();
+ mb = rxfp_ftou (ma, FPRM_ZERO);
+ FPCHECK ();
+ PD (mb);
+ tprintf ("(int) %g = %d\n", int2float (ma), mb);
set_sz (mb, 4);
E (2);
break;
@@ -1352,18 +1479,16 @@ decode_opcode ()
break;
case RXO_machi:
- ll = (long long)(signed short)(GS() >> 16) * (long long)(signed short)(GS2 () >> 16);
- ll <<= 16;
- put_reg64 (acc64, ll + regs.r_acc);
- E1;
- break;
+ MULADD ((long long)(signed short)(GS () >> 16) *
+ (long long)(signed short)(GS2 () >> 16), 16)
+
+ case RXO_maclh:
+ MULADD ((long long)(signed short)(GS ()) *
+ (long long)(signed short)(GS2 () >> 16), 16)
case RXO_maclo:
- ll = (long long)(signed short)(GS()) * (long long)(signed short)(GS2 ());
- ll <<= 16;
- put_reg64 (acc64, ll + regs.r_acc);
- E1;
- break;
+ MULADD ((long long)(signed short)(GS ()) *
+ (long long)(signed short)(GS2 ()), 16)
case RXO_max:
mb = GS();
@@ -1457,6 +1582,36 @@ decode_opcode ()
cycles (1);
break;
+ case RXO_movli:
+ PD (mem_get_si (GS ()));
+ regs.r_li = 1;
+ E1;
+ break;
+
+ case RXO_movco:
+ if (regs.r_li == 1)
+ {
+ mem_put_si (GD (), GS ());
+ PS (0);
+ }
+ else
+ PS (1);
+ regs.r_li = 0;
+ E1;
+ break;
+
+ case RXO_msbhi:
+ MULSUB ((long long)(signed short)(GS () >> 16) *
+ (long long)(signed short)(GS2 () >> 16), 16)
+
+ case RXO_msblh:
+ MULSUB ((long long)(signed short)(GS ()) *
+ (long long)(signed short)(GS2 () >> 16), 16)
+
+ case RXO_msblo:
+ MULSUB ((long long)(signed short)(GS ()) *
+ (long long)(signed short)(GS2 ()), 16)
+
case RXO_mul:
v = US2 ();
ll = (unsigned long long) US1() * (unsigned long long) v;
@@ -1465,43 +1620,67 @@ decode_opcode ()
break;
case RXO_mulhi:
- v = GS2 ();
- ll = (long long)(signed short)(GS() >> 16) * (long long)(signed short)(v >> 16);
- ll <<= 16;
- put_reg64 (acc64, ll);
- E1;
- break;
+ MULACC ((long long)(signed short)(GS () >> 16) *
+ (long long)(signed short)(GS2 () >> 16), 16)
+ case RXO_mullh:
+ MULACC ((long long)(signed short)(GS ()) *
+ (long long)(signed short)(GS2 () >> 16), 16)
case RXO_mullo:
- v = GS2 ();
- ll = (long long)(signed short)(GS()) * (long long)(signed short)(v);
- ll <<= 16;
- put_reg64 (acc64, ll);
- E1;
- break;
+ MULACC ((long long)(signed short)(GS ()) *
+ (long long)(signed short)(GS2 ()), 16)
case RXO_mvfachi:
- PD (get_reg (acchi));
+ get_acc (opcode->op[1].reg - 32, &acc);
+ PD ((acc.lo << GS2 ()) >> 32);
E1;
break;
case RXO_mvfaclo:
- PD (get_reg (acclo));
+ get_acc (opcode->op[1].reg - 32, &acc);
+ PD (acc.lo << GS2 ());
E1;
break;
case RXO_mvfacmi:
- PD (get_reg (accmi));
+ get_acc (opcode->op[1].reg - 32, &acc);
+ PD ((acc.lo << GS2 ()) >> 16);
+ E1;
+ break;
+
+ case RXO_mvfacgu:
+ get_acc (opcode->op[1].reg - 32, &acc);
+ uma = (signed char)acc.hi;
+ umb = GS2 ();
+ if (umb)
+ {
+ uma <<= umb;
+ uma |= ((acc.lo >> (64 - umb)) & 3);
+ }
+ PD (uma);
E1;
break;
case RXO_mvtachi:
- put_reg (acchi, GS ());
+ get_acc (opcode->op[0].reg - 32, &acc);
+ acc.lo &= ((1ULL << 32) - 1);
+ acc.lo |= (unsigned long long) GS () << 32ULL;
+ put_acc (opcode->op[0].reg - 32, &acc);
E1;
break;
case RXO_mvtaclo:
- put_reg (acclo, GS ());
+ get_acc (opcode->op[0].reg - 32, &acc);
+ acc.lo &= ~((1ULL << 32ULL) - 1);
+ acc.lo |= (unsigned long) GS ();
+ put_acc (opcode->op[0].reg - 32, &acc);
+ E1;
+ break;
+
+ case RXO_mvtacgu:
+ get_acc (opcode->op[0].reg - 32, &acc);
+ acc.hi = GS ();
+ put_acc (opcode->op[0].reg - 32, &acc);
E1;
break;
@@ -1560,22 +1739,22 @@ decode_opcode ()
break;
case RXO_racw:
- ll = get_reg64 (acc64) << GS ();
- ll += 0x80000000ULL;
- if ((signed long long)ll > (signed long long)0x00007fff00000000ULL)
- ll = 0x00007fff00000000ULL;
- else if ((signed long long)ll < (signed long long)0xffff800000000000ULL)
- ll = 0xffff800000000000ULL;
- else
- ll &= 0xffffffff00000000ULL;
- put_reg64 (acc64, ll);
- E1;
- break;
+ RAC (0x80000000ULL, 0x00007fff00000000ULL, 0xffff800000000000ULL)
+
+ case RXO_rdacw:
+ RAC (0, 0x00007fff00000000ULL, 0xffffffff80000000ULL)
+
+ case RXO_racl:
+ RAC (0x80000000ULL, 0x7fffffff00000000ULL, 0xffffffff80000000ULL)
+
+ case RXO_rdacl:
+ RAC (0, 0x7fffffff00000000ULL, 0xffff800000000000ULL)
case RXO_rte:
PRIVILEDGED ();
regs.r_pc = poppc ();
regs.r_psw = poppc ();
+ regs.r_li = 0;
if (FLAG_PM)
regs.r_psw |= FLAGBIT_U;
#ifdef CYCLE_ACCURATE
@@ -2130,6 +2309,21 @@ decode_opcode ()
set_zc (0, ((int)uma - (int)umb) >= 0);
break;
+ case RXO_utof:
+ ma = GS ();
+ FPCLEAR ();
+ mb = rxfp_utof (ma, regs.r_fpsw);
+ FPCHECK ();
+ tprintf ("(float) %d = %x\n", ma, mb);
+ PD (mb);
+ if (mb)
+ set_flags (FLAGBIT_Z, 0);
+ else
+ set_flags (FLAGBIT_Z, FLAGBIT_Z);
+ set_flags (FLAGBIT_S, 0);
+ E (2);
+ break;
+
case RXO_wait:
PRIVILEDGED ();
regs.r_psw |= FLAGBIT_I;
--
2.6.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH][RX] instructions test set..
2015-12-27 8:51 [PATCH][RX] v2 instructions support Yoshinori Sato
@ 2015-12-27 8:51 ` Yoshinori Sato
2015-12-27 21:56 ` Mike Frysinger
2015-12-27 21:55 ` [PATCH][RX] v2 instructions support Mike Frysinger
1 sibling, 1 reply; 11+ messages in thread
From: Yoshinori Sato @ 2015-12-27 8:51 UTC (permalink / raw)
To: gdb-patches; +Cc: Yoshinori Sato
---
sim/testsuite/sim/rx/ChangeLog | 11 ++
sim/testsuite/sim/rx/abs.s | 25 +++
sim/testsuite/sim/rx/adc.s | 77 ++++++++++
sim/testsuite/sim/rx/add.s | 108 +++++++++++++
sim/testsuite/sim/rx/allinsn.exp | 25 +++
sim/testsuite/sim/rx/and.s | 79 ++++++++++
sim/testsuite/sim/rx/bcnd.s | 60 ++++++++
sim/testsuite/sim/rx/bmcnd.s | 132 ++++++++++++++++
sim/testsuite/sim/rx/bra.s | 23 +++
sim/testsuite/sim/rx/bset.s | 197 ++++++++++++++++++++++++
sim/testsuite/sim/rx/cmp.s | 74 +++++++++
sim/testsuite/sim/rx/div.s | 52 +++++++
sim/testsuite/sim/rx/emaca.s | 24 +++
sim/testsuite/sim/rx/emsba.s | 24 +++
sim/testsuite/sim/rx/emul.s | 92 +++++++++++
sim/testsuite/sim/rx/emula.s | 24 +++
sim/testsuite/sim/rx/fadd.s | 41 +++++
sim/testsuite/sim/rx/fcmp.s | 37 +++++
sim/testsuite/sim/rx/fdiv.s | 43 ++++++
sim/testsuite/sim/rx/fmul.s | 51 +++++++
sim/testsuite/sim/rx/fsqrt.s | 23 +++
sim/testsuite/sim/rx/fsub.s | 51 +++++++
sim/testsuite/sim/rx/ftoi.s | 37 +++++
sim/testsuite/sim/rx/ftou.s | 37 +++++
sim/testsuite/sim/rx/itof.s | 37 +++++
sim/testsuite/sim/rx/jmp.s | 12 ++
sim/testsuite/sim/rx/machilo.s | 53 +++++++
sim/testsuite/sim/rx/max.s | 45 ++++++
sim/testsuite/sim/rx/min.s | 45 ++++++
sim/testsuite/sim/rx/mov.s | 196 ++++++++++++++++++++++++
sim/testsuite/sim/rx/movlico.s | 22 +++
sim/testsuite/sim/rx/movu.s | 67 ++++++++
sim/testsuite/sim/rx/msbhilo.s | 43 ++++++
sim/testsuite/sim/rx/mul.s | 52 +++++++
sim/testsuite/sim/rx/mulhilo.s | 54 +++++++
sim/testsuite/sim/rx/mvacc.s | 28 ++++
sim/testsuite/sim/rx/mvftc.s | 36 +++++
sim/testsuite/sim/rx/neg.s | 17 +++
sim/testsuite/sim/rx/not.s | 17 +++
sim/testsuite/sim/rx/or.s | 69 +++++++++
sim/testsuite/sim/rx/pushpop.s | 48 ++++++
sim/testsuite/sim/rx/racw.s | 38 +++++
sim/testsuite/sim/rx/rdacw.s | 19 +++
sim/testsuite/sim/rx/rev.s | 14 ++
sim/testsuite/sim/rx/rmpa.s | 23 +++
sim/testsuite/sim/rx/rot.s | 46 ++++++
sim/testsuite/sim/rx/round.s | 37 +++++
sim/testsuite/sim/rx/sat.s | 37 +++++
sim/testsuite/sim/rx/sbb.s | 46 ++++++
sim/testsuite/sim/rx/sccnd.s | 169 +++++++++++++++++++++
sim/testsuite/sim/rx/scmpu.s | 26 ++++
sim/testsuite/sim/rx/shlr.s | 67 ++++++++
sim/testsuite/sim/rx/smovb.s | 53 +++++++
sim/testsuite/sim/rx/smovu.s | 23 +++
sim/testsuite/sim/rx/sstr.s | 44 ++++++
sim/testsuite/sim/rx/stz.s | 52 +++++++
sim/testsuite/sim/rx/sub.s | 53 +++++++
sim/testsuite/sim/rx/suntil.s | 59 ++++++++
sim/testsuite/sim/rx/testutils.inc | 302 +++++++++++++++++++++++++++++++++++++
sim/testsuite/sim/rx/tst.s | 54 +++++++
sim/testsuite/sim/rx/utof.s | 37 +++++
sim/testsuite/sim/rx/xchg.s | 36 +++++
sim/testsuite/sim/rx/xor.s | 58 +++++++
63 files changed, 3481 insertions(+)
create mode 100644 sim/testsuite/sim/rx/ChangeLog
create mode 100644 sim/testsuite/sim/rx/abs.s
create mode 100644 sim/testsuite/sim/rx/adc.s
create mode 100644 sim/testsuite/sim/rx/add.s
create mode 100644 sim/testsuite/sim/rx/allinsn.exp
create mode 100644 sim/testsuite/sim/rx/and.s
create mode 100644 sim/testsuite/sim/rx/bcnd.s
create mode 100644 sim/testsuite/sim/rx/bmcnd.s
create mode 100644 sim/testsuite/sim/rx/bra.s
create mode 100644 sim/testsuite/sim/rx/bset.s
create mode 100644 sim/testsuite/sim/rx/cmp.s
create mode 100644 sim/testsuite/sim/rx/div.s
create mode 100644 sim/testsuite/sim/rx/emaca.s
create mode 100644 sim/testsuite/sim/rx/emsba.s
create mode 100644 sim/testsuite/sim/rx/emul.s
create mode 100644 sim/testsuite/sim/rx/emula.s
create mode 100644 sim/testsuite/sim/rx/fadd.s
create mode 100644 sim/testsuite/sim/rx/fcmp.s
create mode 100644 sim/testsuite/sim/rx/fdiv.s
create mode 100644 sim/testsuite/sim/rx/fmul.s
create mode 100644 sim/testsuite/sim/rx/fsqrt.s
create mode 100644 sim/testsuite/sim/rx/fsub.s
create mode 100644 sim/testsuite/sim/rx/ftoi.s
create mode 100644 sim/testsuite/sim/rx/ftou.s
create mode 100644 sim/testsuite/sim/rx/itof.s
create mode 100644 sim/testsuite/sim/rx/jmp.s
create mode 100644 sim/testsuite/sim/rx/machilo.s
create mode 100644 sim/testsuite/sim/rx/max.s
create mode 100644 sim/testsuite/sim/rx/min.s
create mode 100644 sim/testsuite/sim/rx/mov.s
create mode 100644 sim/testsuite/sim/rx/movlico.s
create mode 100644 sim/testsuite/sim/rx/movu.s
create mode 100644 sim/testsuite/sim/rx/msbhilo.s
create mode 100644 sim/testsuite/sim/rx/mul.s
create mode 100644 sim/testsuite/sim/rx/mulhilo.s
create mode 100644 sim/testsuite/sim/rx/mvacc.s
create mode 100644 sim/testsuite/sim/rx/mvftc.s
create mode 100644 sim/testsuite/sim/rx/neg.s
create mode 100644 sim/testsuite/sim/rx/not.s
create mode 100644 sim/testsuite/sim/rx/or.s
create mode 100644 sim/testsuite/sim/rx/pushpop.s
create mode 100644 sim/testsuite/sim/rx/racw.s
create mode 100644 sim/testsuite/sim/rx/rdacw.s
create mode 100644 sim/testsuite/sim/rx/rev.s
create mode 100644 sim/testsuite/sim/rx/rmpa.s
create mode 100644 sim/testsuite/sim/rx/rot.s
create mode 100644 sim/testsuite/sim/rx/round.s
create mode 100644 sim/testsuite/sim/rx/sat.s
create mode 100644 sim/testsuite/sim/rx/sbb.s
create mode 100644 sim/testsuite/sim/rx/sccnd.s
create mode 100644 sim/testsuite/sim/rx/scmpu.s
create mode 100644 sim/testsuite/sim/rx/shlr.s
create mode 100644 sim/testsuite/sim/rx/smovb.s
create mode 100644 sim/testsuite/sim/rx/smovu.s
create mode 100644 sim/testsuite/sim/rx/sstr.s
create mode 100644 sim/testsuite/sim/rx/stz.s
create mode 100644 sim/testsuite/sim/rx/sub.s
create mode 100644 sim/testsuite/sim/rx/suntil.s
create mode 100644 sim/testsuite/sim/rx/testutils.inc
create mode 100644 sim/testsuite/sim/rx/tst.s
create mode 100644 sim/testsuite/sim/rx/utof.s
create mode 100644 sim/testsuite/sim/rx/xchg.s
create mode 100644 sim/testsuite/sim/rx/xor.s
diff --git a/sim/testsuite/sim/rx/ChangeLog b/sim/testsuite/sim/rx/ChangeLog
new file mode 100644
index 0000000..d149e6a
--- /dev/null
+++ b/sim/testsuite/sim/rx/ChangeLog
@@ -0,0 +1,11 @@
+2015-12-27 Yoshinori Sato <ysatt@users.sourceforge.jp>
+
+ * abs.s, adc.s, add.s, and.s, bcnd.s, bmcnd.s, bra.s, bset.s,
+ cmp.s, div.s, emaca.s, emsba.s, emul.s, emula.s, fadd.s, fcmp.s,
+ fdiv.s, fmul.s, fsqrt.s, fsub.s, ftoi.s, ftou.s, itof.s, jmp.s,
+ machilo.s, max.s, min.s, mov.s, movlico.s, movu.s, msbhilo.s,
+ mul.s, mulhilo.s, mvacc.s, mvftc.s, neg.s, not.s, or.s,pushpop.s,
+ racw.s, rdacw.s, rev.s, rmpa.s, rot.s, round.s, sbb.s, sccnd.s,
+ scmpu.s, shlr.s, smovb.s, smovu.s, sstr.s, stz.s, sub.s, suntil.s,
+ tst.s,utof.s,xchg.s,xor.s: New file.
+ * allinsn.exp: New file.
diff --git a/sim/testsuite/sim/rx/abs.s b/sim/testsuite/sim/rx/abs.s
new file mode 100644
index 0000000..3747797
--- /dev/null
+++ b/sim/testsuite/sim/rx/abs.s
@@ -0,0 +1,25 @@
+# RX testcase for abs
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+abs_dest:
+ mov.l #1,r1
+ abs r1
+ test_h_gr32 1 r1
+ mov.l #-1,r1
+ abs r1
+ test_h_gr32 1 r1
+abs_src_dest:
+ sub r2,r2
+ mov.l #1,r1
+ abs r1,r2
+ test_h_gr32 1 r2
+ sub r2,r2
+ mov.l #-1,r1
+ abs r1,r2
+ test_h_gr32 1 r2
+
+ pass
diff --git a/sim/testsuite/sim/rx/adc.s b/sim/testsuite/sim/rx/adc.s
new file mode 100644
index 0000000..49a8a6e
--- /dev/null
+++ b/sim/testsuite/sim/rx/adc.s
@@ -0,0 +1,77 @@
+# RX testcase for adc
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+adc_imm4:
+ clear_carry_flag
+ mov.l #1,r1
+ adc #2,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 3 r1
+adc_imm8:
+ clear_carry_flag
+ adc #-1,r1
+ test_zero_clear
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 2 r1
+adc_imm16:
+ set_carry_flag
+ adc #0x7ffd,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 0x8000 r1
+adc_imm24:
+ clear_carry_flag
+ adc #0x800000 - 0x8000,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 0x800000 r1
+adc_imm32:
+ clear_carry_flag
+ adc #0x80000000 - 0x800000,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_set
+ test_h_gr32 0x80000000 r1
+adc_reg:
+ clear_carry_flag
+ mov.l #0x80000000,r2
+ adc r2,r1
+ test_zero_set
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 0 r1
+adc_mem_ind:
+ mov.l #val, r2
+ adc [r2].l,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 2 r1
+adc_mem_dsp8:
+ mov.l #val-4, r2
+ adc 4[r2].l,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 4 r1
+adc_mem_dsp16:
+ mov.l #val-0x1000, r2
+ adc 0x1000[r2].l,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 6 r1
+
+ pass
+
+ .data
+val: .long 1
diff --git a/sim/testsuite/sim/rx/add.s b/sim/testsuite/sim/rx/add.s
new file mode 100644
index 0000000..a483d01
--- /dev/null
+++ b/sim/testsuite/sim/rx/add.s
@@ -0,0 +1,108 @@
+# RX testcase for add
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+add_imm4:
+ mov.l #1,r1
+ add #2,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 3 r1
+add_imm8:
+ add #-1,r1
+ test_zero_clear
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 2 r1
+add_imm16:
+ add #0x7ffe,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 0x8000 r1
+add_imm24:
+ add #0x800000 - 0x8000,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 0x800000 r1
+add_imm32:
+ add #0x80000000 - 0x800000,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_set
+ test_h_gr32 0x80000000 r1
+add_reg:
+ mov.l #0x80000000,r2
+ add r2,r1
+ test_zero_set
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 0 r1
+add_mem_ind:
+ mov.l #val, r2
+ add [r2].l,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 1 r1
+add_mem_dsp8:
+ mov.l #val-4, r2
+ add 4[r2].l,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 2 r1
+add_mem_dsp16:
+ mov.l #val-0x1000, r2
+ add 0x1000[r2].l,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 3 r1
+add3_imm4:
+ mov.l #1,r1
+ add #2,r1,r2
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 3 r2
+add3_imm8:
+ add #-1,r1,r2
+ test_zero_set
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 0 r2
+add3_imm16:
+ add #0x7ffe,r1,r2
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 0x7fff r2
+add3_imm24:
+ add #0x7ffffe,r1,r2
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 0x7fffff r2
+add3_imm32:
+ add #0x7ffffffe,r1,r2
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 0x7fffffff r2
+add3_reg:
+ add r1,r1,r2
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 2 r2
+
+ pass
+
+ .data
+val: .long 1
diff --git a/sim/testsuite/sim/rx/allinsn.exp b/sim/testsuite/sim/rx/allinsn.exp
new file mode 100644
index 0000000..e566c62
--- /dev/null
+++ b/sim/testsuite/sim/rx/allinsn.exp
@@ -0,0 +1,25 @@
+# Renesas RX simulator testsuite
+
+if [istarget rx-*-*] {
+ set global_ld_options "-Ttext=0x01000000 --defsym __stack=0x01800000"
+
+ set mach "rx"
+ foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] {
+ # If we're only testing specific files and this isn't one of them,
+ # skip it.
+ if ![runtest_file_p $runtests $src] {
+ continue
+ }
+ run_sim_test $src $mach
+ }
+
+ set mach "rxv2"
+ foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] {
+ # If we're only testing specific files and this isn't one of them,
+ # skip it.
+ if ![runtest_file_p $runtests $src] {
+ continue
+ }
+ run_sim_test $src $mach
+ }
+}
diff --git a/sim/testsuite/sim/rx/and.s b/sim/testsuite/sim/rx/and.s
new file mode 100644
index 0000000..4044562
--- /dev/null
+++ b/sim/testsuite/sim/rx/and.s
@@ -0,0 +1,79 @@
+# RX testcase for and
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+and_imm4:
+ mov.l #2,r1
+ and #2,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 2 r1
+and_imm8:
+ and #0x13,r1
+ test_zero_clear
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 2 r1
+and_imm16:
+ and #0xffff,r1
+ test_zero_clear
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 2 r1
+and_imm24:
+ and #0xffffff,r1
+ test_zero_clear
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 2 r1
+and_imm32:
+ mov.l #0x80000000,r1
+ and #0xffffffff,r1
+ test_zero_clear
+ test_carry_set
+ test_neg_set
+ test_h_gr32 0x80000000 r1
+and_reg:
+ mov.l #0x80000000,r2
+ and r2,r1
+ test_zero_clear
+ test_carry_set
+ test_neg_set
+ test_h_gr32 0x80000000 r1
+and_mem_ind:
+ mov.l #val, r2
+ and [r2].l,r1
+ test_zero_set
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 0 r1
+and_mem_dsp8:
+ mov.l #val-4, r2
+ and 4[r2].l,r1
+ test_zero_set
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 0 r1
+and_mem_dsp16:
+ mov.l #val-0x1000, r2
+ and 0x1000[r2].l,r1
+ test_zero_set
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 0 r1
+and3_reg:
+ mov.l #0x80000000,r2
+ and r2,r1,r3
+ test_zero_set
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 0 r3
+
+ pass
+
+ .data
+val: .long 1
diff --git a/sim/testsuite/sim/rx/bcnd.s b/sim/testsuite/sim/rx/bcnd.s
new file mode 100644
index 0000000..769c4b8
--- /dev/null
+++ b/sim/testsuite/sim/rx/bcnd.s
@@ -0,0 +1,60 @@
+# RX testcase for Bcnd
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ sub r2,r2
+ set_zero_flag
+ beq.s 1f
+ add #1,r2
+1: clear_zero_flag
+ bne.s 2f
+ add #1,r2
+2: test_h_gr32 0 r2
+ mov #10,r1
+ cmp #5,r1
+ bc 3f
+ fail
+3: cmp #15,r1
+ bnc 4f
+ fail
+4: mov #-5,r1
+ cmp #-10,r1
+ bgt 5f
+ fail
+5: cmp #-5,r1
+ ble 6f
+ fail
+6: bge 7f
+ fail
+7: cmp #-1,r1
+ blt 8f
+ fail
+8: mov.l #0xc0000000,r1
+ cmp #0x80000000,r1
+ bgtu 9f
+ fail
+9: mov #1,r1
+ tst r1,r1
+ bpz 11f
+ fail
+11: mov #-1,r1
+ tst r1,r1
+ bn 12f
+ fail
+12: set_overflow_flag
+ bo 13f
+ fail
+13: clear_overflow_flag
+ bno 14f
+ fail
+14: set_zero_flag
+ beq.w 15f
+ fail
+15: clear_zero_flag
+ bne.w 16f
+ fail
+16:
+ pass
diff --git a/sim/testsuite/sim/rx/bmcnd.s b/sim/testsuite/sim/rx/bmcnd.s
new file mode 100644
index 0000000..f3059eb
--- /dev/null
+++ b/sim/testsuite/sim/rx/bmcnd.s
@@ -0,0 +1,132 @@
+# RX testcase for BMcnd
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ mov #val,r2
+ mov #val-4,r3
+ mov #val-0x1000,r4
+ mov #10,r1
+ cmp #5,r1
+ bmc #0,[r2].b
+ bmc #1,4[r3].b
+ bmc #2,0x1000[r4].b
+ bmc #0,r5
+ btst #0,r5
+ test_zero_clear
+ mov.b [r2],r5
+ test_h_gr32 7 r5
+ mov.b #0,[r2]
+ cmp #15,r1
+ bmnc #0,[r2].b
+ bmnc #1,4[r3].b
+ bmnc #2,0x1000[r4].b
+ bmnc #0,r5
+ btst #0,r5
+ test_zero_clear
+ mov.b [r2],r5
+ test_h_gr32 7 r5
+ mov.b #0,[r2]
+ mov #-5,r1
+ cmp #-10,r1
+ bmgt #0,[r2].b
+ bmgt #1,4[r3].b
+ bmgt #2,0x1000[r4].b
+ bmgt #0,r5
+ btst #0,r5
+ test_zero_clear
+ mov.b [r2],r5
+ test_h_gr32 7 r5
+ mov.b #0,[r2]
+ mov #-5,r1
+ cmp #-5,r1
+ bmle #0,[r2].b
+ bmle #1,4[r3].b
+ bmle #2,0x1000[r4].b
+ bmle #0,r5
+ btst #0,r5
+ test_zero_clear
+ mov.b [r2],r5
+ test_h_gr32 7 r5
+ mov.b #0,[r2]
+ mov #-5,r1
+ cmp #-5,r1
+ bmge #0,[r2].b
+ bmge #1,4[r3].b
+ bmge #2,0x1000[r4].b
+ bmge #0,r5
+ btst #0,r5
+ test_zero_clear
+ mov.b [r2],r5
+ test_h_gr32 7 r5
+ mov.b #0,[r2]
+ mov #-5,r1
+ cmp #-1,r1
+ bmlt #0,[r2].b
+ bmlt #1,4[r3].b
+ bmlt #2,0x1000[r4].b
+ bmlt #0,r5
+ btst #0,r5
+ test_zero_clear
+ mov.b [r2],r5
+ test_h_gr32 7 r5
+ mov.b #0,[r2]
+ mov.l #0xc0000000,r1
+ cmp #0x80000000,r1
+ bmgtu #0,[r2].b
+ bmgtu #1,4[r3].b
+ bmgtu #2,0x1000[r4].b
+ bmgtu #0,r5
+ btst #0,r5
+ test_zero_clear
+ mov.b [r2],r5
+ test_h_gr32 7 r5
+ mov.b #0,[r2]
+ mov #1,r1
+ tst r1,r1
+ bmpz #0,[r2].b
+ bmpz #1,4[r3].b
+ bmpz #2,0x1000[r4].b
+ bmpz #0,r5
+ btst #0,r5
+ test_zero_clear
+ mov.b [r2],r5
+ test_h_gr32 7 r5
+ mov.b #0,[r2]
+ mov #-1,r1
+ tst r1,r1
+ bmn #0,[r2].b
+ bmn #1,4[r3].b
+ bmn #2,0x1000[r4].b
+ bmn #0,r5
+ btst #0,r5
+ test_zero_clear
+ mov.b [r2],r5
+ test_h_gr32 7 r5
+ mov.b #0,[r2]
+ set_overflow_flag
+ bmo #0,[r2].b
+ bmo #1,4[r3].b
+ bmo #2,0x1000[r4].b
+ bmo #0,r5
+ btst #0,r5
+ test_zero_clear
+ mov.b [r2],r5
+ test_h_gr32 7 r5
+ mov.b #0,[r2]
+ clear_overflow_flag
+ bmno #0,[r2].b
+ bmno #1,4[r3].b
+ bmno #2,0x1000[r4].b
+ bmno #0,r5
+ btst #0,r5
+ test_zero_clear
+ mov.b [r2],r5
+ test_h_gr32 7 r5
+
+ pass
+
+ .data
+val: .byte 0
diff --git a/sim/testsuite/sim/rx/bra.s b/sim/testsuite/sim/rx/bra.s
new file mode 100644
index 0000000..443d4db
--- /dev/null
+++ b/sim/testsuite/sim/rx/bra.s
@@ -0,0 +1,23 @@
+# RX testcase for bra
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ sub r2,r2
+ bra.s 1f
+ add #1,r2
+1: test_h_gr32 0 r2
+ bra.b 2f
+ fail
+2: bra.w 3f
+ fail
+3: bra.a 4f
+ fail
+4: mov #6f,r1
+ sub #5f,r1
+5: bra r1
+ fail
+6:
+ pass
diff --git a/sim/testsuite/sim/rx/bset.s b/sim/testsuite/sim/rx/bset.s
new file mode 100644
index 0000000..69c6e21
--- /dev/null
+++ b/sim/testsuite/sim/rx/bset.s
@@ -0,0 +1,197 @@
+# RX testcase for bset/bclr/bnot/btst
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+bset_imm_ind:
+ mov.l #val,r2
+ bset #0,[r2].b
+ btst #0,[r2].b
+ test_zero_clear
+ test_carry_set
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 3 r1
+bclr_imm_ind:
+ bclr #1,[r2].b
+ btst #1,[r2].b
+ test_zero_set
+ test_carry_clear
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 1 r1
+bnot_imm_ind:
+ bnot #1,[r2].b
+ btst #1,[r2].b
+ test_zero_clear
+ test_carry_set
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 3 r1
+bset_imm_dsp8:
+ mov.l #val-4,r2
+ bset #2,4[r2].b
+ btst #2,4[r2].b
+ test_zero_clear
+ test_carry_set
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 7 r1
+bclr_imm_dsp8:
+ bclr #2,4[r2].b
+ btst #2,4[r2].b
+ test_zero_set
+ test_carry_clear
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 3 r1
+bnot_imm_dsp8:
+ bnot #2,4[r2].b
+ btst #2,4[r2].b
+ test_zero_clear
+ test_carry_set
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 7 r1
+bset_imm_dsp16:
+ mov.l #val-0x1000,r2
+ bset #2,0x1000[r2].b
+ btst #2,0x1000[r2].b
+ test_zero_clear
+ test_carry_set
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 7 r1
+bclr_imm_dsp16:
+ bclr #2,0x1000[r2].b
+ btst #2,0x1000[r2].b
+ test_zero_set
+ test_carry_clear
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 3 r1
+bnot_imm_dsp16:
+ bnot #2,0x1000[r2].b
+ btst #2,0x1000[r2].b
+ test_zero_clear
+ test_carry_set
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 7 r1
+bset_reg_ind:
+ mov.l #0,r1
+ mov.l #val,r2
+ bset r1,[r2].b
+ btst r1,[r2].b
+ test_zero_clear
+ test_carry_set
+ mov.b [r2],r1
+ test_h_gr32 7 r1
+bclr_reg_ind:
+ mov.l #0,r1
+ bclr r1,[r2].b
+ btst r1,[r2].b
+ test_zero_set
+ test_carry_clear
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 6 r1
+bnot_reg_ind:
+ mov.l #0,r1
+ bnot r1,[r2].b
+ btst r1,[r2].b
+ test_zero_clear
+ test_carry_set
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 7 r1
+bset_reg_dsp8:
+ mov.l #2,r1
+ mov.l #val-4,r2
+ bset r1,4[r2].b
+ btst r1,4[r2].b
+ test_zero_clear
+ test_carry_set
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 7 r1
+bclr_reg_dsp8:
+ mov.l #2,r1
+ bclr r1,4[r2].b
+ btst r1,4[r2].b
+ test_zero_set
+ test_carry_clear
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 3 r1
+bnot_reg_dsp8:
+ mov.l #2,r1
+ bnot r1,4[r2].b
+ btst r1,4[r2].b
+ test_zero_clear
+ test_carry_set
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 7 r1
+bset_reg_dsp16:
+ mov.l #2,r1
+ mov.l #val-0x1000,r2
+ bset r1,0x1000[r2].b
+ btst r1,0x1000[r2].b
+ test_zero_clear
+ test_carry_set
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 7 r1
+bclr_reg_dsp16:
+ mov.l #2,r1
+ bclr r1,0x1000[r2].b
+ btst r1,0x1000[r2].b
+ test_zero_set
+ test_carry_clear
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 3 r1
+bnot_reg_dsp16:
+ mov.l #2,r1
+ bnot r1,0x1000[r2].b
+ btst r1,0x1000[r2].b
+ test_zero_clear
+ test_carry_set
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 7 r1
+bnot_imm_reg:
+ sub r1,r1
+ bnot #1,r1
+ btst #1,r1
+ test_zero_clear
+ test_carry_set
+ test_h_gr32 2 r1
+bset_reg_reg:
+ sub r1,r1
+ mov.l #1,r2
+ bset r2,r1
+ btst r2,r1
+ test_zero_clear
+ test_carry_set
+ test_h_gr32 2 r1
+bclr_reg_reg:
+ bclr r2,r1
+ btst r2,r1
+ test_zero_set
+ test_carry_clear
+ test_h_gr32 0 r1
+bnot_reg_reg:
+ bnot r2,r1
+ btst r2,r1
+ test_zero_clear
+ test_carry_set
+ test_h_gr32 2 r1
+
+ pass
+
+ .data
+val: .byte 2
diff --git a/sim/testsuite/sim/rx/cmp.s b/sim/testsuite/sim/rx/cmp.s
new file mode 100644
index 0000000..73dff9d
--- /dev/null
+++ b/sim/testsuite/sim/rx/cmp.s
@@ -0,0 +1,74 @@
+# RX testcase for cmp
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+cmp_imm4:
+ mov #1,r1
+ cmp #2,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_set
+ test_overflow_clear
+cmp_imm8:
+ cmp #-1,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_overflow_clear
+cmp_imm16:
+ mov #0x8000,r1
+ cmp #0x8000,r1
+ test_zero_set
+ test_carry_set
+ test_neg_clear
+ test_overflow_clear
+cmp_imm24:
+ mov #0x800000,r1
+ cmp #0x7fffff,r1
+ test_zero_clear
+ test_carry_set
+ test_neg_clear
+ test_overflow_clear
+cmp_imm32:
+ mov #0x80000000,r1
+ cmp #0x7fffffff,r1
+ test_zero_clear
+ test_carry_set
+ test_neg_clear
+ test_overflow_set
+cmp_reg:
+ mov.l #0x80000000,r2
+ cmp r2,r1
+ test_zero_set
+ test_carry_set
+ test_neg_clear
+cmp_mem_ind:
+ sub r1,r1
+ mov #val, r2
+ cmp [r2].l,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_set
+ test_overflow_clear
+cmp_mem_dsp8:
+ mov #val-4, r2
+ cmp 4[r2].l,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_set
+ test_overflow_clear
+cmp_mem_dsp16:
+ mov #val-0x1000, r2
+ cmp 0x1000[r2].l,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_set
+ test_overflow_clear
+
+ pass
+
+ .data
+val: .long 1
diff --git a/sim/testsuite/sim/rx/div.s b/sim/testsuite/sim/rx/div.s
new file mode 100644
index 0000000..40b814d
--- /dev/null
+++ b/sim/testsuite/sim/rx/div.s
@@ -0,0 +1,52 @@
+# RX testcase for div/divu
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+div_imm8:
+ mov #2,r1
+ div #2,r1
+ test_h_gr32 1 r1
+div_imm16:
+ mov #0x8000,r1
+ div #0x1000,r1
+ test_h_gr32 8 r1
+div_imm24:
+ mov #0x800000,r1
+ div #0x200000,r1
+ test_h_gr32 4 r1
+div_imm32:
+ mov #0x80000000,r1
+ div #0x40000000,r1
+ test_h_gr32 -2 r1
+divu_imm32:
+ mov #0x80000000,r1
+ divu #0x40000000,r1
+ test_h_gr32 2 r1
+div_reg:
+ mov #0x80000000,r1
+ mov r1,r2
+ div r2,r1
+ test_h_gr32 1 r1
+div_mem_ind:
+ mov #10,r1
+ mov #val, r2
+ div [r2],r1
+ test_h_gr32 5 r1
+div_mem_dsp8:
+ mov #10,r1
+ mov #val-4, r2
+ div 4[r2],r1
+ test_h_gr32 5 r1
+div_mem_dsp16:
+ mov #10,r1
+ mov #val-0x1000, r2
+ div 0x1000[r2],r1
+ test_h_gr32 5 r1
+
+ pass
+
+ .data
+val: .long 2
diff --git a/sim/testsuite/sim/rx/emaca.s b/sim/testsuite/sim/rx/emaca.s
new file mode 100644
index 0000000..e066d57
--- /dev/null
+++ b/sim/testsuite/sim/rx/emaca.s
@@ -0,0 +1,24 @@
+# RX testcase for emaca
+# mach: rxv2
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+ mov #100, r1
+ mov #200, r2
+ emaca r1,r2,a0
+ mvfaclo #0,a0,r1
+ test_h_gr32 20000 r1
+ mvfachi #0,a0,r1
+ test_h_gr32 0 r1
+ mov #300, r1
+ mov #200, r2
+ emaca r1,r2,a1
+ mvfaclo #0,a1,r1
+ test_h_gr32 60000 r1
+ mvfachi #0,a1,r1
+ test_h_gr32 0 r1
+
+ pass
+
diff --git a/sim/testsuite/sim/rx/emsba.s b/sim/testsuite/sim/rx/emsba.s
new file mode 100644
index 0000000..a20c963
--- /dev/null
+++ b/sim/testsuite/sim/rx/emsba.s
@@ -0,0 +1,24 @@
+# RX testcase for emsba
+# mach: rxv2
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+ mov #100, r1
+ mov #200, r2
+ emsba r1,r2,a0
+ mvfaclo #0,a0,r1
+ test_h_gr32 -20000 r1
+ mvfachi #0,a0,r1
+ test_h_gr32 -1 r1
+ mov #300, r1
+ mov #200, r2
+ emsba r1,r2,a1
+ mvfaclo #0,a1,r1
+ test_h_gr32 -60000 r1
+ mvfachi #0,a1,r1
+ test_h_gr32 -1 r1
+
+ pass
+
diff --git a/sim/testsuite/sim/rx/emul.s b/sim/testsuite/sim/rx/emul.s
new file mode 100644
index 0000000..cbbac82
--- /dev/null
+++ b/sim/testsuite/sim/rx/emul.s
@@ -0,0 +1,92 @@
+# RX testcase for emul
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+emul_imm8:
+ mov #0xf0000001,r1
+ emul #0x10,r1
+ test_h_gr32 0x10 r1
+ test_h_gr32 0xffffffff r2
+emul_imm16:
+ emul #1000,r1
+ test_h_gr32 16000 r1
+ test_h_gr32 0 r2
+emul_imm24:
+ mov.l #0x10000,r1
+ emul #0x10000,r1
+ test_h_gr32 0 r1
+ test_h_gr32 1 r2
+emul_imm32:
+ mov.l #0x10,r1
+ emul #0x10000000,r1
+ test_h_gr32 0 r1
+ test_h_gr32 1 r2
+emul_reg:
+ mov #5, r1
+ mov r1,r2
+ emul r2,r1
+ test_h_gr32 25 r1
+ test_h_gr32 0 r2
+emul_mem_ind:
+ mov.l #val, r2
+ emul [r2].l,r1
+ test_h_gr32 50 r1
+ test_h_gr32 0 r2
+emul_mem_dsp8:
+ mov.l #val-4, r2
+ emul 4[r2].l,r1
+ test_h_gr32 100 r1
+ test_h_gr32 0 r2
+emul_mem_dsp16:
+ mov.l #val-0x1000, r2
+ emul 0x1000[r2].l,r1
+ test_h_gr32 200 r1
+ test_h_gr32 0 r2
+emulu_imm8:
+ mov #0xf0000001,r1
+ emulu #0x10,r1
+ test_h_gr32 0x10 r1
+ test_h_gr32 0xf r2
+emulu_imm16:
+ emulu #1000,r1
+ test_h_gr32 16000 r1
+ test_h_gr32 0 r2
+emulu_imm24:
+ mov.l #0x10000,r1
+ emulu #0x10000,r1
+ test_h_gr32 0 r1
+ test_h_gr32 1 r2
+emulu_imm32:
+ mov.l #0x10,r1
+ emulu #0x10000000,r1
+ test_h_gr32 0 r1
+ test_h_gr32 1 r2
+emulu_reg:
+ mov #-5, r1
+ mov r1,r2
+ emul r2,r1
+ test_h_gr32 25 r1
+ test_h_gr32 0 r2
+emulu_mem_ind:
+ mov.l #val, r2
+ emulu [r2].l,r1
+ test_h_gr32 50 r1
+ test_h_gr32 0 r2
+emulu_mem_dsp8:
+ mov.l #val-4, r2
+ emulu 4[r2].l,r1
+ test_h_gr32 100 r1
+ test_h_gr32 0 r2
+emulu_mem_dsp16:
+ mov.l #val-0x1000, r2
+ emulu 0x1000[r2].l,r1
+ test_h_gr32 200 r1
+ test_h_gr32 0 r2
+
+ pass
+
+ .data
+val: .long 2
diff --git a/sim/testsuite/sim/rx/emula.s b/sim/testsuite/sim/rx/emula.s
new file mode 100644
index 0000000..44fbd8a
--- /dev/null
+++ b/sim/testsuite/sim/rx/emula.s
@@ -0,0 +1,24 @@
+# RX testcase for emula
+# mach: rxv2
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+ mov #100, r1
+ mov #200, r2
+ emula r1,r2,a0
+ mvfaclo #0,a0,r1
+ test_h_gr32 20000 r1
+ mvfachi #0,a0,r1
+ test_h_gr32 0 r1
+ mov #300, r1
+ mov #200, r2
+ emula r1,r2,a1
+ mvfaclo #0,a1,r1
+ test_h_gr32 60000 r1
+ mvfachi #0,a1,r1
+ test_h_gr32 0 r1
+
+ pass
+
diff --git a/sim/testsuite/sim/rx/fadd.s b/sim/testsuite/sim/rx/fadd.s
new file mode 100644
index 0000000..430fb38
--- /dev/null
+++ b/sim/testsuite/sim/rx/fadd.s
@@ -0,0 +1,41 @@
+# RX testcase for fadd
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names --defsym cpu=1
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+fadd_imm:
+ mov #1.0,r1
+ fadd #2.0,r1
+ test_h_gr32 3.0 r1
+fadd_reg:
+ mov.l #4.0,r2
+ fadd r2,r1
+ test_h_gr32 7.0 r1
+fadd_mem_ind:
+ mov.l #val, r2
+ fadd [r2].l,r1
+ test_h_gr32 8.0 r1
+fadd_mem_dsp8:
+ mov.l #val-4, r2
+ fadd 4[r2].l,r1
+ test_h_gr32 9.0 r1
+fadd_mem_dsp16:
+ mov.l #val-0x1000, r2
+ fadd 0x1000[r2].l,r1
+ test_h_gr32 10.0 r1
+ .if cpu == 2
+fadd3_reg:
+ mov.l #4.0,r2
+ mov.l #1.0,r3
+ fadd r2,r3,r1
+ test_h_gr32 5.0 r1
+ .endif
+
+ pass
+
+ .data
+val: .float 1.0
+
diff --git a/sim/testsuite/sim/rx/fcmp.s b/sim/testsuite/sim/rx/fcmp.s
new file mode 100644
index 0000000..db06423
--- /dev/null
+++ b/sim/testsuite/sim/rx/fcmp.s
@@ -0,0 +1,37 @@
+# RX testcase for fcmp
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+fcmp_imm:
+ mov #1.0,r1
+ fcmp #2.0,r1
+ test_zero_clear
+ test_neg_set
+fcmp_reg:
+ mov.l #4.0,r2
+ fcmp r2,r1
+ test_zero_clear
+ test_neg_set
+fcmp_mem_ind:
+ mov.l #val, r2
+ fcmp [r2].l,r1
+ test_zero_set
+ test_neg_clear
+fcmp_mem_dsp8:
+ mov.l #val-4, r2
+ fcmp 4[r2].l,r1
+ test_zero_set
+ test_neg_clear
+fcmp_mem_dsp16:
+ mov.l #val-0x1000, r2
+ fcmp 0x1000[r2].l,r1
+ test_zero_set
+ test_neg_clear
+ pass
+
+ .data
+val: .float 1.0
+
diff --git a/sim/testsuite/sim/rx/fdiv.s b/sim/testsuite/sim/rx/fdiv.s
new file mode 100644
index 0000000..540a081
--- /dev/null
+++ b/sim/testsuite/sim/rx/fdiv.s
@@ -0,0 +1,43 @@
+# RX testcase for fdiv
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+fdiv_imm:
+ mov #100.0,r1
+ fdiv #2.0,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 50.0 r1
+fdiv_reg:
+ mov.l #2.0,r2
+ fdiv r2,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 25.0 r1
+fdiv_mem_ind:
+ mov.l #val, r2
+ fdiv [r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 12.5 r1
+fdiv_mem_dsp8:
+ mov.l #val-4, r2
+ fdiv 4[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 6.25 r1
+fdiv_mem_dsp16:
+ mov.l #val-0x1000, r2
+ fdiv 0x1000[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 3.125 r1
+
+ pass
+
+ .data
+val: .float 2.0
+
diff --git a/sim/testsuite/sim/rx/fmul.s b/sim/testsuite/sim/rx/fmul.s
new file mode 100644
index 0000000..d79a6d3
--- /dev/null
+++ b/sim/testsuite/sim/rx/fmul.s
@@ -0,0 +1,51 @@
+# RX testcase for fmul
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names --defsym cpu=1
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+fmul_imm:
+ mov #10.0,r1
+ fmul #2.0,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 20.0 r1
+fmul_reg:
+ mov.l #2.0,r2
+ fmul r2,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 40.0 r1
+fmul_mem_ind:
+ mov.l #val, r2
+ fmul [r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 80.0 r1
+fmul_mem_dsp8:
+ mov.l #val-4, r2
+ fmul 4[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 160.0 r1
+fmul_mem_dsp16:
+ mov.l #val-0x1000, r2
+ fmul 0x1000[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 320.0 r1
+ .if cpu == 2
+fmul3_reg:
+ mov.l #4.0,r2
+ mov.l #6.0,r3
+ fmul r3,r2,r1
+ test_h_gr32 24.0 r1
+ .endif
+
+ pass
+
+ .data
+val: .float 2.0
+
diff --git a/sim/testsuite/sim/rx/fsqrt.s b/sim/testsuite/sim/rx/fsqrt.s
new file mode 100644
index 0000000..3c1d52d
--- /dev/null
+++ b/sim/testsuite/sim/rx/fsqrt.s
@@ -0,0 +1,23 @@
+# RX testcase for add
+# mach: rxv2
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+ mov #4.0,r2
+ fsqrt r2,r1
+ test_h_gr32 2.0 r1
+ mov #val,r2
+ fsqrt [r2],r1
+ test_h_gr32 3.0 r1
+ fsqrt 4[r2],r1
+ test_h_gr32 4.0 r1
+ mov #val - 0x1000 + 8,r2
+ fsqrt 0x1000[r2],r1
+ test_h_gr32 5.0 r1
+
+ pass
+
+ .data
+val: .float 9,16,25
diff --git a/sim/testsuite/sim/rx/fsub.s b/sim/testsuite/sim/rx/fsub.s
new file mode 100644
index 0000000..629a2a0
--- /dev/null
+++ b/sim/testsuite/sim/rx/fsub.s
@@ -0,0 +1,51 @@
+# RX testcase for fsub
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names --defsym cpu=1
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+fsub_imm:
+ mov #10.0,r1
+ fsub #2.0,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 8.0 r1
+fsub_reg:
+ mov.l #2.0,r2
+ fsub r2,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 6.0 r1
+fsub_mem_ind:
+ mov.l #val, r2
+ fsub [r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 4.0 r1
+fsub_mem_dsp8:
+ mov.l #val-4, r2
+ fsub 4[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2.0 r1
+fsub_mem_dsp16:
+ mov.l #val-0x1000, r2
+ fsub 0x1000[r2].l,r1
+ test_zero_set
+ test_neg_clear
+ test_h_gr32 0.0 r1
+ .if cpu == 2
+fsub3_reg:
+ mov.l #4.0,r2
+ mov.l #1.0,r3
+ fsub r3,r2,r1
+ test_h_gr32 3.0 r1
+ .endif
+
+ pass
+
+ .data
+val: .float 2.0
+
diff --git a/sim/testsuite/sim/rx/ftoi.s b/sim/testsuite/sim/rx/ftoi.s
new file mode 100644
index 0000000..0d21f19
--- /dev/null
+++ b/sim/testsuite/sim/rx/ftoi.s
@@ -0,0 +1,37 @@
+# RX testcase for ftoi
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ftoi_reg:
+ mov.l #12.34,r2
+ ftoi r2,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 12 r1
+ftoi_mem_ind:
+ mov.l #val, r2
+ ftoi [r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2 r1
+ftoi_mem_dsp8:
+ mov.l #val-4, r2
+ ftoi 4[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2 r1
+ftoi_mem_dsp16:
+ mov.l #val-0x1000, r2
+ ftoi 0x1000[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2 r1
+
+ pass
+
+ .data
+val: .float 2.345
+
diff --git a/sim/testsuite/sim/rx/ftou.s b/sim/testsuite/sim/rx/ftou.s
new file mode 100644
index 0000000..434933d
--- /dev/null
+++ b/sim/testsuite/sim/rx/ftou.s
@@ -0,0 +1,37 @@
+# RX testcase for ftou
+# mach: rxv2
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+ftou_reg:
+ mov.l #2147483648.0,r2
+ ftou r2,r1
+ test_zero_clear
+ test_neg_set
+ test_h_gr32 -2147483648 r1
+ftou_mem_ind:
+ mov.l #val, r2
+ ftou [r2].l,r1
+ test_zero_clear
+ test_neg_set
+ test_h_gr32 -2147483648 r1
+ftou_mem_dsp8:
+ mov.l #val-4, r2
+ ftou 4[r2].l,r1
+ test_zero_clear
+ test_neg_set
+ test_h_gr32 -2147483648 r1
+ftou_mem_dsp16:
+ mov.l #val-0x1000, r2
+ ftou 0x1000[r2].l,r1
+ test_zero_clear
+ test_neg_set
+ test_h_gr32 -2147483648 r1
+
+ pass
+
+ .data
+val: .float 2147483648.0
+
diff --git a/sim/testsuite/sim/rx/itof.s b/sim/testsuite/sim/rx/itof.s
new file mode 100644
index 0000000..055b42f
--- /dev/null
+++ b/sim/testsuite/sim/rx/itof.s
@@ -0,0 +1,37 @@
+# RX testcase for itof
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+itof_reg:
+ mov.l #12,r2
+ itof r2,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 12.0 r1
+itof_mem_ind:
+ mov.l #val, r2
+ itof [r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2.0 r1
+itof_mem_dsp8:
+ mov.l #val-4, r2
+ itof 4[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2.0 r1
+itof_mem_dsp16:
+ mov.l #val-0x1000, r2
+ itof 0x1000[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2.0 r1
+
+ pass
+
+ .data
+val: .long 2
+
diff --git a/sim/testsuite/sim/rx/jmp.s b/sim/testsuite/sim/rx/jmp.s
new file mode 100644
index 0000000..fe3e3b3
--- /dev/null
+++ b/sim/testsuite/sim/rx/jmp.s
@@ -0,0 +1,12 @@
+# RX testcase for jmp
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ mov #1f,r1
+ jmp r1
+ fail
+1:
+ pass
diff --git a/sim/testsuite/sim/rx/machilo.s b/sim/testsuite/sim/rx/machilo.s
new file mode 100644
index 0000000..2d534ae
--- /dev/null
+++ b/sim/testsuite/sim/rx/machilo.s
@@ -0,0 +1,53 @@
+# RX testcase for add
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names --defsym cpu=1
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+ sub r1,r1
+ mvtachi r1
+ mvtaclo r1
+ mov #0x20000,r1
+ mov #0x30000,r2
+ machi r1,r2
+ mvfacmi r1
+ test_h_gr32 6 r1
+ mvfachi r1
+ test_h_gr32 0 r1
+ mov #0x3,r1
+ mov #0x4,r2
+ maclo r1,r2
+ mvfacmi r1
+ test_h_gr32 0x12 r1
+ mvfachi r1
+ test_h_gr32 0 r1
+ .if cpu == 2
+ sub r1,r1
+ mvtachi r1,a1
+ mvtaclo r1,a1
+ mvtacgu r1,a1
+ mov #0x20000,r1
+ mov #0x30000,r2
+ machi r1,r2,a1
+ mvfacmi #0,a1,r1
+ test_h_gr32 6 r1
+ mvfachi #0,a1,r1
+ test_h_gr32 0 r1
+ mov #0x3,r1
+ mov #0x4,r2
+ maclo r1,r2,a1
+ mvfacmi #0,a1,r1
+ test_h_gr32 0x12 r1
+ mvfachi #0,a1,r1
+ test_h_gr32 0 r1
+ mov #0x4,r1
+ mov #0x50000,r2
+ maclh r1,r2,a1
+ mvfacmi #0,a1,r1
+ test_h_gr32 0x26 r1
+ mvfachi #0,a1,r1
+ test_h_gr32 0 r1
+ .endif
+ pass
diff --git a/sim/testsuite/sim/rx/max.s b/sim/testsuite/sim/rx/max.s
new file mode 100644
index 0000000..aa17928
--- /dev/null
+++ b/sim/testsuite/sim/rx/max.s
@@ -0,0 +1,45 @@
+# RX testcase for max
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+max_imm8:
+ mov #2,r1
+ max #1,r1
+ test_h_gr32 2 r1
+max_imm16:
+ mov #0x8000,r1
+ max #0x1000,r1
+ test_h_gr32 0x8000 r1
+max_imm24:
+ mov #0x100000,r1
+ max #0x200000,r1
+ test_h_gr32 0x200000 r1
+max_imm32:
+ mov #0x80000000,r1
+ max #0x40000000,r1
+ test_h_gr32 0x40000000 r1
+max_reg:
+ mov #0x80000000,r2
+ max r2,r1
+ test_h_gr32 0x40000000 r1
+max_mem_ind:
+ mov #10,r1
+ mov #val, r2
+ max [r2],r1
+ test_h_gr32 10 r1
+max_mem_dsp8:
+ mov #val-4, r2
+ max 4[r2],r1
+ test_h_gr32 10 r1
+max_mem_dsp16:
+ mov #val-0x1000, r2
+ max 0x1000[r2],r1
+ test_h_gr32 10 r1
+
+ pass
+
+ .data
+val: .long 2
diff --git a/sim/testsuite/sim/rx/min.s b/sim/testsuite/sim/rx/min.s
new file mode 100644
index 0000000..53f97c4
--- /dev/null
+++ b/sim/testsuite/sim/rx/min.s
@@ -0,0 +1,45 @@
+# RX testcase for min
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+min_imm8:
+ mov #2,r1
+ min #1,r1
+ test_h_gr32 1 r1
+min_imm16:
+ mov #0x8000,r1
+ min #0x1000,r1
+ test_h_gr32 0x1000 r1
+min_imm24:
+ mov #0x100000,r1
+ min #0x200000,r1
+ test_h_gr32 0x100000 r1
+min_imm32:
+ mov #0x80000000,r1
+ min #0x40000000,r1
+ test_h_gr32 0x80000000 r1
+min_reg:
+ mov #0x80000000,r2
+ min r2,r1
+ test_h_gr32 0x80000000 r1
+min_mem_ind:
+ mov #2,r1
+ mov #val, r2
+ min [r2],r1
+ test_h_gr32 2 r1
+min_mem_dsp8:
+ mov #val-4, r2
+ min 4[r2],r1
+ test_h_gr32 2 r1
+min_mem_dsp16:
+ mov #val-0x1000, r2
+ min 0x1000[r2],r1
+ test_h_gr32 2 r1
+
+ pass
+
+ .data
+val: .long 10
diff --git a/sim/testsuite/sim/rx/mov.s b/sim/testsuite/sim/rx/mov.s
new file mode 100644
index 0000000..9dd45f4
--- /dev/null
+++ b/sim/testsuite/sim/rx/mov.s
@@ -0,0 +1,196 @@
+# RX testcase for mov
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ set_gr_a5a5 1
+ mov #val,r2
+ mov.b r1,[r2]
+ mov.w r1,2[r2]
+ mov.l r1,4[r2]
+ mov.b [r2],r1
+ test_h_gr32 0xffffffa5 r1
+ mov.w 2[r2],r1
+ test_h_gr32 0xffffa5a5 r1
+ mov.l 4[r2],r1
+ test_h_gr32 0xa5a5a5a5 r1
+ mov #1,r1
+ test_h_gr32 1 r1
+ mov.b #0x01,[r2]
+ mov.w #0x23,2[r2]
+ mov.l #0x45,4[r2]
+ mov.b [r2],r1
+ test_h_gr32 0x01 r1
+ mov.w 2[r2],r1
+ test_h_gr32 0x23 r1
+ mov.l 4[r2],r1
+ test_h_gr32 0x45 r1
+ mov #0x10,r1
+ test_h_gr32 0x10 r1
+ mov #0x80,r1
+ test_h_gr32 0x80 r1
+ mov #0x8000,r1
+ test_h_gr32 0x8000 r1
+ mov #0x800000,r1
+ test_h_gr32 0x800000 r1
+ mov #0x80000000,r1
+ test_h_gr32 0x80000000 r1
+ mov #0x80,r1
+ mov.b r1,r2
+ test_h_gr32 0xffffff80 r2
+ mov #0x8000,r1
+ mov.w r1,r2
+ test_h_gr32 0xffff8000 r2
+ mov #0x80000000,r1
+ mov.l r1,r2
+ test_h_gr32 0x80000000 r2
+ mov.l #val,r2
+ mov.l #val-4,r3
+ mov.l #val-0x1000,r4
+ mov.b #0x01,[r2]
+ mov.b [r2],r1
+ test_h_gr32 0x01 r1
+ mov.b #0x23,4[r3]
+ mov.b [r2],r1
+ test_h_gr32 0x23 r1
+ mov.b #0x45,0x1000[r4]
+ mov.b [r2],r1
+ test_h_gr32 0x45 r1
+ mov.w #0x80,[r2]
+ mov.w [r2],r1
+ test_h_gr32 0x80 r1
+ mov.w #0x80,4[r3]
+ mov.w [r2],r1
+ test_h_gr32 0x80 r1
+ mov.w #0x80,0x1000[r4]
+ mov.w [r2],r1
+ test_h_gr32 0x80 r1
+ mov.w #0x1234,[r2]
+ mov.w [r2],r1
+ test_h_gr32 0x1234 r1
+ mov.w #0x4567,4[r3]
+ mov.w [r2],r1
+ test_h_gr32 0x4567 r1
+ mov.w #0x89ab,0x1000[r4]
+ mov.w [r2],r1
+ test_h_gr32 0xffff89ab r1
+ mov.l #0x123456,[r2]
+ mov.l [r2],r1
+ test_h_gr32 0x123456 r1
+ mov.l #0x456789,4[r3]
+ mov.l [r2],r1
+ test_h_gr32 0x456789 r1
+ mov.l #0x89abcd,0x1000[r4]
+ mov.l [r2],r1
+ test_h_gr32 0x89abcd r1
+ mov.l #0x12345678,[r2]
+ mov.l [r2],r1
+ test_h_gr32 0x12345678 r1
+ mov.l #0x89abcdef,4[r3]
+ mov.l [r2],r1
+ test_h_gr32 0x89abcdef r1
+ mov.l #0x76543210,0x1000[r4]
+ mov.l [r2],r1
+ test_h_gr32 0x876543210 r1
+ mov #4,r1
+ mov.b r1,[r1,r3]
+ mov.b [r2],r1
+ test_h_gr32 4 r1
+ mov #2,r1
+ mov.w r1,[r1,r3]
+ mov.w [r2],r1
+ test_h_gr32 2 r1
+ mov #0x1000/4,r1
+ mov.l r1,[r1,r4]
+ mov.l [r2],r1
+ test_h_gr32 0x1000/4 r1
+ mov #val+4,r5
+ mov.b #0x12,[r2]
+ mov.b [r2],[r5]
+ mov.b [r5],r1
+ test_h_gr32 0x12 r1
+ mov.w #0x1234,[r2]
+ mov.w [r2],[r5]
+ mov.w [r5],r1
+ test_h_gr32 0x1234 r1
+ mov.l #0x12345678,[r2]
+ mov.l [r2],[r5]
+ mov.l [r5],r1
+ test_h_gr32 0x12345678 r1
+ mov.b #0x12,[r2]
+ mov.b [r2],8[r3]
+ mov.b 8[r3],r1
+ test_h_gr32 0x12 r1
+ mov.w #0x1234,[r2]
+ mov.w [r2],8[r3]
+ mov.w 8[r3],r1
+ test_h_gr32 0x1234 r1
+ mov.l #0x12345678,[r2]
+ mov.l [r2],8[r3]
+ mov.l 8[r3],r1
+ test_h_gr32 0x12345678 r1
+ mov.b #0x12,[r2]
+ mov.b [r2],0x1004[r4]
+ mov.b 0x1004[r4],r1
+ test_h_gr32 0x12 r1
+ mov.w #0x1234,[r2]
+ mov.w [r2],0x1004[r4]
+ mov.w 0x1004[r4],r1
+ test_h_gr32 0x1234 r1
+ mov.l #0x12345678,[r2]
+ mov.l [r2],0x1004[r4]
+ mov.l 0x1004[r4],r1
+ test_h_gr32 0x12345678 r1
+ mov.b #0x12,[r2]
+ mov.b 4[r3],0x1004[r4]
+ mov.b 0x1004[r4],r1
+ test_h_gr32 0x12 r1
+ mov.w #0x1234,[r2]
+ mov.w 4[r3],0x1004[r4]
+ mov.w 0x1004[r4],r1
+ test_h_gr32 0x1234 r1
+ mov.l #0x12345678,[r2]
+ mov.l 4[r3],0x1004[r4]
+ mov.l 0x1004[r4],r1
+ test_h_gr32 0x12345678 r1
+ mov.b #0x12,[r2]
+ mov.b 0x1000[r4],4[r3]
+ mov.b 4[r3],r1
+ test_h_gr32 0x12 r1
+ mov.w #0x1234,[r2]
+ mov.w 0x1000[r4],4[r3]
+ mov.w 4[r3],r1
+ test_h_gr32 0x1234 r1
+ mov.l #0x12345678,[r2]
+ mov.l 0x1000[r4],4[r3]
+ mov.l 4[r3],r1
+ test_h_gr32 0x12345678 r1
+ mov #val+9,r1
+ mov #0x12345678,r2
+ mov.l r2,[-r1]
+ mov.w r2,[-r1]
+ mov.b r2,[-r1]
+ mov.b [r1+],r2
+ test_h_gr32 0x78 r2
+ mov.w [r1+],r2
+ test_h_gr32 0x5678 r2
+ mov.l [r1+],r2
+ test_h_gr32 0x12345678 r2
+ mov #val,r1
+ mov #0x12345678,r2
+ mov.l r2,[r1+]
+ mov.w r2,[r1+]
+ mov.b r2,[r1+]
+ mov.b [-r1],r2
+ test_h_gr32 0x78 r2
+ mov.w [-r1],r2
+ test_h_gr32 0x5678 r2
+ mov.l [-r1],r2
+ test_h_gr32 0x12345678 r2
+
+ pass
+
+ .data
+val: .space 16
diff --git a/sim/testsuite/sim/rx/movlico.s b/sim/testsuite/sim/rx/movlico.s
new file mode 100644
index 0000000..3c9c8fe
--- /dev/null
+++ b/sim/testsuite/sim/rx/movlico.s
@@ -0,0 +1,22 @@
+# RX testcase for add
+# mach: rxv2
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+ mov.l #0x12345678,r1
+ mov.l #val,r2
+ movco r1,[r2]
+ test_h_gr32 1 r1
+ movli [r2],r1
+ mov #0x5a5a5a5a,r1
+ movco r1,[r2]
+ test_h_gr32 0 r1
+ mov.l [r2],r1
+ test_h_gr32 0x5a5a5a5a r1
+
+ pass
+
+ .data
+val: .long 0xa5a5a5a5
diff --git a/sim/testsuite/sim/rx/movu.s b/sim/testsuite/sim/rx/movu.s
new file mode 100644
index 0000000..5289c94
--- /dev/null
+++ b/sim/testsuite/sim/rx/movu.s
@@ -0,0 +1,67 @@
+# RX testcase for movu
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ set_gr_a5a5 1
+ mov #valb,r2
+ movu.b [r2],r1
+ test_h_gr32 0x80 r1
+ mov #valw,r2
+ movu.w [r2],r1
+ test_h_gr32 0x8000 r1
+ mov #0x8888,r2
+ movu.b r2,r1
+ test_h_gr32 0x88 r1
+ movu.w r2,r1
+ test_h_gr32 0x8888 r1
+ mov #valb,r2
+ movu.b [r2],r10
+ test_h_gr32 0x80 r10
+ mov #valb-0x40,r2
+ movu.b 0x40[r2],r10
+ test_h_gr32 0x80 r10
+ mov #valb-0x1000,r2
+ movu.b 0x1000[r2],r10
+ test_h_gr32 0x80 r10
+ mov #valb-0x1000,r2
+ mov #0x1000,r3
+ movu.b [r3,r2],r10
+ test_h_gr32 0x80 r10
+ mov #valw,r2
+ movu.w [r2],r10
+ test_h_gr32 0x8000 r10
+ mov #valw-0x40,r2
+ movu.w 0x40[r2],r10
+ test_h_gr32 0x8000 r10
+ mov #valw-0x1000,r2
+ movu.w 0x1000[r2],r10
+ test_h_gr32 0x8000 r10
+ mov #valw-0x1000,r2
+ mov #0x1000/2,r3
+ movu.w [r3,r2],r10
+ test_h_gr32 0x8000 r10
+ mov #valb,r2
+ movu.b [r2+],r1
+ test_h_gr32 0x80 r1
+ test_h_gr32 valb+1 r2
+ mov #valw,r2
+ movu.w [r2+],r1
+ test_h_gr32 0x8000 r1
+ test_h_gr32 valw+2 r2
+ mov #valb+1,r2
+ movu.b [-r2],r1
+ test_h_gr32 0x80 r1
+ test_h_gr32 valb r2
+ mov #valw+2,r2
+ movu.w [-r2],r1
+ test_h_gr32 0x8000 r1
+ test_h_gr32 valw r2
+
+ pass
+
+ .data
+valw: .word 0x8000
+valb: .byte 0x80
diff --git a/sim/testsuite/sim/rx/msbhilo.s b/sim/testsuite/sim/rx/msbhilo.s
new file mode 100644
index 0000000..3a21981
--- /dev/null
+++ b/sim/testsuite/sim/rx/msbhilo.s
@@ -0,0 +1,43 @@
+# RX testcase for add
+# mach: rxv2
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+ mov #0x20000,r1
+ mov #0x30000,r2
+ msbhi r1,r2,a0
+ mvfacmi r1
+ test_h_gr32 -6 r1
+ mvfachi r1
+ test_h_gr32 -1 r1
+ mov #0x3,r1
+ mov #0x4,r2
+ msblo r1,r2,a0
+ mvfacmi r1
+ test_h_gr32 -18 r1
+ mvfachi r1
+ test_h_gr32 -1 r1
+ mov #0x20000,r1
+ mov #0x30000,r2
+ msbhi r1,r2,a1
+ mvfacmi #0,a1,r1
+ test_h_gr32 -6 r1
+ mvfachi #0,a1,r1
+ test_h_gr32 -1 r1
+ mov #0x3,r1
+ mov #0x4,r2
+ msblo r1,r2,a1
+ mvfacmi #0,a1,r1
+ test_h_gr32 -18 r1
+ mvfachi #0,a1,r1
+ test_h_gr32 -1 r1
+ mov #0x4,r1
+ mov #0x50000,r2
+ msblh r1,r2,a1
+ mvfacmi #0,a1,r1
+ test_h_gr32 -38 r1
+ mvfachi #0,a1,r1
+ test_h_gr32 -1 r1
+ pass
diff --git a/sim/testsuite/sim/rx/mul.s b/sim/testsuite/sim/rx/mul.s
new file mode 100644
index 0000000..979acd7
--- /dev/null
+++ b/sim/testsuite/sim/rx/mul.s
@@ -0,0 +1,52 @@
+# RX testcase for mul
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+mul_imm4:
+ mov.l #3,r1
+ mul #3,r1
+ test_h_gr32 9 r1
+mul_imm8:
+ mul #20,r1
+ test_h_gr32 180 r1
+mul_imm16:
+ mul #1000,r1
+ test_h_gr32 180000 r1
+mul_imm24:
+ mov.l #3,r1
+ mul #0x10000,r1
+ test_h_gr32 0x30000 r1
+mul_imm32:
+ mov.l #3,r1
+ mul #0x1000000,r1
+ test_h_gr32 0x3000000 r1
+mul_reg:
+ mov #5, r1
+ mov r1,r2
+ mul r2,r1
+ test_h_gr32 25 r1
+mul_mem_ind:
+ mov.l #val, r2
+ mul [r2].l,r1
+ test_h_gr32 50 r1
+mul_mem_dsp8:
+ mov.l #val-4, r2
+ mul 4[r2].l,r1
+ test_h_gr32 100 r1
+mul_mem_dsp16:
+ mov.l #val-0x1000, r2
+ mul 0x1000[r2].l,r1
+ test_h_gr32 200 r1
+mul3_reg:
+ mov #6, r1
+ mov r1,r2
+ mul r1,r2,r3
+ test_h_gr32 36 r3
+
+ pass
+
+ .data
+val: .long 2
diff --git a/sim/testsuite/sim/rx/mulhilo.s b/sim/testsuite/sim/rx/mulhilo.s
new file mode 100644
index 0000000..083d10c
--- /dev/null
+++ b/sim/testsuite/sim/rx/mulhilo.s
@@ -0,0 +1,54 @@
+# RX testcase for add
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names --defsym cpu=1
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+ sub r1,r1
+ mvtachi r1
+ mvtaclo r1
+ mov #0x20000,r1
+ mov #0x30000,r2
+ mulhi r1,r2
+ mvfacmi r1
+ test_h_gr32 0x6 r1
+ mvfachi r1
+ test_h_gr32 0 r1
+ mov #0x3,r1
+ mov #0x4,r2
+ mullo r1,r2
+ mvfacmi r1
+ test_h_gr32 0xc r1
+ mvfachi r1
+ test_h_gr32 0 r1
+ .if cpu == 2
+ sub r1,r1
+ mvtachi r1,a1
+ mvtaclo r1,a1
+ mvtacgu r1,a1
+ mov #0x20000,r1
+ mov #0x30000,r2
+ mulhi r1,r2,a1
+ mvfacmi #0,a1,r1
+ test_h_gr32 0x6 r1
+ mvfachi #0,a1,r1
+ test_h_gr32 0 r1
+ mov #0x3,r1
+ mov #0x4,r2
+ mullo r1,r2,a1
+ mvfacmi #0,a1,r1
+ test_h_gr32 0xc r1
+ mvfachi #0,a1,r1
+ test_h_gr32 0 r1
+ mov #0x4,r1
+ mov #0x50000,r2
+ mullh r1,r2,a1
+ mvfacmi #0,a1,r1
+ test_h_gr32 0x14 r1
+ mvfachi #0,a1,r1
+ test_h_gr32 0 r1
+ .endif
+
+ pass
diff --git a/sim/testsuite/sim/rx/mvacc.s b/sim/testsuite/sim/rx/mvacc.s
new file mode 100644
index 0000000..ac6d3f4
--- /dev/null
+++ b/sim/testsuite/sim/rx/mvacc.s
@@ -0,0 +1,28 @@
+# RX testcase for add
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names --defsym cpu=1
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+ mov #0x12345678,r1
+ mvtachi r1
+ mvtaclo r1
+ mvfacmi r1
+ test_h_gr32 0x56781234 r1
+ mvfachi r1
+ test_h_gr32 0x12345678 r1
+ .if cpu == 2
+ mvtacgu r1,a0
+ mvfacmi #1,a0,r1
+ test_h_gr32 0xacf02468 r1
+ mvfachi #2,a0,r1
+ test_h_gr32 0x48d159e0 r1
+ mvfacgu #0,a0,r1
+ test_h_gr32 0x78 r1
+ mvfaclo #0,a0,r1
+ test_h_gr32 0x12345678 r1
+ .endif
+
+ pass
diff --git a/sim/testsuite/sim/rx/mvftc.s b/sim/testsuite/sim/rx/mvftc.s
new file mode 100644
index 0000000..ed98ba8
--- /dev/null
+++ b/sim/testsuite/sim/rx/mvftc.s
@@ -0,0 +1,36 @@
+# RX testcase for mvfc/mvtc
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ mov #0x1,r1
+ mvtc r1,ISP
+ mov #0x2,r1
+ mvtc r1,USP
+ mov #0x3,r1
+ mvtc r1,INTB
+ mov #0x4,r1
+ mvtc r1,BPC
+ mov #0x5,r1
+ mvtc r1,BPSW
+ mov #0x6,r1
+ mvtc r1,FINTV
+ mvfc ISP,r1
+ test_h_gr32 1 r1
+ mvfc USP,r1
+ test_h_gr32 2 r1
+ mvfc INTB,r1
+ test_h_gr32 3 r1
+ mvfc BPC,r1
+ test_h_gr32 4 r1
+ mvfc BPSW,r1
+ test_h_gr32 5 r1
+ mvfc FINTV,r1
+ test_h_gr32 6 r1
+
+ pass
+
+ .data
+val: .long 2
diff --git a/sim/testsuite/sim/rx/neg.s b/sim/testsuite/sim/rx/neg.s
new file mode 100644
index 0000000..7eb6dbf
--- /dev/null
+++ b/sim/testsuite/sim/rx/neg.s
@@ -0,0 +1,17 @@
+# RX testcase for neg
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ mov #1,r1
+ neg r1
+ test_h_gr32 -1 r1
+ neg r1,r2
+ test_h_gr32 1 r2
+
+ pass
+
+ .data
+val: .long 2
diff --git a/sim/testsuite/sim/rx/not.s b/sim/testsuite/sim/rx/not.s
new file mode 100644
index 0000000..f78203a
--- /dev/null
+++ b/sim/testsuite/sim/rx/not.s
@@ -0,0 +1,17 @@
+# RX testcase for not
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ mov #1,r1
+ not r1
+ test_h_gr32 0xfffffffe r1
+ not r1,r2
+ test_h_gr32 1 r2
+
+ pass
+
+ .data
+val: .long 2
diff --git a/sim/testsuite/sim/rx/or.s b/sim/testsuite/sim/rx/or.s
new file mode 100644
index 0000000..1fdd286
--- /dev/null
+++ b/sim/testsuite/sim/rx/or.s
@@ -0,0 +1,69 @@
+# RX testcase for or
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+or_imm4:
+ mov #2,r1
+ or #1,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 3 r1
+or_imm8:
+ or #0x10,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x13 r1
+or_imm16:
+ or #0x1000,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x1013 r1
+or_imm24:
+ or #0x100000,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x101013 r1
+or_imm32:
+ or #0x10000000,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x10101013 r1
+or_reg:
+ mov.l #0x20000000,r2
+ or r2,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x30101013 r1
+or_mem_ind:
+ mov #val, r2
+ or [r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x3010101b r1
+or_mem_dsp8:
+ mov #val-4, r2
+ or 4[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x3010101b r1
+or_mem_dsp16:
+ sub r1,r1
+ mov #val-0x1000, r2
+ or 0x1000[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 8 r1
+or3_reg:
+ mov.l #0x80000000,r2
+ or r2,r1,r3
+ test_zero_clear
+ test_neg_set
+ test_h_gr32 0x80000008 r3
+
+ pass
+
+ .data
+val: .long 8
diff --git a/sim/testsuite/sim/rx/pushpop.s b/sim/testsuite/sim/rx/pushpop.s
new file mode 100644
index 0000000..b0d6ce2
--- /dev/null
+++ b/sim/testsuite/sim/rx/pushpop.s
@@ -0,0 +1,48 @@
+# RX testcase for push/pop
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ mov #1,r1
+ push.l r1
+ mov #val,r1
+ push [r1]
+ mov #val-4,r1
+ push 4[r1]
+ mov #val-0x1000,r1
+ push 0x1000[r1]
+ pop r4
+ pop r3
+ pop r2
+ pop r1
+ test_h_gr32 1 r1
+ test_h_gr32 2 r2
+ test_h_gr32 2 r3
+ test_h_gr32 2 r4
+ mov #123456,r1
+ mvtc r1,intb
+ pushc intb
+ popc intb
+ mvfc intb,r2
+ test_h_gr32 123456 r2
+ mov #1,r1
+ mov #2,r2
+ mov #3,r3
+ mov #4,r4
+ pushm r1-r4
+ sub r1,r1
+ sub r2,r2
+ sub r3,r3
+ sub r4,r4
+ popm r1-r4
+ test_h_gr32 1 r1
+ test_h_gr32 2 r2
+ test_h_gr32 3 r3
+ test_h_gr32 4 r4
+
+ pass
+
+ .data
+val: .long 2
diff --git a/sim/testsuite/sim/rx/racw.s b/sim/testsuite/sim/rx/racw.s
new file mode 100644
index 0000000..bae6f5a
--- /dev/null
+++ b/sim/testsuite/sim/rx/racw.s
@@ -0,0 +1,38 @@
+# RX testcase for add
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names --defsym cpu=1
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+ mov #0x40000000,r1
+ mvtaclo r1
+ sub r1,r1
+ mvtachi r1
+ racw #1
+ mvfacmi r1
+ test_h_gr32 0x10000 r1
+ mvfachi r1
+ test_h_gr32 1 r1
+ .if cpu == 2
+ mov #0x40000000,r1
+ mvtaclo r1,a1
+ sub r1,r1
+ mvtachi r1,a1
+ racw #2,a1
+ mvfacmi #0,a1,r1
+ test_h_gr32 0x10000 r1
+ mvfachi #0,a1,r1
+ test_h_gr32 1 r1
+ mov #0x80,r1
+ mvtacgu r1,a1
+ racl #1,a1
+ mvfacmi #0,a1,r1
+ test_h_gr32 0x20000 r1
+ mvfachi #0,a1,r1
+ test_h_gr32 2 r1
+ mvfacgu #0,a1,r1
+ test_h_gr32 0 r1
+ .endif
+ pass
diff --git a/sim/testsuite/sim/rx/rdacw.s b/sim/testsuite/sim/rx/rdacw.s
new file mode 100644
index 0000000..66186ed
--- /dev/null
+++ b/sim/testsuite/sim/rx/rdacw.s
@@ -0,0 +1,19 @@
+# RX testcase for rdacw
+# mach: rxv2
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+ mov.l #-1,r1
+ mvtaclo r1,a0
+ rdacw #2,a0
+ mvfacmi #0,a0,r1
+ test_h_gr32 0x30000 r1
+ mov.l #-1,r1
+ mvtaclo r1,a0
+ rdacl #2,a0
+ mvfacmi #0,a0,r1
+ test_h_gr32 0xf0000 r1
+
+ pass
diff --git a/sim/testsuite/sim/rx/rev.s b/sim/testsuite/sim/rx/rev.s
new file mode 100644
index 0000000..120cb58
--- /dev/null
+++ b/sim/testsuite/sim/rx/rev.s
@@ -0,0 +1,14 @@
+# RX testcase for revl/revw
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ mov #0x12345678,r1
+ revl r1,r2
+ test_h_gr32 0x78563412 r2
+ revw r1,r2
+ test_h_gr32 0x34127856 r2
+
+ pass
diff --git a/sim/testsuite/sim/rx/rmpa.s b/sim/testsuite/sim/rx/rmpa.s
new file mode 100644
index 0000000..e1b67cb
--- /dev/null
+++ b/sim/testsuite/sim/rx/rmpa.s
@@ -0,0 +1,23 @@
+# RX testcase for rmpa
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ sub r4,r4
+ sub r5,r5
+ sub r6,r6
+ mov #val1,r1
+ mov #val2,r2
+ mov #10,r3
+ rmpa.w
+ test_h_gr32 110 r4
+ test_h_gr32 0 r5
+ test_h_gr32 0 r6
+ pass
+
+ .data
+val1: .word 1,2,3,4,5,6,7,8,9,10
+val2: .word 10,9,8,7,6,5,4,3,2,1
+
diff --git a/sim/testsuite/sim/rx/rot.s b/sim/testsuite/sim/rx/rot.s
new file mode 100644
index 0000000..38a459f
--- /dev/null
+++ b/sim/testsuite/sim/rx/rot.s
@@ -0,0 +1,46 @@
+# RX testcase for rolc/rorc/rotl/rotr
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ clear_carry_flag
+ mov.l #0x80000000,r1
+ rolc r1
+ test_carry_set
+ test_zero_set
+ test_neg_clear
+ test_h_gr32 0 r1
+ clear_carry_flag
+ rorc r1
+ test_carry_clear
+ test_zero_set
+ test_neg_clear
+ test_h_gr32 0 r1
+ mov.l #0x80000000,r1
+ rotl #1,r1
+ test_carry_set
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 1 r1
+ mov #1,r2
+ rotl r2,r1
+ test_carry_clear
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2 r1
+ rotr #1,r1
+ test_carry_clear
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 1 r1
+ rotr r2,r1
+ test_carry_set
+ test_zero_clear
+ test_neg_set
+ test_h_gr32 0x80000000 r1
+ pass
+
+ .data
+val: .long 2
diff --git a/sim/testsuite/sim/rx/round.s b/sim/testsuite/sim/rx/round.s
new file mode 100644
index 0000000..cef2e24
--- /dev/null
+++ b/sim/testsuite/sim/rx/round.s
@@ -0,0 +1,37 @@
+# RX testcase for round
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+round_reg:
+ mov.l #12.68,r2
+ round r2,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 13 r1
+round_mem_ind:
+ mov.l #val, r2
+ round [r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2 r1
+round_mem_dsp8:
+ mov.l #val-4, r2
+ round 4[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2 r1
+round_mem_dsp16:
+ mov.l #val-0x1000, r2
+ round 0x1000[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2 r1
+
+ pass
+
+ .data
+val: .float 2.345
+
diff --git a/sim/testsuite/sim/rx/sat.s b/sim/testsuite/sim/rx/sat.s
new file mode 100644
index 0000000..3dc38ed
--- /dev/null
+++ b/sim/testsuite/sim/rx/sat.s
@@ -0,0 +1,37 @@
+# RX testcase for fadd
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names --defsym cpu=1
+
+ .include "testutils.inc"
+
+ start
+sat: sub r1,r1
+ sub r4,r4
+ sub r5,r5
+ sub r6,r6
+ clear_overflow_flag
+ sat r1
+ satr
+ test_h_gr32 0 r1
+ test_h_gr32 0 r6
+ test_h_gr32 0 r5
+ test_h_gr32 0 r4
+
+ set_overflow_flag
+ clear_neg_flag
+ sat r1
+ satr
+ test_h_gr32 0x80000000 r1
+ test_h_gr32 0 r6
+ test_h_gr32 0x7fffffff r5
+ test_h_gr32 0xffffffff r4
+ set_overflow_flag
+ set_neg_flag
+ sat r1
+ satr
+ test_h_gr32 0x7fffffff r1
+ test_h_gr32 0xffffffff r6
+ test_h_gr32 0x80000000 r5
+ test_h_gr32 0x00000000 r4
+
+ pass
diff --git a/sim/testsuite/sim/rx/sbb.s b/sim/testsuite/sim/rx/sbb.s
new file mode 100644
index 0000000..0316508
--- /dev/null
+++ b/sim/testsuite/sim/rx/sbb.s
@@ -0,0 +1,46 @@
+# RX testcase for sbb
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+sbb_reg:
+ clear_carry_flag
+ mov.l #2,r1
+ mov.l #1,r2
+ sbb r2,r1
+ test_zero_set
+ test_carry_set
+ test_neg_clear
+ test_overflow_clear
+ test_h_gr32 0 r1
+sbb_mem_ind:
+ mov.l #val, r2
+ sbb [r2].l,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_set
+ test_overflow_clear
+ test_h_gr32 -1 r1
+sbb_mem_dsp8:
+ mov.l #val-4, r2
+ sbb 4[r2].l,r1
+ test_zero_clear
+ test_carry_set
+ test_neg_set
+ test_overflow_clear
+ test_h_gr32 -2 r1
+sbb_mem_dsp16:
+ mov.l #val-0x1000, r2
+ sbb 0x1000[r2].l,r1
+ test_zero_clear
+ test_carry_set
+ test_neg_set
+ test_overflow_clear
+ test_h_gr32 -3 r1
+
+ pass
+
+ .data
+val: .long 1
diff --git a/sim/testsuite/sim/rx/sccnd.s b/sim/testsuite/sim/rx/sccnd.s
new file mode 100644
index 0000000..686e3cb
--- /dev/null
+++ b/sim/testsuite/sim/rx/sccnd.s
@@ -0,0 +1,169 @@
+# RX testcase for SCcnd
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ mov #val,r2
+ mov #val-4,r3
+ mov #val-0x1000,r4
+ mov #10,r1
+ cmp #5,r1
+ scc.b [r2]
+ scc.b 5[r3]
+ scc.b 0x1002[r4]
+ scc.l r5
+ test_h_gr32 1 r5
+ mov.b [r2],r5
+ test_h_gr32 1 r5
+ mov.b 1[r2],r5
+ test_h_gr32 1 r5
+ mov.b 2[r2],r5
+ test_h_gr32 1 r5
+ mov.b #0,[r2]
+ cmp #15,r1
+ scnc.b [r2]
+ scnc.b 5[r3]
+ scnc.b 0x1002[r4]
+ scnc.l r5
+ test_h_gr32 1 r5
+ mov.b [r2],r5
+ test_h_gr32 1 r5
+ mov.b 1[r2],r5
+ test_h_gr32 1 r5
+ mov.b 2[r2],r5
+ test_h_gr32 1 r5
+ mov #-5,r1
+ cmp #-10,r1
+ scgt.b [r2]
+ scgt.b 5[r3]
+ scgt.b 0x1002[r4]
+ scgt.l r5
+ test_h_gr32 1 r5
+ mov.b [r2],r5
+ test_h_gr32 1 r5
+ mov.b 1[r2],r5
+ test_h_gr32 1 r5
+ mov.b 2[r2],r5
+ test_h_gr32 1 r5
+ mov #-5,r1
+ cmp #-5,r1
+ scle.b [r2]
+ scle.b 5[r3]
+ scle.b 0x1002[r4]
+ scle.l r5
+ test_h_gr32 1 r5
+ mov.b [r2],r5
+ test_h_gr32 1 r5
+ mov.b 1[r2],r5
+ test_h_gr32 1 r5
+ mov.b 2[r2],r5
+ test_h_gr32 1 r5
+ mov #-5,r1
+ cmp #-5,r1
+ scge.b [r2]
+ scge.b 5[r3]
+ scge.b 0x1002[r4]
+ scge.l r5
+ test_h_gr32 1 r5
+ mov.b [r2],r5
+ test_h_gr32 1 r5
+ mov.b 1[r2],r5
+ test_h_gr32 1 r5
+ mov.b 2[r2],r5
+ test_h_gr32 1 r5
+ mov #-5,r1
+ cmp #-1,r1
+ sclt.b [r2]
+ sclt.b 5[r3]
+ sclt.b 0x1002[r4]
+ sclt.l r5
+ test_h_gr32 1 r5
+ mov.b [r2],r5
+ test_h_gr32 1 r5
+ mov.b 1[r2],r5
+ test_h_gr32 1 r5
+ mov.b 2[r2],r5
+ test_h_gr32 1 r5
+ mov.l #0xc0000000,r1
+ cmp #0x80000000,r1
+ scgtu.b [r2]
+ scgtu.b 5[r3]
+ scgtu.b 0x1002[r4]
+ scgtu.l r5
+ test_h_gr32 1 r5
+ mov.b [r2],r5
+ test_h_gr32 1 r5
+ mov.b 1[r2],r5
+ test_h_gr32 1 r5
+ mov.b 2[r2],r5
+ test_h_gr32 1 r5
+ mov.l #0xc0000000,r1
+ cmp #0xc0000000,r1
+ scle.b [r2]
+ scle.b 5[r3]
+ scle.b 0x1002[r4]
+ scle.l r5
+ test_h_gr32 1 r5
+ mov.b [r2],r5
+ test_h_gr32 1 r5
+ mov.b 1[r2],r5
+ test_h_gr32 1 r5
+ mov.b 2[r2],r5
+ test_h_gr32 1 r5
+ mov #1,r1
+ tst r1,r1
+ scpz.b [r2]
+ scpz.b 5[r3]
+ scpz.b 0x1002[r4]
+ scpz.l r5
+ test_h_gr32 1 r5
+ mov.b [r2],r5
+ test_h_gr32 1 r5
+ mov.b 1[r2],r5
+ test_h_gr32 1 r5
+ mov.b 2[r2],r5
+ test_h_gr32 1 r5
+ mov #-1,r1
+ tst r1,r1
+ scn.b [r2]
+ scn.b 5[r3]
+ scn.b 0x1002[r4]
+ scn.l r5
+ test_h_gr32 1 r5
+ mov.b [r2],r5
+ test_h_gr32 1 r5
+ mov.b 1[r2],r5
+ test_h_gr32 1 r5
+ mov.b 2[r2],r5
+ test_h_gr32 1 r5
+ set_overflow_flag
+ sco.b [r2]
+ sco.b 5[r3]
+ sco.b 0x1002[r4]
+ sco.l r5
+ test_h_gr32 1 r5
+ mov.b [r2],r5
+ test_h_gr32 1 r5
+ mov.b 1[r2],r5
+ test_h_gr32 1 r5
+ mov.b 2[r2],r5
+ test_h_gr32 1 r5
+ clear_overflow_flag
+ scno.b [r2]
+ scno.b 5[r3]
+ scno.b 0x1002[r4]
+ scno.l r5
+ test_h_gr32 1 r5
+ mov.b [r2],r5
+ test_h_gr32 1 r5
+ mov.b 1[r2],r5
+ test_h_gr32 1 r5
+ mov.b 2[r2],r5
+ test_h_gr32 1 r5
+
+ pass
+
+ .data
+val: .space 8
diff --git a/sim/testsuite/sim/rx/scmpu.s b/sim/testsuite/sim/rx/scmpu.s
new file mode 100644
index 0000000..01c614e
--- /dev/null
+++ b/sim/testsuite/sim/rx/scmpu.s
@@ -0,0 +1,26 @@
+# RX testcase for scmpu
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ mov #str1,r1
+ mov #str1_ok,r2
+ mov #128,r3
+ scmpu
+ test_zero_set
+ test_carry_set
+ mov #str1,r1
+ mov #str1_ng,r2
+ mov #128,r3
+ scmpu
+ test_zero_clear
+ test_carry_set
+
+ pass
+
+ .data
+str1: .asciz "abcdefghijklmnopqrstuvwxyz"
+str1_ok: .asciz "abcdefghijklmnopqrstuvwxyz"
+str1_ng: .asciz "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
diff --git a/sim/testsuite/sim/rx/shlr.s b/sim/testsuite/sim/rx/shlr.s
new file mode 100644
index 0000000..e329af5
--- /dev/null
+++ b/sim/testsuite/sim/rx/shlr.s
@@ -0,0 +1,67 @@
+# RX testcase for SCcnd
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ mov #0x80000000,r1
+ shar #1,r1
+ test_carry_clear
+ test_zero_clear
+ test_neg_set
+ test_overflow_clear
+ test_h_gr32 0xc0000000 r1
+ mov #1,r2
+ shar r2,r1
+ test_carry_clear
+ test_zero_clear
+ test_neg_set
+ test_overflow_clear
+ test_h_gr32 0xe0000000 r1
+ shar #1,r1,r2
+ test_carry_clear
+ test_zero_clear
+ test_neg_set
+ test_overflow_clear
+ test_h_gr32 0xf0000000 r2
+ shll #1,r1
+ test_carry_set
+ test_zero_clear
+ test_neg_set
+ test_overflow_clear
+ test_h_gr32 0xc0000000 r1
+ mov #1,r2
+ shll r2,r1
+ test_carry_set
+ test_zero_clear
+ test_neg_set
+ test_overflow_clear
+ test_h_gr32 0x80000000 r1
+ shll #1,r1,r2
+ test_carry_set
+ test_zero_set
+ test_neg_clear
+ test_overflow_set
+ test_h_gr32 0x00000000 r2
+ mov #0xaaaaaaaa,r1
+ shlr #1,r1
+ test_carry_clear
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x55555555 r1
+ mov #1,r2
+ shlr r2,r1
+ test_carry_set
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x2aaaaaaa r1
+ shlr #1,r1,r2
+ test_carry_clear
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x15555555 r2
+
+ pass
+
+ .data
diff --git a/sim/testsuite/sim/rx/smovb.s b/sim/testsuite/sim/rx/smovb.s
new file mode 100644
index 0000000..26226df
--- /dev/null
+++ b/sim/testsuite/sim/rx/smovb.s
@@ -0,0 +1,53 @@
+# RX testcase for smovb
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ mov #src+127,r2
+ mov #dst+127,r1
+ mov #128,r3
+ smovb
+ add #1,r1
+ add #1,r2
+ mov #128,r3
+1: mov.b [r1],r4
+ cmp [r2].b,r4
+ bne __fail
+ mov.b #0,[r1]
+ add #1,r1
+ add #1,r2
+ sub #1,r3
+ bpz 1b
+ mov #src,r2
+ mov #dst,r1
+ mov #128,r3
+ smovf
+ mov #128,r3
+ mov #src,r2
+ mov #dst,r1
+1: mov.b [r1],r4
+ cmp [r2].b,r4
+ bne __fail
+ mov.b #0,[r1]
+ add #1,r1
+ add #1,r2
+ sub #1,r3
+ bpz 1b
+
+ pass
+__fail:
+ fail
+ exit 1
+
+ .data
+src:
+ data = 0
+ .rept 128
+ .byte data
+ data = data + 1
+ .endr
+dst:
+ .space 128
+
diff --git a/sim/testsuite/sim/rx/smovu.s b/sim/testsuite/sim/rx/smovu.s
new file mode 100644
index 0000000..a715918
--- /dev/null
+++ b/sim/testsuite/sim/rx/smovu.s
@@ -0,0 +1,23 @@
+# RX testcase for smovu
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ mov #str1,r2
+ mov #str1_dst,r1
+ mov #128,r3
+ smovu
+ mov #str1,r2
+ mov #str1_dst,r1
+ mov #128,r3
+ scmpu
+ test_zero_set
+
+ pass
+
+ .data
+str1: .asciz "abcdefghijklmnopqrstuvwxyz"
+str1_dst:
+ .space 27
diff --git a/sim/testsuite/sim/rx/sstr.s b/sim/testsuite/sim/rx/sstr.s
new file mode 100644
index 0000000..1ef0737
--- /dev/null
+++ b/sim/testsuite/sim/rx/sstr.s
@@ -0,0 +1,44 @@
+# RX testcase for sstr
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ mov #0x12345678,r2
+ mov #dst,r1
+ mov #128,r3
+ sstr.b
+ mov #128,r3
+ mov #dst,r1
+1: mov.b [r1+],r2
+ test_h_gr32 0x78 r2
+ sub #1,r3
+ bne 1b
+ mov #0x12345678,r2
+ mov #dst,r1
+ mov #128/2,r3
+ sstr.w
+ mov #128/2,r3
+ mov #dst,r1
+1: mov.w [r1+],r2
+ test_h_gr32 0x5678 r2
+ sub #1,r3
+ bne 1b
+ mov #0x12345678,r2
+ mov #dst,r1
+ mov #128/4,r3
+ sstr.l
+ mov #128/4,r3
+ mov #dst,r1
+1: mov.l [r1+],r2
+ test_h_gr32 0x12345678 r2
+ sub #1,r3
+ bne 1b
+
+ pass
+
+ .data
+dst:
+ .space 128
+
diff --git a/sim/testsuite/sim/rx/stz.s b/sim/testsuite/sim/rx/stz.s
new file mode 100644
index 0000000..a808c78
--- /dev/null
+++ b/sim/testsuite/sim/rx/stz.s
@@ -0,0 +1,52 @@
+# RX testcase for sstr
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names --defsym cpu=1
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+ clear_zero_flag
+ stnz #1, r1
+ stnz #0x100, r2
+ stnz #0x10000, r3
+ stnz #0x1000000, r4
+ stz #2, r1
+ stz #0x200, r2
+ stz #0x20000, r3
+ stz #0x2000000, r4
+ test_h_gr32 1 r1
+ test_h_gr32 0x100 r2
+ test_h_gr32 0x10000 r3
+ test_h_gr32 0x1000000 r4
+ set_zero_flag
+ stnz #1, r1
+ stnz #0x100, r2
+ stnz #0x10000, r3
+ stnz #0x1000000, r4
+ stz #2, r1
+ stz #0x200, r2
+ stz #0x20000, r3
+ stz #0x2000000, r4
+ test_h_gr32 2 r1
+ test_h_gr32 0x200 r2
+ test_h_gr32 0x20000 r3
+ test_h_gr32 0x2000000 r4
+
+ .if cpu == 2
+ mov #1,r1
+ mov #2,r2
+ clear_zero_flag
+ stz r2,r1
+ test_h_gr32 1 r1
+ clear_zero_flag
+ stnz r2,r1
+ test_h_gr32 2 r1
+ .endif
+
+ pass
+
+ .data
+dst:
+ .space 128
+
diff --git a/sim/testsuite/sim/rx/sub.s b/sim/testsuite/sim/rx/sub.s
new file mode 100644
index 0000000..cbc6d18
--- /dev/null
+++ b/sim/testsuite/sim/rx/sub.s
@@ -0,0 +1,53 @@
+# RX testcase for sub
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+sub_imm4:
+ mov.l #2,r1
+ sub #1,r1
+ test_zero_clear
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 1 r1
+sub_reg:
+ mov.l #1,r2
+ sub r2,r1
+ test_zero_set
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 0 r1
+sub_mem_ind:
+ mov.l #val, r2
+ sub [r2].l,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_set
+ test_h_gr32 -1 r1
+sub_mem_dsp8:
+ mov.l #val-4, r2
+ sub 4[r2].l,r1
+ test_zero_clear
+ test_carry_set
+ test_neg_set
+ test_h_gr32 -2 r1
+sub_mem_dsp16:
+ mov.l #val-0x1000, r2
+ sub 0x1000[r2].l,r1
+ test_zero_clear
+ test_carry_set
+ test_neg_set
+ test_h_gr32 -3 r1
+sub3_reg:
+ sub r1,r1,r2
+ test_zero_set
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 0 r2
+
+ pass
+
+ .data
+val: .long 1
diff --git a/sim/testsuite/sim/rx/suntil.s b/sim/testsuite/sim/rx/suntil.s
new file mode 100644
index 0000000..79bd268
--- /dev/null
+++ b/sim/testsuite/sim/rx/suntil.s
@@ -0,0 +1,59 @@
+# RX testcase for suntil
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ mov #until,r1
+ mov #127,r2
+ mov #128,r3
+ suntil.b
+ test_zero_set
+ test_h_gr32 0 r3
+ mov #until,r1
+ mov #0x7f7e,r2
+ mov #128/2,r3
+ suntil.w
+ test_zero_set
+ test_h_gr32 0 r3
+ mov #until,r1
+ mov #0x7f7e7d7c,r2
+ mov #128/4,r3
+ suntil.l
+ test_zero_set
+ test_h_gr32 0 r3
+
+ mov #while,r1
+ mov #0,r2
+ mov #128,r3
+ swhile.b
+ test_zero_clear
+ test_h_gr32 3 r3
+ mov #while,r1
+ mov #0,r2
+ mov #128/2,r3
+ swhile.w
+ test_zero_clear
+ test_h_gr32 1 r3
+ mov #while,r1
+ mov #0,r2
+ mov #128/4,r3
+ swhile.l
+ test_zero_clear
+ test_h_gr32 0 r3
+
+ pass
+
+ .data
+until:
+ data = 0
+ .rept 128
+ .byte data
+ data = data + 1
+ .endr
+while:
+ .rept 31
+ .long 0
+ .endr
+ .long 0x01010101
diff --git a/sim/testsuite/sim/rx/testutils.inc b/sim/testsuite/sim/rx/testutils.inc
new file mode 100644
index 0000000..06977ae
--- /dev/null
+++ b/sim/testsuite/sim/rx/testutils.inc
@@ -0,0 +1,302 @@
+# Support macros for the Renesas RX assembly test cases.
+
+; Set up a minimal machine state
+ .macro start
+
+ .text
+ .align 2
+ .global _start
+_start:
+ bra _main
+
+ .data
+ .align 2
+ .global pass_str
+ .global fail_str
+ .global ok_str
+pass_str:
+ .ascii "pass\n"
+fail_str:
+ .ascii "fail\n"
+ok_str:
+ .ascii "ok\n"
+
+ .text
+ .global _write_and_exit
+_write_and_exit:
+;ssize_t write(int fd, const void *buf, size_t count);
+;Integer arguments have to be zero extended.
+ mov.l #5,r5
+ int #255
+ mov.l r4,r1
+ bra _exit
+
+ .global _exit
+_exit:
+ mov.l #1,r5
+ int #255
+
+ .global _main
+_main:
+ .endm
+
+
+; Exit with an exit code
+ .macro exit code
+ mov.l #\code, r1
+ bra _exit
+ .endm
+
+; Output "pass\n"
+ .macro pass
+ mov.l #0, r1 ; fd == stdout
+ mov.l #pass_str, r2 ; buf == "pass\n"
+ mov.l #5, r3 ; len == 5
+ sub r4,r4
+ bra _write_and_exit
+ .endm
+
+; Output "fail\n"
+ .macro fail
+ mov.l #0, r1 ; fd == stdout
+ mov.l #fail_str, r2 ; buf == "fail\n"
+ mov.l #5, r3 ; len == 5
+ mov.l #1,r4
+ bra _write_and_exit
+ .endm
+
+
+; Load an 8-bit immediate value into a general register
+; (reg must be r0l - r7l or r0h - r7h)
+ .macro mvi_h_gr8 val reg
+ mov.b #\val, \reg
+ .endm
+
+; Load a 16-bit immediate value into a general register
+; (reg must be r0 - r7)
+ .macro mvi_h_gr16 val reg
+ mov.w #\val, \reg
+ .endm
+
+; Load a 32-bit immediate value into a general register
+; (reg must be er0 - er7)
+ .macro mvi_h_gr32 val reg
+ mov.l #\val, \reg
+ .endm
+
+; Test the value of an 8-bit immediate against a general register
+; (reg must be r0l - r7l or r0h - r7h)
+ .macro test_h_gr8 val reg
+ cmp.b #\val, \reg
+ beq .Ltest_gr8\@
+ fail
+.Ltest_gr8\@:
+ .endm
+
+; Test the value of a 16-bit immediate against a general register
+; (reg must be r0 - r7)
+ .macro test_h_gr16 val reg h=h l=l
+ cmp.w #\val, \reg
+ beq .Ltest_gr16\@
+ fail
+.Ltest_gr16\@:
+ .endm
+
+; Test the value of a 32-bit immediate against a general register
+; (reg must be er0 - er7)
+ .macro test_h_gr32 val reg
+ cmp #\val, \reg
+ beq .Ltest_gr32\@
+ fail
+.Ltest_gr32\@:
+ .endm
+
+; Set a general register to the fixed pattern 'a5a5a5a5'
+ .macro set_gr_a5a5 reg
+ mov.l #0xa5a5a5a5, r\reg
+ .endm
+
+; Set all general registers to the fixed pattern 'a5a5a5a5'
+ .macro set_grs_a5a5
+ mov.l #0xa5a5a5a5, r1
+ mov.l #0xa5a5a5a5, r2
+ mov.l #0xa5a5a5a5, r3
+ mov.l #0xa5a5a5a5, r4
+ mov.l #0xa5a5a5a5, r5
+ mov.l #0xa5a5a5a5, r6
+ mov.l #0xa5a5a5a5, r7
+ mov.l #0xa5a5a5a5, r8
+ mov.l #0xa5a5a5a5, r9
+ mov.l #0xa5a5a5a5, r10
+ mov.l #0xa5a5a5a5, r11
+ mov.l #0xa5a5a5a5, r12
+ mov.l #0xa5a5a5a5, r13
+ mov.l #0xa5a5a5a5, r14
+ mov.l #0xa5a5a5a5, r15
+ .endm
+
+; Test that a general register contains the fixed pattern 'a5a5a5a5'
+ .macro test_gr_a5a5 reg
+ test_h_gr32 0xa5a5a5a5 r\reg
+ .endm
+
+; Test that all general regs contain the fixed pattern 'a5a5a5a5'
+ .macro test_grs_a5a5
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ test_gr_a5a5 8
+ test_gr_a5a5 9
+ test_gr_a5a5 10
+ test_gr_a5a5 11
+ test_gr_a5a5 12
+ test_gr_a5a5 13
+ test_gr_a5a5 14
+ test_gr_a5a5 15
+ .endm
+
+; Set condition code register to an explicit value
+ .macro set_ccr val
+ mvtc #\val, psw
+ .endm
+
+; Set all condition code flags to zero
+ .macro set_ccr_zero
+ mvtc #0, psw
+ .endm
+
+; Set carry flag true
+ .macro set_carry_flag
+ setpsw c
+ .endm
+
+; Clear carry flag
+ .macro clear_carry_flag
+ clrpsw c
+ .endm
+
+; Set zero flag true
+ .macro set_zero_flag
+ setpsw z
+ .endm
+
+; Clear zero flag
+ .macro clear_zero_flag
+ clrpsw z
+ .endm
+
+; Set sign flag true
+ .macro set_neg_flag
+ setpsw s
+ .endm
+
+; Clear sign flag
+ .macro clear_neg_flag
+ clrpsw s
+ .endm
+
+; Set overflow flag true
+ .macro set_overflow_flag
+ setpsw o
+ .endm
+
+; Clear overflow flag
+ .macro clear_overflow_flag
+ clrpsw o
+ .endm
+
+; Test that carry flag is clear
+ .macro test_carry_clear
+ bnc .Lcc\@
+ fail ; carry flag not clear
+.Lcc\@:
+ .endm
+
+; Test that carry flag is set
+ .macro test_carry_set
+ bc .Lcs\@
+ fail ; carry flag not clear
+.Lcs\@:
+ .endm
+
+; Test that overflow flag is clear
+ .macro test_ovf_clear
+ bno .Lvc\@
+ fail ; overflow flag not clear
+.Lvc\@:
+ .endm
+
+; Test that overflow flag is set
+ .macro test_ovf_set
+ bo .Lvs\@
+ fail ; overflow flag not clear
+.Lvs\@:
+ .endm
+
+; Test that zero flag is clear
+ .macro test_zero_clear
+ bne .Lne\@
+ fail ; zero flag not clear
+.Lne\@:
+ .endm
+
+; Test that zero flag is set
+ .macro test_zero_set
+ beq .Leq\@
+ fail ; zero flag not clear
+.Leq\@:
+ .endm
+
+; Test that neg flag is clear
+ .macro test_neg_clear
+ bpz .Lneg\@
+ fail ; negative flag not clear
+.Lneg\@:
+ .endm
+
+; Test that neg flag is set
+ .macro test_neg_set
+ bn .Lneg\@
+ fail ; negative flag not clear
+.Lneg\@:
+ .endm
+
+; Test that overflow flag is clear
+ .macro test_overflow_clear
+ bno .Loverflow\@
+ fail ; negative flag not clear
+.Loverflow\@:
+ .endm
+
+; Test that overflow flag is set
+ .macro test_overflow_set
+ bo .Loverflow\@
+ fail ; negative flag not clear
+.Loverflow\@:
+ .endm
+
+; Test ccr against an explicit value
+ .macro test_ccr val
+ .text
+ mov.l r1,[-r0]
+ mvfc psw, r1
+ cmp #\val, r1
+ bne .Ltcc\@
+ fail
+.Ltcc\@:
+ mov.l [r0+],r1
+ .endm
+
+; Test that all (accessable) condition codes are clear
+ .macro test_cc_clear
+ test_carry_clear
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+ ; leaves H, I, U, and UI untested
+ .endm
+
diff --git a/sim/testsuite/sim/rx/tst.s b/sim/testsuite/sim/rx/tst.s
new file mode 100644
index 0000000..7736675
--- /dev/null
+++ b/sim/testsuite/sim/rx/tst.s
@@ -0,0 +1,54 @@
+# RX testcase for tst
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+tst_imm4:
+ mov.l #2,r1
+ tst #2,r1
+ test_zero_clear
+ test_neg_clear
+tst_imm8:
+ tst #0x13,r1
+ test_zero_clear
+ test_neg_clear
+tst_imm16:
+ tst #0xffff,r1
+ test_zero_clear
+ test_neg_clear
+tst_imm24:
+ tst #0xffffff,r1
+ test_zero_clear
+ test_neg_clear
+tst_imm32:
+ mov.l #0x80000000,r1
+ tst #0xffffffff,r1
+ test_zero_clear
+ test_neg_set
+tst_reg:
+ mov.l #0x80000000,r2
+ tst r2,r1
+ test_zero_clear
+ test_neg_set
+tst_mem_ind:
+ mov.l #val, r2
+ tst [r2].l,r1
+ test_zero_set
+ test_neg_clear
+tst_mem_dsp8:
+ mov.l #val-4, r2
+ tst 4[r2].l,r1
+ test_zero_set
+ test_neg_clear
+tst_mem_dsp16:
+ mov.l #val-0x1000, r2
+ tst 0x1000[r2].l,r1
+ test_zero_set
+ test_neg_clear
+
+ pass
+
+ .data
+val: .long 1
diff --git a/sim/testsuite/sim/rx/utof.s b/sim/testsuite/sim/rx/utof.s
new file mode 100644
index 0000000..2dee2bf
--- /dev/null
+++ b/sim/testsuite/sim/rx/utof.s
@@ -0,0 +1,37 @@
+# RX testcase for utof
+# mach: rxv2
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+utof_reg:
+ mov.l #2147483648,r2
+ utof r2,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2147483648.0 r1
+utof_mem_ind:
+ mov.l #val, r2
+ utof [r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2147483648.0 r1
+utof_mem_dsp8:
+ mov.l #val-4, r2
+ utof 4[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2147483648.0 r1
+utof_mem_dsp16:
+ mov.l #val-0x1000, r2
+ utof 0x1000[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2147483648.0 r1
+
+ pass
+
+ .data
+val: .long 2147483648
+
diff --git a/sim/testsuite/sim/rx/xchg.s b/sim/testsuite/sim/rx/xchg.s
new file mode 100644
index 0000000..b1098be
--- /dev/null
+++ b/sim/testsuite/sim/rx/xchg.s
@@ -0,0 +1,36 @@
+# RX testcase for xchg
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+xchg_reg:
+ mov.l #1,r1
+ mov.l #2,r2
+ xchg r2,r1
+ test_h_gr32 1 r2
+ test_h_gr32 2 r1
+xchg_mem_ind:
+ mov.l #val, r2
+ xchg [r2].l,r1
+ mov.l [r2],r3
+ test_h_gr32 1 r1
+ test_h_gr32 2 r3
+tst_mem_dsp8:
+ mov.l #val-4, r2
+ xchg 4[r2].l,r1
+ mov.l 4[r2],r3
+ test_h_gr32 2 r1
+ test_h_gr32 1 r3
+tst_mem_dsp16:
+ mov.l #val-0x1000, r2
+ xchg 0x1000[r2].l,r1
+ mov.l 0x1000[r2],r3
+ test_h_gr32 1 r1
+ test_h_gr32 2 r3
+
+ pass
+
+ .data
+val: .long 1
diff --git a/sim/testsuite/sim/rx/xor.s b/sim/testsuite/sim/rx/xor.s
new file mode 100644
index 0000000..0e22199
--- /dev/null
+++ b/sim/testsuite/sim/rx/xor.s
@@ -0,0 +1,58 @@
+# RX testcase for xor
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+xor_imm8:
+ sub r1,r1
+ xor #0x10,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x10 r1
+xor_imm16:
+ xor #0x1010,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x1000 r1
+xor_imm24:
+ xor #0x101000,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x100000 r1
+xor_imm32:
+ xor #0x10100000,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x10000000 r1
+xor_reg:
+ mov.l #0x20000000,r2
+ xor r2,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x30000000 r1
+xor_mem_ind:
+ mov #val, r2
+ xor [r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x30000008 r1
+xor_mem_dsp8:
+ mov #val-4, r2
+ xor 4[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x30000000 r1
+xor_mem_dsp16:
+ sub r1,r1
+ mov #val-0x1000, r2
+ xor 0x1000[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 8 r1
+
+ pass
+
+ .data
+val: .long 8
--
2.6.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH][RX] v2 instructions support
2015-12-27 8:51 [PATCH][RX] v2 instructions support Yoshinori Sato
2015-12-27 8:51 ` [PATCH][RX] instructions test set Yoshinori Sato
@ 2015-12-27 21:55 ` Mike Frysinger
2015-12-28 12:34 ` Yoshinori Sato
2016-01-06 2:43 ` DJ Delorie
1 sibling, 2 replies; 11+ messages in thread
From: Mike Frysinger @ 2015-12-27 21:55 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: gdb-patches, dj
[-- Attachment #1: Type: text/plain, Size: 101 bytes --]
looks good to me, but you might want a review from dj@ wrt the isa as
i'm not familiar with rx
-mike
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH][RX] instructions test set..
2015-12-27 8:51 ` [PATCH][RX] instructions test set Yoshinori Sato
@ 2015-12-27 21:56 ` Mike Frysinger
0 siblings, 0 replies; 11+ messages in thread
From: Mike Frysinger @ 2015-12-27 21:56 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: gdb-patches
[-- Attachment #1: Type: text/plain, Size: 961 bytes --]
On 27 Dec 2015 17:51, Yoshinori Sato wrote:
> index 0000000..e566c62
> --- /dev/null
> +++ b/sim/testsuite/sim/rx/allinsn.exp
> @@ -0,0 +1,25 @@
> +# Renesas RX simulator testsuite
> +
> +if [istarget rx-*-*] {
> + set global_ld_options "-Ttext=0x01000000 --defsym __stack=0x01800000"
> +
> + set mach "rx"
> + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] {
> + # If we're only testing specific files and this isn't one of them,
> + # skip it.
> + if ![runtest_file_p $runtests $src] {
> + continue
> + }
> + run_sim_test $src $mach
> + }
> +
> + set mach "rxv2"
> + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] {
> + # If we're only testing specific files and this isn't one of them,
> + # skip it.
> + if ![runtest_file_p $runtests $src] {
> + continue
> + }
> + run_sim_test $src $mach
> + }
> +}
doesn't it work if you call run_sim_test once with both rx & rxv2 ?
then you only need one loop.
-mike
[-- Attachment #2: Digital signature --]
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH][RX] v2 instructions support
2015-12-27 21:55 ` [PATCH][RX] v2 instructions support Mike Frysinger
@ 2015-12-28 12:34 ` Yoshinori Sato
2016-01-06 2:43 ` DJ Delorie
1 sibling, 0 replies; 11+ messages in thread
From: Yoshinori Sato @ 2015-12-28 12:34 UTC (permalink / raw)
To: Yoshinori Sato, gdb-patches, dj
On Mon, 28 Dec 2015 06:55:43 +0900,
Mike Frysinger wrote:
>
> looks good to me, but you might want a review from dj@ wrt the isa as
> i'm not familiar with rx
> -mike
OK.
Thanks.
--
Yoshinori Sato
<ysato@users.sourceforge.jp>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH][RX] v2 instructions support
2015-12-27 21:55 ` [PATCH][RX] v2 instructions support Mike Frysinger
2015-12-28 12:34 ` Yoshinori Sato
@ 2016-01-06 2:43 ` DJ Delorie
2016-01-06 8:23 ` Yoshinori Sato
1 sibling, 1 reply; 11+ messages in thread
From: DJ Delorie @ 2016-01-06 2:43 UTC (permalink / raw)
To: Mike Frysinger; +Cc: ysato, gdb-patches
> looks good to me, but you might want a review from dj@ wrt the isa as
> i'm not familiar with rx
Looks OK to me. My only concern is whether the testsuite passes on
real v2 hardware.
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH][RX] v2 instructions support
2016-01-06 2:43 ` DJ Delorie
@ 2016-01-06 8:23 ` Yoshinori Sato
0 siblings, 0 replies; 11+ messages in thread
From: Yoshinori Sato @ 2016-01-06 8:23 UTC (permalink / raw)
To: DJ Delorie; +Cc: Mike Frysinger, gdb-patches
On Wed, 06 Jan 2016 11:43:30 +0900,
DJ Delorie wrote:
>
>
> > looks good to me, but you might want a review from dj@ wrt the isa as
> > i'm not familiar with rx
>
> Looks OK to me. My only concern is whether the testsuite passes on
> real v2 hardware.
I got same result RX64M cpu on my testcase.
--
Yoshinori Sato
<ysato@users.sourceforge.jp>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH][RX] instructions test set.
2015-12-28 12:37 [PATCH][RX] instructions test set Yoshinori Sato
@ 2015-12-28 17:28 ` Mike Frysinger
0 siblings, 0 replies; 11+ messages in thread
From: Mike Frysinger @ 2015-12-28 17:28 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: gdb-patches
[-- Attachment #1: Type: text/plain, Size: 47 bytes --]
lgtm. always love to see testsuites :).
-mike
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH][RX] instructions test set.
@ 2015-12-28 12:37 Yoshinori Sato
2015-12-28 17:28 ` Mike Frysinger
0 siblings, 1 reply; 11+ messages in thread
From: Yoshinori Sato @ 2015-12-28 12:37 UTC (permalink / raw)
To: gdb-patches; +Cc: Yoshinori Sato
---
sim/testsuite/sim/rx/ChangeLog | 11 ++
sim/testsuite/sim/rx/abs.s | 25 +++
sim/testsuite/sim/rx/adc.s | 77 ++++++++++
sim/testsuite/sim/rx/add.s | 108 +++++++++++++
sim/testsuite/sim/rx/allinsn.exp | 14 ++
sim/testsuite/sim/rx/and.s | 79 ++++++++++
sim/testsuite/sim/rx/bcnd.s | 60 ++++++++
sim/testsuite/sim/rx/bmcnd.s | 132 ++++++++++++++++
sim/testsuite/sim/rx/bra.s | 23 +++
sim/testsuite/sim/rx/bset.s | 197 ++++++++++++++++++++++++
sim/testsuite/sim/rx/cmp.s | 74 +++++++++
sim/testsuite/sim/rx/div.s | 52 +++++++
sim/testsuite/sim/rx/emaca.s | 24 +++
sim/testsuite/sim/rx/emsba.s | 24 +++
sim/testsuite/sim/rx/emul.s | 92 +++++++++++
sim/testsuite/sim/rx/emula.s | 24 +++
sim/testsuite/sim/rx/fadd.s | 41 +++++
sim/testsuite/sim/rx/fcmp.s | 37 +++++
sim/testsuite/sim/rx/fdiv.s | 43 ++++++
sim/testsuite/sim/rx/fmul.s | 51 +++++++
sim/testsuite/sim/rx/fsqrt.s | 23 +++
sim/testsuite/sim/rx/fsub.s | 51 +++++++
sim/testsuite/sim/rx/ftoi.s | 37 +++++
sim/testsuite/sim/rx/ftou.s | 37 +++++
sim/testsuite/sim/rx/itof.s | 37 +++++
sim/testsuite/sim/rx/jmp.s | 12 ++
sim/testsuite/sim/rx/machilo.s | 53 +++++++
sim/testsuite/sim/rx/max.s | 45 ++++++
sim/testsuite/sim/rx/min.s | 45 ++++++
sim/testsuite/sim/rx/mov.s | 196 ++++++++++++++++++++++++
sim/testsuite/sim/rx/movlico.s | 22 +++
sim/testsuite/sim/rx/movu.s | 67 ++++++++
sim/testsuite/sim/rx/msbhilo.s | 43 ++++++
sim/testsuite/sim/rx/mul.s | 52 +++++++
sim/testsuite/sim/rx/mulhilo.s | 54 +++++++
sim/testsuite/sim/rx/mvacc.s | 28 ++++
sim/testsuite/sim/rx/mvftc.s | 36 +++++
sim/testsuite/sim/rx/neg.s | 17 +++
sim/testsuite/sim/rx/not.s | 17 +++
sim/testsuite/sim/rx/or.s | 69 +++++++++
sim/testsuite/sim/rx/pushpop.s | 48 ++++++
sim/testsuite/sim/rx/racw.s | 38 +++++
sim/testsuite/sim/rx/rdacw.s | 19 +++
sim/testsuite/sim/rx/rev.s | 14 ++
sim/testsuite/sim/rx/rmpa.s | 23 +++
sim/testsuite/sim/rx/rot.s | 46 ++++++
sim/testsuite/sim/rx/round.s | 37 +++++
sim/testsuite/sim/rx/sat.s | 37 +++++
sim/testsuite/sim/rx/sbb.s | 46 ++++++
sim/testsuite/sim/rx/sccnd.s | 169 +++++++++++++++++++++
sim/testsuite/sim/rx/scmpu.s | 26 ++++
sim/testsuite/sim/rx/shlr.s | 67 ++++++++
sim/testsuite/sim/rx/smovb.s | 53 +++++++
sim/testsuite/sim/rx/smovu.s | 23 +++
sim/testsuite/sim/rx/sstr.s | 44 ++++++
sim/testsuite/sim/rx/stz.s | 52 +++++++
sim/testsuite/sim/rx/sub.s | 53 +++++++
sim/testsuite/sim/rx/suntil.s | 59 ++++++++
sim/testsuite/sim/rx/testutils.inc | 302 +++++++++++++++++++++++++++++++++++++
sim/testsuite/sim/rx/tst.s | 54 +++++++
sim/testsuite/sim/rx/utof.s | 37 +++++
sim/testsuite/sim/rx/xchg.s | 36 +++++
sim/testsuite/sim/rx/xor.s | 58 +++++++
63 files changed, 3470 insertions(+)
create mode 100644 sim/testsuite/sim/rx/ChangeLog
create mode 100644 sim/testsuite/sim/rx/abs.s
create mode 100644 sim/testsuite/sim/rx/adc.s
create mode 100644 sim/testsuite/sim/rx/add.s
create mode 100644 sim/testsuite/sim/rx/allinsn.exp
create mode 100644 sim/testsuite/sim/rx/and.s
create mode 100644 sim/testsuite/sim/rx/bcnd.s
create mode 100644 sim/testsuite/sim/rx/bmcnd.s
create mode 100644 sim/testsuite/sim/rx/bra.s
create mode 100644 sim/testsuite/sim/rx/bset.s
create mode 100644 sim/testsuite/sim/rx/cmp.s
create mode 100644 sim/testsuite/sim/rx/div.s
create mode 100644 sim/testsuite/sim/rx/emaca.s
create mode 100644 sim/testsuite/sim/rx/emsba.s
create mode 100644 sim/testsuite/sim/rx/emul.s
create mode 100644 sim/testsuite/sim/rx/emula.s
create mode 100644 sim/testsuite/sim/rx/fadd.s
create mode 100644 sim/testsuite/sim/rx/fcmp.s
create mode 100644 sim/testsuite/sim/rx/fdiv.s
create mode 100644 sim/testsuite/sim/rx/fmul.s
create mode 100644 sim/testsuite/sim/rx/fsqrt.s
create mode 100644 sim/testsuite/sim/rx/fsub.s
create mode 100644 sim/testsuite/sim/rx/ftoi.s
create mode 100644 sim/testsuite/sim/rx/ftou.s
create mode 100644 sim/testsuite/sim/rx/itof.s
create mode 100644 sim/testsuite/sim/rx/jmp.s
create mode 100644 sim/testsuite/sim/rx/machilo.s
create mode 100644 sim/testsuite/sim/rx/max.s
create mode 100644 sim/testsuite/sim/rx/min.s
create mode 100644 sim/testsuite/sim/rx/mov.s
create mode 100644 sim/testsuite/sim/rx/movlico.s
create mode 100644 sim/testsuite/sim/rx/movu.s
create mode 100644 sim/testsuite/sim/rx/msbhilo.s
create mode 100644 sim/testsuite/sim/rx/mul.s
create mode 100644 sim/testsuite/sim/rx/mulhilo.s
create mode 100644 sim/testsuite/sim/rx/mvacc.s
create mode 100644 sim/testsuite/sim/rx/mvftc.s
create mode 100644 sim/testsuite/sim/rx/neg.s
create mode 100644 sim/testsuite/sim/rx/not.s
create mode 100644 sim/testsuite/sim/rx/or.s
create mode 100644 sim/testsuite/sim/rx/pushpop.s
create mode 100644 sim/testsuite/sim/rx/racw.s
create mode 100644 sim/testsuite/sim/rx/rdacw.s
create mode 100644 sim/testsuite/sim/rx/rev.s
create mode 100644 sim/testsuite/sim/rx/rmpa.s
create mode 100644 sim/testsuite/sim/rx/rot.s
create mode 100644 sim/testsuite/sim/rx/round.s
create mode 100644 sim/testsuite/sim/rx/sat.s
create mode 100644 sim/testsuite/sim/rx/sbb.s
create mode 100644 sim/testsuite/sim/rx/sccnd.s
create mode 100644 sim/testsuite/sim/rx/scmpu.s
create mode 100644 sim/testsuite/sim/rx/shlr.s
create mode 100644 sim/testsuite/sim/rx/smovb.s
create mode 100644 sim/testsuite/sim/rx/smovu.s
create mode 100644 sim/testsuite/sim/rx/sstr.s
create mode 100644 sim/testsuite/sim/rx/stz.s
create mode 100644 sim/testsuite/sim/rx/sub.s
create mode 100644 sim/testsuite/sim/rx/suntil.s
create mode 100644 sim/testsuite/sim/rx/testutils.inc
create mode 100644 sim/testsuite/sim/rx/tst.s
create mode 100644 sim/testsuite/sim/rx/utof.s
create mode 100644 sim/testsuite/sim/rx/xchg.s
create mode 100644 sim/testsuite/sim/rx/xor.s
diff --git a/sim/testsuite/sim/rx/ChangeLog b/sim/testsuite/sim/rx/ChangeLog
new file mode 100644
index 0000000..d149e6a
--- /dev/null
+++ b/sim/testsuite/sim/rx/ChangeLog
@@ -0,0 +1,11 @@
+2015-12-25 Yoshinori Sato <ysatt@users.sourceforge.jp>
+
+ * abs.s, adc.s, add.s, and.s, bcnd.s, bmcnd.s, bra.s, bset.s,
+ cmp.s, div.s, emaca.s, emsba.s, emul.s, emula.s, fadd.s, fcmp.s,
+ fdiv.s, fmul.s, fsqrt.s, fsub.s, ftoi.s, ftou.s, itof.s, jmp.s,
+ machilo.s, max.s, min.s, mov.s, movlico.s, movu.s, msbhilo.s,
+ mul.s, mulhilo.s, mvacc.s, mvftc.s, neg.s, not.s, or.s,pushpop.s,
+ racw.s, rdacw.s, rev.s, rmpa.s, rot.s, round.s, sbb.s, sccnd.s,
+ scmpu.s, shlr.s, smovb.s, smovu.s, sstr.s, stz.s, sub.s, suntil.s,
+ tst.s,utof.s,xchg.s,xor.s: New file.
+ * allinsn.exp: New file.
diff --git a/sim/testsuite/sim/rx/abs.s b/sim/testsuite/sim/rx/abs.s
new file mode 100644
index 0000000..3747797
--- /dev/null
+++ b/sim/testsuite/sim/rx/abs.s
@@ -0,0 +1,25 @@
+# RX testcase for abs
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+abs_dest:
+ mov.l #1,r1
+ abs r1
+ test_h_gr32 1 r1
+ mov.l #-1,r1
+ abs r1
+ test_h_gr32 1 r1
+abs_src_dest:
+ sub r2,r2
+ mov.l #1,r1
+ abs r1,r2
+ test_h_gr32 1 r2
+ sub r2,r2
+ mov.l #-1,r1
+ abs r1,r2
+ test_h_gr32 1 r2
+
+ pass
diff --git a/sim/testsuite/sim/rx/adc.s b/sim/testsuite/sim/rx/adc.s
new file mode 100644
index 0000000..49a8a6e
--- /dev/null
+++ b/sim/testsuite/sim/rx/adc.s
@@ -0,0 +1,77 @@
+# RX testcase for adc
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+adc_imm4:
+ clear_carry_flag
+ mov.l #1,r1
+ adc #2,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 3 r1
+adc_imm8:
+ clear_carry_flag
+ adc #-1,r1
+ test_zero_clear
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 2 r1
+adc_imm16:
+ set_carry_flag
+ adc #0x7ffd,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 0x8000 r1
+adc_imm24:
+ clear_carry_flag
+ adc #0x800000 - 0x8000,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 0x800000 r1
+adc_imm32:
+ clear_carry_flag
+ adc #0x80000000 - 0x800000,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_set
+ test_h_gr32 0x80000000 r1
+adc_reg:
+ clear_carry_flag
+ mov.l #0x80000000,r2
+ adc r2,r1
+ test_zero_set
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 0 r1
+adc_mem_ind:
+ mov.l #val, r2
+ adc [r2].l,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 2 r1
+adc_mem_dsp8:
+ mov.l #val-4, r2
+ adc 4[r2].l,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 4 r1
+adc_mem_dsp16:
+ mov.l #val-0x1000, r2
+ adc 0x1000[r2].l,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 6 r1
+
+ pass
+
+ .data
+val: .long 1
diff --git a/sim/testsuite/sim/rx/add.s b/sim/testsuite/sim/rx/add.s
new file mode 100644
index 0000000..a483d01
--- /dev/null
+++ b/sim/testsuite/sim/rx/add.s
@@ -0,0 +1,108 @@
+# RX testcase for add
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+add_imm4:
+ mov.l #1,r1
+ add #2,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 3 r1
+add_imm8:
+ add #-1,r1
+ test_zero_clear
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 2 r1
+add_imm16:
+ add #0x7ffe,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 0x8000 r1
+add_imm24:
+ add #0x800000 - 0x8000,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 0x800000 r1
+add_imm32:
+ add #0x80000000 - 0x800000,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_set
+ test_h_gr32 0x80000000 r1
+add_reg:
+ mov.l #0x80000000,r2
+ add r2,r1
+ test_zero_set
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 0 r1
+add_mem_ind:
+ mov.l #val, r2
+ add [r2].l,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 1 r1
+add_mem_dsp8:
+ mov.l #val-4, r2
+ add 4[r2].l,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 2 r1
+add_mem_dsp16:
+ mov.l #val-0x1000, r2
+ add 0x1000[r2].l,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 3 r1
+add3_imm4:
+ mov.l #1,r1
+ add #2,r1,r2
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 3 r2
+add3_imm8:
+ add #-1,r1,r2
+ test_zero_set
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 0 r2
+add3_imm16:
+ add #0x7ffe,r1,r2
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 0x7fff r2
+add3_imm24:
+ add #0x7ffffe,r1,r2
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 0x7fffff r2
+add3_imm32:
+ add #0x7ffffffe,r1,r2
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 0x7fffffff r2
+add3_reg:
+ add r1,r1,r2
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 2 r2
+
+ pass
+
+ .data
+val: .long 1
diff --git a/sim/testsuite/sim/rx/allinsn.exp b/sim/testsuite/sim/rx/allinsn.exp
new file mode 100644
index 0000000..09b9282
--- /dev/null
+++ b/sim/testsuite/sim/rx/allinsn.exp
@@ -0,0 +1,14 @@
+# Renesas RX simulator testsuite
+
+if [istarget rx-*-*] {
+ set global_ld_options "-Ttext=0x01000000 --defsym __stack=0x01800000"
+
+ foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] {
+ # If we're only testing specific files and this isn't one of them,
+ # skip it.
+ if ![runtest_file_p $runtests $src] {
+ continue
+ }
+ run_sim_test $src "rx rxv2"
+ }
+}
diff --git a/sim/testsuite/sim/rx/and.s b/sim/testsuite/sim/rx/and.s
new file mode 100644
index 0000000..4044562
--- /dev/null
+++ b/sim/testsuite/sim/rx/and.s
@@ -0,0 +1,79 @@
+# RX testcase for and
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+and_imm4:
+ mov.l #2,r1
+ and #2,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 2 r1
+and_imm8:
+ and #0x13,r1
+ test_zero_clear
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 2 r1
+and_imm16:
+ and #0xffff,r1
+ test_zero_clear
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 2 r1
+and_imm24:
+ and #0xffffff,r1
+ test_zero_clear
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 2 r1
+and_imm32:
+ mov.l #0x80000000,r1
+ and #0xffffffff,r1
+ test_zero_clear
+ test_carry_set
+ test_neg_set
+ test_h_gr32 0x80000000 r1
+and_reg:
+ mov.l #0x80000000,r2
+ and r2,r1
+ test_zero_clear
+ test_carry_set
+ test_neg_set
+ test_h_gr32 0x80000000 r1
+and_mem_ind:
+ mov.l #val, r2
+ and [r2].l,r1
+ test_zero_set
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 0 r1
+and_mem_dsp8:
+ mov.l #val-4, r2
+ and 4[r2].l,r1
+ test_zero_set
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 0 r1
+and_mem_dsp16:
+ mov.l #val-0x1000, r2
+ and 0x1000[r2].l,r1
+ test_zero_set
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 0 r1
+and3_reg:
+ mov.l #0x80000000,r2
+ and r2,r1,r3
+ test_zero_set
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 0 r3
+
+ pass
+
+ .data
+val: .long 1
diff --git a/sim/testsuite/sim/rx/bcnd.s b/sim/testsuite/sim/rx/bcnd.s
new file mode 100644
index 0000000..769c4b8
--- /dev/null
+++ b/sim/testsuite/sim/rx/bcnd.s
@@ -0,0 +1,60 @@
+# RX testcase for Bcnd
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ sub r2,r2
+ set_zero_flag
+ beq.s 1f
+ add #1,r2
+1: clear_zero_flag
+ bne.s 2f
+ add #1,r2
+2: test_h_gr32 0 r2
+ mov #10,r1
+ cmp #5,r1
+ bc 3f
+ fail
+3: cmp #15,r1
+ bnc 4f
+ fail
+4: mov #-5,r1
+ cmp #-10,r1
+ bgt 5f
+ fail
+5: cmp #-5,r1
+ ble 6f
+ fail
+6: bge 7f
+ fail
+7: cmp #-1,r1
+ blt 8f
+ fail
+8: mov.l #0xc0000000,r1
+ cmp #0x80000000,r1
+ bgtu 9f
+ fail
+9: mov #1,r1
+ tst r1,r1
+ bpz 11f
+ fail
+11: mov #-1,r1
+ tst r1,r1
+ bn 12f
+ fail
+12: set_overflow_flag
+ bo 13f
+ fail
+13: clear_overflow_flag
+ bno 14f
+ fail
+14: set_zero_flag
+ beq.w 15f
+ fail
+15: clear_zero_flag
+ bne.w 16f
+ fail
+16:
+ pass
diff --git a/sim/testsuite/sim/rx/bmcnd.s b/sim/testsuite/sim/rx/bmcnd.s
new file mode 100644
index 0000000..f3059eb
--- /dev/null
+++ b/sim/testsuite/sim/rx/bmcnd.s
@@ -0,0 +1,132 @@
+# RX testcase for BMcnd
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ mov #val,r2
+ mov #val-4,r3
+ mov #val-0x1000,r4
+ mov #10,r1
+ cmp #5,r1
+ bmc #0,[r2].b
+ bmc #1,4[r3].b
+ bmc #2,0x1000[r4].b
+ bmc #0,r5
+ btst #0,r5
+ test_zero_clear
+ mov.b [r2],r5
+ test_h_gr32 7 r5
+ mov.b #0,[r2]
+ cmp #15,r1
+ bmnc #0,[r2].b
+ bmnc #1,4[r3].b
+ bmnc #2,0x1000[r4].b
+ bmnc #0,r5
+ btst #0,r5
+ test_zero_clear
+ mov.b [r2],r5
+ test_h_gr32 7 r5
+ mov.b #0,[r2]
+ mov #-5,r1
+ cmp #-10,r1
+ bmgt #0,[r2].b
+ bmgt #1,4[r3].b
+ bmgt #2,0x1000[r4].b
+ bmgt #0,r5
+ btst #0,r5
+ test_zero_clear
+ mov.b [r2],r5
+ test_h_gr32 7 r5
+ mov.b #0,[r2]
+ mov #-5,r1
+ cmp #-5,r1
+ bmle #0,[r2].b
+ bmle #1,4[r3].b
+ bmle #2,0x1000[r4].b
+ bmle #0,r5
+ btst #0,r5
+ test_zero_clear
+ mov.b [r2],r5
+ test_h_gr32 7 r5
+ mov.b #0,[r2]
+ mov #-5,r1
+ cmp #-5,r1
+ bmge #0,[r2].b
+ bmge #1,4[r3].b
+ bmge #2,0x1000[r4].b
+ bmge #0,r5
+ btst #0,r5
+ test_zero_clear
+ mov.b [r2],r5
+ test_h_gr32 7 r5
+ mov.b #0,[r2]
+ mov #-5,r1
+ cmp #-1,r1
+ bmlt #0,[r2].b
+ bmlt #1,4[r3].b
+ bmlt #2,0x1000[r4].b
+ bmlt #0,r5
+ btst #0,r5
+ test_zero_clear
+ mov.b [r2],r5
+ test_h_gr32 7 r5
+ mov.b #0,[r2]
+ mov.l #0xc0000000,r1
+ cmp #0x80000000,r1
+ bmgtu #0,[r2].b
+ bmgtu #1,4[r3].b
+ bmgtu #2,0x1000[r4].b
+ bmgtu #0,r5
+ btst #0,r5
+ test_zero_clear
+ mov.b [r2],r5
+ test_h_gr32 7 r5
+ mov.b #0,[r2]
+ mov #1,r1
+ tst r1,r1
+ bmpz #0,[r2].b
+ bmpz #1,4[r3].b
+ bmpz #2,0x1000[r4].b
+ bmpz #0,r5
+ btst #0,r5
+ test_zero_clear
+ mov.b [r2],r5
+ test_h_gr32 7 r5
+ mov.b #0,[r2]
+ mov #-1,r1
+ tst r1,r1
+ bmn #0,[r2].b
+ bmn #1,4[r3].b
+ bmn #2,0x1000[r4].b
+ bmn #0,r5
+ btst #0,r5
+ test_zero_clear
+ mov.b [r2],r5
+ test_h_gr32 7 r5
+ mov.b #0,[r2]
+ set_overflow_flag
+ bmo #0,[r2].b
+ bmo #1,4[r3].b
+ bmo #2,0x1000[r4].b
+ bmo #0,r5
+ btst #0,r5
+ test_zero_clear
+ mov.b [r2],r5
+ test_h_gr32 7 r5
+ mov.b #0,[r2]
+ clear_overflow_flag
+ bmno #0,[r2].b
+ bmno #1,4[r3].b
+ bmno #2,0x1000[r4].b
+ bmno #0,r5
+ btst #0,r5
+ test_zero_clear
+ mov.b [r2],r5
+ test_h_gr32 7 r5
+
+ pass
+
+ .data
+val: .byte 0
diff --git a/sim/testsuite/sim/rx/bra.s b/sim/testsuite/sim/rx/bra.s
new file mode 100644
index 0000000..443d4db
--- /dev/null
+++ b/sim/testsuite/sim/rx/bra.s
@@ -0,0 +1,23 @@
+# RX testcase for bra
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ sub r2,r2
+ bra.s 1f
+ add #1,r2
+1: test_h_gr32 0 r2
+ bra.b 2f
+ fail
+2: bra.w 3f
+ fail
+3: bra.a 4f
+ fail
+4: mov #6f,r1
+ sub #5f,r1
+5: bra r1
+ fail
+6:
+ pass
diff --git a/sim/testsuite/sim/rx/bset.s b/sim/testsuite/sim/rx/bset.s
new file mode 100644
index 0000000..69c6e21
--- /dev/null
+++ b/sim/testsuite/sim/rx/bset.s
@@ -0,0 +1,197 @@
+# RX testcase for bset/bclr/bnot/btst
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+bset_imm_ind:
+ mov.l #val,r2
+ bset #0,[r2].b
+ btst #0,[r2].b
+ test_zero_clear
+ test_carry_set
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 3 r1
+bclr_imm_ind:
+ bclr #1,[r2].b
+ btst #1,[r2].b
+ test_zero_set
+ test_carry_clear
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 1 r1
+bnot_imm_ind:
+ bnot #1,[r2].b
+ btst #1,[r2].b
+ test_zero_clear
+ test_carry_set
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 3 r1
+bset_imm_dsp8:
+ mov.l #val-4,r2
+ bset #2,4[r2].b
+ btst #2,4[r2].b
+ test_zero_clear
+ test_carry_set
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 7 r1
+bclr_imm_dsp8:
+ bclr #2,4[r2].b
+ btst #2,4[r2].b
+ test_zero_set
+ test_carry_clear
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 3 r1
+bnot_imm_dsp8:
+ bnot #2,4[r2].b
+ btst #2,4[r2].b
+ test_zero_clear
+ test_carry_set
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 7 r1
+bset_imm_dsp16:
+ mov.l #val-0x1000,r2
+ bset #2,0x1000[r2].b
+ btst #2,0x1000[r2].b
+ test_zero_clear
+ test_carry_set
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 7 r1
+bclr_imm_dsp16:
+ bclr #2,0x1000[r2].b
+ btst #2,0x1000[r2].b
+ test_zero_set
+ test_carry_clear
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 3 r1
+bnot_imm_dsp16:
+ bnot #2,0x1000[r2].b
+ btst #2,0x1000[r2].b
+ test_zero_clear
+ test_carry_set
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 7 r1
+bset_reg_ind:
+ mov.l #0,r1
+ mov.l #val,r2
+ bset r1,[r2].b
+ btst r1,[r2].b
+ test_zero_clear
+ test_carry_set
+ mov.b [r2],r1
+ test_h_gr32 7 r1
+bclr_reg_ind:
+ mov.l #0,r1
+ bclr r1,[r2].b
+ btst r1,[r2].b
+ test_zero_set
+ test_carry_clear
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 6 r1
+bnot_reg_ind:
+ mov.l #0,r1
+ bnot r1,[r2].b
+ btst r1,[r2].b
+ test_zero_clear
+ test_carry_set
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 7 r1
+bset_reg_dsp8:
+ mov.l #2,r1
+ mov.l #val-4,r2
+ bset r1,4[r2].b
+ btst r1,4[r2].b
+ test_zero_clear
+ test_carry_set
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 7 r1
+bclr_reg_dsp8:
+ mov.l #2,r1
+ bclr r1,4[r2].b
+ btst r1,4[r2].b
+ test_zero_set
+ test_carry_clear
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 3 r1
+bnot_reg_dsp8:
+ mov.l #2,r1
+ bnot r1,4[r2].b
+ btst r1,4[r2].b
+ test_zero_clear
+ test_carry_set
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 7 r1
+bset_reg_dsp16:
+ mov.l #2,r1
+ mov.l #val-0x1000,r2
+ bset r1,0x1000[r2].b
+ btst r1,0x1000[r2].b
+ test_zero_clear
+ test_carry_set
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 7 r1
+bclr_reg_dsp16:
+ mov.l #2,r1
+ bclr r1,0x1000[r2].b
+ btst r1,0x1000[r2].b
+ test_zero_set
+ test_carry_clear
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 3 r1
+bnot_reg_dsp16:
+ mov.l #2,r1
+ bnot r1,0x1000[r2].b
+ btst r1,0x1000[r2].b
+ test_zero_clear
+ test_carry_set
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 7 r1
+bnot_imm_reg:
+ sub r1,r1
+ bnot #1,r1
+ btst #1,r1
+ test_zero_clear
+ test_carry_set
+ test_h_gr32 2 r1
+bset_reg_reg:
+ sub r1,r1
+ mov.l #1,r2
+ bset r2,r1
+ btst r2,r1
+ test_zero_clear
+ test_carry_set
+ test_h_gr32 2 r1
+bclr_reg_reg:
+ bclr r2,r1
+ btst r2,r1
+ test_zero_set
+ test_carry_clear
+ test_h_gr32 0 r1
+bnot_reg_reg:
+ bnot r2,r1
+ btst r2,r1
+ test_zero_clear
+ test_carry_set
+ test_h_gr32 2 r1
+
+ pass
+
+ .data
+val: .byte 2
diff --git a/sim/testsuite/sim/rx/cmp.s b/sim/testsuite/sim/rx/cmp.s
new file mode 100644
index 0000000..73dff9d
--- /dev/null
+++ b/sim/testsuite/sim/rx/cmp.s
@@ -0,0 +1,74 @@
+# RX testcase for cmp
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+cmp_imm4:
+ mov #1,r1
+ cmp #2,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_set
+ test_overflow_clear
+cmp_imm8:
+ cmp #-1,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_overflow_clear
+cmp_imm16:
+ mov #0x8000,r1
+ cmp #0x8000,r1
+ test_zero_set
+ test_carry_set
+ test_neg_clear
+ test_overflow_clear
+cmp_imm24:
+ mov #0x800000,r1
+ cmp #0x7fffff,r1
+ test_zero_clear
+ test_carry_set
+ test_neg_clear
+ test_overflow_clear
+cmp_imm32:
+ mov #0x80000000,r1
+ cmp #0x7fffffff,r1
+ test_zero_clear
+ test_carry_set
+ test_neg_clear
+ test_overflow_set
+cmp_reg:
+ mov.l #0x80000000,r2
+ cmp r2,r1
+ test_zero_set
+ test_carry_set
+ test_neg_clear
+cmp_mem_ind:
+ sub r1,r1
+ mov #val, r2
+ cmp [r2].l,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_set
+ test_overflow_clear
+cmp_mem_dsp8:
+ mov #val-4, r2
+ cmp 4[r2].l,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_set
+ test_overflow_clear
+cmp_mem_dsp16:
+ mov #val-0x1000, r2
+ cmp 0x1000[r2].l,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_set
+ test_overflow_clear
+
+ pass
+
+ .data
+val: .long 1
diff --git a/sim/testsuite/sim/rx/div.s b/sim/testsuite/sim/rx/div.s
new file mode 100644
index 0000000..40b814d
--- /dev/null
+++ b/sim/testsuite/sim/rx/div.s
@@ -0,0 +1,52 @@
+# RX testcase for div/divu
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+div_imm8:
+ mov #2,r1
+ div #2,r1
+ test_h_gr32 1 r1
+div_imm16:
+ mov #0x8000,r1
+ div #0x1000,r1
+ test_h_gr32 8 r1
+div_imm24:
+ mov #0x800000,r1
+ div #0x200000,r1
+ test_h_gr32 4 r1
+div_imm32:
+ mov #0x80000000,r1
+ div #0x40000000,r1
+ test_h_gr32 -2 r1
+divu_imm32:
+ mov #0x80000000,r1
+ divu #0x40000000,r1
+ test_h_gr32 2 r1
+div_reg:
+ mov #0x80000000,r1
+ mov r1,r2
+ div r2,r1
+ test_h_gr32 1 r1
+div_mem_ind:
+ mov #10,r1
+ mov #val, r2
+ div [r2],r1
+ test_h_gr32 5 r1
+div_mem_dsp8:
+ mov #10,r1
+ mov #val-4, r2
+ div 4[r2],r1
+ test_h_gr32 5 r1
+div_mem_dsp16:
+ mov #10,r1
+ mov #val-0x1000, r2
+ div 0x1000[r2],r1
+ test_h_gr32 5 r1
+
+ pass
+
+ .data
+val: .long 2
diff --git a/sim/testsuite/sim/rx/emaca.s b/sim/testsuite/sim/rx/emaca.s
new file mode 100644
index 0000000..e066d57
--- /dev/null
+++ b/sim/testsuite/sim/rx/emaca.s
@@ -0,0 +1,24 @@
+# RX testcase for emaca
+# mach: rxv2
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+ mov #100, r1
+ mov #200, r2
+ emaca r1,r2,a0
+ mvfaclo #0,a0,r1
+ test_h_gr32 20000 r1
+ mvfachi #0,a0,r1
+ test_h_gr32 0 r1
+ mov #300, r1
+ mov #200, r2
+ emaca r1,r2,a1
+ mvfaclo #0,a1,r1
+ test_h_gr32 60000 r1
+ mvfachi #0,a1,r1
+ test_h_gr32 0 r1
+
+ pass
+
diff --git a/sim/testsuite/sim/rx/emsba.s b/sim/testsuite/sim/rx/emsba.s
new file mode 100644
index 0000000..a20c963
--- /dev/null
+++ b/sim/testsuite/sim/rx/emsba.s
@@ -0,0 +1,24 @@
+# RX testcase for emsba
+# mach: rxv2
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+ mov #100, r1
+ mov #200, r2
+ emsba r1,r2,a0
+ mvfaclo #0,a0,r1
+ test_h_gr32 -20000 r1
+ mvfachi #0,a0,r1
+ test_h_gr32 -1 r1
+ mov #300, r1
+ mov #200, r2
+ emsba r1,r2,a1
+ mvfaclo #0,a1,r1
+ test_h_gr32 -60000 r1
+ mvfachi #0,a1,r1
+ test_h_gr32 -1 r1
+
+ pass
+
diff --git a/sim/testsuite/sim/rx/emul.s b/sim/testsuite/sim/rx/emul.s
new file mode 100644
index 0000000..cbbac82
--- /dev/null
+++ b/sim/testsuite/sim/rx/emul.s
@@ -0,0 +1,92 @@
+# RX testcase for emul
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+emul_imm8:
+ mov #0xf0000001,r1
+ emul #0x10,r1
+ test_h_gr32 0x10 r1
+ test_h_gr32 0xffffffff r2
+emul_imm16:
+ emul #1000,r1
+ test_h_gr32 16000 r1
+ test_h_gr32 0 r2
+emul_imm24:
+ mov.l #0x10000,r1
+ emul #0x10000,r1
+ test_h_gr32 0 r1
+ test_h_gr32 1 r2
+emul_imm32:
+ mov.l #0x10,r1
+ emul #0x10000000,r1
+ test_h_gr32 0 r1
+ test_h_gr32 1 r2
+emul_reg:
+ mov #5, r1
+ mov r1,r2
+ emul r2,r1
+ test_h_gr32 25 r1
+ test_h_gr32 0 r2
+emul_mem_ind:
+ mov.l #val, r2
+ emul [r2].l,r1
+ test_h_gr32 50 r1
+ test_h_gr32 0 r2
+emul_mem_dsp8:
+ mov.l #val-4, r2
+ emul 4[r2].l,r1
+ test_h_gr32 100 r1
+ test_h_gr32 0 r2
+emul_mem_dsp16:
+ mov.l #val-0x1000, r2
+ emul 0x1000[r2].l,r1
+ test_h_gr32 200 r1
+ test_h_gr32 0 r2
+emulu_imm8:
+ mov #0xf0000001,r1
+ emulu #0x10,r1
+ test_h_gr32 0x10 r1
+ test_h_gr32 0xf r2
+emulu_imm16:
+ emulu #1000,r1
+ test_h_gr32 16000 r1
+ test_h_gr32 0 r2
+emulu_imm24:
+ mov.l #0x10000,r1
+ emulu #0x10000,r1
+ test_h_gr32 0 r1
+ test_h_gr32 1 r2
+emulu_imm32:
+ mov.l #0x10,r1
+ emulu #0x10000000,r1
+ test_h_gr32 0 r1
+ test_h_gr32 1 r2
+emulu_reg:
+ mov #-5, r1
+ mov r1,r2
+ emul r2,r1
+ test_h_gr32 25 r1
+ test_h_gr32 0 r2
+emulu_mem_ind:
+ mov.l #val, r2
+ emulu [r2].l,r1
+ test_h_gr32 50 r1
+ test_h_gr32 0 r2
+emulu_mem_dsp8:
+ mov.l #val-4, r2
+ emulu 4[r2].l,r1
+ test_h_gr32 100 r1
+ test_h_gr32 0 r2
+emulu_mem_dsp16:
+ mov.l #val-0x1000, r2
+ emulu 0x1000[r2].l,r1
+ test_h_gr32 200 r1
+ test_h_gr32 0 r2
+
+ pass
+
+ .data
+val: .long 2
diff --git a/sim/testsuite/sim/rx/emula.s b/sim/testsuite/sim/rx/emula.s
new file mode 100644
index 0000000..44fbd8a
--- /dev/null
+++ b/sim/testsuite/sim/rx/emula.s
@@ -0,0 +1,24 @@
+# RX testcase for emula
+# mach: rxv2
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+ mov #100, r1
+ mov #200, r2
+ emula r1,r2,a0
+ mvfaclo #0,a0,r1
+ test_h_gr32 20000 r1
+ mvfachi #0,a0,r1
+ test_h_gr32 0 r1
+ mov #300, r1
+ mov #200, r2
+ emula r1,r2,a1
+ mvfaclo #0,a1,r1
+ test_h_gr32 60000 r1
+ mvfachi #0,a1,r1
+ test_h_gr32 0 r1
+
+ pass
+
diff --git a/sim/testsuite/sim/rx/fadd.s b/sim/testsuite/sim/rx/fadd.s
new file mode 100644
index 0000000..430fb38
--- /dev/null
+++ b/sim/testsuite/sim/rx/fadd.s
@@ -0,0 +1,41 @@
+# RX testcase for fadd
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names --defsym cpu=1
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+fadd_imm:
+ mov #1.0,r1
+ fadd #2.0,r1
+ test_h_gr32 3.0 r1
+fadd_reg:
+ mov.l #4.0,r2
+ fadd r2,r1
+ test_h_gr32 7.0 r1
+fadd_mem_ind:
+ mov.l #val, r2
+ fadd [r2].l,r1
+ test_h_gr32 8.0 r1
+fadd_mem_dsp8:
+ mov.l #val-4, r2
+ fadd 4[r2].l,r1
+ test_h_gr32 9.0 r1
+fadd_mem_dsp16:
+ mov.l #val-0x1000, r2
+ fadd 0x1000[r2].l,r1
+ test_h_gr32 10.0 r1
+ .if cpu == 2
+fadd3_reg:
+ mov.l #4.0,r2
+ mov.l #1.0,r3
+ fadd r2,r3,r1
+ test_h_gr32 5.0 r1
+ .endif
+
+ pass
+
+ .data
+val: .float 1.0
+
diff --git a/sim/testsuite/sim/rx/fcmp.s b/sim/testsuite/sim/rx/fcmp.s
new file mode 100644
index 0000000..db06423
--- /dev/null
+++ b/sim/testsuite/sim/rx/fcmp.s
@@ -0,0 +1,37 @@
+# RX testcase for fcmp
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+fcmp_imm:
+ mov #1.0,r1
+ fcmp #2.0,r1
+ test_zero_clear
+ test_neg_set
+fcmp_reg:
+ mov.l #4.0,r2
+ fcmp r2,r1
+ test_zero_clear
+ test_neg_set
+fcmp_mem_ind:
+ mov.l #val, r2
+ fcmp [r2].l,r1
+ test_zero_set
+ test_neg_clear
+fcmp_mem_dsp8:
+ mov.l #val-4, r2
+ fcmp 4[r2].l,r1
+ test_zero_set
+ test_neg_clear
+fcmp_mem_dsp16:
+ mov.l #val-0x1000, r2
+ fcmp 0x1000[r2].l,r1
+ test_zero_set
+ test_neg_clear
+ pass
+
+ .data
+val: .float 1.0
+
diff --git a/sim/testsuite/sim/rx/fdiv.s b/sim/testsuite/sim/rx/fdiv.s
new file mode 100644
index 0000000..540a081
--- /dev/null
+++ b/sim/testsuite/sim/rx/fdiv.s
@@ -0,0 +1,43 @@
+# RX testcase for fdiv
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+fdiv_imm:
+ mov #100.0,r1
+ fdiv #2.0,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 50.0 r1
+fdiv_reg:
+ mov.l #2.0,r2
+ fdiv r2,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 25.0 r1
+fdiv_mem_ind:
+ mov.l #val, r2
+ fdiv [r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 12.5 r1
+fdiv_mem_dsp8:
+ mov.l #val-4, r2
+ fdiv 4[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 6.25 r1
+fdiv_mem_dsp16:
+ mov.l #val-0x1000, r2
+ fdiv 0x1000[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 3.125 r1
+
+ pass
+
+ .data
+val: .float 2.0
+
diff --git a/sim/testsuite/sim/rx/fmul.s b/sim/testsuite/sim/rx/fmul.s
new file mode 100644
index 0000000..d79a6d3
--- /dev/null
+++ b/sim/testsuite/sim/rx/fmul.s
@@ -0,0 +1,51 @@
+# RX testcase for fmul
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names --defsym cpu=1
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+fmul_imm:
+ mov #10.0,r1
+ fmul #2.0,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 20.0 r1
+fmul_reg:
+ mov.l #2.0,r2
+ fmul r2,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 40.0 r1
+fmul_mem_ind:
+ mov.l #val, r2
+ fmul [r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 80.0 r1
+fmul_mem_dsp8:
+ mov.l #val-4, r2
+ fmul 4[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 160.0 r1
+fmul_mem_dsp16:
+ mov.l #val-0x1000, r2
+ fmul 0x1000[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 320.0 r1
+ .if cpu == 2
+fmul3_reg:
+ mov.l #4.0,r2
+ mov.l #6.0,r3
+ fmul r3,r2,r1
+ test_h_gr32 24.0 r1
+ .endif
+
+ pass
+
+ .data
+val: .float 2.0
+
diff --git a/sim/testsuite/sim/rx/fsqrt.s b/sim/testsuite/sim/rx/fsqrt.s
new file mode 100644
index 0000000..3c1d52d
--- /dev/null
+++ b/sim/testsuite/sim/rx/fsqrt.s
@@ -0,0 +1,23 @@
+# RX testcase for add
+# mach: rxv2
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+ mov #4.0,r2
+ fsqrt r2,r1
+ test_h_gr32 2.0 r1
+ mov #val,r2
+ fsqrt [r2],r1
+ test_h_gr32 3.0 r1
+ fsqrt 4[r2],r1
+ test_h_gr32 4.0 r1
+ mov #val - 0x1000 + 8,r2
+ fsqrt 0x1000[r2],r1
+ test_h_gr32 5.0 r1
+
+ pass
+
+ .data
+val: .float 9,16,25
diff --git a/sim/testsuite/sim/rx/fsub.s b/sim/testsuite/sim/rx/fsub.s
new file mode 100644
index 0000000..629a2a0
--- /dev/null
+++ b/sim/testsuite/sim/rx/fsub.s
@@ -0,0 +1,51 @@
+# RX testcase for fsub
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names --defsym cpu=1
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+fsub_imm:
+ mov #10.0,r1
+ fsub #2.0,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 8.0 r1
+fsub_reg:
+ mov.l #2.0,r2
+ fsub r2,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 6.0 r1
+fsub_mem_ind:
+ mov.l #val, r2
+ fsub [r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 4.0 r1
+fsub_mem_dsp8:
+ mov.l #val-4, r2
+ fsub 4[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2.0 r1
+fsub_mem_dsp16:
+ mov.l #val-0x1000, r2
+ fsub 0x1000[r2].l,r1
+ test_zero_set
+ test_neg_clear
+ test_h_gr32 0.0 r1
+ .if cpu == 2
+fsub3_reg:
+ mov.l #4.0,r2
+ mov.l #1.0,r3
+ fsub r3,r2,r1
+ test_h_gr32 3.0 r1
+ .endif
+
+ pass
+
+ .data
+val: .float 2.0
+
diff --git a/sim/testsuite/sim/rx/ftoi.s b/sim/testsuite/sim/rx/ftoi.s
new file mode 100644
index 0000000..0d21f19
--- /dev/null
+++ b/sim/testsuite/sim/rx/ftoi.s
@@ -0,0 +1,37 @@
+# RX testcase for ftoi
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ftoi_reg:
+ mov.l #12.34,r2
+ ftoi r2,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 12 r1
+ftoi_mem_ind:
+ mov.l #val, r2
+ ftoi [r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2 r1
+ftoi_mem_dsp8:
+ mov.l #val-4, r2
+ ftoi 4[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2 r1
+ftoi_mem_dsp16:
+ mov.l #val-0x1000, r2
+ ftoi 0x1000[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2 r1
+
+ pass
+
+ .data
+val: .float 2.345
+
diff --git a/sim/testsuite/sim/rx/ftou.s b/sim/testsuite/sim/rx/ftou.s
new file mode 100644
index 0000000..434933d
--- /dev/null
+++ b/sim/testsuite/sim/rx/ftou.s
@@ -0,0 +1,37 @@
+# RX testcase for ftou
+# mach: rxv2
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+ftou_reg:
+ mov.l #2147483648.0,r2
+ ftou r2,r1
+ test_zero_clear
+ test_neg_set
+ test_h_gr32 -2147483648 r1
+ftou_mem_ind:
+ mov.l #val, r2
+ ftou [r2].l,r1
+ test_zero_clear
+ test_neg_set
+ test_h_gr32 -2147483648 r1
+ftou_mem_dsp8:
+ mov.l #val-4, r2
+ ftou 4[r2].l,r1
+ test_zero_clear
+ test_neg_set
+ test_h_gr32 -2147483648 r1
+ftou_mem_dsp16:
+ mov.l #val-0x1000, r2
+ ftou 0x1000[r2].l,r1
+ test_zero_clear
+ test_neg_set
+ test_h_gr32 -2147483648 r1
+
+ pass
+
+ .data
+val: .float 2147483648.0
+
diff --git a/sim/testsuite/sim/rx/itof.s b/sim/testsuite/sim/rx/itof.s
new file mode 100644
index 0000000..055b42f
--- /dev/null
+++ b/sim/testsuite/sim/rx/itof.s
@@ -0,0 +1,37 @@
+# RX testcase for itof
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+itof_reg:
+ mov.l #12,r2
+ itof r2,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 12.0 r1
+itof_mem_ind:
+ mov.l #val, r2
+ itof [r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2.0 r1
+itof_mem_dsp8:
+ mov.l #val-4, r2
+ itof 4[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2.0 r1
+itof_mem_dsp16:
+ mov.l #val-0x1000, r2
+ itof 0x1000[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2.0 r1
+
+ pass
+
+ .data
+val: .long 2
+
diff --git a/sim/testsuite/sim/rx/jmp.s b/sim/testsuite/sim/rx/jmp.s
new file mode 100644
index 0000000..fe3e3b3
--- /dev/null
+++ b/sim/testsuite/sim/rx/jmp.s
@@ -0,0 +1,12 @@
+# RX testcase for jmp
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ mov #1f,r1
+ jmp r1
+ fail
+1:
+ pass
diff --git a/sim/testsuite/sim/rx/machilo.s b/sim/testsuite/sim/rx/machilo.s
new file mode 100644
index 0000000..2d534ae
--- /dev/null
+++ b/sim/testsuite/sim/rx/machilo.s
@@ -0,0 +1,53 @@
+# RX testcase for add
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names --defsym cpu=1
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+ sub r1,r1
+ mvtachi r1
+ mvtaclo r1
+ mov #0x20000,r1
+ mov #0x30000,r2
+ machi r1,r2
+ mvfacmi r1
+ test_h_gr32 6 r1
+ mvfachi r1
+ test_h_gr32 0 r1
+ mov #0x3,r1
+ mov #0x4,r2
+ maclo r1,r2
+ mvfacmi r1
+ test_h_gr32 0x12 r1
+ mvfachi r1
+ test_h_gr32 0 r1
+ .if cpu == 2
+ sub r1,r1
+ mvtachi r1,a1
+ mvtaclo r1,a1
+ mvtacgu r1,a1
+ mov #0x20000,r1
+ mov #0x30000,r2
+ machi r1,r2,a1
+ mvfacmi #0,a1,r1
+ test_h_gr32 6 r1
+ mvfachi #0,a1,r1
+ test_h_gr32 0 r1
+ mov #0x3,r1
+ mov #0x4,r2
+ maclo r1,r2,a1
+ mvfacmi #0,a1,r1
+ test_h_gr32 0x12 r1
+ mvfachi #0,a1,r1
+ test_h_gr32 0 r1
+ mov #0x4,r1
+ mov #0x50000,r2
+ maclh r1,r2,a1
+ mvfacmi #0,a1,r1
+ test_h_gr32 0x26 r1
+ mvfachi #0,a1,r1
+ test_h_gr32 0 r1
+ .endif
+ pass
diff --git a/sim/testsuite/sim/rx/max.s b/sim/testsuite/sim/rx/max.s
new file mode 100644
index 0000000..aa17928
--- /dev/null
+++ b/sim/testsuite/sim/rx/max.s
@@ -0,0 +1,45 @@
+# RX testcase for max
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+max_imm8:
+ mov #2,r1
+ max #1,r1
+ test_h_gr32 2 r1
+max_imm16:
+ mov #0x8000,r1
+ max #0x1000,r1
+ test_h_gr32 0x8000 r1
+max_imm24:
+ mov #0x100000,r1
+ max #0x200000,r1
+ test_h_gr32 0x200000 r1
+max_imm32:
+ mov #0x80000000,r1
+ max #0x40000000,r1
+ test_h_gr32 0x40000000 r1
+max_reg:
+ mov #0x80000000,r2
+ max r2,r1
+ test_h_gr32 0x40000000 r1
+max_mem_ind:
+ mov #10,r1
+ mov #val, r2
+ max [r2],r1
+ test_h_gr32 10 r1
+max_mem_dsp8:
+ mov #val-4, r2
+ max 4[r2],r1
+ test_h_gr32 10 r1
+max_mem_dsp16:
+ mov #val-0x1000, r2
+ max 0x1000[r2],r1
+ test_h_gr32 10 r1
+
+ pass
+
+ .data
+val: .long 2
diff --git a/sim/testsuite/sim/rx/min.s b/sim/testsuite/sim/rx/min.s
new file mode 100644
index 0000000..53f97c4
--- /dev/null
+++ b/sim/testsuite/sim/rx/min.s
@@ -0,0 +1,45 @@
+# RX testcase for min
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+min_imm8:
+ mov #2,r1
+ min #1,r1
+ test_h_gr32 1 r1
+min_imm16:
+ mov #0x8000,r1
+ min #0x1000,r1
+ test_h_gr32 0x1000 r1
+min_imm24:
+ mov #0x100000,r1
+ min #0x200000,r1
+ test_h_gr32 0x100000 r1
+min_imm32:
+ mov #0x80000000,r1
+ min #0x40000000,r1
+ test_h_gr32 0x80000000 r1
+min_reg:
+ mov #0x80000000,r2
+ min r2,r1
+ test_h_gr32 0x80000000 r1
+min_mem_ind:
+ mov #2,r1
+ mov #val, r2
+ min [r2],r1
+ test_h_gr32 2 r1
+min_mem_dsp8:
+ mov #val-4, r2
+ min 4[r2],r1
+ test_h_gr32 2 r1
+min_mem_dsp16:
+ mov #val-0x1000, r2
+ min 0x1000[r2],r1
+ test_h_gr32 2 r1
+
+ pass
+
+ .data
+val: .long 10
diff --git a/sim/testsuite/sim/rx/mov.s b/sim/testsuite/sim/rx/mov.s
new file mode 100644
index 0000000..9dd45f4
--- /dev/null
+++ b/sim/testsuite/sim/rx/mov.s
@@ -0,0 +1,196 @@
+# RX testcase for mov
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ set_gr_a5a5 1
+ mov #val,r2
+ mov.b r1,[r2]
+ mov.w r1,2[r2]
+ mov.l r1,4[r2]
+ mov.b [r2],r1
+ test_h_gr32 0xffffffa5 r1
+ mov.w 2[r2],r1
+ test_h_gr32 0xffffa5a5 r1
+ mov.l 4[r2],r1
+ test_h_gr32 0xa5a5a5a5 r1
+ mov #1,r1
+ test_h_gr32 1 r1
+ mov.b #0x01,[r2]
+ mov.w #0x23,2[r2]
+ mov.l #0x45,4[r2]
+ mov.b [r2],r1
+ test_h_gr32 0x01 r1
+ mov.w 2[r2],r1
+ test_h_gr32 0x23 r1
+ mov.l 4[r2],r1
+ test_h_gr32 0x45 r1
+ mov #0x10,r1
+ test_h_gr32 0x10 r1
+ mov #0x80,r1
+ test_h_gr32 0x80 r1
+ mov #0x8000,r1
+ test_h_gr32 0x8000 r1
+ mov #0x800000,r1
+ test_h_gr32 0x800000 r1
+ mov #0x80000000,r1
+ test_h_gr32 0x80000000 r1
+ mov #0x80,r1
+ mov.b r1,r2
+ test_h_gr32 0xffffff80 r2
+ mov #0x8000,r1
+ mov.w r1,r2
+ test_h_gr32 0xffff8000 r2
+ mov #0x80000000,r1
+ mov.l r1,r2
+ test_h_gr32 0x80000000 r2
+ mov.l #val,r2
+ mov.l #val-4,r3
+ mov.l #val-0x1000,r4
+ mov.b #0x01,[r2]
+ mov.b [r2],r1
+ test_h_gr32 0x01 r1
+ mov.b #0x23,4[r3]
+ mov.b [r2],r1
+ test_h_gr32 0x23 r1
+ mov.b #0x45,0x1000[r4]
+ mov.b [r2],r1
+ test_h_gr32 0x45 r1
+ mov.w #0x80,[r2]
+ mov.w [r2],r1
+ test_h_gr32 0x80 r1
+ mov.w #0x80,4[r3]
+ mov.w [r2],r1
+ test_h_gr32 0x80 r1
+ mov.w #0x80,0x1000[r4]
+ mov.w [r2],r1
+ test_h_gr32 0x80 r1
+ mov.w #0x1234,[r2]
+ mov.w [r2],r1
+ test_h_gr32 0x1234 r1
+ mov.w #0x4567,4[r3]
+ mov.w [r2],r1
+ test_h_gr32 0x4567 r1
+ mov.w #0x89ab,0x1000[r4]
+ mov.w [r2],r1
+ test_h_gr32 0xffff89ab r1
+ mov.l #0x123456,[r2]
+ mov.l [r2],r1
+ test_h_gr32 0x123456 r1
+ mov.l #0x456789,4[r3]
+ mov.l [r2],r1
+ test_h_gr32 0x456789 r1
+ mov.l #0x89abcd,0x1000[r4]
+ mov.l [r2],r1
+ test_h_gr32 0x89abcd r1
+ mov.l #0x12345678,[r2]
+ mov.l [r2],r1
+ test_h_gr32 0x12345678 r1
+ mov.l #0x89abcdef,4[r3]
+ mov.l [r2],r1
+ test_h_gr32 0x89abcdef r1
+ mov.l #0x76543210,0x1000[r4]
+ mov.l [r2],r1
+ test_h_gr32 0x876543210 r1
+ mov #4,r1
+ mov.b r1,[r1,r3]
+ mov.b [r2],r1
+ test_h_gr32 4 r1
+ mov #2,r1
+ mov.w r1,[r1,r3]
+ mov.w [r2],r1
+ test_h_gr32 2 r1
+ mov #0x1000/4,r1
+ mov.l r1,[r1,r4]
+ mov.l [r2],r1
+ test_h_gr32 0x1000/4 r1
+ mov #val+4,r5
+ mov.b #0x12,[r2]
+ mov.b [r2],[r5]
+ mov.b [r5],r1
+ test_h_gr32 0x12 r1
+ mov.w #0x1234,[r2]
+ mov.w [r2],[r5]
+ mov.w [r5],r1
+ test_h_gr32 0x1234 r1
+ mov.l #0x12345678,[r2]
+ mov.l [r2],[r5]
+ mov.l [r5],r1
+ test_h_gr32 0x12345678 r1
+ mov.b #0x12,[r2]
+ mov.b [r2],8[r3]
+ mov.b 8[r3],r1
+ test_h_gr32 0x12 r1
+ mov.w #0x1234,[r2]
+ mov.w [r2],8[r3]
+ mov.w 8[r3],r1
+ test_h_gr32 0x1234 r1
+ mov.l #0x12345678,[r2]
+ mov.l [r2],8[r3]
+ mov.l 8[r3],r1
+ test_h_gr32 0x12345678 r1
+ mov.b #0x12,[r2]
+ mov.b [r2],0x1004[r4]
+ mov.b 0x1004[r4],r1
+ test_h_gr32 0x12 r1
+ mov.w #0x1234,[r2]
+ mov.w [r2],0x1004[r4]
+ mov.w 0x1004[r4],r1
+ test_h_gr32 0x1234 r1
+ mov.l #0x12345678,[r2]
+ mov.l [r2],0x1004[r4]
+ mov.l 0x1004[r4],r1
+ test_h_gr32 0x12345678 r1
+ mov.b #0x12,[r2]
+ mov.b 4[r3],0x1004[r4]
+ mov.b 0x1004[r4],r1
+ test_h_gr32 0x12 r1
+ mov.w #0x1234,[r2]
+ mov.w 4[r3],0x1004[r4]
+ mov.w 0x1004[r4],r1
+ test_h_gr32 0x1234 r1
+ mov.l #0x12345678,[r2]
+ mov.l 4[r3],0x1004[r4]
+ mov.l 0x1004[r4],r1
+ test_h_gr32 0x12345678 r1
+ mov.b #0x12,[r2]
+ mov.b 0x1000[r4],4[r3]
+ mov.b 4[r3],r1
+ test_h_gr32 0x12 r1
+ mov.w #0x1234,[r2]
+ mov.w 0x1000[r4],4[r3]
+ mov.w 4[r3],r1
+ test_h_gr32 0x1234 r1
+ mov.l #0x12345678,[r2]
+ mov.l 0x1000[r4],4[r3]
+ mov.l 4[r3],r1
+ test_h_gr32 0x12345678 r1
+ mov #val+9,r1
+ mov #0x12345678,r2
+ mov.l r2,[-r1]
+ mov.w r2,[-r1]
+ mov.b r2,[-r1]
+ mov.b [r1+],r2
+ test_h_gr32 0x78 r2
+ mov.w [r1+],r2
+ test_h_gr32 0x5678 r2
+ mov.l [r1+],r2
+ test_h_gr32 0x12345678 r2
+ mov #val,r1
+ mov #0x12345678,r2
+ mov.l r2,[r1+]
+ mov.w r2,[r1+]
+ mov.b r2,[r1+]
+ mov.b [-r1],r2
+ test_h_gr32 0x78 r2
+ mov.w [-r1],r2
+ test_h_gr32 0x5678 r2
+ mov.l [-r1],r2
+ test_h_gr32 0x12345678 r2
+
+ pass
+
+ .data
+val: .space 16
diff --git a/sim/testsuite/sim/rx/movlico.s b/sim/testsuite/sim/rx/movlico.s
new file mode 100644
index 0000000..3c9c8fe
--- /dev/null
+++ b/sim/testsuite/sim/rx/movlico.s
@@ -0,0 +1,22 @@
+# RX testcase for add
+# mach: rxv2
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+ mov.l #0x12345678,r1
+ mov.l #val,r2
+ movco r1,[r2]
+ test_h_gr32 1 r1
+ movli [r2],r1
+ mov #0x5a5a5a5a,r1
+ movco r1,[r2]
+ test_h_gr32 0 r1
+ mov.l [r2],r1
+ test_h_gr32 0x5a5a5a5a r1
+
+ pass
+
+ .data
+val: .long 0xa5a5a5a5
diff --git a/sim/testsuite/sim/rx/movu.s b/sim/testsuite/sim/rx/movu.s
new file mode 100644
index 0000000..5289c94
--- /dev/null
+++ b/sim/testsuite/sim/rx/movu.s
@@ -0,0 +1,67 @@
+# RX testcase for movu
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ set_gr_a5a5 1
+ mov #valb,r2
+ movu.b [r2],r1
+ test_h_gr32 0x80 r1
+ mov #valw,r2
+ movu.w [r2],r1
+ test_h_gr32 0x8000 r1
+ mov #0x8888,r2
+ movu.b r2,r1
+ test_h_gr32 0x88 r1
+ movu.w r2,r1
+ test_h_gr32 0x8888 r1
+ mov #valb,r2
+ movu.b [r2],r10
+ test_h_gr32 0x80 r10
+ mov #valb-0x40,r2
+ movu.b 0x40[r2],r10
+ test_h_gr32 0x80 r10
+ mov #valb-0x1000,r2
+ movu.b 0x1000[r2],r10
+ test_h_gr32 0x80 r10
+ mov #valb-0x1000,r2
+ mov #0x1000,r3
+ movu.b [r3,r2],r10
+ test_h_gr32 0x80 r10
+ mov #valw,r2
+ movu.w [r2],r10
+ test_h_gr32 0x8000 r10
+ mov #valw-0x40,r2
+ movu.w 0x40[r2],r10
+ test_h_gr32 0x8000 r10
+ mov #valw-0x1000,r2
+ movu.w 0x1000[r2],r10
+ test_h_gr32 0x8000 r10
+ mov #valw-0x1000,r2
+ mov #0x1000/2,r3
+ movu.w [r3,r2],r10
+ test_h_gr32 0x8000 r10
+ mov #valb,r2
+ movu.b [r2+],r1
+ test_h_gr32 0x80 r1
+ test_h_gr32 valb+1 r2
+ mov #valw,r2
+ movu.w [r2+],r1
+ test_h_gr32 0x8000 r1
+ test_h_gr32 valw+2 r2
+ mov #valb+1,r2
+ movu.b [-r2],r1
+ test_h_gr32 0x80 r1
+ test_h_gr32 valb r2
+ mov #valw+2,r2
+ movu.w [-r2],r1
+ test_h_gr32 0x8000 r1
+ test_h_gr32 valw r2
+
+ pass
+
+ .data
+valw: .word 0x8000
+valb: .byte 0x80
diff --git a/sim/testsuite/sim/rx/msbhilo.s b/sim/testsuite/sim/rx/msbhilo.s
new file mode 100644
index 0000000..3a21981
--- /dev/null
+++ b/sim/testsuite/sim/rx/msbhilo.s
@@ -0,0 +1,43 @@
+# RX testcase for add
+# mach: rxv2
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+ mov #0x20000,r1
+ mov #0x30000,r2
+ msbhi r1,r2,a0
+ mvfacmi r1
+ test_h_gr32 -6 r1
+ mvfachi r1
+ test_h_gr32 -1 r1
+ mov #0x3,r1
+ mov #0x4,r2
+ msblo r1,r2,a0
+ mvfacmi r1
+ test_h_gr32 -18 r1
+ mvfachi r1
+ test_h_gr32 -1 r1
+ mov #0x20000,r1
+ mov #0x30000,r2
+ msbhi r1,r2,a1
+ mvfacmi #0,a1,r1
+ test_h_gr32 -6 r1
+ mvfachi #0,a1,r1
+ test_h_gr32 -1 r1
+ mov #0x3,r1
+ mov #0x4,r2
+ msblo r1,r2,a1
+ mvfacmi #0,a1,r1
+ test_h_gr32 -18 r1
+ mvfachi #0,a1,r1
+ test_h_gr32 -1 r1
+ mov #0x4,r1
+ mov #0x50000,r2
+ msblh r1,r2,a1
+ mvfacmi #0,a1,r1
+ test_h_gr32 -38 r1
+ mvfachi #0,a1,r1
+ test_h_gr32 -1 r1
+ pass
diff --git a/sim/testsuite/sim/rx/mul.s b/sim/testsuite/sim/rx/mul.s
new file mode 100644
index 0000000..979acd7
--- /dev/null
+++ b/sim/testsuite/sim/rx/mul.s
@@ -0,0 +1,52 @@
+# RX testcase for mul
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+mul_imm4:
+ mov.l #3,r1
+ mul #3,r1
+ test_h_gr32 9 r1
+mul_imm8:
+ mul #20,r1
+ test_h_gr32 180 r1
+mul_imm16:
+ mul #1000,r1
+ test_h_gr32 180000 r1
+mul_imm24:
+ mov.l #3,r1
+ mul #0x10000,r1
+ test_h_gr32 0x30000 r1
+mul_imm32:
+ mov.l #3,r1
+ mul #0x1000000,r1
+ test_h_gr32 0x3000000 r1
+mul_reg:
+ mov #5, r1
+ mov r1,r2
+ mul r2,r1
+ test_h_gr32 25 r1
+mul_mem_ind:
+ mov.l #val, r2
+ mul [r2].l,r1
+ test_h_gr32 50 r1
+mul_mem_dsp8:
+ mov.l #val-4, r2
+ mul 4[r2].l,r1
+ test_h_gr32 100 r1
+mul_mem_dsp16:
+ mov.l #val-0x1000, r2
+ mul 0x1000[r2].l,r1
+ test_h_gr32 200 r1
+mul3_reg:
+ mov #6, r1
+ mov r1,r2
+ mul r1,r2,r3
+ test_h_gr32 36 r3
+
+ pass
+
+ .data
+val: .long 2
diff --git a/sim/testsuite/sim/rx/mulhilo.s b/sim/testsuite/sim/rx/mulhilo.s
new file mode 100644
index 0000000..083d10c
--- /dev/null
+++ b/sim/testsuite/sim/rx/mulhilo.s
@@ -0,0 +1,54 @@
+# RX testcase for add
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names --defsym cpu=1
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+ sub r1,r1
+ mvtachi r1
+ mvtaclo r1
+ mov #0x20000,r1
+ mov #0x30000,r2
+ mulhi r1,r2
+ mvfacmi r1
+ test_h_gr32 0x6 r1
+ mvfachi r1
+ test_h_gr32 0 r1
+ mov #0x3,r1
+ mov #0x4,r2
+ mullo r1,r2
+ mvfacmi r1
+ test_h_gr32 0xc r1
+ mvfachi r1
+ test_h_gr32 0 r1
+ .if cpu == 2
+ sub r1,r1
+ mvtachi r1,a1
+ mvtaclo r1,a1
+ mvtacgu r1,a1
+ mov #0x20000,r1
+ mov #0x30000,r2
+ mulhi r1,r2,a1
+ mvfacmi #0,a1,r1
+ test_h_gr32 0x6 r1
+ mvfachi #0,a1,r1
+ test_h_gr32 0 r1
+ mov #0x3,r1
+ mov #0x4,r2
+ mullo r1,r2,a1
+ mvfacmi #0,a1,r1
+ test_h_gr32 0xc r1
+ mvfachi #0,a1,r1
+ test_h_gr32 0 r1
+ mov #0x4,r1
+ mov #0x50000,r2
+ mullh r1,r2,a1
+ mvfacmi #0,a1,r1
+ test_h_gr32 0x14 r1
+ mvfachi #0,a1,r1
+ test_h_gr32 0 r1
+ .endif
+
+ pass
diff --git a/sim/testsuite/sim/rx/mvacc.s b/sim/testsuite/sim/rx/mvacc.s
new file mode 100644
index 0000000..ac6d3f4
--- /dev/null
+++ b/sim/testsuite/sim/rx/mvacc.s
@@ -0,0 +1,28 @@
+# RX testcase for add
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names --defsym cpu=1
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+ mov #0x12345678,r1
+ mvtachi r1
+ mvtaclo r1
+ mvfacmi r1
+ test_h_gr32 0x56781234 r1
+ mvfachi r1
+ test_h_gr32 0x12345678 r1
+ .if cpu == 2
+ mvtacgu r1,a0
+ mvfacmi #1,a0,r1
+ test_h_gr32 0xacf02468 r1
+ mvfachi #2,a0,r1
+ test_h_gr32 0x48d159e0 r1
+ mvfacgu #0,a0,r1
+ test_h_gr32 0x78 r1
+ mvfaclo #0,a0,r1
+ test_h_gr32 0x12345678 r1
+ .endif
+
+ pass
diff --git a/sim/testsuite/sim/rx/mvftc.s b/sim/testsuite/sim/rx/mvftc.s
new file mode 100644
index 0000000..ed98ba8
--- /dev/null
+++ b/sim/testsuite/sim/rx/mvftc.s
@@ -0,0 +1,36 @@
+# RX testcase for mvfc/mvtc
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ mov #0x1,r1
+ mvtc r1,ISP
+ mov #0x2,r1
+ mvtc r1,USP
+ mov #0x3,r1
+ mvtc r1,INTB
+ mov #0x4,r1
+ mvtc r1,BPC
+ mov #0x5,r1
+ mvtc r1,BPSW
+ mov #0x6,r1
+ mvtc r1,FINTV
+ mvfc ISP,r1
+ test_h_gr32 1 r1
+ mvfc USP,r1
+ test_h_gr32 2 r1
+ mvfc INTB,r1
+ test_h_gr32 3 r1
+ mvfc BPC,r1
+ test_h_gr32 4 r1
+ mvfc BPSW,r1
+ test_h_gr32 5 r1
+ mvfc FINTV,r1
+ test_h_gr32 6 r1
+
+ pass
+
+ .data
+val: .long 2
diff --git a/sim/testsuite/sim/rx/neg.s b/sim/testsuite/sim/rx/neg.s
new file mode 100644
index 0000000..7eb6dbf
--- /dev/null
+++ b/sim/testsuite/sim/rx/neg.s
@@ -0,0 +1,17 @@
+# RX testcase for neg
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ mov #1,r1
+ neg r1
+ test_h_gr32 -1 r1
+ neg r1,r2
+ test_h_gr32 1 r2
+
+ pass
+
+ .data
+val: .long 2
diff --git a/sim/testsuite/sim/rx/not.s b/sim/testsuite/sim/rx/not.s
new file mode 100644
index 0000000..f78203a
--- /dev/null
+++ b/sim/testsuite/sim/rx/not.s
@@ -0,0 +1,17 @@
+# RX testcase for not
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ mov #1,r1
+ not r1
+ test_h_gr32 0xfffffffe r1
+ not r1,r2
+ test_h_gr32 1 r2
+
+ pass
+
+ .data
+val: .long 2
diff --git a/sim/testsuite/sim/rx/or.s b/sim/testsuite/sim/rx/or.s
new file mode 100644
index 0000000..1fdd286
--- /dev/null
+++ b/sim/testsuite/sim/rx/or.s
@@ -0,0 +1,69 @@
+# RX testcase for or
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+or_imm4:
+ mov #2,r1
+ or #1,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 3 r1
+or_imm8:
+ or #0x10,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x13 r1
+or_imm16:
+ or #0x1000,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x1013 r1
+or_imm24:
+ or #0x100000,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x101013 r1
+or_imm32:
+ or #0x10000000,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x10101013 r1
+or_reg:
+ mov.l #0x20000000,r2
+ or r2,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x30101013 r1
+or_mem_ind:
+ mov #val, r2
+ or [r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x3010101b r1
+or_mem_dsp8:
+ mov #val-4, r2
+ or 4[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x3010101b r1
+or_mem_dsp16:
+ sub r1,r1
+ mov #val-0x1000, r2
+ or 0x1000[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 8 r1
+or3_reg:
+ mov.l #0x80000000,r2
+ or r2,r1,r3
+ test_zero_clear
+ test_neg_set
+ test_h_gr32 0x80000008 r3
+
+ pass
+
+ .data
+val: .long 8
diff --git a/sim/testsuite/sim/rx/pushpop.s b/sim/testsuite/sim/rx/pushpop.s
new file mode 100644
index 0000000..b0d6ce2
--- /dev/null
+++ b/sim/testsuite/sim/rx/pushpop.s
@@ -0,0 +1,48 @@
+# RX testcase for push/pop
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ mov #1,r1
+ push.l r1
+ mov #val,r1
+ push [r1]
+ mov #val-4,r1
+ push 4[r1]
+ mov #val-0x1000,r1
+ push 0x1000[r1]
+ pop r4
+ pop r3
+ pop r2
+ pop r1
+ test_h_gr32 1 r1
+ test_h_gr32 2 r2
+ test_h_gr32 2 r3
+ test_h_gr32 2 r4
+ mov #123456,r1
+ mvtc r1,intb
+ pushc intb
+ popc intb
+ mvfc intb,r2
+ test_h_gr32 123456 r2
+ mov #1,r1
+ mov #2,r2
+ mov #3,r3
+ mov #4,r4
+ pushm r1-r4
+ sub r1,r1
+ sub r2,r2
+ sub r3,r3
+ sub r4,r4
+ popm r1-r4
+ test_h_gr32 1 r1
+ test_h_gr32 2 r2
+ test_h_gr32 3 r3
+ test_h_gr32 4 r4
+
+ pass
+
+ .data
+val: .long 2
diff --git a/sim/testsuite/sim/rx/racw.s b/sim/testsuite/sim/rx/racw.s
new file mode 100644
index 0000000..bae6f5a
--- /dev/null
+++ b/sim/testsuite/sim/rx/racw.s
@@ -0,0 +1,38 @@
+# RX testcase for add
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names --defsym cpu=1
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+ mov #0x40000000,r1
+ mvtaclo r1
+ sub r1,r1
+ mvtachi r1
+ racw #1
+ mvfacmi r1
+ test_h_gr32 0x10000 r1
+ mvfachi r1
+ test_h_gr32 1 r1
+ .if cpu == 2
+ mov #0x40000000,r1
+ mvtaclo r1,a1
+ sub r1,r1
+ mvtachi r1,a1
+ racw #2,a1
+ mvfacmi #0,a1,r1
+ test_h_gr32 0x10000 r1
+ mvfachi #0,a1,r1
+ test_h_gr32 1 r1
+ mov #0x80,r1
+ mvtacgu r1,a1
+ racl #1,a1
+ mvfacmi #0,a1,r1
+ test_h_gr32 0x20000 r1
+ mvfachi #0,a1,r1
+ test_h_gr32 2 r1
+ mvfacgu #0,a1,r1
+ test_h_gr32 0 r1
+ .endif
+ pass
diff --git a/sim/testsuite/sim/rx/rdacw.s b/sim/testsuite/sim/rx/rdacw.s
new file mode 100644
index 0000000..66186ed
--- /dev/null
+++ b/sim/testsuite/sim/rx/rdacw.s
@@ -0,0 +1,19 @@
+# RX testcase for rdacw
+# mach: rxv2
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+ mov.l #-1,r1
+ mvtaclo r1,a0
+ rdacw #2,a0
+ mvfacmi #0,a0,r1
+ test_h_gr32 0x30000 r1
+ mov.l #-1,r1
+ mvtaclo r1,a0
+ rdacl #2,a0
+ mvfacmi #0,a0,r1
+ test_h_gr32 0xf0000 r1
+
+ pass
diff --git a/sim/testsuite/sim/rx/rev.s b/sim/testsuite/sim/rx/rev.s
new file mode 100644
index 0000000..120cb58
--- /dev/null
+++ b/sim/testsuite/sim/rx/rev.s
@@ -0,0 +1,14 @@
+# RX testcase for revl/revw
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ mov #0x12345678,r1
+ revl r1,r2
+ test_h_gr32 0x78563412 r2
+ revw r1,r2
+ test_h_gr32 0x34127856 r2
+
+ pass
diff --git a/sim/testsuite/sim/rx/rmpa.s b/sim/testsuite/sim/rx/rmpa.s
new file mode 100644
index 0000000..e1b67cb
--- /dev/null
+++ b/sim/testsuite/sim/rx/rmpa.s
@@ -0,0 +1,23 @@
+# RX testcase for rmpa
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ sub r4,r4
+ sub r5,r5
+ sub r6,r6
+ mov #val1,r1
+ mov #val2,r2
+ mov #10,r3
+ rmpa.w
+ test_h_gr32 110 r4
+ test_h_gr32 0 r5
+ test_h_gr32 0 r6
+ pass
+
+ .data
+val1: .word 1,2,3,4,5,6,7,8,9,10
+val2: .word 10,9,8,7,6,5,4,3,2,1
+
diff --git a/sim/testsuite/sim/rx/rot.s b/sim/testsuite/sim/rx/rot.s
new file mode 100644
index 0000000..38a459f
--- /dev/null
+++ b/sim/testsuite/sim/rx/rot.s
@@ -0,0 +1,46 @@
+# RX testcase for rolc/rorc/rotl/rotr
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ clear_carry_flag
+ mov.l #0x80000000,r1
+ rolc r1
+ test_carry_set
+ test_zero_set
+ test_neg_clear
+ test_h_gr32 0 r1
+ clear_carry_flag
+ rorc r1
+ test_carry_clear
+ test_zero_set
+ test_neg_clear
+ test_h_gr32 0 r1
+ mov.l #0x80000000,r1
+ rotl #1,r1
+ test_carry_set
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 1 r1
+ mov #1,r2
+ rotl r2,r1
+ test_carry_clear
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2 r1
+ rotr #1,r1
+ test_carry_clear
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 1 r1
+ rotr r2,r1
+ test_carry_set
+ test_zero_clear
+ test_neg_set
+ test_h_gr32 0x80000000 r1
+ pass
+
+ .data
+val: .long 2
diff --git a/sim/testsuite/sim/rx/round.s b/sim/testsuite/sim/rx/round.s
new file mode 100644
index 0000000..cef2e24
--- /dev/null
+++ b/sim/testsuite/sim/rx/round.s
@@ -0,0 +1,37 @@
+# RX testcase for round
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+round_reg:
+ mov.l #12.68,r2
+ round r2,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 13 r1
+round_mem_ind:
+ mov.l #val, r2
+ round [r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2 r1
+round_mem_dsp8:
+ mov.l #val-4, r2
+ round 4[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2 r1
+round_mem_dsp16:
+ mov.l #val-0x1000, r2
+ round 0x1000[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2 r1
+
+ pass
+
+ .data
+val: .float 2.345
+
diff --git a/sim/testsuite/sim/rx/sat.s b/sim/testsuite/sim/rx/sat.s
new file mode 100644
index 0000000..3dc38ed
--- /dev/null
+++ b/sim/testsuite/sim/rx/sat.s
@@ -0,0 +1,37 @@
+# RX testcase for fadd
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names --defsym cpu=1
+
+ .include "testutils.inc"
+
+ start
+sat: sub r1,r1
+ sub r4,r4
+ sub r5,r5
+ sub r6,r6
+ clear_overflow_flag
+ sat r1
+ satr
+ test_h_gr32 0 r1
+ test_h_gr32 0 r6
+ test_h_gr32 0 r5
+ test_h_gr32 0 r4
+
+ set_overflow_flag
+ clear_neg_flag
+ sat r1
+ satr
+ test_h_gr32 0x80000000 r1
+ test_h_gr32 0 r6
+ test_h_gr32 0x7fffffff r5
+ test_h_gr32 0xffffffff r4
+ set_overflow_flag
+ set_neg_flag
+ sat r1
+ satr
+ test_h_gr32 0x7fffffff r1
+ test_h_gr32 0xffffffff r6
+ test_h_gr32 0x80000000 r5
+ test_h_gr32 0x00000000 r4
+
+ pass
diff --git a/sim/testsuite/sim/rx/sbb.s b/sim/testsuite/sim/rx/sbb.s
new file mode 100644
index 0000000..0316508
--- /dev/null
+++ b/sim/testsuite/sim/rx/sbb.s
@@ -0,0 +1,46 @@
+# RX testcase for sbb
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+sbb_reg:
+ clear_carry_flag
+ mov.l #2,r1
+ mov.l #1,r2
+ sbb r2,r1
+ test_zero_set
+ test_carry_set
+ test_neg_clear
+ test_overflow_clear
+ test_h_gr32 0 r1
+sbb_mem_ind:
+ mov.l #val, r2
+ sbb [r2].l,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_set
+ test_overflow_clear
+ test_h_gr32 -1 r1
+sbb_mem_dsp8:
+ mov.l #val-4, r2
+ sbb 4[r2].l,r1
+ test_zero_clear
+ test_carry_set
+ test_neg_set
+ test_overflow_clear
+ test_h_gr32 -2 r1
+sbb_mem_dsp16:
+ mov.l #val-0x1000, r2
+ sbb 0x1000[r2].l,r1
+ test_zero_clear
+ test_carry_set
+ test_neg_set
+ test_overflow_clear
+ test_h_gr32 -3 r1
+
+ pass
+
+ .data
+val: .long 1
diff --git a/sim/testsuite/sim/rx/sccnd.s b/sim/testsuite/sim/rx/sccnd.s
new file mode 100644
index 0000000..686e3cb
--- /dev/null
+++ b/sim/testsuite/sim/rx/sccnd.s
@@ -0,0 +1,169 @@
+# RX testcase for SCcnd
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ mov #val,r2
+ mov #val-4,r3
+ mov #val-0x1000,r4
+ mov #10,r1
+ cmp #5,r1
+ scc.b [r2]
+ scc.b 5[r3]
+ scc.b 0x1002[r4]
+ scc.l r5
+ test_h_gr32 1 r5
+ mov.b [r2],r5
+ test_h_gr32 1 r5
+ mov.b 1[r2],r5
+ test_h_gr32 1 r5
+ mov.b 2[r2],r5
+ test_h_gr32 1 r5
+ mov.b #0,[r2]
+ cmp #15,r1
+ scnc.b [r2]
+ scnc.b 5[r3]
+ scnc.b 0x1002[r4]
+ scnc.l r5
+ test_h_gr32 1 r5
+ mov.b [r2],r5
+ test_h_gr32 1 r5
+ mov.b 1[r2],r5
+ test_h_gr32 1 r5
+ mov.b 2[r2],r5
+ test_h_gr32 1 r5
+ mov #-5,r1
+ cmp #-10,r1
+ scgt.b [r2]
+ scgt.b 5[r3]
+ scgt.b 0x1002[r4]
+ scgt.l r5
+ test_h_gr32 1 r5
+ mov.b [r2],r5
+ test_h_gr32 1 r5
+ mov.b 1[r2],r5
+ test_h_gr32 1 r5
+ mov.b 2[r2],r5
+ test_h_gr32 1 r5
+ mov #-5,r1
+ cmp #-5,r1
+ scle.b [r2]
+ scle.b 5[r3]
+ scle.b 0x1002[r4]
+ scle.l r5
+ test_h_gr32 1 r5
+ mov.b [r2],r5
+ test_h_gr32 1 r5
+ mov.b 1[r2],r5
+ test_h_gr32 1 r5
+ mov.b 2[r2],r5
+ test_h_gr32 1 r5
+ mov #-5,r1
+ cmp #-5,r1
+ scge.b [r2]
+ scge.b 5[r3]
+ scge.b 0x1002[r4]
+ scge.l r5
+ test_h_gr32 1 r5
+ mov.b [r2],r5
+ test_h_gr32 1 r5
+ mov.b 1[r2],r5
+ test_h_gr32 1 r5
+ mov.b 2[r2],r5
+ test_h_gr32 1 r5
+ mov #-5,r1
+ cmp #-1,r1
+ sclt.b [r2]
+ sclt.b 5[r3]
+ sclt.b 0x1002[r4]
+ sclt.l r5
+ test_h_gr32 1 r5
+ mov.b [r2],r5
+ test_h_gr32 1 r5
+ mov.b 1[r2],r5
+ test_h_gr32 1 r5
+ mov.b 2[r2],r5
+ test_h_gr32 1 r5
+ mov.l #0xc0000000,r1
+ cmp #0x80000000,r1
+ scgtu.b [r2]
+ scgtu.b 5[r3]
+ scgtu.b 0x1002[r4]
+ scgtu.l r5
+ test_h_gr32 1 r5
+ mov.b [r2],r5
+ test_h_gr32 1 r5
+ mov.b 1[r2],r5
+ test_h_gr32 1 r5
+ mov.b 2[r2],r5
+ test_h_gr32 1 r5
+ mov.l #0xc0000000,r1
+ cmp #0xc0000000,r1
+ scle.b [r2]
+ scle.b 5[r3]
+ scle.b 0x1002[r4]
+ scle.l r5
+ test_h_gr32 1 r5
+ mov.b [r2],r5
+ test_h_gr32 1 r5
+ mov.b 1[r2],r5
+ test_h_gr32 1 r5
+ mov.b 2[r2],r5
+ test_h_gr32 1 r5
+ mov #1,r1
+ tst r1,r1
+ scpz.b [r2]
+ scpz.b 5[r3]
+ scpz.b 0x1002[r4]
+ scpz.l r5
+ test_h_gr32 1 r5
+ mov.b [r2],r5
+ test_h_gr32 1 r5
+ mov.b 1[r2],r5
+ test_h_gr32 1 r5
+ mov.b 2[r2],r5
+ test_h_gr32 1 r5
+ mov #-1,r1
+ tst r1,r1
+ scn.b [r2]
+ scn.b 5[r3]
+ scn.b 0x1002[r4]
+ scn.l r5
+ test_h_gr32 1 r5
+ mov.b [r2],r5
+ test_h_gr32 1 r5
+ mov.b 1[r2],r5
+ test_h_gr32 1 r5
+ mov.b 2[r2],r5
+ test_h_gr32 1 r5
+ set_overflow_flag
+ sco.b [r2]
+ sco.b 5[r3]
+ sco.b 0x1002[r4]
+ sco.l r5
+ test_h_gr32 1 r5
+ mov.b [r2],r5
+ test_h_gr32 1 r5
+ mov.b 1[r2],r5
+ test_h_gr32 1 r5
+ mov.b 2[r2],r5
+ test_h_gr32 1 r5
+ clear_overflow_flag
+ scno.b [r2]
+ scno.b 5[r3]
+ scno.b 0x1002[r4]
+ scno.l r5
+ test_h_gr32 1 r5
+ mov.b [r2],r5
+ test_h_gr32 1 r5
+ mov.b 1[r2],r5
+ test_h_gr32 1 r5
+ mov.b 2[r2],r5
+ test_h_gr32 1 r5
+
+ pass
+
+ .data
+val: .space 8
diff --git a/sim/testsuite/sim/rx/scmpu.s b/sim/testsuite/sim/rx/scmpu.s
new file mode 100644
index 0000000..01c614e
--- /dev/null
+++ b/sim/testsuite/sim/rx/scmpu.s
@@ -0,0 +1,26 @@
+# RX testcase for scmpu
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ mov #str1,r1
+ mov #str1_ok,r2
+ mov #128,r3
+ scmpu
+ test_zero_set
+ test_carry_set
+ mov #str1,r1
+ mov #str1_ng,r2
+ mov #128,r3
+ scmpu
+ test_zero_clear
+ test_carry_set
+
+ pass
+
+ .data
+str1: .asciz "abcdefghijklmnopqrstuvwxyz"
+str1_ok: .asciz "abcdefghijklmnopqrstuvwxyz"
+str1_ng: .asciz "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
diff --git a/sim/testsuite/sim/rx/shlr.s b/sim/testsuite/sim/rx/shlr.s
new file mode 100644
index 0000000..e329af5
--- /dev/null
+++ b/sim/testsuite/sim/rx/shlr.s
@@ -0,0 +1,67 @@
+# RX testcase for SCcnd
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ mov #0x80000000,r1
+ shar #1,r1
+ test_carry_clear
+ test_zero_clear
+ test_neg_set
+ test_overflow_clear
+ test_h_gr32 0xc0000000 r1
+ mov #1,r2
+ shar r2,r1
+ test_carry_clear
+ test_zero_clear
+ test_neg_set
+ test_overflow_clear
+ test_h_gr32 0xe0000000 r1
+ shar #1,r1,r2
+ test_carry_clear
+ test_zero_clear
+ test_neg_set
+ test_overflow_clear
+ test_h_gr32 0xf0000000 r2
+ shll #1,r1
+ test_carry_set
+ test_zero_clear
+ test_neg_set
+ test_overflow_clear
+ test_h_gr32 0xc0000000 r1
+ mov #1,r2
+ shll r2,r1
+ test_carry_set
+ test_zero_clear
+ test_neg_set
+ test_overflow_clear
+ test_h_gr32 0x80000000 r1
+ shll #1,r1,r2
+ test_carry_set
+ test_zero_set
+ test_neg_clear
+ test_overflow_set
+ test_h_gr32 0x00000000 r2
+ mov #0xaaaaaaaa,r1
+ shlr #1,r1
+ test_carry_clear
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x55555555 r1
+ mov #1,r2
+ shlr r2,r1
+ test_carry_set
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x2aaaaaaa r1
+ shlr #1,r1,r2
+ test_carry_clear
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x15555555 r2
+
+ pass
+
+ .data
diff --git a/sim/testsuite/sim/rx/smovb.s b/sim/testsuite/sim/rx/smovb.s
new file mode 100644
index 0000000..26226df
--- /dev/null
+++ b/sim/testsuite/sim/rx/smovb.s
@@ -0,0 +1,53 @@
+# RX testcase for smovb
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ mov #src+127,r2
+ mov #dst+127,r1
+ mov #128,r3
+ smovb
+ add #1,r1
+ add #1,r2
+ mov #128,r3
+1: mov.b [r1],r4
+ cmp [r2].b,r4
+ bne __fail
+ mov.b #0,[r1]
+ add #1,r1
+ add #1,r2
+ sub #1,r3
+ bpz 1b
+ mov #src,r2
+ mov #dst,r1
+ mov #128,r3
+ smovf
+ mov #128,r3
+ mov #src,r2
+ mov #dst,r1
+1: mov.b [r1],r4
+ cmp [r2].b,r4
+ bne __fail
+ mov.b #0,[r1]
+ add #1,r1
+ add #1,r2
+ sub #1,r3
+ bpz 1b
+
+ pass
+__fail:
+ fail
+ exit 1
+
+ .data
+src:
+ data = 0
+ .rept 128
+ .byte data
+ data = data + 1
+ .endr
+dst:
+ .space 128
+
diff --git a/sim/testsuite/sim/rx/smovu.s b/sim/testsuite/sim/rx/smovu.s
new file mode 100644
index 0000000..a715918
--- /dev/null
+++ b/sim/testsuite/sim/rx/smovu.s
@@ -0,0 +1,23 @@
+# RX testcase for smovu
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ mov #str1,r2
+ mov #str1_dst,r1
+ mov #128,r3
+ smovu
+ mov #str1,r2
+ mov #str1_dst,r1
+ mov #128,r3
+ scmpu
+ test_zero_set
+
+ pass
+
+ .data
+str1: .asciz "abcdefghijklmnopqrstuvwxyz"
+str1_dst:
+ .space 27
diff --git a/sim/testsuite/sim/rx/sstr.s b/sim/testsuite/sim/rx/sstr.s
new file mode 100644
index 0000000..1ef0737
--- /dev/null
+++ b/sim/testsuite/sim/rx/sstr.s
@@ -0,0 +1,44 @@
+# RX testcase for sstr
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ mov #0x12345678,r2
+ mov #dst,r1
+ mov #128,r3
+ sstr.b
+ mov #128,r3
+ mov #dst,r1
+1: mov.b [r1+],r2
+ test_h_gr32 0x78 r2
+ sub #1,r3
+ bne 1b
+ mov #0x12345678,r2
+ mov #dst,r1
+ mov #128/2,r3
+ sstr.w
+ mov #128/2,r3
+ mov #dst,r1
+1: mov.w [r1+],r2
+ test_h_gr32 0x5678 r2
+ sub #1,r3
+ bne 1b
+ mov #0x12345678,r2
+ mov #dst,r1
+ mov #128/4,r3
+ sstr.l
+ mov #128/4,r3
+ mov #dst,r1
+1: mov.l [r1+],r2
+ test_h_gr32 0x12345678 r2
+ sub #1,r3
+ bne 1b
+
+ pass
+
+ .data
+dst:
+ .space 128
+
diff --git a/sim/testsuite/sim/rx/stz.s b/sim/testsuite/sim/rx/stz.s
new file mode 100644
index 0000000..a808c78
--- /dev/null
+++ b/sim/testsuite/sim/rx/stz.s
@@ -0,0 +1,52 @@
+# RX testcase for sstr
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names --defsym cpu=1
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+ clear_zero_flag
+ stnz #1, r1
+ stnz #0x100, r2
+ stnz #0x10000, r3
+ stnz #0x1000000, r4
+ stz #2, r1
+ stz #0x200, r2
+ stz #0x20000, r3
+ stz #0x2000000, r4
+ test_h_gr32 1 r1
+ test_h_gr32 0x100 r2
+ test_h_gr32 0x10000 r3
+ test_h_gr32 0x1000000 r4
+ set_zero_flag
+ stnz #1, r1
+ stnz #0x100, r2
+ stnz #0x10000, r3
+ stnz #0x1000000, r4
+ stz #2, r1
+ stz #0x200, r2
+ stz #0x20000, r3
+ stz #0x2000000, r4
+ test_h_gr32 2 r1
+ test_h_gr32 0x200 r2
+ test_h_gr32 0x20000 r3
+ test_h_gr32 0x2000000 r4
+
+ .if cpu == 2
+ mov #1,r1
+ mov #2,r2
+ clear_zero_flag
+ stz r2,r1
+ test_h_gr32 1 r1
+ clear_zero_flag
+ stnz r2,r1
+ test_h_gr32 2 r1
+ .endif
+
+ pass
+
+ .data
+dst:
+ .space 128
+
diff --git a/sim/testsuite/sim/rx/sub.s b/sim/testsuite/sim/rx/sub.s
new file mode 100644
index 0000000..cbc6d18
--- /dev/null
+++ b/sim/testsuite/sim/rx/sub.s
@@ -0,0 +1,53 @@
+# RX testcase for sub
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+sub_imm4:
+ mov.l #2,r1
+ sub #1,r1
+ test_zero_clear
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 1 r1
+sub_reg:
+ mov.l #1,r2
+ sub r2,r1
+ test_zero_set
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 0 r1
+sub_mem_ind:
+ mov.l #val, r2
+ sub [r2].l,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_set
+ test_h_gr32 -1 r1
+sub_mem_dsp8:
+ mov.l #val-4, r2
+ sub 4[r2].l,r1
+ test_zero_clear
+ test_carry_set
+ test_neg_set
+ test_h_gr32 -2 r1
+sub_mem_dsp16:
+ mov.l #val-0x1000, r2
+ sub 0x1000[r2].l,r1
+ test_zero_clear
+ test_carry_set
+ test_neg_set
+ test_h_gr32 -3 r1
+sub3_reg:
+ sub r1,r1,r2
+ test_zero_set
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 0 r2
+
+ pass
+
+ .data
+val: .long 1
diff --git a/sim/testsuite/sim/rx/suntil.s b/sim/testsuite/sim/rx/suntil.s
new file mode 100644
index 0000000..79bd268
--- /dev/null
+++ b/sim/testsuite/sim/rx/suntil.s
@@ -0,0 +1,59 @@
+# RX testcase for suntil
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ mov #until,r1
+ mov #127,r2
+ mov #128,r3
+ suntil.b
+ test_zero_set
+ test_h_gr32 0 r3
+ mov #until,r1
+ mov #0x7f7e,r2
+ mov #128/2,r3
+ suntil.w
+ test_zero_set
+ test_h_gr32 0 r3
+ mov #until,r1
+ mov #0x7f7e7d7c,r2
+ mov #128/4,r3
+ suntil.l
+ test_zero_set
+ test_h_gr32 0 r3
+
+ mov #while,r1
+ mov #0,r2
+ mov #128,r3
+ swhile.b
+ test_zero_clear
+ test_h_gr32 3 r3
+ mov #while,r1
+ mov #0,r2
+ mov #128/2,r3
+ swhile.w
+ test_zero_clear
+ test_h_gr32 1 r3
+ mov #while,r1
+ mov #0,r2
+ mov #128/4,r3
+ swhile.l
+ test_zero_clear
+ test_h_gr32 0 r3
+
+ pass
+
+ .data
+until:
+ data = 0
+ .rept 128
+ .byte data
+ data = data + 1
+ .endr
+while:
+ .rept 31
+ .long 0
+ .endr
+ .long 0x01010101
diff --git a/sim/testsuite/sim/rx/testutils.inc b/sim/testsuite/sim/rx/testutils.inc
new file mode 100644
index 0000000..06977ae
--- /dev/null
+++ b/sim/testsuite/sim/rx/testutils.inc
@@ -0,0 +1,302 @@
+# Support macros for the Renesas RX assembly test cases.
+
+; Set up a minimal machine state
+ .macro start
+
+ .text
+ .align 2
+ .global _start
+_start:
+ bra _main
+
+ .data
+ .align 2
+ .global pass_str
+ .global fail_str
+ .global ok_str
+pass_str:
+ .ascii "pass\n"
+fail_str:
+ .ascii "fail\n"
+ok_str:
+ .ascii "ok\n"
+
+ .text
+ .global _write_and_exit
+_write_and_exit:
+;ssize_t write(int fd, const void *buf, size_t count);
+;Integer arguments have to be zero extended.
+ mov.l #5,r5
+ int #255
+ mov.l r4,r1
+ bra _exit
+
+ .global _exit
+_exit:
+ mov.l #1,r5
+ int #255
+
+ .global _main
+_main:
+ .endm
+
+
+; Exit with an exit code
+ .macro exit code
+ mov.l #\code, r1
+ bra _exit
+ .endm
+
+; Output "pass\n"
+ .macro pass
+ mov.l #0, r1 ; fd == stdout
+ mov.l #pass_str, r2 ; buf == "pass\n"
+ mov.l #5, r3 ; len == 5
+ sub r4,r4
+ bra _write_and_exit
+ .endm
+
+; Output "fail\n"
+ .macro fail
+ mov.l #0, r1 ; fd == stdout
+ mov.l #fail_str, r2 ; buf == "fail\n"
+ mov.l #5, r3 ; len == 5
+ mov.l #1,r4
+ bra _write_and_exit
+ .endm
+
+
+; Load an 8-bit immediate value into a general register
+; (reg must be r0l - r7l or r0h - r7h)
+ .macro mvi_h_gr8 val reg
+ mov.b #\val, \reg
+ .endm
+
+; Load a 16-bit immediate value into a general register
+; (reg must be r0 - r7)
+ .macro mvi_h_gr16 val reg
+ mov.w #\val, \reg
+ .endm
+
+; Load a 32-bit immediate value into a general register
+; (reg must be er0 - er7)
+ .macro mvi_h_gr32 val reg
+ mov.l #\val, \reg
+ .endm
+
+; Test the value of an 8-bit immediate against a general register
+; (reg must be r0l - r7l or r0h - r7h)
+ .macro test_h_gr8 val reg
+ cmp.b #\val, \reg
+ beq .Ltest_gr8\@
+ fail
+.Ltest_gr8\@:
+ .endm
+
+; Test the value of a 16-bit immediate against a general register
+; (reg must be r0 - r7)
+ .macro test_h_gr16 val reg h=h l=l
+ cmp.w #\val, \reg
+ beq .Ltest_gr16\@
+ fail
+.Ltest_gr16\@:
+ .endm
+
+; Test the value of a 32-bit immediate against a general register
+; (reg must be er0 - er7)
+ .macro test_h_gr32 val reg
+ cmp #\val, \reg
+ beq .Ltest_gr32\@
+ fail
+.Ltest_gr32\@:
+ .endm
+
+; Set a general register to the fixed pattern 'a5a5a5a5'
+ .macro set_gr_a5a5 reg
+ mov.l #0xa5a5a5a5, r\reg
+ .endm
+
+; Set all general registers to the fixed pattern 'a5a5a5a5'
+ .macro set_grs_a5a5
+ mov.l #0xa5a5a5a5, r1
+ mov.l #0xa5a5a5a5, r2
+ mov.l #0xa5a5a5a5, r3
+ mov.l #0xa5a5a5a5, r4
+ mov.l #0xa5a5a5a5, r5
+ mov.l #0xa5a5a5a5, r6
+ mov.l #0xa5a5a5a5, r7
+ mov.l #0xa5a5a5a5, r8
+ mov.l #0xa5a5a5a5, r9
+ mov.l #0xa5a5a5a5, r10
+ mov.l #0xa5a5a5a5, r11
+ mov.l #0xa5a5a5a5, r12
+ mov.l #0xa5a5a5a5, r13
+ mov.l #0xa5a5a5a5, r14
+ mov.l #0xa5a5a5a5, r15
+ .endm
+
+; Test that a general register contains the fixed pattern 'a5a5a5a5'
+ .macro test_gr_a5a5 reg
+ test_h_gr32 0xa5a5a5a5 r\reg
+ .endm
+
+; Test that all general regs contain the fixed pattern 'a5a5a5a5'
+ .macro test_grs_a5a5
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ test_gr_a5a5 8
+ test_gr_a5a5 9
+ test_gr_a5a5 10
+ test_gr_a5a5 11
+ test_gr_a5a5 12
+ test_gr_a5a5 13
+ test_gr_a5a5 14
+ test_gr_a5a5 15
+ .endm
+
+; Set condition code register to an explicit value
+ .macro set_ccr val
+ mvtc #\val, psw
+ .endm
+
+; Set all condition code flags to zero
+ .macro set_ccr_zero
+ mvtc #0, psw
+ .endm
+
+; Set carry flag true
+ .macro set_carry_flag
+ setpsw c
+ .endm
+
+; Clear carry flag
+ .macro clear_carry_flag
+ clrpsw c
+ .endm
+
+; Set zero flag true
+ .macro set_zero_flag
+ setpsw z
+ .endm
+
+; Clear zero flag
+ .macro clear_zero_flag
+ clrpsw z
+ .endm
+
+; Set sign flag true
+ .macro set_neg_flag
+ setpsw s
+ .endm
+
+; Clear sign flag
+ .macro clear_neg_flag
+ clrpsw s
+ .endm
+
+; Set overflow flag true
+ .macro set_overflow_flag
+ setpsw o
+ .endm
+
+; Clear overflow flag
+ .macro clear_overflow_flag
+ clrpsw o
+ .endm
+
+; Test that carry flag is clear
+ .macro test_carry_clear
+ bnc .Lcc\@
+ fail ; carry flag not clear
+.Lcc\@:
+ .endm
+
+; Test that carry flag is set
+ .macro test_carry_set
+ bc .Lcs\@
+ fail ; carry flag not clear
+.Lcs\@:
+ .endm
+
+; Test that overflow flag is clear
+ .macro test_ovf_clear
+ bno .Lvc\@
+ fail ; overflow flag not clear
+.Lvc\@:
+ .endm
+
+; Test that overflow flag is set
+ .macro test_ovf_set
+ bo .Lvs\@
+ fail ; overflow flag not clear
+.Lvs\@:
+ .endm
+
+; Test that zero flag is clear
+ .macro test_zero_clear
+ bne .Lne\@
+ fail ; zero flag not clear
+.Lne\@:
+ .endm
+
+; Test that zero flag is set
+ .macro test_zero_set
+ beq .Leq\@
+ fail ; zero flag not clear
+.Leq\@:
+ .endm
+
+; Test that neg flag is clear
+ .macro test_neg_clear
+ bpz .Lneg\@
+ fail ; negative flag not clear
+.Lneg\@:
+ .endm
+
+; Test that neg flag is set
+ .macro test_neg_set
+ bn .Lneg\@
+ fail ; negative flag not clear
+.Lneg\@:
+ .endm
+
+; Test that overflow flag is clear
+ .macro test_overflow_clear
+ bno .Loverflow\@
+ fail ; negative flag not clear
+.Loverflow\@:
+ .endm
+
+; Test that overflow flag is set
+ .macro test_overflow_set
+ bo .Loverflow\@
+ fail ; negative flag not clear
+.Loverflow\@:
+ .endm
+
+; Test ccr against an explicit value
+ .macro test_ccr val
+ .text
+ mov.l r1,[-r0]
+ mvfc psw, r1
+ cmp #\val, r1
+ bne .Ltcc\@
+ fail
+.Ltcc\@:
+ mov.l [r0+],r1
+ .endm
+
+; Test that all (accessable) condition codes are clear
+ .macro test_cc_clear
+ test_carry_clear
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+ ; leaves H, I, U, and UI untested
+ .endm
+
diff --git a/sim/testsuite/sim/rx/tst.s b/sim/testsuite/sim/rx/tst.s
new file mode 100644
index 0000000..7736675
--- /dev/null
+++ b/sim/testsuite/sim/rx/tst.s
@@ -0,0 +1,54 @@
+# RX testcase for tst
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+tst_imm4:
+ mov.l #2,r1
+ tst #2,r1
+ test_zero_clear
+ test_neg_clear
+tst_imm8:
+ tst #0x13,r1
+ test_zero_clear
+ test_neg_clear
+tst_imm16:
+ tst #0xffff,r1
+ test_zero_clear
+ test_neg_clear
+tst_imm24:
+ tst #0xffffff,r1
+ test_zero_clear
+ test_neg_clear
+tst_imm32:
+ mov.l #0x80000000,r1
+ tst #0xffffffff,r1
+ test_zero_clear
+ test_neg_set
+tst_reg:
+ mov.l #0x80000000,r2
+ tst r2,r1
+ test_zero_clear
+ test_neg_set
+tst_mem_ind:
+ mov.l #val, r2
+ tst [r2].l,r1
+ test_zero_set
+ test_neg_clear
+tst_mem_dsp8:
+ mov.l #val-4, r2
+ tst 4[r2].l,r1
+ test_zero_set
+ test_neg_clear
+tst_mem_dsp16:
+ mov.l #val-0x1000, r2
+ tst 0x1000[r2].l,r1
+ test_zero_set
+ test_neg_clear
+
+ pass
+
+ .data
+val: .long 1
diff --git a/sim/testsuite/sim/rx/utof.s b/sim/testsuite/sim/rx/utof.s
new file mode 100644
index 0000000..2dee2bf
--- /dev/null
+++ b/sim/testsuite/sim/rx/utof.s
@@ -0,0 +1,37 @@
+# RX testcase for utof
+# mach: rxv2
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+utof_reg:
+ mov.l #2147483648,r2
+ utof r2,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2147483648.0 r1
+utof_mem_ind:
+ mov.l #val, r2
+ utof [r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2147483648.0 r1
+utof_mem_dsp8:
+ mov.l #val-4, r2
+ utof 4[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2147483648.0 r1
+utof_mem_dsp16:
+ mov.l #val-0x1000, r2
+ utof 0x1000[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2147483648.0 r1
+
+ pass
+
+ .data
+val: .long 2147483648
+
diff --git a/sim/testsuite/sim/rx/xchg.s b/sim/testsuite/sim/rx/xchg.s
new file mode 100644
index 0000000..b1098be
--- /dev/null
+++ b/sim/testsuite/sim/rx/xchg.s
@@ -0,0 +1,36 @@
+# RX testcase for xchg
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+xchg_reg:
+ mov.l #1,r1
+ mov.l #2,r2
+ xchg r2,r1
+ test_h_gr32 1 r2
+ test_h_gr32 2 r1
+xchg_mem_ind:
+ mov.l #val, r2
+ xchg [r2].l,r1
+ mov.l [r2],r3
+ test_h_gr32 1 r1
+ test_h_gr32 2 r3
+tst_mem_dsp8:
+ mov.l #val-4, r2
+ xchg 4[r2].l,r1
+ mov.l 4[r2],r3
+ test_h_gr32 2 r1
+ test_h_gr32 1 r3
+tst_mem_dsp16:
+ mov.l #val-0x1000, r2
+ xchg 0x1000[r2].l,r1
+ mov.l 0x1000[r2],r3
+ test_h_gr32 1 r1
+ test_h_gr32 2 r3
+
+ pass
+
+ .data
+val: .long 1
diff --git a/sim/testsuite/sim/rx/xor.s b/sim/testsuite/sim/rx/xor.s
new file mode 100644
index 0000000..0e22199
--- /dev/null
+++ b/sim/testsuite/sim/rx/xor.s
@@ -0,0 +1,58 @@
+# RX testcase for xor
+# mach: rx rxv2
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+xor_imm8:
+ sub r1,r1
+ xor #0x10,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x10 r1
+xor_imm16:
+ xor #0x1010,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x1000 r1
+xor_imm24:
+ xor #0x101000,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x100000 r1
+xor_imm32:
+ xor #0x10100000,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x10000000 r1
+xor_reg:
+ mov.l #0x20000000,r2
+ xor r2,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x30000000 r1
+xor_mem_ind:
+ mov #val, r2
+ xor [r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x30000008 r1
+xor_mem_dsp8:
+ mov #val-4, r2
+ xor 4[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x30000000 r1
+xor_mem_dsp16:
+ sub r1,r1
+ mov #val-0x1000, r2
+ xor 0x1000[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 8 r1
+
+ pass
+
+ .data
+val: .long 8
--
2.6.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH][RX] instructions test set.
2015-12-25 14:20 ` [PATCH][RX] instructions test set Yoshinori Sato
@ 2015-12-25 17:04 ` Mike Frysinger
0 siblings, 0 replies; 11+ messages in thread
From: Mike Frysinger @ 2015-12-25 17:04 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: gdb-patches
[-- Attachment #1: Type: text/plain, Size: 817 bytes --]
On 25 Dec 2015 23:19, Yoshinori Sato wrote:
> --- /dev/null
> +++ b/sim/testsuite/sim/rx/abs.s
> @@ -0,0 +1,25 @@
> +# RX testcase for abs
> +# mach: all
i think you want to use "rx rxv2" instead of "all"
> --- /dev/null
> +++ b/sim/testsuite/sim/rx/allinsn.exp
> @@ -0,0 +1,67 @@
> +# Renesas RX simulator testsuite
> +
> +set all "rx rxv2"
> +set global_ld_options "-Ttext=0x01000000 --defsym __stack=0x01800000"
move these inside of the "if" statement
> +if [istarget rx-*-*] then {
drop the "then" keyword
> + run_sim_test abs.s $all
instead of listing them all out, look at how testsuite/sim/msp430/allinsn.exp
is written using a loop and glob. i think passing down $all for all of the
tests should be fine, even the later ones where you pass rxv2. the framework
should skip things as needed.
-mike
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH][RX] instructions test set.
2015-12-25 14:20 [PATCH][RX] v2 instructions support Yoshinori Sato
@ 2015-12-25 14:20 ` Yoshinori Sato
2015-12-25 17:04 ` Mike Frysinger
0 siblings, 1 reply; 11+ messages in thread
From: Yoshinori Sato @ 2015-12-25 14:20 UTC (permalink / raw)
To: gdb-patches; +Cc: Yoshinori Sato
---
sim/testsuite/sim/rx/ChangeLog | 11 ++
sim/testsuite/sim/rx/abs.s | 25 +++
sim/testsuite/sim/rx/adc.s | 77 ++++++++++
sim/testsuite/sim/rx/add.s | 108 +++++++++++++
sim/testsuite/sim/rx/allinsn.exp | 67 ++++++++
sim/testsuite/sim/rx/and.s | 79 ++++++++++
sim/testsuite/sim/rx/bcnd.s | 60 ++++++++
sim/testsuite/sim/rx/bmcnd.s | 132 ++++++++++++++++
sim/testsuite/sim/rx/bra.s | 23 +++
sim/testsuite/sim/rx/bset.s | 197 ++++++++++++++++++++++++
sim/testsuite/sim/rx/cmp.s | 74 +++++++++
sim/testsuite/sim/rx/div.s | 52 +++++++
sim/testsuite/sim/rx/emaca.s | 24 +++
sim/testsuite/sim/rx/emsba.s | 24 +++
sim/testsuite/sim/rx/emul.s | 92 +++++++++++
sim/testsuite/sim/rx/emula.s | 24 +++
sim/testsuite/sim/rx/fadd.s | 41 +++++
sim/testsuite/sim/rx/fcmp.s | 37 +++++
sim/testsuite/sim/rx/fdiv.s | 43 ++++++
sim/testsuite/sim/rx/fmul.s | 51 +++++++
sim/testsuite/sim/rx/fsqrt.s | 23 +++
sim/testsuite/sim/rx/fsub.s | 51 +++++++
sim/testsuite/sim/rx/ftoi.s | 37 +++++
sim/testsuite/sim/rx/ftou.s | 37 +++++
sim/testsuite/sim/rx/itof.s | 37 +++++
sim/testsuite/sim/rx/jmp.s | 12 ++
sim/testsuite/sim/rx/machilo.s | 53 +++++++
sim/testsuite/sim/rx/max.s | 45 ++++++
sim/testsuite/sim/rx/min.s | 45 ++++++
sim/testsuite/sim/rx/mov.s | 196 ++++++++++++++++++++++++
sim/testsuite/sim/rx/movlico.s | 22 +++
sim/testsuite/sim/rx/movu.s | 67 ++++++++
sim/testsuite/sim/rx/msbhilo.s | 43 ++++++
sim/testsuite/sim/rx/mul.s | 52 +++++++
sim/testsuite/sim/rx/mulhilo.s | 54 +++++++
sim/testsuite/sim/rx/mvacc.s | 28 ++++
sim/testsuite/sim/rx/mvftc.s | 36 +++++
sim/testsuite/sim/rx/neg.s | 17 +++
sim/testsuite/sim/rx/not.s | 17 +++
sim/testsuite/sim/rx/or.s | 69 +++++++++
sim/testsuite/sim/rx/pushpop.s | 48 ++++++
sim/testsuite/sim/rx/racw.s | 38 +++++
sim/testsuite/sim/rx/rdacw.s | 19 +++
sim/testsuite/sim/rx/rev.s | 14 ++
sim/testsuite/sim/rx/rmpa.s | 23 +++
sim/testsuite/sim/rx/rot.s | 46 ++++++
sim/testsuite/sim/rx/round.s | 37 +++++
sim/testsuite/sim/rx/sat.s | 37 +++++
sim/testsuite/sim/rx/sbb.s | 46 ++++++
sim/testsuite/sim/rx/sccnd.s | 169 +++++++++++++++++++++
sim/testsuite/sim/rx/scmpu.s | 26 ++++
sim/testsuite/sim/rx/shlr.s | 67 ++++++++
sim/testsuite/sim/rx/smovb.s | 53 +++++++
sim/testsuite/sim/rx/smovu.s | 23 +++
sim/testsuite/sim/rx/sstr.s | 44 ++++++
sim/testsuite/sim/rx/stz.s | 52 +++++++
sim/testsuite/sim/rx/sub.s | 53 +++++++
sim/testsuite/sim/rx/suntil.s | 59 ++++++++
sim/testsuite/sim/rx/testutils.inc | 302 +++++++++++++++++++++++++++++++++++++
sim/testsuite/sim/rx/tst.s | 54 +++++++
sim/testsuite/sim/rx/utof.s | 37 +++++
sim/testsuite/sim/rx/xchg.s | 36 +++++
sim/testsuite/sim/rx/xor.s | 58 +++++++
63 files changed, 3523 insertions(+)
create mode 100644 sim/testsuite/sim/rx/ChangeLog
create mode 100644 sim/testsuite/sim/rx/abs.s
create mode 100644 sim/testsuite/sim/rx/adc.s
create mode 100644 sim/testsuite/sim/rx/add.s
create mode 100644 sim/testsuite/sim/rx/allinsn.exp
create mode 100644 sim/testsuite/sim/rx/and.s
create mode 100644 sim/testsuite/sim/rx/bcnd.s
create mode 100644 sim/testsuite/sim/rx/bmcnd.s
create mode 100644 sim/testsuite/sim/rx/bra.s
create mode 100644 sim/testsuite/sim/rx/bset.s
create mode 100644 sim/testsuite/sim/rx/cmp.s
create mode 100644 sim/testsuite/sim/rx/div.s
create mode 100644 sim/testsuite/sim/rx/emaca.s
create mode 100644 sim/testsuite/sim/rx/emsba.s
create mode 100644 sim/testsuite/sim/rx/emul.s
create mode 100644 sim/testsuite/sim/rx/emula.s
create mode 100644 sim/testsuite/sim/rx/fadd.s
create mode 100644 sim/testsuite/sim/rx/fcmp.s
create mode 100644 sim/testsuite/sim/rx/fdiv.s
create mode 100644 sim/testsuite/sim/rx/fmul.s
create mode 100644 sim/testsuite/sim/rx/fsqrt.s
create mode 100644 sim/testsuite/sim/rx/fsub.s
create mode 100644 sim/testsuite/sim/rx/ftoi.s
create mode 100644 sim/testsuite/sim/rx/ftou.s
create mode 100644 sim/testsuite/sim/rx/itof.s
create mode 100644 sim/testsuite/sim/rx/jmp.s
create mode 100644 sim/testsuite/sim/rx/machilo.s
create mode 100644 sim/testsuite/sim/rx/max.s
create mode 100644 sim/testsuite/sim/rx/min.s
create mode 100644 sim/testsuite/sim/rx/mov.s
create mode 100644 sim/testsuite/sim/rx/movlico.s
create mode 100644 sim/testsuite/sim/rx/movu.s
create mode 100644 sim/testsuite/sim/rx/msbhilo.s
create mode 100644 sim/testsuite/sim/rx/mul.s
create mode 100644 sim/testsuite/sim/rx/mulhilo.s
create mode 100644 sim/testsuite/sim/rx/mvacc.s
create mode 100644 sim/testsuite/sim/rx/mvftc.s
create mode 100644 sim/testsuite/sim/rx/neg.s
create mode 100644 sim/testsuite/sim/rx/not.s
create mode 100644 sim/testsuite/sim/rx/or.s
create mode 100644 sim/testsuite/sim/rx/pushpop.s
create mode 100644 sim/testsuite/sim/rx/racw.s
create mode 100644 sim/testsuite/sim/rx/rdacw.s
create mode 100644 sim/testsuite/sim/rx/rev.s
create mode 100644 sim/testsuite/sim/rx/rmpa.s
create mode 100644 sim/testsuite/sim/rx/rot.s
create mode 100644 sim/testsuite/sim/rx/round.s
create mode 100644 sim/testsuite/sim/rx/sat.s
create mode 100644 sim/testsuite/sim/rx/sbb.s
create mode 100644 sim/testsuite/sim/rx/sccnd.s
create mode 100644 sim/testsuite/sim/rx/scmpu.s
create mode 100644 sim/testsuite/sim/rx/shlr.s
create mode 100644 sim/testsuite/sim/rx/smovb.s
create mode 100644 sim/testsuite/sim/rx/smovu.s
create mode 100644 sim/testsuite/sim/rx/sstr.s
create mode 100644 sim/testsuite/sim/rx/stz.s
create mode 100644 sim/testsuite/sim/rx/sub.s
create mode 100644 sim/testsuite/sim/rx/suntil.s
create mode 100644 sim/testsuite/sim/rx/testutils.inc
create mode 100644 sim/testsuite/sim/rx/tst.s
create mode 100644 sim/testsuite/sim/rx/utof.s
create mode 100644 sim/testsuite/sim/rx/xchg.s
create mode 100644 sim/testsuite/sim/rx/xor.s
diff --git a/sim/testsuite/sim/rx/ChangeLog b/sim/testsuite/sim/rx/ChangeLog
new file mode 100644
index 0000000..d149e6a
--- /dev/null
+++ b/sim/testsuite/sim/rx/ChangeLog
@@ -0,0 +1,11 @@
+2015-12-25 Yoshinori Sato <ysatt@users.sourceforge.jp>
+
+ * abs.s, adc.s, add.s, and.s, bcnd.s, bmcnd.s, bra.s, bset.s,
+ cmp.s, div.s, emaca.s, emsba.s, emul.s, emula.s, fadd.s, fcmp.s,
+ fdiv.s, fmul.s, fsqrt.s, fsub.s, ftoi.s, ftou.s, itof.s, jmp.s,
+ machilo.s, max.s, min.s, mov.s, movlico.s, movu.s, msbhilo.s,
+ mul.s, mulhilo.s, mvacc.s, mvftc.s, neg.s, not.s, or.s,pushpop.s,
+ racw.s, rdacw.s, rev.s, rmpa.s, rot.s, round.s, sbb.s, sccnd.s,
+ scmpu.s, shlr.s, smovb.s, smovu.s, sstr.s, stz.s, sub.s, suntil.s,
+ tst.s,utof.s,xchg.s,xor.s: New file.
+ * allinsn.exp: New file.
diff --git a/sim/testsuite/sim/rx/abs.s b/sim/testsuite/sim/rx/abs.s
new file mode 100644
index 0000000..c4a4889
--- /dev/null
+++ b/sim/testsuite/sim/rx/abs.s
@@ -0,0 +1,25 @@
+# RX testcase for abs
+# mach: all
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+abs_dest:
+ mov.l #1,r1
+ abs r1
+ test_h_gr32 1 r1
+ mov.l #-1,r1
+ abs r1
+ test_h_gr32 1 r1
+abs_src_dest:
+ sub r2,r2
+ mov.l #1,r1
+ abs r1,r2
+ test_h_gr32 1 r2
+ sub r2,r2
+ mov.l #-1,r1
+ abs r1,r2
+ test_h_gr32 1 r2
+
+ pass
diff --git a/sim/testsuite/sim/rx/adc.s b/sim/testsuite/sim/rx/adc.s
new file mode 100644
index 0000000..c3ff0d5
--- /dev/null
+++ b/sim/testsuite/sim/rx/adc.s
@@ -0,0 +1,77 @@
+# RX testcase for adc
+# mach: all
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+adc_imm4:
+ clear_carry_flag
+ mov.l #1,r1
+ adc #2,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 3 r1
+adc_imm8:
+ clear_carry_flag
+ adc #-1,r1
+ test_zero_clear
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 2 r1
+adc_imm16:
+ set_carry_flag
+ adc #0x7ffd,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 0x8000 r1
+adc_imm24:
+ clear_carry_flag
+ adc #0x800000 - 0x8000,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 0x800000 r1
+adc_imm32:
+ clear_carry_flag
+ adc #0x80000000 - 0x800000,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_set
+ test_h_gr32 0x80000000 r1
+adc_reg:
+ clear_carry_flag
+ mov.l #0x80000000,r2
+ adc r2,r1
+ test_zero_set
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 0 r1
+adc_mem_ind:
+ mov.l #val, r2
+ adc [r2].l,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 2 r1
+adc_mem_dsp8:
+ mov.l #val-4, r2
+ adc 4[r2].l,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 4 r1
+adc_mem_dsp16:
+ mov.l #val-0x1000, r2
+ adc 0x1000[r2].l,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 6 r1
+
+ pass
+
+ .data
+val: .long 1
diff --git a/sim/testsuite/sim/rx/add.s b/sim/testsuite/sim/rx/add.s
new file mode 100644
index 0000000..ac37826
--- /dev/null
+++ b/sim/testsuite/sim/rx/add.s
@@ -0,0 +1,108 @@
+# RX testcase for add
+# mach: all
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+add_imm4:
+ mov.l #1,r1
+ add #2,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 3 r1
+add_imm8:
+ add #-1,r1
+ test_zero_clear
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 2 r1
+add_imm16:
+ add #0x7ffe,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 0x8000 r1
+add_imm24:
+ add #0x800000 - 0x8000,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 0x800000 r1
+add_imm32:
+ add #0x80000000 - 0x800000,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_set
+ test_h_gr32 0x80000000 r1
+add_reg:
+ mov.l #0x80000000,r2
+ add r2,r1
+ test_zero_set
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 0 r1
+add_mem_ind:
+ mov.l #val, r2
+ add [r2].l,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 1 r1
+add_mem_dsp8:
+ mov.l #val-4, r2
+ add 4[r2].l,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 2 r1
+add_mem_dsp16:
+ mov.l #val-0x1000, r2
+ add 0x1000[r2].l,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 3 r1
+add3_imm4:
+ mov.l #1,r1
+ add #2,r1,r2
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 3 r2
+add3_imm8:
+ add #-1,r1,r2
+ test_zero_set
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 0 r2
+add3_imm16:
+ add #0x7ffe,r1,r2
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 0x7fff r2
+add3_imm24:
+ add #0x7ffffe,r1,r2
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 0x7fffff r2
+add3_imm32:
+ add #0x7ffffffe,r1,r2
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 0x7fffffff r2
+add3_reg:
+ add r1,r1,r2
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 2 r2
+
+ pass
+
+ .data
+val: .long 1
diff --git a/sim/testsuite/sim/rx/allinsn.exp b/sim/testsuite/sim/rx/allinsn.exp
new file mode 100644
index 0000000..4491c56
--- /dev/null
+++ b/sim/testsuite/sim/rx/allinsn.exp
@@ -0,0 +1,67 @@
+# Renesas RX simulator testsuite
+
+set all "rx rxv2"
+set global_ld_options "-Ttext=0x01000000 --defsym __stack=0x01800000"
+
+if [istarget rx-*-*] then {
+ run_sim_test abs.s $all
+ run_sim_test adc.s $all
+ run_sim_test add.s $all
+ run_sim_test and.s $all
+ run_sim_test bset.s $all
+ run_sim_test bcnd.s $all
+ run_sim_test bmcnd.s $all
+ run_sim_test bra.s $all
+ run_sim_test cmp.s $all
+ run_sim_test div.s $all
+ run_sim_test emul.s $all
+ run_sim_test jmp.s $all
+ run_sim_test max.s $all
+ run_sim_test min.s $all
+ run_sim_test mov.s $all
+ run_sim_test movu.s $all
+ run_sim_test mul.s $all
+ run_sim_test mvftc.s $all
+ run_sim_test neg.s $all
+ run_sim_test not.s $all
+ run_sim_test or.s $all
+ run_sim_test pushpop.s $all
+ run_sim_test rev.s $all
+ run_sim_test rot.s $all
+ run_sim_test rmpa.s $all
+ run_sim_test sat.s $all
+ run_sim_test sbb.s $all
+ run_sim_test sccnd.s $all
+ run_sim_test scmpu.s $all
+ run_sim_test shlr.s $all
+ run_sim_test smovb.s $all
+ run_sim_test smovu.s $all
+ run_sim_test sstr.s $all
+ run_sim_test stz.s $all
+ run_sim_test sub.s $all
+ run_sim_test suntil.s $all
+ run_sim_test tst.s $all
+ run_sim_test xchg.s $all
+ run_sim_test xor.s $all
+ run_sim_test fadd.s $all
+ run_sim_test fcmp.s $all
+ run_sim_test fdiv.s $all
+ run_sim_test fmul.s $all
+ run_sim_test fsub.s $all
+ run_sim_test ftoi.s $all
+ run_sim_test itof.s $all
+ run_sim_test round.s $all
+ run_sim_test mvacc.s $all
+ run_sim_test machilo.s $all
+ run_sim_test mulhilo.s $all
+ run_sim_test racw.s $all
+ run_sim_test movlico.s rxv2
+ run_sim_test fsqrt.s rxv2
+ run_sim_test ftou.s rxv2
+ run_sim_test utof.s rxv2
+ run_sim_test emaca.s rxv2
+ run_sim_test emsba.s rxv2
+ run_sim_test emula.s rxv2
+ run_sim_test msbhilo.s rxv2
+ run_sim_test rdacw.s rxv2
+}
diff --git a/sim/testsuite/sim/rx/and.s b/sim/testsuite/sim/rx/and.s
new file mode 100644
index 0000000..5d8940a
--- /dev/null
+++ b/sim/testsuite/sim/rx/and.s
@@ -0,0 +1,79 @@
+# RX testcase for and
+# mach: all
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+and_imm4:
+ mov.l #2,r1
+ and #2,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_h_gr32 2 r1
+and_imm8:
+ and #0x13,r1
+ test_zero_clear
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 2 r1
+and_imm16:
+ and #0xffff,r1
+ test_zero_clear
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 2 r1
+and_imm24:
+ and #0xffffff,r1
+ test_zero_clear
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 2 r1
+and_imm32:
+ mov.l #0x80000000,r1
+ and #0xffffffff,r1
+ test_zero_clear
+ test_carry_set
+ test_neg_set
+ test_h_gr32 0x80000000 r1
+and_reg:
+ mov.l #0x80000000,r2
+ and r2,r1
+ test_zero_clear
+ test_carry_set
+ test_neg_set
+ test_h_gr32 0x80000000 r1
+and_mem_ind:
+ mov.l #val, r2
+ and [r2].l,r1
+ test_zero_set
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 0 r1
+and_mem_dsp8:
+ mov.l #val-4, r2
+ and 4[r2].l,r1
+ test_zero_set
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 0 r1
+and_mem_dsp16:
+ mov.l #val-0x1000, r2
+ and 0x1000[r2].l,r1
+ test_zero_set
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 0 r1
+and3_reg:
+ mov.l #0x80000000,r2
+ and r2,r1,r3
+ test_zero_set
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 0 r3
+
+ pass
+
+ .data
+val: .long 1
diff --git a/sim/testsuite/sim/rx/bcnd.s b/sim/testsuite/sim/rx/bcnd.s
new file mode 100644
index 0000000..549ab23
--- /dev/null
+++ b/sim/testsuite/sim/rx/bcnd.s
@@ -0,0 +1,60 @@
+# RX testcase for Bcnd
+# mach: all
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ sub r2,r2
+ set_zero_flag
+ beq.s 1f
+ add #1,r2
+1: clear_zero_flag
+ bne.s 2f
+ add #1,r2
+2: test_h_gr32 0 r2
+ mov #10,r1
+ cmp #5,r1
+ bc 3f
+ fail
+3: cmp #15,r1
+ bnc 4f
+ fail
+4: mov #-5,r1
+ cmp #-10,r1
+ bgt 5f
+ fail
+5: cmp #-5,r1
+ ble 6f
+ fail
+6: bge 7f
+ fail
+7: cmp #-1,r1
+ blt 8f
+ fail
+8: mov.l #0xc0000000,r1
+ cmp #0x80000000,r1
+ bgtu 9f
+ fail
+9: mov #1,r1
+ tst r1,r1
+ bpz 11f
+ fail
+11: mov #-1,r1
+ tst r1,r1
+ bn 12f
+ fail
+12: set_overflow_flag
+ bo 13f
+ fail
+13: clear_overflow_flag
+ bno 14f
+ fail
+14: set_zero_flag
+ beq.w 15f
+ fail
+15: clear_zero_flag
+ bne.w 16f
+ fail
+16:
+ pass
diff --git a/sim/testsuite/sim/rx/bmcnd.s b/sim/testsuite/sim/rx/bmcnd.s
new file mode 100644
index 0000000..f42270a
--- /dev/null
+++ b/sim/testsuite/sim/rx/bmcnd.s
@@ -0,0 +1,132 @@
+# RX testcase for BMcnd
+# mach: all
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ mov #val,r2
+ mov #val-4,r3
+ mov #val-0x1000,r4
+ mov #10,r1
+ cmp #5,r1
+ bmc #0,[r2].b
+ bmc #1,4[r3].b
+ bmc #2,0x1000[r4].b
+ bmc #0,r5
+ btst #0,r5
+ test_zero_clear
+ mov.b [r2],r5
+ test_h_gr32 7 r5
+ mov.b #0,[r2]
+ cmp #15,r1
+ bmnc #0,[r2].b
+ bmnc #1,4[r3].b
+ bmnc #2,0x1000[r4].b
+ bmnc #0,r5
+ btst #0,r5
+ test_zero_clear
+ mov.b [r2],r5
+ test_h_gr32 7 r5
+ mov.b #0,[r2]
+ mov #-5,r1
+ cmp #-10,r1
+ bmgt #0,[r2].b
+ bmgt #1,4[r3].b
+ bmgt #2,0x1000[r4].b
+ bmgt #0,r5
+ btst #0,r5
+ test_zero_clear
+ mov.b [r2],r5
+ test_h_gr32 7 r5
+ mov.b #0,[r2]
+ mov #-5,r1
+ cmp #-5,r1
+ bmle #0,[r2].b
+ bmle #1,4[r3].b
+ bmle #2,0x1000[r4].b
+ bmle #0,r5
+ btst #0,r5
+ test_zero_clear
+ mov.b [r2],r5
+ test_h_gr32 7 r5
+ mov.b #0,[r2]
+ mov #-5,r1
+ cmp #-5,r1
+ bmge #0,[r2].b
+ bmge #1,4[r3].b
+ bmge #2,0x1000[r4].b
+ bmge #0,r5
+ btst #0,r5
+ test_zero_clear
+ mov.b [r2],r5
+ test_h_gr32 7 r5
+ mov.b #0,[r2]
+ mov #-5,r1
+ cmp #-1,r1
+ bmlt #0,[r2].b
+ bmlt #1,4[r3].b
+ bmlt #2,0x1000[r4].b
+ bmlt #0,r5
+ btst #0,r5
+ test_zero_clear
+ mov.b [r2],r5
+ test_h_gr32 7 r5
+ mov.b #0,[r2]
+ mov.l #0xc0000000,r1
+ cmp #0x80000000,r1
+ bmgtu #0,[r2].b
+ bmgtu #1,4[r3].b
+ bmgtu #2,0x1000[r4].b
+ bmgtu #0,r5
+ btst #0,r5
+ test_zero_clear
+ mov.b [r2],r5
+ test_h_gr32 7 r5
+ mov.b #0,[r2]
+ mov #1,r1
+ tst r1,r1
+ bmpz #0,[r2].b
+ bmpz #1,4[r3].b
+ bmpz #2,0x1000[r4].b
+ bmpz #0,r5
+ btst #0,r5
+ test_zero_clear
+ mov.b [r2],r5
+ test_h_gr32 7 r5
+ mov.b #0,[r2]
+ mov #-1,r1
+ tst r1,r1
+ bmn #0,[r2].b
+ bmn #1,4[r3].b
+ bmn #2,0x1000[r4].b
+ bmn #0,r5
+ btst #0,r5
+ test_zero_clear
+ mov.b [r2],r5
+ test_h_gr32 7 r5
+ mov.b #0,[r2]
+ set_overflow_flag
+ bmo #0,[r2].b
+ bmo #1,4[r3].b
+ bmo #2,0x1000[r4].b
+ bmo #0,r5
+ btst #0,r5
+ test_zero_clear
+ mov.b [r2],r5
+ test_h_gr32 7 r5
+ mov.b #0,[r2]
+ clear_overflow_flag
+ bmno #0,[r2].b
+ bmno #1,4[r3].b
+ bmno #2,0x1000[r4].b
+ bmno #0,r5
+ btst #0,r5
+ test_zero_clear
+ mov.b [r2],r5
+ test_h_gr32 7 r5
+
+ pass
+
+ .data
+val: .byte 0
diff --git a/sim/testsuite/sim/rx/bra.s b/sim/testsuite/sim/rx/bra.s
new file mode 100644
index 0000000..9db31c6
--- /dev/null
+++ b/sim/testsuite/sim/rx/bra.s
@@ -0,0 +1,23 @@
+# RX testcase for bra
+# mach: all
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ sub r2,r2
+ bra.s 1f
+ add #1,r2
+1: test_h_gr32 0 r2
+ bra.b 2f
+ fail
+2: bra.w 3f
+ fail
+3: bra.a 4f
+ fail
+4: mov #6f,r1
+ sub #5f,r1
+5: bra r1
+ fail
+6:
+ pass
diff --git a/sim/testsuite/sim/rx/bset.s b/sim/testsuite/sim/rx/bset.s
new file mode 100644
index 0000000..5deda54
--- /dev/null
+++ b/sim/testsuite/sim/rx/bset.s
@@ -0,0 +1,197 @@
+# RX testcase for bset/bclr/bnot/btst
+# mach: all
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+bset_imm_ind:
+ mov.l #val,r2
+ bset #0,[r2].b
+ btst #0,[r2].b
+ test_zero_clear
+ test_carry_set
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 3 r1
+bclr_imm_ind:
+ bclr #1,[r2].b
+ btst #1,[r2].b
+ test_zero_set
+ test_carry_clear
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 1 r1
+bnot_imm_ind:
+ bnot #1,[r2].b
+ btst #1,[r2].b
+ test_zero_clear
+ test_carry_set
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 3 r1
+bset_imm_dsp8:
+ mov.l #val-4,r2
+ bset #2,4[r2].b
+ btst #2,4[r2].b
+ test_zero_clear
+ test_carry_set
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 7 r1
+bclr_imm_dsp8:
+ bclr #2,4[r2].b
+ btst #2,4[r2].b
+ test_zero_set
+ test_carry_clear
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 3 r1
+bnot_imm_dsp8:
+ bnot #2,4[r2].b
+ btst #2,4[r2].b
+ test_zero_clear
+ test_carry_set
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 7 r1
+bset_imm_dsp16:
+ mov.l #val-0x1000,r2
+ bset #2,0x1000[r2].b
+ btst #2,0x1000[r2].b
+ test_zero_clear
+ test_carry_set
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 7 r1
+bclr_imm_dsp16:
+ bclr #2,0x1000[r2].b
+ btst #2,0x1000[r2].b
+ test_zero_set
+ test_carry_clear
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 3 r1
+bnot_imm_dsp16:
+ bnot #2,0x1000[r2].b
+ btst #2,0x1000[r2].b
+ test_zero_clear
+ test_carry_set
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 7 r1
+bset_reg_ind:
+ mov.l #0,r1
+ mov.l #val,r2
+ bset r1,[r2].b
+ btst r1,[r2].b
+ test_zero_clear
+ test_carry_set
+ mov.b [r2],r1
+ test_h_gr32 7 r1
+bclr_reg_ind:
+ mov.l #0,r1
+ bclr r1,[r2].b
+ btst r1,[r2].b
+ test_zero_set
+ test_carry_clear
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 6 r1
+bnot_reg_ind:
+ mov.l #0,r1
+ bnot r1,[r2].b
+ btst r1,[r2].b
+ test_zero_clear
+ test_carry_set
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 7 r1
+bset_reg_dsp8:
+ mov.l #2,r1
+ mov.l #val-4,r2
+ bset r1,4[r2].b
+ btst r1,4[r2].b
+ test_zero_clear
+ test_carry_set
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 7 r1
+bclr_reg_dsp8:
+ mov.l #2,r1
+ bclr r1,4[r2].b
+ btst r1,4[r2].b
+ test_zero_set
+ test_carry_clear
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 3 r1
+bnot_reg_dsp8:
+ mov.l #2,r1
+ bnot r1,4[r2].b
+ btst r1,4[r2].b
+ test_zero_clear
+ test_carry_set
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 7 r1
+bset_reg_dsp16:
+ mov.l #2,r1
+ mov.l #val-0x1000,r2
+ bset r1,0x1000[r2].b
+ btst r1,0x1000[r2].b
+ test_zero_clear
+ test_carry_set
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 7 r1
+bclr_reg_dsp16:
+ mov.l #2,r1
+ bclr r1,0x1000[r2].b
+ btst r1,0x1000[r2].b
+ test_zero_set
+ test_carry_clear
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 3 r1
+bnot_reg_dsp16:
+ mov.l #2,r1
+ bnot r1,0x1000[r2].b
+ btst r1,0x1000[r2].b
+ test_zero_clear
+ test_carry_set
+ mov.l #val,r1
+ mov.b [r1],r1
+ test_h_gr32 7 r1
+bnot_imm_reg:
+ sub r1,r1
+ bnot #1,r1
+ btst #1,r1
+ test_zero_clear
+ test_carry_set
+ test_h_gr32 2 r1
+bset_reg_reg:
+ sub r1,r1
+ mov.l #1,r2
+ bset r2,r1
+ btst r2,r1
+ test_zero_clear
+ test_carry_set
+ test_h_gr32 2 r1
+bclr_reg_reg:
+ bclr r2,r1
+ btst r2,r1
+ test_zero_set
+ test_carry_clear
+ test_h_gr32 0 r1
+bnot_reg_reg:
+ bnot r2,r1
+ btst r2,r1
+ test_zero_clear
+ test_carry_set
+ test_h_gr32 2 r1
+
+ pass
+
+ .data
+val: .byte 2
diff --git a/sim/testsuite/sim/rx/cmp.s b/sim/testsuite/sim/rx/cmp.s
new file mode 100644
index 0000000..49e81ec
--- /dev/null
+++ b/sim/testsuite/sim/rx/cmp.s
@@ -0,0 +1,74 @@
+# RX testcase for cmp
+# mach: all
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+cmp_imm4:
+ mov #1,r1
+ cmp #2,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_set
+ test_overflow_clear
+cmp_imm8:
+ cmp #-1,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_clear
+ test_overflow_clear
+cmp_imm16:
+ mov #0x8000,r1
+ cmp #0x8000,r1
+ test_zero_set
+ test_carry_set
+ test_neg_clear
+ test_overflow_clear
+cmp_imm24:
+ mov #0x800000,r1
+ cmp #0x7fffff,r1
+ test_zero_clear
+ test_carry_set
+ test_neg_clear
+ test_overflow_clear
+cmp_imm32:
+ mov #0x80000000,r1
+ cmp #0x7fffffff,r1
+ test_zero_clear
+ test_carry_set
+ test_neg_clear
+ test_overflow_set
+cmp_reg:
+ mov.l #0x80000000,r2
+ cmp r2,r1
+ test_zero_set
+ test_carry_set
+ test_neg_clear
+cmp_mem_ind:
+ sub r1,r1
+ mov #val, r2
+ cmp [r2].l,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_set
+ test_overflow_clear
+cmp_mem_dsp8:
+ mov #val-4, r2
+ cmp 4[r2].l,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_set
+ test_overflow_clear
+cmp_mem_dsp16:
+ mov #val-0x1000, r2
+ cmp 0x1000[r2].l,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_set
+ test_overflow_clear
+
+ pass
+
+ .data
+val: .long 1
diff --git a/sim/testsuite/sim/rx/div.s b/sim/testsuite/sim/rx/div.s
new file mode 100644
index 0000000..630c954
--- /dev/null
+++ b/sim/testsuite/sim/rx/div.s
@@ -0,0 +1,52 @@
+# RX testcase for div/divu
+# mach: all
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+div_imm8:
+ mov #2,r1
+ div #2,r1
+ test_h_gr32 1 r1
+div_imm16:
+ mov #0x8000,r1
+ div #0x1000,r1
+ test_h_gr32 8 r1
+div_imm24:
+ mov #0x800000,r1
+ div #0x200000,r1
+ test_h_gr32 4 r1
+div_imm32:
+ mov #0x80000000,r1
+ div #0x40000000,r1
+ test_h_gr32 -2 r1
+divu_imm32:
+ mov #0x80000000,r1
+ divu #0x40000000,r1
+ test_h_gr32 2 r1
+div_reg:
+ mov #0x80000000,r1
+ mov r1,r2
+ div r2,r1
+ test_h_gr32 1 r1
+div_mem_ind:
+ mov #10,r1
+ mov #val, r2
+ div [r2],r1
+ test_h_gr32 5 r1
+div_mem_dsp8:
+ mov #10,r1
+ mov #val-4, r2
+ div 4[r2],r1
+ test_h_gr32 5 r1
+div_mem_dsp16:
+ mov #10,r1
+ mov #val-0x1000, r2
+ div 0x1000[r2],r1
+ test_h_gr32 5 r1
+
+ pass
+
+ .data
+val: .long 2
diff --git a/sim/testsuite/sim/rx/emaca.s b/sim/testsuite/sim/rx/emaca.s
new file mode 100644
index 0000000..e066d57
--- /dev/null
+++ b/sim/testsuite/sim/rx/emaca.s
@@ -0,0 +1,24 @@
+# RX testcase for emaca
+# mach: rxv2
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+ mov #100, r1
+ mov #200, r2
+ emaca r1,r2,a0
+ mvfaclo #0,a0,r1
+ test_h_gr32 20000 r1
+ mvfachi #0,a0,r1
+ test_h_gr32 0 r1
+ mov #300, r1
+ mov #200, r2
+ emaca r1,r2,a1
+ mvfaclo #0,a1,r1
+ test_h_gr32 60000 r1
+ mvfachi #0,a1,r1
+ test_h_gr32 0 r1
+
+ pass
+
diff --git a/sim/testsuite/sim/rx/emsba.s b/sim/testsuite/sim/rx/emsba.s
new file mode 100644
index 0000000..a20c963
--- /dev/null
+++ b/sim/testsuite/sim/rx/emsba.s
@@ -0,0 +1,24 @@
+# RX testcase for emsba
+# mach: rxv2
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+ mov #100, r1
+ mov #200, r2
+ emsba r1,r2,a0
+ mvfaclo #0,a0,r1
+ test_h_gr32 -20000 r1
+ mvfachi #0,a0,r1
+ test_h_gr32 -1 r1
+ mov #300, r1
+ mov #200, r2
+ emsba r1,r2,a1
+ mvfaclo #0,a1,r1
+ test_h_gr32 -60000 r1
+ mvfachi #0,a1,r1
+ test_h_gr32 -1 r1
+
+ pass
+
diff --git a/sim/testsuite/sim/rx/emul.s b/sim/testsuite/sim/rx/emul.s
new file mode 100644
index 0000000..15c65dc
--- /dev/null
+++ b/sim/testsuite/sim/rx/emul.s
@@ -0,0 +1,92 @@
+# RX testcase for emul
+# mach: all
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+emul_imm8:
+ mov #0xf0000001,r1
+ emul #0x10,r1
+ test_h_gr32 0x10 r1
+ test_h_gr32 0xffffffff r2
+emul_imm16:
+ emul #1000,r1
+ test_h_gr32 16000 r1
+ test_h_gr32 0 r2
+emul_imm24:
+ mov.l #0x10000,r1
+ emul #0x10000,r1
+ test_h_gr32 0 r1
+ test_h_gr32 1 r2
+emul_imm32:
+ mov.l #0x10,r1
+ emul #0x10000000,r1
+ test_h_gr32 0 r1
+ test_h_gr32 1 r2
+emul_reg:
+ mov #5, r1
+ mov r1,r2
+ emul r2,r1
+ test_h_gr32 25 r1
+ test_h_gr32 0 r2
+emul_mem_ind:
+ mov.l #val, r2
+ emul [r2].l,r1
+ test_h_gr32 50 r1
+ test_h_gr32 0 r2
+emul_mem_dsp8:
+ mov.l #val-4, r2
+ emul 4[r2].l,r1
+ test_h_gr32 100 r1
+ test_h_gr32 0 r2
+emul_mem_dsp16:
+ mov.l #val-0x1000, r2
+ emul 0x1000[r2].l,r1
+ test_h_gr32 200 r1
+ test_h_gr32 0 r2
+emulu_imm8:
+ mov #0xf0000001,r1
+ emulu #0x10,r1
+ test_h_gr32 0x10 r1
+ test_h_gr32 0xf r2
+emulu_imm16:
+ emulu #1000,r1
+ test_h_gr32 16000 r1
+ test_h_gr32 0 r2
+emulu_imm24:
+ mov.l #0x10000,r1
+ emulu #0x10000,r1
+ test_h_gr32 0 r1
+ test_h_gr32 1 r2
+emulu_imm32:
+ mov.l #0x10,r1
+ emulu #0x10000000,r1
+ test_h_gr32 0 r1
+ test_h_gr32 1 r2
+emulu_reg:
+ mov #-5, r1
+ mov r1,r2
+ emul r2,r1
+ test_h_gr32 25 r1
+ test_h_gr32 0 r2
+emulu_mem_ind:
+ mov.l #val, r2
+ emulu [r2].l,r1
+ test_h_gr32 50 r1
+ test_h_gr32 0 r2
+emulu_mem_dsp8:
+ mov.l #val-4, r2
+ emulu 4[r2].l,r1
+ test_h_gr32 100 r1
+ test_h_gr32 0 r2
+emulu_mem_dsp16:
+ mov.l #val-0x1000, r2
+ emulu 0x1000[r2].l,r1
+ test_h_gr32 200 r1
+ test_h_gr32 0 r2
+
+ pass
+
+ .data
+val: .long 2
diff --git a/sim/testsuite/sim/rx/emula.s b/sim/testsuite/sim/rx/emula.s
new file mode 100644
index 0000000..44fbd8a
--- /dev/null
+++ b/sim/testsuite/sim/rx/emula.s
@@ -0,0 +1,24 @@
+# RX testcase for emula
+# mach: rxv2
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+ mov #100, r1
+ mov #200, r2
+ emula r1,r2,a0
+ mvfaclo #0,a0,r1
+ test_h_gr32 20000 r1
+ mvfachi #0,a0,r1
+ test_h_gr32 0 r1
+ mov #300, r1
+ mov #200, r2
+ emula r1,r2,a1
+ mvfaclo #0,a1,r1
+ test_h_gr32 60000 r1
+ mvfachi #0,a1,r1
+ test_h_gr32 0 r1
+
+ pass
+
diff --git a/sim/testsuite/sim/rx/fadd.s b/sim/testsuite/sim/rx/fadd.s
new file mode 100644
index 0000000..5bab004
--- /dev/null
+++ b/sim/testsuite/sim/rx/fadd.s
@@ -0,0 +1,41 @@
+# RX testcase for fadd
+# mach: all
+# as(rx): --muse-conventional-section-names --defsym cpu=1
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+fadd_imm:
+ mov #1.0,r1
+ fadd #2.0,r1
+ test_h_gr32 3.0 r1
+fadd_reg:
+ mov.l #4.0,r2
+ fadd r2,r1
+ test_h_gr32 7.0 r1
+fadd_mem_ind:
+ mov.l #val, r2
+ fadd [r2].l,r1
+ test_h_gr32 8.0 r1
+fadd_mem_dsp8:
+ mov.l #val-4, r2
+ fadd 4[r2].l,r1
+ test_h_gr32 9.0 r1
+fadd_mem_dsp16:
+ mov.l #val-0x1000, r2
+ fadd 0x1000[r2].l,r1
+ test_h_gr32 10.0 r1
+ .if cpu == 2
+fadd3_reg:
+ mov.l #4.0,r2
+ mov.l #1.0,r3
+ fadd r2,r3,r1
+ test_h_gr32 5.0 r1
+ .endif
+
+ pass
+
+ .data
+val: .float 1.0
+
diff --git a/sim/testsuite/sim/rx/fcmp.s b/sim/testsuite/sim/rx/fcmp.s
new file mode 100644
index 0000000..264de4d
--- /dev/null
+++ b/sim/testsuite/sim/rx/fcmp.s
@@ -0,0 +1,37 @@
+# RX testcase for fcmp
+# mach: all
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+fcmp_imm:
+ mov #1.0,r1
+ fcmp #2.0,r1
+ test_zero_clear
+ test_neg_set
+fcmp_reg:
+ mov.l #4.0,r2
+ fcmp r2,r1
+ test_zero_clear
+ test_neg_set
+fcmp_mem_ind:
+ mov.l #val, r2
+ fcmp [r2].l,r1
+ test_zero_set
+ test_neg_clear
+fcmp_mem_dsp8:
+ mov.l #val-4, r2
+ fcmp 4[r2].l,r1
+ test_zero_set
+ test_neg_clear
+fcmp_mem_dsp16:
+ mov.l #val-0x1000, r2
+ fcmp 0x1000[r2].l,r1
+ test_zero_set
+ test_neg_clear
+ pass
+
+ .data
+val: .float 1.0
+
diff --git a/sim/testsuite/sim/rx/fdiv.s b/sim/testsuite/sim/rx/fdiv.s
new file mode 100644
index 0000000..9e4f390
--- /dev/null
+++ b/sim/testsuite/sim/rx/fdiv.s
@@ -0,0 +1,43 @@
+# RX testcase for fdiv
+# mach: all
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+fdiv_imm:
+ mov #100.0,r1
+ fdiv #2.0,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 50.0 r1
+fdiv_reg:
+ mov.l #2.0,r2
+ fdiv r2,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 25.0 r1
+fdiv_mem_ind:
+ mov.l #val, r2
+ fdiv [r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 12.5 r1
+fdiv_mem_dsp8:
+ mov.l #val-4, r2
+ fdiv 4[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 6.25 r1
+fdiv_mem_dsp16:
+ mov.l #val-0x1000, r2
+ fdiv 0x1000[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 3.125 r1
+
+ pass
+
+ .data
+val: .float 2.0
+
diff --git a/sim/testsuite/sim/rx/fmul.s b/sim/testsuite/sim/rx/fmul.s
new file mode 100644
index 0000000..9988591
--- /dev/null
+++ b/sim/testsuite/sim/rx/fmul.s
@@ -0,0 +1,51 @@
+# RX testcase for fmul
+# mach: all
+# as(rx): --muse-conventional-section-names --defsym cpu=1
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+fmul_imm:
+ mov #10.0,r1
+ fmul #2.0,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 20.0 r1
+fmul_reg:
+ mov.l #2.0,r2
+ fmul r2,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 40.0 r1
+fmul_mem_ind:
+ mov.l #val, r2
+ fmul [r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 80.0 r1
+fmul_mem_dsp8:
+ mov.l #val-4, r2
+ fmul 4[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 160.0 r1
+fmul_mem_dsp16:
+ mov.l #val-0x1000, r2
+ fmul 0x1000[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 320.0 r1
+ .if cpu == 2
+fmul3_reg:
+ mov.l #4.0,r2
+ mov.l #6.0,r3
+ fmul r3,r2,r1
+ test_h_gr32 24.0 r1
+ .endif
+
+ pass
+
+ .data
+val: .float 2.0
+
diff --git a/sim/testsuite/sim/rx/fsqrt.s b/sim/testsuite/sim/rx/fsqrt.s
new file mode 100644
index 0000000..3c1d52d
--- /dev/null
+++ b/sim/testsuite/sim/rx/fsqrt.s
@@ -0,0 +1,23 @@
+# RX testcase for add
+# mach: rxv2
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+ mov #4.0,r2
+ fsqrt r2,r1
+ test_h_gr32 2.0 r1
+ mov #val,r2
+ fsqrt [r2],r1
+ test_h_gr32 3.0 r1
+ fsqrt 4[r2],r1
+ test_h_gr32 4.0 r1
+ mov #val - 0x1000 + 8,r2
+ fsqrt 0x1000[r2],r1
+ test_h_gr32 5.0 r1
+
+ pass
+
+ .data
+val: .float 9,16,25
diff --git a/sim/testsuite/sim/rx/fsub.s b/sim/testsuite/sim/rx/fsub.s
new file mode 100644
index 0000000..b804f3f
--- /dev/null
+++ b/sim/testsuite/sim/rx/fsub.s
@@ -0,0 +1,51 @@
+# RX testcase for fsub
+# mach: all
+# as(rx): --muse-conventional-section-names --defsym cpu=1
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+fsub_imm:
+ mov #10.0,r1
+ fsub #2.0,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 8.0 r1
+fsub_reg:
+ mov.l #2.0,r2
+ fsub r2,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 6.0 r1
+fsub_mem_ind:
+ mov.l #val, r2
+ fsub [r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 4.0 r1
+fsub_mem_dsp8:
+ mov.l #val-4, r2
+ fsub 4[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2.0 r1
+fsub_mem_dsp16:
+ mov.l #val-0x1000, r2
+ fsub 0x1000[r2].l,r1
+ test_zero_set
+ test_neg_clear
+ test_h_gr32 0.0 r1
+ .if cpu == 2
+fsub3_reg:
+ mov.l #4.0,r2
+ mov.l #1.0,r3
+ fsub r3,r2,r1
+ test_h_gr32 3.0 r1
+ .endif
+
+ pass
+
+ .data
+val: .float 2.0
+
diff --git a/sim/testsuite/sim/rx/ftoi.s b/sim/testsuite/sim/rx/ftoi.s
new file mode 100644
index 0000000..6e21366
--- /dev/null
+++ b/sim/testsuite/sim/rx/ftoi.s
@@ -0,0 +1,37 @@
+# RX testcase for ftoi
+# mach: all
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ftoi_reg:
+ mov.l #12.34,r2
+ ftoi r2,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 12 r1
+ftoi_mem_ind:
+ mov.l #val, r2
+ ftoi [r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2 r1
+ftoi_mem_dsp8:
+ mov.l #val-4, r2
+ ftoi 4[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2 r1
+ftoi_mem_dsp16:
+ mov.l #val-0x1000, r2
+ ftoi 0x1000[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2 r1
+
+ pass
+
+ .data
+val: .float 2.345
+
diff --git a/sim/testsuite/sim/rx/ftou.s b/sim/testsuite/sim/rx/ftou.s
new file mode 100644
index 0000000..434933d
--- /dev/null
+++ b/sim/testsuite/sim/rx/ftou.s
@@ -0,0 +1,37 @@
+# RX testcase for ftou
+# mach: rxv2
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+ftou_reg:
+ mov.l #2147483648.0,r2
+ ftou r2,r1
+ test_zero_clear
+ test_neg_set
+ test_h_gr32 -2147483648 r1
+ftou_mem_ind:
+ mov.l #val, r2
+ ftou [r2].l,r1
+ test_zero_clear
+ test_neg_set
+ test_h_gr32 -2147483648 r1
+ftou_mem_dsp8:
+ mov.l #val-4, r2
+ ftou 4[r2].l,r1
+ test_zero_clear
+ test_neg_set
+ test_h_gr32 -2147483648 r1
+ftou_mem_dsp16:
+ mov.l #val-0x1000, r2
+ ftou 0x1000[r2].l,r1
+ test_zero_clear
+ test_neg_set
+ test_h_gr32 -2147483648 r1
+
+ pass
+
+ .data
+val: .float 2147483648.0
+
diff --git a/sim/testsuite/sim/rx/itof.s b/sim/testsuite/sim/rx/itof.s
new file mode 100644
index 0000000..8c2cf99
--- /dev/null
+++ b/sim/testsuite/sim/rx/itof.s
@@ -0,0 +1,37 @@
+# RX testcase for itof
+# mach: all
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+itof_reg:
+ mov.l #12,r2
+ itof r2,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 12.0 r1
+itof_mem_ind:
+ mov.l #val, r2
+ itof [r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2.0 r1
+itof_mem_dsp8:
+ mov.l #val-4, r2
+ itof 4[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2.0 r1
+itof_mem_dsp16:
+ mov.l #val-0x1000, r2
+ itof 0x1000[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2.0 r1
+
+ pass
+
+ .data
+val: .long 2
+
diff --git a/sim/testsuite/sim/rx/jmp.s b/sim/testsuite/sim/rx/jmp.s
new file mode 100644
index 0000000..4a3d576
--- /dev/null
+++ b/sim/testsuite/sim/rx/jmp.s
@@ -0,0 +1,12 @@
+# RX testcase for jmp
+# mach: all
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ mov #1f,r1
+ jmp r1
+ fail
+1:
+ pass
diff --git a/sim/testsuite/sim/rx/machilo.s b/sim/testsuite/sim/rx/machilo.s
new file mode 100644
index 0000000..4955905
--- /dev/null
+++ b/sim/testsuite/sim/rx/machilo.s
@@ -0,0 +1,53 @@
+# RX testcase for add
+# mach: all
+# as(rx): --muse-conventional-section-names --defsym cpu=1
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+ sub r1,r1
+ mvtachi r1
+ mvtaclo r1
+ mov #0x20000,r1
+ mov #0x30000,r2
+ machi r1,r2
+ mvfacmi r1
+ test_h_gr32 6 r1
+ mvfachi r1
+ test_h_gr32 0 r1
+ mov #0x3,r1
+ mov #0x4,r2
+ maclo r1,r2
+ mvfacmi r1
+ test_h_gr32 0x12 r1
+ mvfachi r1
+ test_h_gr32 0 r1
+ .if cpu == 2
+ sub r1,r1
+ mvtachi r1,a1
+ mvtaclo r1,a1
+ mvtacgu r1,a1
+ mov #0x20000,r1
+ mov #0x30000,r2
+ machi r1,r2,a1
+ mvfacmi #0,a1,r1
+ test_h_gr32 6 r1
+ mvfachi #0,a1,r1
+ test_h_gr32 0 r1
+ mov #0x3,r1
+ mov #0x4,r2
+ maclo r1,r2,a1
+ mvfacmi #0,a1,r1
+ test_h_gr32 0x12 r1
+ mvfachi #0,a1,r1
+ test_h_gr32 0 r1
+ mov #0x4,r1
+ mov #0x50000,r2
+ maclh r1,r2,a1
+ mvfacmi #0,a1,r1
+ test_h_gr32 0x26 r1
+ mvfachi #0,a1,r1
+ test_h_gr32 0 r1
+ .endif
+ pass
diff --git a/sim/testsuite/sim/rx/max.s b/sim/testsuite/sim/rx/max.s
new file mode 100644
index 0000000..b27f3cd
--- /dev/null
+++ b/sim/testsuite/sim/rx/max.s
@@ -0,0 +1,45 @@
+# RX testcase for max
+# mach: all
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+max_imm8:
+ mov #2,r1
+ max #1,r1
+ test_h_gr32 2 r1
+max_imm16:
+ mov #0x8000,r1
+ max #0x1000,r1
+ test_h_gr32 0x8000 r1
+max_imm24:
+ mov #0x100000,r1
+ max #0x200000,r1
+ test_h_gr32 0x200000 r1
+max_imm32:
+ mov #0x80000000,r1
+ max #0x40000000,r1
+ test_h_gr32 0x40000000 r1
+max_reg:
+ mov #0x80000000,r2
+ max r2,r1
+ test_h_gr32 0x40000000 r1
+max_mem_ind:
+ mov #10,r1
+ mov #val, r2
+ max [r2],r1
+ test_h_gr32 10 r1
+max_mem_dsp8:
+ mov #val-4, r2
+ max 4[r2],r1
+ test_h_gr32 10 r1
+max_mem_dsp16:
+ mov #val-0x1000, r2
+ max 0x1000[r2],r1
+ test_h_gr32 10 r1
+
+ pass
+
+ .data
+val: .long 2
diff --git a/sim/testsuite/sim/rx/min.s b/sim/testsuite/sim/rx/min.s
new file mode 100644
index 0000000..ebfe730
--- /dev/null
+++ b/sim/testsuite/sim/rx/min.s
@@ -0,0 +1,45 @@
+# RX testcase for min
+# mach: all
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+min_imm8:
+ mov #2,r1
+ min #1,r1
+ test_h_gr32 1 r1
+min_imm16:
+ mov #0x8000,r1
+ min #0x1000,r1
+ test_h_gr32 0x1000 r1
+min_imm24:
+ mov #0x100000,r1
+ min #0x200000,r1
+ test_h_gr32 0x100000 r1
+min_imm32:
+ mov #0x80000000,r1
+ min #0x40000000,r1
+ test_h_gr32 0x80000000 r1
+min_reg:
+ mov #0x80000000,r2
+ min r2,r1
+ test_h_gr32 0x80000000 r1
+min_mem_ind:
+ mov #2,r1
+ mov #val, r2
+ min [r2],r1
+ test_h_gr32 2 r1
+min_mem_dsp8:
+ mov #val-4, r2
+ min 4[r2],r1
+ test_h_gr32 2 r1
+min_mem_dsp16:
+ mov #val-0x1000, r2
+ min 0x1000[r2],r1
+ test_h_gr32 2 r1
+
+ pass
+
+ .data
+val: .long 10
diff --git a/sim/testsuite/sim/rx/mov.s b/sim/testsuite/sim/rx/mov.s
new file mode 100644
index 0000000..a998e1f
--- /dev/null
+++ b/sim/testsuite/sim/rx/mov.s
@@ -0,0 +1,196 @@
+# RX testcase for mov
+# mach: all
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ set_gr_a5a5 1
+ mov #val,r2
+ mov.b r1,[r2]
+ mov.w r1,2[r2]
+ mov.l r1,4[r2]
+ mov.b [r2],r1
+ test_h_gr32 0xffffffa5 r1
+ mov.w 2[r2],r1
+ test_h_gr32 0xffffa5a5 r1
+ mov.l 4[r2],r1
+ test_h_gr32 0xa5a5a5a5 r1
+ mov #1,r1
+ test_h_gr32 1 r1
+ mov.b #0x01,[r2]
+ mov.w #0x23,2[r2]
+ mov.l #0x45,4[r2]
+ mov.b [r2],r1
+ test_h_gr32 0x01 r1
+ mov.w 2[r2],r1
+ test_h_gr32 0x23 r1
+ mov.l 4[r2],r1
+ test_h_gr32 0x45 r1
+ mov #0x10,r1
+ test_h_gr32 0x10 r1
+ mov #0x80,r1
+ test_h_gr32 0x80 r1
+ mov #0x8000,r1
+ test_h_gr32 0x8000 r1
+ mov #0x800000,r1
+ test_h_gr32 0x800000 r1
+ mov #0x80000000,r1
+ test_h_gr32 0x80000000 r1
+ mov #0x80,r1
+ mov.b r1,r2
+ test_h_gr32 0xffffff80 r2
+ mov #0x8000,r1
+ mov.w r1,r2
+ test_h_gr32 0xffff8000 r2
+ mov #0x80000000,r1
+ mov.l r1,r2
+ test_h_gr32 0x80000000 r2
+ mov.l #val,r2
+ mov.l #val-4,r3
+ mov.l #val-0x1000,r4
+ mov.b #0x01,[r2]
+ mov.b [r2],r1
+ test_h_gr32 0x01 r1
+ mov.b #0x23,4[r3]
+ mov.b [r2],r1
+ test_h_gr32 0x23 r1
+ mov.b #0x45,0x1000[r4]
+ mov.b [r2],r1
+ test_h_gr32 0x45 r1
+ mov.w #0x80,[r2]
+ mov.w [r2],r1
+ test_h_gr32 0x80 r1
+ mov.w #0x80,4[r3]
+ mov.w [r2],r1
+ test_h_gr32 0x80 r1
+ mov.w #0x80,0x1000[r4]
+ mov.w [r2],r1
+ test_h_gr32 0x80 r1
+ mov.w #0x1234,[r2]
+ mov.w [r2],r1
+ test_h_gr32 0x1234 r1
+ mov.w #0x4567,4[r3]
+ mov.w [r2],r1
+ test_h_gr32 0x4567 r1
+ mov.w #0x89ab,0x1000[r4]
+ mov.w [r2],r1
+ test_h_gr32 0xffff89ab r1
+ mov.l #0x123456,[r2]
+ mov.l [r2],r1
+ test_h_gr32 0x123456 r1
+ mov.l #0x456789,4[r3]
+ mov.l [r2],r1
+ test_h_gr32 0x456789 r1
+ mov.l #0x89abcd,0x1000[r4]
+ mov.l [r2],r1
+ test_h_gr32 0x89abcd r1
+ mov.l #0x12345678,[r2]
+ mov.l [r2],r1
+ test_h_gr32 0x12345678 r1
+ mov.l #0x89abcdef,4[r3]
+ mov.l [r2],r1
+ test_h_gr32 0x89abcdef r1
+ mov.l #0x76543210,0x1000[r4]
+ mov.l [r2],r1
+ test_h_gr32 0x876543210 r1
+ mov #4,r1
+ mov.b r1,[r1,r3]
+ mov.b [r2],r1
+ test_h_gr32 4 r1
+ mov #2,r1
+ mov.w r1,[r1,r3]
+ mov.w [r2],r1
+ test_h_gr32 2 r1
+ mov #0x1000/4,r1
+ mov.l r1,[r1,r4]
+ mov.l [r2],r1
+ test_h_gr32 0x1000/4 r1
+ mov #val+4,r5
+ mov.b #0x12,[r2]
+ mov.b [r2],[r5]
+ mov.b [r5],r1
+ test_h_gr32 0x12 r1
+ mov.w #0x1234,[r2]
+ mov.w [r2],[r5]
+ mov.w [r5],r1
+ test_h_gr32 0x1234 r1
+ mov.l #0x12345678,[r2]
+ mov.l [r2],[r5]
+ mov.l [r5],r1
+ test_h_gr32 0x12345678 r1
+ mov.b #0x12,[r2]
+ mov.b [r2],8[r3]
+ mov.b 8[r3],r1
+ test_h_gr32 0x12 r1
+ mov.w #0x1234,[r2]
+ mov.w [r2],8[r3]
+ mov.w 8[r3],r1
+ test_h_gr32 0x1234 r1
+ mov.l #0x12345678,[r2]
+ mov.l [r2],8[r3]
+ mov.l 8[r3],r1
+ test_h_gr32 0x12345678 r1
+ mov.b #0x12,[r2]
+ mov.b [r2],0x1004[r4]
+ mov.b 0x1004[r4],r1
+ test_h_gr32 0x12 r1
+ mov.w #0x1234,[r2]
+ mov.w [r2],0x1004[r4]
+ mov.w 0x1004[r4],r1
+ test_h_gr32 0x1234 r1
+ mov.l #0x12345678,[r2]
+ mov.l [r2],0x1004[r4]
+ mov.l 0x1004[r4],r1
+ test_h_gr32 0x12345678 r1
+ mov.b #0x12,[r2]
+ mov.b 4[r3],0x1004[r4]
+ mov.b 0x1004[r4],r1
+ test_h_gr32 0x12 r1
+ mov.w #0x1234,[r2]
+ mov.w 4[r3],0x1004[r4]
+ mov.w 0x1004[r4],r1
+ test_h_gr32 0x1234 r1
+ mov.l #0x12345678,[r2]
+ mov.l 4[r3],0x1004[r4]
+ mov.l 0x1004[r4],r1
+ test_h_gr32 0x12345678 r1
+ mov.b #0x12,[r2]
+ mov.b 0x1000[r4],4[r3]
+ mov.b 4[r3],r1
+ test_h_gr32 0x12 r1
+ mov.w #0x1234,[r2]
+ mov.w 0x1000[r4],4[r3]
+ mov.w 4[r3],r1
+ test_h_gr32 0x1234 r1
+ mov.l #0x12345678,[r2]
+ mov.l 0x1000[r4],4[r3]
+ mov.l 4[r3],r1
+ test_h_gr32 0x12345678 r1
+ mov #val+9,r1
+ mov #0x12345678,r2
+ mov.l r2,[-r1]
+ mov.w r2,[-r1]
+ mov.b r2,[-r1]
+ mov.b [r1+],r2
+ test_h_gr32 0x78 r2
+ mov.w [r1+],r2
+ test_h_gr32 0x5678 r2
+ mov.l [r1+],r2
+ test_h_gr32 0x12345678 r2
+ mov #val,r1
+ mov #0x12345678,r2
+ mov.l r2,[r1+]
+ mov.w r2,[r1+]
+ mov.b r2,[r1+]
+ mov.b [-r1],r2
+ test_h_gr32 0x78 r2
+ mov.w [-r1],r2
+ test_h_gr32 0x5678 r2
+ mov.l [-r1],r2
+ test_h_gr32 0x12345678 r2
+
+ pass
+
+ .data
+val: .space 16
diff --git a/sim/testsuite/sim/rx/movlico.s b/sim/testsuite/sim/rx/movlico.s
new file mode 100644
index 0000000..3c9c8fe
--- /dev/null
+++ b/sim/testsuite/sim/rx/movlico.s
@@ -0,0 +1,22 @@
+# RX testcase for add
+# mach: rxv2
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+ mov.l #0x12345678,r1
+ mov.l #val,r2
+ movco r1,[r2]
+ test_h_gr32 1 r1
+ movli [r2],r1
+ mov #0x5a5a5a5a,r1
+ movco r1,[r2]
+ test_h_gr32 0 r1
+ mov.l [r2],r1
+ test_h_gr32 0x5a5a5a5a r1
+
+ pass
+
+ .data
+val: .long 0xa5a5a5a5
diff --git a/sim/testsuite/sim/rx/movu.s b/sim/testsuite/sim/rx/movu.s
new file mode 100644
index 0000000..33d2433
--- /dev/null
+++ b/sim/testsuite/sim/rx/movu.s
@@ -0,0 +1,67 @@
+# RX testcase for movu
+# mach: all
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ set_gr_a5a5 1
+ mov #valb,r2
+ movu.b [r2],r1
+ test_h_gr32 0x80 r1
+ mov #valw,r2
+ movu.w [r2],r1
+ test_h_gr32 0x8000 r1
+ mov #0x8888,r2
+ movu.b r2,r1
+ test_h_gr32 0x88 r1
+ movu.w r2,r1
+ test_h_gr32 0x8888 r1
+ mov #valb,r2
+ movu.b [r2],r10
+ test_h_gr32 0x80 r10
+ mov #valb-0x40,r2
+ movu.b 0x40[r2],r10
+ test_h_gr32 0x80 r10
+ mov #valb-0x1000,r2
+ movu.b 0x1000[r2],r10
+ test_h_gr32 0x80 r10
+ mov #valb-0x1000,r2
+ mov #0x1000,r3
+ movu.b [r3,r2],r10
+ test_h_gr32 0x80 r10
+ mov #valw,r2
+ movu.w [r2],r10
+ test_h_gr32 0x8000 r10
+ mov #valw-0x40,r2
+ movu.w 0x40[r2],r10
+ test_h_gr32 0x8000 r10
+ mov #valw-0x1000,r2
+ movu.w 0x1000[r2],r10
+ test_h_gr32 0x8000 r10
+ mov #valw-0x1000,r2
+ mov #0x1000/2,r3
+ movu.w [r3,r2],r10
+ test_h_gr32 0x8000 r10
+ mov #valb,r2
+ movu.b [r2+],r1
+ test_h_gr32 0x80 r1
+ test_h_gr32 valb+1 r2
+ mov #valw,r2
+ movu.w [r2+],r1
+ test_h_gr32 0x8000 r1
+ test_h_gr32 valw+2 r2
+ mov #valb+1,r2
+ movu.b [-r2],r1
+ test_h_gr32 0x80 r1
+ test_h_gr32 valb r2
+ mov #valw+2,r2
+ movu.w [-r2],r1
+ test_h_gr32 0x8000 r1
+ test_h_gr32 valw r2
+
+ pass
+
+ .data
+valw: .word 0x8000
+valb: .byte 0x80
diff --git a/sim/testsuite/sim/rx/msbhilo.s b/sim/testsuite/sim/rx/msbhilo.s
new file mode 100644
index 0000000..3a21981
--- /dev/null
+++ b/sim/testsuite/sim/rx/msbhilo.s
@@ -0,0 +1,43 @@
+# RX testcase for add
+# mach: rxv2
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+ mov #0x20000,r1
+ mov #0x30000,r2
+ msbhi r1,r2,a0
+ mvfacmi r1
+ test_h_gr32 -6 r1
+ mvfachi r1
+ test_h_gr32 -1 r1
+ mov #0x3,r1
+ mov #0x4,r2
+ msblo r1,r2,a0
+ mvfacmi r1
+ test_h_gr32 -18 r1
+ mvfachi r1
+ test_h_gr32 -1 r1
+ mov #0x20000,r1
+ mov #0x30000,r2
+ msbhi r1,r2,a1
+ mvfacmi #0,a1,r1
+ test_h_gr32 -6 r1
+ mvfachi #0,a1,r1
+ test_h_gr32 -1 r1
+ mov #0x3,r1
+ mov #0x4,r2
+ msblo r1,r2,a1
+ mvfacmi #0,a1,r1
+ test_h_gr32 -18 r1
+ mvfachi #0,a1,r1
+ test_h_gr32 -1 r1
+ mov #0x4,r1
+ mov #0x50000,r2
+ msblh r1,r2,a1
+ mvfacmi #0,a1,r1
+ test_h_gr32 -38 r1
+ mvfachi #0,a1,r1
+ test_h_gr32 -1 r1
+ pass
diff --git a/sim/testsuite/sim/rx/mul.s b/sim/testsuite/sim/rx/mul.s
new file mode 100644
index 0000000..7784f27
--- /dev/null
+++ b/sim/testsuite/sim/rx/mul.s
@@ -0,0 +1,52 @@
+# RX testcase for mul
+# mach: all
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+mul_imm4:
+ mov.l #3,r1
+ mul #3,r1
+ test_h_gr32 9 r1
+mul_imm8:
+ mul #20,r1
+ test_h_gr32 180 r1
+mul_imm16:
+ mul #1000,r1
+ test_h_gr32 180000 r1
+mul_imm24:
+ mov.l #3,r1
+ mul #0x10000,r1
+ test_h_gr32 0x30000 r1
+mul_imm32:
+ mov.l #3,r1
+ mul #0x1000000,r1
+ test_h_gr32 0x3000000 r1
+mul_reg:
+ mov #5, r1
+ mov r1,r2
+ mul r2,r1
+ test_h_gr32 25 r1
+mul_mem_ind:
+ mov.l #val, r2
+ mul [r2].l,r1
+ test_h_gr32 50 r1
+mul_mem_dsp8:
+ mov.l #val-4, r2
+ mul 4[r2].l,r1
+ test_h_gr32 100 r1
+mul_mem_dsp16:
+ mov.l #val-0x1000, r2
+ mul 0x1000[r2].l,r1
+ test_h_gr32 200 r1
+mul3_reg:
+ mov #6, r1
+ mov r1,r2
+ mul r1,r2,r3
+ test_h_gr32 36 r3
+
+ pass
+
+ .data
+val: .long 2
diff --git a/sim/testsuite/sim/rx/mulhilo.s b/sim/testsuite/sim/rx/mulhilo.s
new file mode 100644
index 0000000..979ea75
--- /dev/null
+++ b/sim/testsuite/sim/rx/mulhilo.s
@@ -0,0 +1,54 @@
+# RX testcase for add
+# mach: all
+# as(rx): --muse-conventional-section-names --defsym cpu=1
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+ sub r1,r1
+ mvtachi r1
+ mvtaclo r1
+ mov #0x20000,r1
+ mov #0x30000,r2
+ mulhi r1,r2
+ mvfacmi r1
+ test_h_gr32 0x6 r1
+ mvfachi r1
+ test_h_gr32 0 r1
+ mov #0x3,r1
+ mov #0x4,r2
+ mullo r1,r2
+ mvfacmi r1
+ test_h_gr32 0xc r1
+ mvfachi r1
+ test_h_gr32 0 r1
+ .if cpu == 2
+ sub r1,r1
+ mvtachi r1,a1
+ mvtaclo r1,a1
+ mvtacgu r1,a1
+ mov #0x20000,r1
+ mov #0x30000,r2
+ mulhi r1,r2,a1
+ mvfacmi #0,a1,r1
+ test_h_gr32 0x6 r1
+ mvfachi #0,a1,r1
+ test_h_gr32 0 r1
+ mov #0x3,r1
+ mov #0x4,r2
+ mullo r1,r2,a1
+ mvfacmi #0,a1,r1
+ test_h_gr32 0xc r1
+ mvfachi #0,a1,r1
+ test_h_gr32 0 r1
+ mov #0x4,r1
+ mov #0x50000,r2
+ mullh r1,r2,a1
+ mvfacmi #0,a1,r1
+ test_h_gr32 0x14 r1
+ mvfachi #0,a1,r1
+ test_h_gr32 0 r1
+ .endif
+
+ pass
diff --git a/sim/testsuite/sim/rx/mvacc.s b/sim/testsuite/sim/rx/mvacc.s
new file mode 100644
index 0000000..ef8fc3a
--- /dev/null
+++ b/sim/testsuite/sim/rx/mvacc.s
@@ -0,0 +1,28 @@
+# RX testcase for add
+# mach: all
+# as(rx): --muse-conventional-section-names --defsym cpu=1
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+ mov #0x12345678,r1
+ mvtachi r1
+ mvtaclo r1
+ mvfacmi r1
+ test_h_gr32 0x56781234 r1
+ mvfachi r1
+ test_h_gr32 0x12345678 r1
+ .if cpu == 2
+ mvtacgu r1,a0
+ mvfacmi #1,a0,r1
+ test_h_gr32 0xacf02468 r1
+ mvfachi #2,a0,r1
+ test_h_gr32 0x48d159e0 r1
+ mvfacgu #0,a0,r1
+ test_h_gr32 0x78 r1
+ mvfaclo #0,a0,r1
+ test_h_gr32 0x12345678 r1
+ .endif
+
+ pass
diff --git a/sim/testsuite/sim/rx/mvftc.s b/sim/testsuite/sim/rx/mvftc.s
new file mode 100644
index 0000000..41e51f0
--- /dev/null
+++ b/sim/testsuite/sim/rx/mvftc.s
@@ -0,0 +1,36 @@
+# RX testcase for mvfc/mvtc
+# mach: all
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ mov #0x1,r1
+ mvtc r1,ISP
+ mov #0x2,r1
+ mvtc r1,USP
+ mov #0x3,r1
+ mvtc r1,INTB
+ mov #0x4,r1
+ mvtc r1,BPC
+ mov #0x5,r1
+ mvtc r1,BPSW
+ mov #0x6,r1
+ mvtc r1,FINTV
+ mvfc ISP,r1
+ test_h_gr32 1 r1
+ mvfc USP,r1
+ test_h_gr32 2 r1
+ mvfc INTB,r1
+ test_h_gr32 3 r1
+ mvfc BPC,r1
+ test_h_gr32 4 r1
+ mvfc BPSW,r1
+ test_h_gr32 5 r1
+ mvfc FINTV,r1
+ test_h_gr32 6 r1
+
+ pass
+
+ .data
+val: .long 2
diff --git a/sim/testsuite/sim/rx/neg.s b/sim/testsuite/sim/rx/neg.s
new file mode 100644
index 0000000..805614b
--- /dev/null
+++ b/sim/testsuite/sim/rx/neg.s
@@ -0,0 +1,17 @@
+# RX testcase for neg
+# mach: all
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ mov #1,r1
+ neg r1
+ test_h_gr32 -1 r1
+ neg r1,r2
+ test_h_gr32 1 r2
+
+ pass
+
+ .data
+val: .long 2
diff --git a/sim/testsuite/sim/rx/not.s b/sim/testsuite/sim/rx/not.s
new file mode 100644
index 0000000..f7ff5c2
--- /dev/null
+++ b/sim/testsuite/sim/rx/not.s
@@ -0,0 +1,17 @@
+# RX testcase for not
+# mach: all
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ mov #1,r1
+ not r1
+ test_h_gr32 0xfffffffe r1
+ not r1,r2
+ test_h_gr32 1 r2
+
+ pass
+
+ .data
+val: .long 2
diff --git a/sim/testsuite/sim/rx/or.s b/sim/testsuite/sim/rx/or.s
new file mode 100644
index 0000000..ef8065e
--- /dev/null
+++ b/sim/testsuite/sim/rx/or.s
@@ -0,0 +1,69 @@
+# RX testcase for or
+# mach: all
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+or_imm4:
+ mov #2,r1
+ or #1,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 3 r1
+or_imm8:
+ or #0x10,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x13 r1
+or_imm16:
+ or #0x1000,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x1013 r1
+or_imm24:
+ or #0x100000,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x101013 r1
+or_imm32:
+ or #0x10000000,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x10101013 r1
+or_reg:
+ mov.l #0x20000000,r2
+ or r2,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x30101013 r1
+or_mem_ind:
+ mov #val, r2
+ or [r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x3010101b r1
+or_mem_dsp8:
+ mov #val-4, r2
+ or 4[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x3010101b r1
+or_mem_dsp16:
+ sub r1,r1
+ mov #val-0x1000, r2
+ or 0x1000[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 8 r1
+or3_reg:
+ mov.l #0x80000000,r2
+ or r2,r1,r3
+ test_zero_clear
+ test_neg_set
+ test_h_gr32 0x80000008 r3
+
+ pass
+
+ .data
+val: .long 8
diff --git a/sim/testsuite/sim/rx/pushpop.s b/sim/testsuite/sim/rx/pushpop.s
new file mode 100644
index 0000000..38b11df
--- /dev/null
+++ b/sim/testsuite/sim/rx/pushpop.s
@@ -0,0 +1,48 @@
+# RX testcase for push/pop
+# mach: all
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ mov #1,r1
+ push.l r1
+ mov #val,r1
+ push [r1]
+ mov #val-4,r1
+ push 4[r1]
+ mov #val-0x1000,r1
+ push 0x1000[r1]
+ pop r4
+ pop r3
+ pop r2
+ pop r1
+ test_h_gr32 1 r1
+ test_h_gr32 2 r2
+ test_h_gr32 2 r3
+ test_h_gr32 2 r4
+ mov #123456,r1
+ mvtc r1,intb
+ pushc intb
+ popc intb
+ mvfc intb,r2
+ test_h_gr32 123456 r2
+ mov #1,r1
+ mov #2,r2
+ mov #3,r3
+ mov #4,r4
+ pushm r1-r4
+ sub r1,r1
+ sub r2,r2
+ sub r3,r3
+ sub r4,r4
+ popm r1-r4
+ test_h_gr32 1 r1
+ test_h_gr32 2 r2
+ test_h_gr32 3 r3
+ test_h_gr32 4 r4
+
+ pass
+
+ .data
+val: .long 2
diff --git a/sim/testsuite/sim/rx/racw.s b/sim/testsuite/sim/rx/racw.s
new file mode 100644
index 0000000..08acf2b
--- /dev/null
+++ b/sim/testsuite/sim/rx/racw.s
@@ -0,0 +1,38 @@
+# RX testcase for add
+# mach: all
+# as(rx): --muse-conventional-section-names --defsym cpu=1
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+ mov #0x40000000,r1
+ mvtaclo r1
+ sub r1,r1
+ mvtachi r1
+ racw #1
+ mvfacmi r1
+ test_h_gr32 0x10000 r1
+ mvfachi r1
+ test_h_gr32 1 r1
+ .if cpu == 2
+ mov #0x40000000,r1
+ mvtaclo r1,a1
+ sub r1,r1
+ mvtachi r1,a1
+ racw #2,a1
+ mvfacmi #0,a1,r1
+ test_h_gr32 0x10000 r1
+ mvfachi #0,a1,r1
+ test_h_gr32 1 r1
+ mov #0x80,r1
+ mvtacgu r1,a1
+ racl #1,a1
+ mvfacmi #0,a1,r1
+ test_h_gr32 0x20000 r1
+ mvfachi #0,a1,r1
+ test_h_gr32 2 r1
+ mvfacgu #0,a1,r1
+ test_h_gr32 0 r1
+ .endif
+ pass
diff --git a/sim/testsuite/sim/rx/rdacw.s b/sim/testsuite/sim/rx/rdacw.s
new file mode 100644
index 0000000..66186ed
--- /dev/null
+++ b/sim/testsuite/sim/rx/rdacw.s
@@ -0,0 +1,19 @@
+# RX testcase for rdacw
+# mach: rxv2
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+ mov.l #-1,r1
+ mvtaclo r1,a0
+ rdacw #2,a0
+ mvfacmi #0,a0,r1
+ test_h_gr32 0x30000 r1
+ mov.l #-1,r1
+ mvtaclo r1,a0
+ rdacl #2,a0
+ mvfacmi #0,a0,r1
+ test_h_gr32 0xf0000 r1
+
+ pass
diff --git a/sim/testsuite/sim/rx/rev.s b/sim/testsuite/sim/rx/rev.s
new file mode 100644
index 0000000..329e277
--- /dev/null
+++ b/sim/testsuite/sim/rx/rev.s
@@ -0,0 +1,14 @@
+# RX testcase for revl/revw
+# mach: all
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ mov #0x12345678,r1
+ revl r1,r2
+ test_h_gr32 0x78563412 r2
+ revw r1,r2
+ test_h_gr32 0x34127856 r2
+
+ pass
diff --git a/sim/testsuite/sim/rx/rmpa.s b/sim/testsuite/sim/rx/rmpa.s
new file mode 100644
index 0000000..c82186b
--- /dev/null
+++ b/sim/testsuite/sim/rx/rmpa.s
@@ -0,0 +1,23 @@
+# RX testcase for rmpa
+# mach: all
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ sub r4,r4
+ sub r5,r5
+ sub r6,r6
+ mov #val1,r1
+ mov #val2,r2
+ mov #10,r3
+ rmpa.w
+ test_h_gr32 110 r4
+ test_h_gr32 0 r5
+ test_h_gr32 0 r6
+ pass
+
+ .data
+val1: .word 1,2,3,4,5,6,7,8,9,10
+val2: .word 10,9,8,7,6,5,4,3,2,1
+
diff --git a/sim/testsuite/sim/rx/rot.s b/sim/testsuite/sim/rx/rot.s
new file mode 100644
index 0000000..e648eff
--- /dev/null
+++ b/sim/testsuite/sim/rx/rot.s
@@ -0,0 +1,46 @@
+# RX testcase for rolc/rorc/rotl/rotr
+# mach: all
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ clear_carry_flag
+ mov.l #0x80000000,r1
+ rolc r1
+ test_carry_set
+ test_zero_set
+ test_neg_clear
+ test_h_gr32 0 r1
+ clear_carry_flag
+ rorc r1
+ test_carry_clear
+ test_zero_set
+ test_neg_clear
+ test_h_gr32 0 r1
+ mov.l #0x80000000,r1
+ rotl #1,r1
+ test_carry_set
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 1 r1
+ mov #1,r2
+ rotl r2,r1
+ test_carry_clear
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2 r1
+ rotr #1,r1
+ test_carry_clear
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 1 r1
+ rotr r2,r1
+ test_carry_set
+ test_zero_clear
+ test_neg_set
+ test_h_gr32 0x80000000 r1
+ pass
+
+ .data
+val: .long 2
diff --git a/sim/testsuite/sim/rx/round.s b/sim/testsuite/sim/rx/round.s
new file mode 100644
index 0000000..4e5ee2c
--- /dev/null
+++ b/sim/testsuite/sim/rx/round.s
@@ -0,0 +1,37 @@
+# RX testcase for round
+# mach: all
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+round_reg:
+ mov.l #12.68,r2
+ round r2,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 13 r1
+round_mem_ind:
+ mov.l #val, r2
+ round [r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2 r1
+round_mem_dsp8:
+ mov.l #val-4, r2
+ round 4[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2 r1
+round_mem_dsp16:
+ mov.l #val-0x1000, r2
+ round 0x1000[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2 r1
+
+ pass
+
+ .data
+val: .float 2.345
+
diff --git a/sim/testsuite/sim/rx/sat.s b/sim/testsuite/sim/rx/sat.s
new file mode 100644
index 0000000..4b58434
--- /dev/null
+++ b/sim/testsuite/sim/rx/sat.s
@@ -0,0 +1,37 @@
+# RX testcase for fadd
+# mach: all
+# as(rx): --muse-conventional-section-names --defsym cpu=1
+
+ .include "testutils.inc"
+
+ start
+sat: sub r1,r1
+ sub r4,r4
+ sub r5,r5
+ sub r6,r6
+ clear_overflow_flag
+ sat r1
+ satr
+ test_h_gr32 0 r1
+ test_h_gr32 0 r6
+ test_h_gr32 0 r5
+ test_h_gr32 0 r4
+
+ set_overflow_flag
+ clear_neg_flag
+ sat r1
+ satr
+ test_h_gr32 0x80000000 r1
+ test_h_gr32 0 r6
+ test_h_gr32 0x7fffffff r5
+ test_h_gr32 0xffffffff r4
+ set_overflow_flag
+ set_neg_flag
+ sat r1
+ satr
+ test_h_gr32 0x7fffffff r1
+ test_h_gr32 0xffffffff r6
+ test_h_gr32 0x80000000 r5
+ test_h_gr32 0x00000000 r4
+
+ pass
diff --git a/sim/testsuite/sim/rx/sbb.s b/sim/testsuite/sim/rx/sbb.s
new file mode 100644
index 0000000..efe48ea
--- /dev/null
+++ b/sim/testsuite/sim/rx/sbb.s
@@ -0,0 +1,46 @@
+# RX testcase for sbb
+# mach: all
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+sbb_reg:
+ clear_carry_flag
+ mov.l #2,r1
+ mov.l #1,r2
+ sbb r2,r1
+ test_zero_set
+ test_carry_set
+ test_neg_clear
+ test_overflow_clear
+ test_h_gr32 0 r1
+sbb_mem_ind:
+ mov.l #val, r2
+ sbb [r2].l,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_set
+ test_overflow_clear
+ test_h_gr32 -1 r1
+sbb_mem_dsp8:
+ mov.l #val-4, r2
+ sbb 4[r2].l,r1
+ test_zero_clear
+ test_carry_set
+ test_neg_set
+ test_overflow_clear
+ test_h_gr32 -2 r1
+sbb_mem_dsp16:
+ mov.l #val-0x1000, r2
+ sbb 0x1000[r2].l,r1
+ test_zero_clear
+ test_carry_set
+ test_neg_set
+ test_overflow_clear
+ test_h_gr32 -3 r1
+
+ pass
+
+ .data
+val: .long 1
diff --git a/sim/testsuite/sim/rx/sccnd.s b/sim/testsuite/sim/rx/sccnd.s
new file mode 100644
index 0000000..ca6eb94
--- /dev/null
+++ b/sim/testsuite/sim/rx/sccnd.s
@@ -0,0 +1,169 @@
+# RX testcase for SCcnd
+# mach: all
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ mov #val,r2
+ mov #val-4,r3
+ mov #val-0x1000,r4
+ mov #10,r1
+ cmp #5,r1
+ scc.b [r2]
+ scc.b 5[r3]
+ scc.b 0x1002[r4]
+ scc.l r5
+ test_h_gr32 1 r5
+ mov.b [r2],r5
+ test_h_gr32 1 r5
+ mov.b 1[r2],r5
+ test_h_gr32 1 r5
+ mov.b 2[r2],r5
+ test_h_gr32 1 r5
+ mov.b #0,[r2]
+ cmp #15,r1
+ scnc.b [r2]
+ scnc.b 5[r3]
+ scnc.b 0x1002[r4]
+ scnc.l r5
+ test_h_gr32 1 r5
+ mov.b [r2],r5
+ test_h_gr32 1 r5
+ mov.b 1[r2],r5
+ test_h_gr32 1 r5
+ mov.b 2[r2],r5
+ test_h_gr32 1 r5
+ mov #-5,r1
+ cmp #-10,r1
+ scgt.b [r2]
+ scgt.b 5[r3]
+ scgt.b 0x1002[r4]
+ scgt.l r5
+ test_h_gr32 1 r5
+ mov.b [r2],r5
+ test_h_gr32 1 r5
+ mov.b 1[r2],r5
+ test_h_gr32 1 r5
+ mov.b 2[r2],r5
+ test_h_gr32 1 r5
+ mov #-5,r1
+ cmp #-5,r1
+ scle.b [r2]
+ scle.b 5[r3]
+ scle.b 0x1002[r4]
+ scle.l r5
+ test_h_gr32 1 r5
+ mov.b [r2],r5
+ test_h_gr32 1 r5
+ mov.b 1[r2],r5
+ test_h_gr32 1 r5
+ mov.b 2[r2],r5
+ test_h_gr32 1 r5
+ mov #-5,r1
+ cmp #-5,r1
+ scge.b [r2]
+ scge.b 5[r3]
+ scge.b 0x1002[r4]
+ scge.l r5
+ test_h_gr32 1 r5
+ mov.b [r2],r5
+ test_h_gr32 1 r5
+ mov.b 1[r2],r5
+ test_h_gr32 1 r5
+ mov.b 2[r2],r5
+ test_h_gr32 1 r5
+ mov #-5,r1
+ cmp #-1,r1
+ sclt.b [r2]
+ sclt.b 5[r3]
+ sclt.b 0x1002[r4]
+ sclt.l r5
+ test_h_gr32 1 r5
+ mov.b [r2],r5
+ test_h_gr32 1 r5
+ mov.b 1[r2],r5
+ test_h_gr32 1 r5
+ mov.b 2[r2],r5
+ test_h_gr32 1 r5
+ mov.l #0xc0000000,r1
+ cmp #0x80000000,r1
+ scgtu.b [r2]
+ scgtu.b 5[r3]
+ scgtu.b 0x1002[r4]
+ scgtu.l r5
+ test_h_gr32 1 r5
+ mov.b [r2],r5
+ test_h_gr32 1 r5
+ mov.b 1[r2],r5
+ test_h_gr32 1 r5
+ mov.b 2[r2],r5
+ test_h_gr32 1 r5
+ mov.l #0xc0000000,r1
+ cmp #0xc0000000,r1
+ scle.b [r2]
+ scle.b 5[r3]
+ scle.b 0x1002[r4]
+ scle.l r5
+ test_h_gr32 1 r5
+ mov.b [r2],r5
+ test_h_gr32 1 r5
+ mov.b 1[r2],r5
+ test_h_gr32 1 r5
+ mov.b 2[r2],r5
+ test_h_gr32 1 r5
+ mov #1,r1
+ tst r1,r1
+ scpz.b [r2]
+ scpz.b 5[r3]
+ scpz.b 0x1002[r4]
+ scpz.l r5
+ test_h_gr32 1 r5
+ mov.b [r2],r5
+ test_h_gr32 1 r5
+ mov.b 1[r2],r5
+ test_h_gr32 1 r5
+ mov.b 2[r2],r5
+ test_h_gr32 1 r5
+ mov #-1,r1
+ tst r1,r1
+ scn.b [r2]
+ scn.b 5[r3]
+ scn.b 0x1002[r4]
+ scn.l r5
+ test_h_gr32 1 r5
+ mov.b [r2],r5
+ test_h_gr32 1 r5
+ mov.b 1[r2],r5
+ test_h_gr32 1 r5
+ mov.b 2[r2],r5
+ test_h_gr32 1 r5
+ set_overflow_flag
+ sco.b [r2]
+ sco.b 5[r3]
+ sco.b 0x1002[r4]
+ sco.l r5
+ test_h_gr32 1 r5
+ mov.b [r2],r5
+ test_h_gr32 1 r5
+ mov.b 1[r2],r5
+ test_h_gr32 1 r5
+ mov.b 2[r2],r5
+ test_h_gr32 1 r5
+ clear_overflow_flag
+ scno.b [r2]
+ scno.b 5[r3]
+ scno.b 0x1002[r4]
+ scno.l r5
+ test_h_gr32 1 r5
+ mov.b [r2],r5
+ test_h_gr32 1 r5
+ mov.b 1[r2],r5
+ test_h_gr32 1 r5
+ mov.b 2[r2],r5
+ test_h_gr32 1 r5
+
+ pass
+
+ .data
+val: .space 8
diff --git a/sim/testsuite/sim/rx/scmpu.s b/sim/testsuite/sim/rx/scmpu.s
new file mode 100644
index 0000000..ec80ec7
--- /dev/null
+++ b/sim/testsuite/sim/rx/scmpu.s
@@ -0,0 +1,26 @@
+# RX testcase for scmpu
+# mach: all
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ mov #str1,r1
+ mov #str1_ok,r2
+ mov #128,r3
+ scmpu
+ test_zero_set
+ test_carry_set
+ mov #str1,r1
+ mov #str1_ng,r2
+ mov #128,r3
+ scmpu
+ test_zero_clear
+ test_carry_set
+
+ pass
+
+ .data
+str1: .asciz "abcdefghijklmnopqrstuvwxyz"
+str1_ok: .asciz "abcdefghijklmnopqrstuvwxyz"
+str1_ng: .asciz "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
diff --git a/sim/testsuite/sim/rx/shlr.s b/sim/testsuite/sim/rx/shlr.s
new file mode 100644
index 0000000..293e643
--- /dev/null
+++ b/sim/testsuite/sim/rx/shlr.s
@@ -0,0 +1,67 @@
+# RX testcase for SCcnd
+# mach: all
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ mov #0x80000000,r1
+ shar #1,r1
+ test_carry_clear
+ test_zero_clear
+ test_neg_set
+ test_overflow_clear
+ test_h_gr32 0xc0000000 r1
+ mov #1,r2
+ shar r2,r1
+ test_carry_clear
+ test_zero_clear
+ test_neg_set
+ test_overflow_clear
+ test_h_gr32 0xe0000000 r1
+ shar #1,r1,r2
+ test_carry_clear
+ test_zero_clear
+ test_neg_set
+ test_overflow_clear
+ test_h_gr32 0xf0000000 r2
+ shll #1,r1
+ test_carry_set
+ test_zero_clear
+ test_neg_set
+ test_overflow_clear
+ test_h_gr32 0xc0000000 r1
+ mov #1,r2
+ shll r2,r1
+ test_carry_set
+ test_zero_clear
+ test_neg_set
+ test_overflow_clear
+ test_h_gr32 0x80000000 r1
+ shll #1,r1,r2
+ test_carry_set
+ test_zero_set
+ test_neg_clear
+ test_overflow_set
+ test_h_gr32 0x00000000 r2
+ mov #0xaaaaaaaa,r1
+ shlr #1,r1
+ test_carry_clear
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x55555555 r1
+ mov #1,r2
+ shlr r2,r1
+ test_carry_set
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x2aaaaaaa r1
+ shlr #1,r1,r2
+ test_carry_clear
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x15555555 r2
+
+ pass
+
+ .data
diff --git a/sim/testsuite/sim/rx/smovb.s b/sim/testsuite/sim/rx/smovb.s
new file mode 100644
index 0000000..e3f4614
--- /dev/null
+++ b/sim/testsuite/sim/rx/smovb.s
@@ -0,0 +1,53 @@
+# RX testcase for smovb
+# mach: all
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ mov #src+127,r2
+ mov #dst+127,r1
+ mov #128,r3
+ smovb
+ add #1,r1
+ add #1,r2
+ mov #128,r3
+1: mov.b [r1],r4
+ cmp [r2].b,r4
+ bne __fail
+ mov.b #0,[r1]
+ add #1,r1
+ add #1,r2
+ sub #1,r3
+ bpz 1b
+ mov #src,r2
+ mov #dst,r1
+ mov #128,r3
+ smovf
+ mov #128,r3
+ mov #src,r2
+ mov #dst,r1
+1: mov.b [r1],r4
+ cmp [r2].b,r4
+ bne __fail
+ mov.b #0,[r1]
+ add #1,r1
+ add #1,r2
+ sub #1,r3
+ bpz 1b
+
+ pass
+__fail:
+ fail
+ exit 1
+
+ .data
+src:
+ data = 0
+ .rept 128
+ .byte data
+ data = data + 1
+ .endr
+dst:
+ .space 128
+
diff --git a/sim/testsuite/sim/rx/smovu.s b/sim/testsuite/sim/rx/smovu.s
new file mode 100644
index 0000000..e5be9b6
--- /dev/null
+++ b/sim/testsuite/sim/rx/smovu.s
@@ -0,0 +1,23 @@
+# RX testcase for smovu
+# mach: all
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ mov #str1,r2
+ mov #str1_dst,r1
+ mov #128,r3
+ smovu
+ mov #str1,r2
+ mov #str1_dst,r1
+ mov #128,r3
+ scmpu
+ test_zero_set
+
+ pass
+
+ .data
+str1: .asciz "abcdefghijklmnopqrstuvwxyz"
+str1_dst:
+ .space 27
diff --git a/sim/testsuite/sim/rx/sstr.s b/sim/testsuite/sim/rx/sstr.s
new file mode 100644
index 0000000..77e61b3
--- /dev/null
+++ b/sim/testsuite/sim/rx/sstr.s
@@ -0,0 +1,44 @@
+# RX testcase for sstr
+# mach: all
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ mov #0x12345678,r2
+ mov #dst,r1
+ mov #128,r3
+ sstr.b
+ mov #128,r3
+ mov #dst,r1
+1: mov.b [r1+],r2
+ test_h_gr32 0x78 r2
+ sub #1,r3
+ bne 1b
+ mov #0x12345678,r2
+ mov #dst,r1
+ mov #128/2,r3
+ sstr.w
+ mov #128/2,r3
+ mov #dst,r1
+1: mov.w [r1+],r2
+ test_h_gr32 0x5678 r2
+ sub #1,r3
+ bne 1b
+ mov #0x12345678,r2
+ mov #dst,r1
+ mov #128/4,r3
+ sstr.l
+ mov #128/4,r3
+ mov #dst,r1
+1: mov.l [r1+],r2
+ test_h_gr32 0x12345678 r2
+ sub #1,r3
+ bne 1b
+
+ pass
+
+ .data
+dst:
+ .space 128
+
diff --git a/sim/testsuite/sim/rx/stz.s b/sim/testsuite/sim/rx/stz.s
new file mode 100644
index 0000000..b479319
--- /dev/null
+++ b/sim/testsuite/sim/rx/stz.s
@@ -0,0 +1,52 @@
+# RX testcase for sstr
+# mach: all
+# as(rx): --muse-conventional-section-names --defsym cpu=1
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+ clear_zero_flag
+ stnz #1, r1
+ stnz #0x100, r2
+ stnz #0x10000, r3
+ stnz #0x1000000, r4
+ stz #2, r1
+ stz #0x200, r2
+ stz #0x20000, r3
+ stz #0x2000000, r4
+ test_h_gr32 1 r1
+ test_h_gr32 0x100 r2
+ test_h_gr32 0x10000 r3
+ test_h_gr32 0x1000000 r4
+ set_zero_flag
+ stnz #1, r1
+ stnz #0x100, r2
+ stnz #0x10000, r3
+ stnz #0x1000000, r4
+ stz #2, r1
+ stz #0x200, r2
+ stz #0x20000, r3
+ stz #0x2000000, r4
+ test_h_gr32 2 r1
+ test_h_gr32 0x200 r2
+ test_h_gr32 0x20000 r3
+ test_h_gr32 0x2000000 r4
+
+ .if cpu == 2
+ mov #1,r1
+ mov #2,r2
+ clear_zero_flag
+ stz r2,r1
+ test_h_gr32 1 r1
+ clear_zero_flag
+ stnz r2,r1
+ test_h_gr32 2 r1
+ .endif
+
+ pass
+
+ .data
+dst:
+ .space 128
+
diff --git a/sim/testsuite/sim/rx/sub.s b/sim/testsuite/sim/rx/sub.s
new file mode 100644
index 0000000..20ad73b
--- /dev/null
+++ b/sim/testsuite/sim/rx/sub.s
@@ -0,0 +1,53 @@
+# RX testcase for sub
+# mach: all
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+sub_imm4:
+ mov.l #2,r1
+ sub #1,r1
+ test_zero_clear
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 1 r1
+sub_reg:
+ mov.l #1,r2
+ sub r2,r1
+ test_zero_set
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 0 r1
+sub_mem_ind:
+ mov.l #val, r2
+ sub [r2].l,r1
+ test_zero_clear
+ test_carry_clear
+ test_neg_set
+ test_h_gr32 -1 r1
+sub_mem_dsp8:
+ mov.l #val-4, r2
+ sub 4[r2].l,r1
+ test_zero_clear
+ test_carry_set
+ test_neg_set
+ test_h_gr32 -2 r1
+sub_mem_dsp16:
+ mov.l #val-0x1000, r2
+ sub 0x1000[r2].l,r1
+ test_zero_clear
+ test_carry_set
+ test_neg_set
+ test_h_gr32 -3 r1
+sub3_reg:
+ sub r1,r1,r2
+ test_zero_set
+ test_carry_set
+ test_neg_clear
+ test_h_gr32 0 r2
+
+ pass
+
+ .data
+val: .long 1
diff --git a/sim/testsuite/sim/rx/suntil.s b/sim/testsuite/sim/rx/suntil.s
new file mode 100644
index 0000000..a0b75c3
--- /dev/null
+++ b/sim/testsuite/sim/rx/suntil.s
@@ -0,0 +1,59 @@
+# RX testcase for suntil
+# mach: all
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+ mov #until,r1
+ mov #127,r2
+ mov #128,r3
+ suntil.b
+ test_zero_set
+ test_h_gr32 0 r3
+ mov #until,r1
+ mov #0x7f7e,r2
+ mov #128/2,r3
+ suntil.w
+ test_zero_set
+ test_h_gr32 0 r3
+ mov #until,r1
+ mov #0x7f7e7d7c,r2
+ mov #128/4,r3
+ suntil.l
+ test_zero_set
+ test_h_gr32 0 r3
+
+ mov #while,r1
+ mov #0,r2
+ mov #128,r3
+ swhile.b
+ test_zero_clear
+ test_h_gr32 3 r3
+ mov #while,r1
+ mov #0,r2
+ mov #128/2,r3
+ swhile.w
+ test_zero_clear
+ test_h_gr32 1 r3
+ mov #while,r1
+ mov #0,r2
+ mov #128/4,r3
+ swhile.l
+ test_zero_clear
+ test_h_gr32 0 r3
+
+ pass
+
+ .data
+until:
+ data = 0
+ .rept 128
+ .byte data
+ data = data + 1
+ .endr
+while:
+ .rept 31
+ .long 0
+ .endr
+ .long 0x01010101
diff --git a/sim/testsuite/sim/rx/testutils.inc b/sim/testsuite/sim/rx/testutils.inc
new file mode 100644
index 0000000..06977ae
--- /dev/null
+++ b/sim/testsuite/sim/rx/testutils.inc
@@ -0,0 +1,302 @@
+# Support macros for the Renesas RX assembly test cases.
+
+; Set up a minimal machine state
+ .macro start
+
+ .text
+ .align 2
+ .global _start
+_start:
+ bra _main
+
+ .data
+ .align 2
+ .global pass_str
+ .global fail_str
+ .global ok_str
+pass_str:
+ .ascii "pass\n"
+fail_str:
+ .ascii "fail\n"
+ok_str:
+ .ascii "ok\n"
+
+ .text
+ .global _write_and_exit
+_write_and_exit:
+;ssize_t write(int fd, const void *buf, size_t count);
+;Integer arguments have to be zero extended.
+ mov.l #5,r5
+ int #255
+ mov.l r4,r1
+ bra _exit
+
+ .global _exit
+_exit:
+ mov.l #1,r5
+ int #255
+
+ .global _main
+_main:
+ .endm
+
+
+; Exit with an exit code
+ .macro exit code
+ mov.l #\code, r1
+ bra _exit
+ .endm
+
+; Output "pass\n"
+ .macro pass
+ mov.l #0, r1 ; fd == stdout
+ mov.l #pass_str, r2 ; buf == "pass\n"
+ mov.l #5, r3 ; len == 5
+ sub r4,r4
+ bra _write_and_exit
+ .endm
+
+; Output "fail\n"
+ .macro fail
+ mov.l #0, r1 ; fd == stdout
+ mov.l #fail_str, r2 ; buf == "fail\n"
+ mov.l #5, r3 ; len == 5
+ mov.l #1,r4
+ bra _write_and_exit
+ .endm
+
+
+; Load an 8-bit immediate value into a general register
+; (reg must be r0l - r7l or r0h - r7h)
+ .macro mvi_h_gr8 val reg
+ mov.b #\val, \reg
+ .endm
+
+; Load a 16-bit immediate value into a general register
+; (reg must be r0 - r7)
+ .macro mvi_h_gr16 val reg
+ mov.w #\val, \reg
+ .endm
+
+; Load a 32-bit immediate value into a general register
+; (reg must be er0 - er7)
+ .macro mvi_h_gr32 val reg
+ mov.l #\val, \reg
+ .endm
+
+; Test the value of an 8-bit immediate against a general register
+; (reg must be r0l - r7l or r0h - r7h)
+ .macro test_h_gr8 val reg
+ cmp.b #\val, \reg
+ beq .Ltest_gr8\@
+ fail
+.Ltest_gr8\@:
+ .endm
+
+; Test the value of a 16-bit immediate against a general register
+; (reg must be r0 - r7)
+ .macro test_h_gr16 val reg h=h l=l
+ cmp.w #\val, \reg
+ beq .Ltest_gr16\@
+ fail
+.Ltest_gr16\@:
+ .endm
+
+; Test the value of a 32-bit immediate against a general register
+; (reg must be er0 - er7)
+ .macro test_h_gr32 val reg
+ cmp #\val, \reg
+ beq .Ltest_gr32\@
+ fail
+.Ltest_gr32\@:
+ .endm
+
+; Set a general register to the fixed pattern 'a5a5a5a5'
+ .macro set_gr_a5a5 reg
+ mov.l #0xa5a5a5a5, r\reg
+ .endm
+
+; Set all general registers to the fixed pattern 'a5a5a5a5'
+ .macro set_grs_a5a5
+ mov.l #0xa5a5a5a5, r1
+ mov.l #0xa5a5a5a5, r2
+ mov.l #0xa5a5a5a5, r3
+ mov.l #0xa5a5a5a5, r4
+ mov.l #0xa5a5a5a5, r5
+ mov.l #0xa5a5a5a5, r6
+ mov.l #0xa5a5a5a5, r7
+ mov.l #0xa5a5a5a5, r8
+ mov.l #0xa5a5a5a5, r9
+ mov.l #0xa5a5a5a5, r10
+ mov.l #0xa5a5a5a5, r11
+ mov.l #0xa5a5a5a5, r12
+ mov.l #0xa5a5a5a5, r13
+ mov.l #0xa5a5a5a5, r14
+ mov.l #0xa5a5a5a5, r15
+ .endm
+
+; Test that a general register contains the fixed pattern 'a5a5a5a5'
+ .macro test_gr_a5a5 reg
+ test_h_gr32 0xa5a5a5a5 r\reg
+ .endm
+
+; Test that all general regs contain the fixed pattern 'a5a5a5a5'
+ .macro test_grs_a5a5
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ test_gr_a5a5 8
+ test_gr_a5a5 9
+ test_gr_a5a5 10
+ test_gr_a5a5 11
+ test_gr_a5a5 12
+ test_gr_a5a5 13
+ test_gr_a5a5 14
+ test_gr_a5a5 15
+ .endm
+
+; Set condition code register to an explicit value
+ .macro set_ccr val
+ mvtc #\val, psw
+ .endm
+
+; Set all condition code flags to zero
+ .macro set_ccr_zero
+ mvtc #0, psw
+ .endm
+
+; Set carry flag true
+ .macro set_carry_flag
+ setpsw c
+ .endm
+
+; Clear carry flag
+ .macro clear_carry_flag
+ clrpsw c
+ .endm
+
+; Set zero flag true
+ .macro set_zero_flag
+ setpsw z
+ .endm
+
+; Clear zero flag
+ .macro clear_zero_flag
+ clrpsw z
+ .endm
+
+; Set sign flag true
+ .macro set_neg_flag
+ setpsw s
+ .endm
+
+; Clear sign flag
+ .macro clear_neg_flag
+ clrpsw s
+ .endm
+
+; Set overflow flag true
+ .macro set_overflow_flag
+ setpsw o
+ .endm
+
+; Clear overflow flag
+ .macro clear_overflow_flag
+ clrpsw o
+ .endm
+
+; Test that carry flag is clear
+ .macro test_carry_clear
+ bnc .Lcc\@
+ fail ; carry flag not clear
+.Lcc\@:
+ .endm
+
+; Test that carry flag is set
+ .macro test_carry_set
+ bc .Lcs\@
+ fail ; carry flag not clear
+.Lcs\@:
+ .endm
+
+; Test that overflow flag is clear
+ .macro test_ovf_clear
+ bno .Lvc\@
+ fail ; overflow flag not clear
+.Lvc\@:
+ .endm
+
+; Test that overflow flag is set
+ .macro test_ovf_set
+ bo .Lvs\@
+ fail ; overflow flag not clear
+.Lvs\@:
+ .endm
+
+; Test that zero flag is clear
+ .macro test_zero_clear
+ bne .Lne\@
+ fail ; zero flag not clear
+.Lne\@:
+ .endm
+
+; Test that zero flag is set
+ .macro test_zero_set
+ beq .Leq\@
+ fail ; zero flag not clear
+.Leq\@:
+ .endm
+
+; Test that neg flag is clear
+ .macro test_neg_clear
+ bpz .Lneg\@
+ fail ; negative flag not clear
+.Lneg\@:
+ .endm
+
+; Test that neg flag is set
+ .macro test_neg_set
+ bn .Lneg\@
+ fail ; negative flag not clear
+.Lneg\@:
+ .endm
+
+; Test that overflow flag is clear
+ .macro test_overflow_clear
+ bno .Loverflow\@
+ fail ; negative flag not clear
+.Loverflow\@:
+ .endm
+
+; Test that overflow flag is set
+ .macro test_overflow_set
+ bo .Loverflow\@
+ fail ; negative flag not clear
+.Loverflow\@:
+ .endm
+
+; Test ccr against an explicit value
+ .macro test_ccr val
+ .text
+ mov.l r1,[-r0]
+ mvfc psw, r1
+ cmp #\val, r1
+ bne .Ltcc\@
+ fail
+.Ltcc\@:
+ mov.l [r0+],r1
+ .endm
+
+; Test that all (accessable) condition codes are clear
+ .macro test_cc_clear
+ test_carry_clear
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+ ; leaves H, I, U, and UI untested
+ .endm
+
diff --git a/sim/testsuite/sim/rx/tst.s b/sim/testsuite/sim/rx/tst.s
new file mode 100644
index 0000000..cdb2c73
--- /dev/null
+++ b/sim/testsuite/sim/rx/tst.s
@@ -0,0 +1,54 @@
+# RX testcase for tst
+# mach: all
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+tst_imm4:
+ mov.l #2,r1
+ tst #2,r1
+ test_zero_clear
+ test_neg_clear
+tst_imm8:
+ tst #0x13,r1
+ test_zero_clear
+ test_neg_clear
+tst_imm16:
+ tst #0xffff,r1
+ test_zero_clear
+ test_neg_clear
+tst_imm24:
+ tst #0xffffff,r1
+ test_zero_clear
+ test_neg_clear
+tst_imm32:
+ mov.l #0x80000000,r1
+ tst #0xffffffff,r1
+ test_zero_clear
+ test_neg_set
+tst_reg:
+ mov.l #0x80000000,r2
+ tst r2,r1
+ test_zero_clear
+ test_neg_set
+tst_mem_ind:
+ mov.l #val, r2
+ tst [r2].l,r1
+ test_zero_set
+ test_neg_clear
+tst_mem_dsp8:
+ mov.l #val-4, r2
+ tst 4[r2].l,r1
+ test_zero_set
+ test_neg_clear
+tst_mem_dsp16:
+ mov.l #val-0x1000, r2
+ tst 0x1000[r2].l,r1
+ test_zero_set
+ test_neg_clear
+
+ pass
+
+ .data
+val: .long 1
diff --git a/sim/testsuite/sim/rx/utof.s b/sim/testsuite/sim/rx/utof.s
new file mode 100644
index 0000000..2dee2bf
--- /dev/null
+++ b/sim/testsuite/sim/rx/utof.s
@@ -0,0 +1,37 @@
+# RX testcase for utof
+# mach: rxv2
+# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2
+
+ .include "testutils.inc"
+
+ start
+utof_reg:
+ mov.l #2147483648,r2
+ utof r2,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2147483648.0 r1
+utof_mem_ind:
+ mov.l #val, r2
+ utof [r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2147483648.0 r1
+utof_mem_dsp8:
+ mov.l #val-4, r2
+ utof 4[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2147483648.0 r1
+utof_mem_dsp16:
+ mov.l #val-0x1000, r2
+ utof 0x1000[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 2147483648.0 r1
+
+ pass
+
+ .data
+val: .long 2147483648
+
diff --git a/sim/testsuite/sim/rx/xchg.s b/sim/testsuite/sim/rx/xchg.s
new file mode 100644
index 0000000..ee7deb4
--- /dev/null
+++ b/sim/testsuite/sim/rx/xchg.s
@@ -0,0 +1,36 @@
+# RX testcase for xchg
+# mach: all
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+xchg_reg:
+ mov.l #1,r1
+ mov.l #2,r2
+ xchg r2,r1
+ test_h_gr32 1 r2
+ test_h_gr32 2 r1
+xchg_mem_ind:
+ mov.l #val, r2
+ xchg [r2].l,r1
+ mov.l [r2],r3
+ test_h_gr32 1 r1
+ test_h_gr32 2 r3
+tst_mem_dsp8:
+ mov.l #val-4, r2
+ xchg 4[r2].l,r1
+ mov.l 4[r2],r3
+ test_h_gr32 2 r1
+ test_h_gr32 1 r3
+tst_mem_dsp16:
+ mov.l #val-0x1000, r2
+ xchg 0x1000[r2].l,r1
+ mov.l 0x1000[r2],r3
+ test_h_gr32 1 r1
+ test_h_gr32 2 r3
+
+ pass
+
+ .data
+val: .long 1
diff --git a/sim/testsuite/sim/rx/xor.s b/sim/testsuite/sim/rx/xor.s
new file mode 100644
index 0000000..1324b2c
--- /dev/null
+++ b/sim/testsuite/sim/rx/xor.s
@@ -0,0 +1,58 @@
+# RX testcase for xor
+# mach: all
+# as(rx): --muse-conventional-section-names
+
+ .include "testutils.inc"
+
+ start
+xor_imm8:
+ sub r1,r1
+ xor #0x10,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x10 r1
+xor_imm16:
+ xor #0x1010,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x1000 r1
+xor_imm24:
+ xor #0x101000,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x100000 r1
+xor_imm32:
+ xor #0x10100000,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x10000000 r1
+xor_reg:
+ mov.l #0x20000000,r2
+ xor r2,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x30000000 r1
+xor_mem_ind:
+ mov #val, r2
+ xor [r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x30000008 r1
+xor_mem_dsp8:
+ mov #val-4, r2
+ xor 4[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 0x30000000 r1
+xor_mem_dsp16:
+ sub r1,r1
+ mov #val-0x1000, r2
+ xor 0x1000[r2].l,r1
+ test_zero_clear
+ test_neg_clear
+ test_h_gr32 8 r1
+
+ pass
+
+ .data
+val: .long 8
--
2.6.1
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2016-01-06 8:23 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
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2015-12-27 8:51 [PATCH][RX] v2 instructions support Yoshinori Sato
2015-12-27 8:51 ` [PATCH][RX] instructions test set Yoshinori Sato
2015-12-27 21:56 ` Mike Frysinger
2015-12-27 21:55 ` [PATCH][RX] v2 instructions support Mike Frysinger
2015-12-28 12:34 ` Yoshinori Sato
2016-01-06 2:43 ` DJ Delorie
2016-01-06 8:23 ` Yoshinori Sato
-- strict thread matches above, loose matches on Subject: below --
2015-12-28 12:37 [PATCH][RX] instructions test set Yoshinori Sato
2015-12-28 17:28 ` Mike Frysinger
2015-12-25 14:20 [PATCH][RX] v2 instructions support Yoshinori Sato
2015-12-25 14:20 ` [PATCH][RX] instructions test set Yoshinori Sato
2015-12-25 17:04 ` Mike Frysinger
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